“PROGRAMMABLE PATTERN GENERATOR”FINAL PRESENTATION

Students :Or Shperling & Liron Ulman

Instructor :Ina Rivkin

Project’s Goals & Definitions

Designing an On-Line configurable “Pattern Generator” using 2 implementations:(1) Xilinx IP-Core DDS (Direct Digital Synthesizer).(2) A memory which will be use as a LUT for the pattern values, with a logic which will govern the memory output.

User’s trigger will initiate sine output. Test the implementations on ML605 platform.

Project’s requirements (1)

Configuration phase- Inserting required Frequency and initial phase.

‘Start’ initiates system iteration. Some delay after ‘Start’, our system is ready for trigger.

‘Trigger in’ is 1KHz PRI [Pulse Repetition Interval].

1st ‘Trigger in’ initiates 4 channels of sine signal with different frequency and different phase.

Every ‘Trigger in’ reset the phase of all channels to the initial phase.

‘Stop’ means : “End of current iteration”.

Project’s requirements (2)

Trigger_out is an output for the A/D to inform the Sine is ready.

Trigger_out(t) = Trigger_in+ delay = Trigger_in (t – (T1 + TDM ))T1 = Our module delay from triggerTDM = Analogue receiver delay

At least 32 sampling points per sine period.

Data width according to D/A width – typically 24 bits.

DSPReceiver : Analog Pre-Processing

D/A D/AD/AD/A

A/D

TRIGGER_OUT

SystemControllerTRIGGER_IN

STARTSTOP

X t X t 5 GHz

Low Frequency

POFF_CONFIG

DATA_IN

Our design sitson Virtex-6 FPGA

ML605 BoardPINC_CONFIG

SINE0 SINE1 SINE2 SINE3

Frequencies analysis Signal resolution and clock frequency

dictates maximal sine frequency :

Our clock is produced by a DCM unit which is fed by 66 MHz board crystal’s “User Clock”.

We’ve examined some clock frequency till satisfactory results have been achieved.

sin 32clk clkf ff

samples per period

Implementation First Implementation – DDS

Using a built-in library unit- Direct Digital Synthesizer - to compute the sine.

Second Implementation- Memory Our own implementation and logic design, using memory units and logic.

Each implementaion has 2 options: -Blocked memory-Distributed memory

Block Diagram

CESCLRWEREG_SELECT

CONFIG_DATA0CONFIG_DATA1CONFIG_DATA2CONFIG_DATA3

SINE0SINE1SINE2SINE3

4 Channels Synthesizer (DDS/ Memory Design)

DATA_IN0

TRIGGER_INTRIGGER_OUT

PHASE_OUT0PHASE_OUT1PHASE_OUT2PHASE_OUT3

Programmable Delay

CESCLR

WEREG_SELECT

STATE_OUT

PINC_CONFIG

POFF_CONFIG

START

STOP

TRIGGER_IN

Controller

PINC_CONFIG

PINC_CONFIG_DEB

START_DEB

STOP_DEB

POFF_CONFIG_DEBPOFF_

CONFIG

STARTSTOP

Inputs Debouncer

RESET TRIGGER

Trigger GeneratorCONFIG_

DATA0

CONFIG_DATA0

CONFIG_DATA2

CONFIG_DATA3

Configurator

DATA_IN1DATA_IN2DATA_IN3

DCM

CLK_OUT

CLK_INclk_sig

clk_sig

clk_sig

clk_sig

clk_sig

clk_sig

RESETRESET

RESET

RESET

RESET

RESET

RESE

TRESET

RDYRDY

USER_CLK

Controller States Machine

idle_state

TRIGGER_IN

TRIGEER_IN

run_state reset_phase_state

wait4trig_state

poff_config_state

STOP

STATE_OUT= “000”

State= “100”

STATE_OUT = “011”

State= “101”

STOP

PINC_

CONF

IG

CE , SCLR

CE

STO

P

STOP

CE , SCLR

STOP

WE

STATE_OUT = “010”

WE

POFF_CONFIG

START

STATE_OUT = “001”

pinc_config_state

REG_SELCET = ‘1’

REG_SELECT = ‘0’

Input Trigger- a trigger generator producing triggers

on wanted intervals.In real system- trigger injected from outside

Data- 8 dip switches selecting 4 different modes for each channel: 4 frequencies- full, double, 4 times and 8 times the original frequency. 4 phases-In real system- as many bits as wanted from outside

30, , ,2 2

Trigger Out

TRIG_IN Flip-Flop Flip-Flop Flip-Flop TRIG_OUT…CLKCLKCLK

CLK

Shift Register (size determined by user)

DDS Implementaionusing xilinx DDS IP coreDDS BLOCK DIAGRAM

SINE[0..SINE_WIDTH-1]

DDS Module0

PHASE_OUT[0..PHASE_WIDTH-1]

CESCLRWE

REG_SELECTDATA[0..PHASE_WIDTH-1]

SINE[0..SINE_WIDTH-1]

DDS Module3

PHASE_OUT[0..PHASE_WIDTH-1]

CESCLRWE

REG_SELECTDATA[0..PHASE_WIDTH-1]

CONFIG_DATA0

CONFIG_DATA2

CESCLRREG_SELECT

WE SINE0PHASE_OUT0

SINE3

PHASE_OUT3

DDS results- Distributed550 MHz clock, sampled at 550 MHz – on Logic AnalyzerMaximal possible frequency

No noise !

DDS results-DistributedTrigger in action

6 clocks after trigger, the phase resets to 0.

DDS results550 MHz clock, sampled at 4 GHz – on Logic Analyzer

Significant noise ! Let us focus on one particular “spike”

Zoom on “Spike”

Zoom on “Spike”

There is a 500ps (at least) long transient : “11010000””11110010” (TransientValue) ”10111010”.

The Tpd of the DDS is longer than 250ps which is the sampling

interval, and therefore we see the transient which occurs within the Tpd.

DDS results- Blocked550 MHz clock, sampled at 550 MHz –on Logic AnalyzerMaximal possible frequency

No noise !

DDS results- BlockedTrigger in action

6 clocks after trigger, the phase resets to 0.

Conclusions Maximal frequency is :

550 MHz is the maximal working frequency of Xilinx’s DDS core.

sin

55017.1875

32MHz

f MHz

Sine generator – Memory implementation

0

Sin( )sin(2π)

00000

Sine

Addresses jump will be determined by initialized frequency.

Initial address will be determined by initialized phase

Required memory size: 32*word width *4 channelsFor word width=32: 4096

3132

0000100010

1111011111

Memory implementation – “Sine Generator” Block Diagram

DOUTA

CLK A

ADDR A

ROM

POFF REG

CLK

Address Generator

RESET

PINC

POFF

CE

ADDRESSSINE

PHASE_OUT

SCLRRESETSCLRCE

RESET

PINC REG

RESET

RESET

RESET

CLK

WE

WE

pinc_sig

poff_sig

10

0

1

DATA

WE DATA

DATA

REG SELECT

Memory implementation – Address Generator Block Diagram

Address GeneratorRESET

PINC

POFF

CE ADDRESS

SCLR

CLK

+

WE

REGISTER

RESET

0

1DATA

OUT

Option 1- Blocked memory

Pros-* dedicated memory blocks on board.

* Decreased noise at high frequency - because it is synchronous the critical path is shorter and Tpd is shorter.

Cons–* extra cycle delay from trig because of synchronous read

Blocked Memory results700 MHz clock, sampled at 700 MHz – on Logic AnalyzorMaximal possible frequency

No noise !

Delay from trigger

3 Clocks from trigger, the phase resets

Blocked Memory results700 MHz clock, sampled at 4 GHz – on Logic Analyzor

Significant noise. Like was explained before, spikes are transients which occurs within the Tpd of the ROM.

Block memory Conclusions

Maximal frequency is :

sin

70021.875

32MHz

f MHz

Option 2- Distributed memory

Pros-* only 2 cycles delay from trig (instead of 3)

Cons –* no dedicated blocks, implemented with other components.* Might decrease performance on heavy designs* Noisier at high frequencies – because it is not synchronous the logics’ delay is added to the ROMs’ delay causing higher Tpd.

Distributed Memory Results

500 MHz clock, sampled at 500 MHz– on Logic Analyser

No Noise !

Distributed Memory Results

Delay from trigger

2 Clocks from trigger, the phase resets

Distributed Memory Results

700 MHz clock, sampled at 700 MHz

Maximal possible frequency

Noise exists but is not significant – good enough.

Distributed Memory Results

Delay from trigger

2 Clocks from trigger, the phase resets.

Conclusions Maximal frequency is :

sin

70021.875

32MHz

f MHz

Blocked Memory results700 MHz clock – 22 samples per

period , sampled at 700 MHz – on Logic Analyzer

No Noise !

Blocked Memory results700 MHz clock – 22 samples per

period - Delay from Trigger

3 Clocks from trigger, the phase resets.

Conclusions Maximal frequency is :

sin

70031.8

22MHz

f MHz

Prefomance and Utalization comparison (1)

LUT used as Memory (out of 58,400)

LUT used as logic(out of 150,720)

Mem usage (out of 832)

Delay from Trig(in cycles)

Max Freq. Implem-entaion

0 166 4 6 550MHz DDS- Blocked

48 165 0 6 550MHz DDS- Distributed

0 156 4 3 700MHz Memory-Blocked

0 172 0 2 700MHz (with a “little” noise)500MHz (noise free)

Memory- Distributed

Prefomance and Utalization comparison (2)

LUT used as Memory (out of 58,400)

LUT used as logic(out of 150,720)

Mem usage (out of 832)

Delay from Trig(in cycles)

Max Freq. Implem-entaion

0 156 4 3 700MHz Memory- Blocked – 22 samples per period

Main Problems encountered Physical switches noise- the switches

produced significant noise interfering with the proper operation of the system. Solution: Debouncer

Chipscope noise- Significant noise was sampled in the chipscope.Solution: Sampling with Logic Analyzer. Chipscope false sampling

Future Project Development

Add an interface with an outer system such as PC.

Interfacing with D2A and sampling the analog signal with scope.

Add an analog noise filter to overcome unwanted noise.

Implement and/or use a higher frequency clock, to achieve higher operating frequency.

Gantt Chart

Finish design based on DDS module

Perfomance testing on board

Design sine generator based on memory module

Memory controller design

Integration and Logic Simulation and board implementation

Perfomance testing on board

Mid Term14/4/2013

Original Final 1/7/2013

Actual Final9/6/2013

Demonstration!

Thank you for listening!