process(clk25, rst) begin if rst= '0' then div '0'); elsif rising_edge(clk25)...

4
cess(clk25, rst) egin if rst= '0' then div <= (others=> '0'); elsif rising_edge(clk25) then div<= div + 1; end if; process; _in<= div(div'left); s(clk_in, rst) n f rst= '0' then idx <= 0; lsif rising_edge(clk_in) then if idx= 3 then idx<= 0; else idx<= idx + 1; end if; nd if; ocess; idx = 0 idx = 1 idx = 2 idx = 3 idx = 0 idx = 1 idx = 2 idx = 3 idx = 0 idx = 1 idx = 2 idx = 3 . . . . . . . . . . . . . . . . . . . . . . signal div: unsigned (2 downto 0); div = 000 div = 001 div = 010 div = 011 div = 100 div = 101 div = 110 div = 111 div = 000 div = 001 div = 010 div = 011 div = 100 div = 101 div = 110 div = 111 . . . . . . . . . . . . . . . . . . . . . 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 idx = 0 idx = 1 idx = 2 idx = 3 idx = 0 idx = 1 idx = 2

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Page 1: Process(clk25, rst) begin if rst= '0' then div '0'); elsif rising_edge(clk25) then div

process(clk25, rst) begin if rst= '0' then div <= (others=> '0'); elsif rising_edge(clk25) then div<= div + 1; end if;end process;

clk_in<= div(div'left);

process(clk_in, rst) begin if rst= '0' then idx <= 0; elsif rising_edge(clk_in) then if idx= 3 then idx<= 0; else idx<= idx + 1; end if; end if;end process;

idx = 0 idx = 1 idx = 2 idx = 3idx = 0 idx = 1 idx = 2 idx = 3 idx = 0 idx = 1 idx = 2 idx = 3. . . . . . . . . . . . . . . . . . . . . . .

signal div: unsigned (2 downto 0);

div = 000 div = 001 div = 010 div = 011 div = 100div = 101 div = 110 div = 111div = 000 div = 001 div = 010 div = 011 div = 100div = 101 div = 110 div = 111. . . . . . . . . . . . . . . . . . . . . . . . . . .

000

001

010

011

100

101

110

111

000

idx = 0

idx = 1

idx = 2

idx = 3

idx = 0

idx = 1

idx = 2

Page 2: Process(clk25, rst) begin if rst= '0' then div '0'); elsif rising_edge(clk25) then div

process(clk_in, rst)begin if rst= '0' then

cs <= '0';ext_a <= (others=> '0');ext_d <= (others=> '0');

elsif rising_edge(clk_in) thencase idx is

when 0=> ext_a<= "00" & rs;when 1=> cs <= '1';ext_d<= cmd;when 2=> cs <= '0';when 3=> null;

end case; end if;end process;

ext_rw<= '0';cs_lcd <= cs;csn_lcd<= '0';

rs = 0 - instrução

rs = 1 - dados

8 bits dados

LCD activo

idx = 0

idx = 1

idx = 2

idx = 3

idx = 0

idx = 1

idx = 2

Page 3: Process(clk25, rst) begin if rst= '0' then div '0'); elsif rising_edge(clk25) then div

process(clk_in, rst)begin if rst= '0' then

cmd <= x"00";rs <= '1';reset <= '1';cnt <= (others => '0');

elsif rising_edge(clk_in) thenif idx = 2 then cnt <= cnt + 1;end if;if (reset ='0') then case cnt is -- DADOD

when "000000" => cmd <= x"80"; rs <= '0'; -- 1º LINHAwhen "000001" => cmd <= "00110000"; rs <= '1';-- . . . . . . . . .when "010001" => cmd <= x"C0"; rs <= '0'; -- 2º LINHAwhen "010010" => cmd <= "00110001"; rs <= '1';-- . . . . . . . . . . . . . . . . . . . . when others => cmd <= x"80"; rs <= '0';

end case;

else -- INSTRUÇÔES (INITIALISAÇÂO) case cnt is

when "000000" => cmd <= x"38"; rs <= '0';-- . . . . . . . . . . . . .when others => null;

end case;end if;

end if;end process;

Page 4: Process(clk25, rst) begin if rst= '0' then div '0'); elsif rising_edge(clk25) then div

case cnt iswhen "000000" => cmd <= x"80"; rs <= '0';when "000001" => cmd <= "00110000"; rs <= '1';when "000010" => cmd <= "00110001"; rs <= '1';when "000011" => cmd <= x"20"; rs <= '1';when "000100" => cmd <= "00110010"; rs <= '1';when "000101" => cmd <= "00110011"; rs <= '1';when "000110" => cmd <= x"20"; rs <= '1';when "000111" => cmd <= "00110100"; rs <= '1';when "001000" => cmd <= "00110101"; rs <= '1';when "001001" => cmd <= x"20"; rs <= '1';when "001010" => cmd <= "00110110"; rs <= '1';when "001011" => cmd <= "00110111"; rs <= '1';when "001100" => cmd <= x"20"; rs <= '1';when "001101" => cmd <= "00111000"; rs <= '1';when "001110" => cmd <= "00111001"; rs <= '1';when "001111" => cmd <= x"20"; rs <= '1';when "010000" => cmd <= x"20"; rs <= '1';

when "010001" => cmd <= x"C0"; rs <= '0';when "010010" => cmd <= "00110001"; rs <= '1';when "010011" => cmd <= "00110000"; rs <= '1';when "010100" => cmd <= x"20"; rs <= '1';when "010101" => cmd <= std_logic_vector(to_unsigned(character'pos('A'), 8)); rs <= '1';when "010110" => cmd <= x"20"; rs <= '1';when "010111" => cmd <= DIP_in; rs <= '1';when "011000" => cmd <= x"20"; rs <= '1';when "011001" => cmd <= "0011000" & push_B; rs <= '1';when "011010" => cmd <= x"20"; rs <= '1';when "011011" => cmd <= std_logic_vector(to_unsigned(character'pos(line(1)), 8)); rs <= '1';when "011100" => cmd <= std_logic_vector(to_unsigned(character'pos(line(2)), 8)); rs <= '1';when "011101" => cmd <= std_logic_vector(to_unsigned(character'pos(line(3)), 8)); rs <= '1';when "011110" => cmd <= std_logic_vector(to_unsigned(character'pos(line(4)), 8)); rs <= '1';when "011111" => cmd <= x"20"; rs <= '1';when "100000" => cmd <= x"20"; rs <= '1';when "100001" => cmd <= "00110" & soma; rs <= '1';when others => cmd <= x"80"; rs <= '0';

end case;