probabilistic modelling of performance parameters of carbon nanotube transistors
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Probabilistic modelling of performance parameters of Carbon Nanotube transistors. Department of Electrical and Computer Engineering. By Yaman Sangar Amitesh Narayan Snehal Mhatre. Overview. Motivation Introduction CMOS v/s CNTFETs CNT Technology - Challenges - PowerPoint PPT PresentationTRANSCRIPT
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Probabilistic modelling of performance parameters of Carbon Nanotube transistors
Department of Electrical and Computer Engineering
ByYaman Sangar
Amitesh NarayanSnehal Mhatre
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Overview■ Motivation■ Introduction■ CMOS v/s CNTFETs■ CNT Technology - Challenges■ Probabilistic model of faults■ Modelling performance parameters:◻ION / IOFF tuning ratio
◻Gate delay◻Noise Margin
■ Conclusion
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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters:
ION / IOFF tuning ratio Gate delay Noise Margin
Conclusion
04/29/2014 2
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MOTIVATION: Why CNTFET?
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■ Dennard Scaling might not last long■ Increased performance by better algorithms?■ More parallelism?■ Alternatives to CMOS - FinFETs, Ge-nanowire FET, Si-
nanowire FET, wrap-around gate MOS, graphene ribbon FET ■ What about an inherently faster and less power consuming
device?■ Yay CNTFET – faster with low power
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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters:
ION / IOFF tuning ratio Gate delay Noise Margin
Conclusion
04/29/2014 4
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Carbon Nanotubes
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■ CNT is a tubular form of carbon with diameter as small as 1nm
■ CNT is configurationally equivalent to a 2-D graphene sheet rolled into a tube.
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Types of CNTs
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■ Single Walled CNT (SWNT)■ Double Walled CNT (DWNT)■ Multiple Walled CNT (MWNT)
■ Depending on Chiral angle:• Semiconducting CNT (s-CNT)• Metallic CNT (m-CNT)
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Properties of CNTs
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■ Strong and very flexible molecular material■ Electrical conductivity is 6 times that of copper■ High current carrying capacity■ Thermal conductivity is 15 times more than copper■ Toxicity?
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CNTFET
How CNTs conduct?
■ Gate used to electrostatically induce carriers into tube■ Ballistic Transport
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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters:
ION / IOFF tuning ratio Gate delay Noise Margin
Conclusion
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Circuit FET Delay (In Picoseconds)
Power (In uWatts)
Inverter CMOS 16.58 9.81
CNT 3.78 0.25
2 Input Nand CMOS 24.32 20.67
CNT 5.98 0.69
2 Input Nor CMOS 39.26 22.13
CNT 6.49 0.48
Simulation based Comparison between CMOS and CNT technology
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04/29/2014 11Better delay
Circuit FET Delay (In Picoseconds)
Power (In uWatts)
Inverter CMOS 16.58 9.81
CNT 3.78 0.25
2 Input Nand CMOS 24.32 20.67
CNT 5.98 0.69
2 Input Nor CMOS 39.26 22.13
CNT 6.49 0.48
Simulation based Comparison between CMOS and CNT technology
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04/29/2014 12Better delay
At lower power!
Circuit FET Delay (In Picoseconds)
Power (In uWatts)
Inverter CMOS 16.58 9.81
CNT 3.78 0.25
2 Input Nand CMOS 24.32 20.67
CNT 5.98 0.69
2 Input Nor CMOS 39.26 22.13
CNT 6.49 0.48
Simulation based Comparison between CMOS and CNT technology
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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters:
ION / IOFF tuning ratio Gate delay Noise Margin
Conclusion
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■ Major CNT specific variations■ CNT density variation■ Metallic CNT induced count variation■ CNT diameter variation■ CNT misalignment■ CNT doping variation
Challenges with CNT technology
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■ Unavoidable process variations
■ Performance parameters affected
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CNT density variation CNT diameter variation
■ Current variation
■ Threshold voltage variation
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CNT Misalignment CNT doping variation
■ Changes effective CNT length■ Short between CNTs■ Incorrect logic functionality■ Reduction in drive current
■ May not lead to unipolar behavior
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Metallic CNT induced count variation
m-CNTs-CNT
■ Excessive leakage current■ Increases power consumption■ Changes gate delay■ Inferior noise performance■ Defective functionality
s-CNT
m-CNT
Vgs
Cur
rent
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Removal of m-CNTFETs
■ VMR Technique : A special layout called VMR structure consisting of inter-digitated electrodes at minimum metal pitch is fabricated. M-CNT electrical breakdown performed by applying high voltage all at once using VMR. M-CNTs are burnt out and unwanted sections of VMR are later removed.
■ Using Thermal and Fluidic Process: Preferential thermal desorption of the alkyls from the semiconducting nanotubes and further dissolution of m-CNTs in chloroform.
■ Chemical Etching: Diameter dependent etching technique which removes all m-CNTs below a cutoff diameter.
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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters:
ION / IOFF tuning ratio Gate delay Noise Margin
Conclusion
04/29/2014 19
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Probabilistic model of CNT count variation due to m-CNTs
■ ps = probability of s-CNT■ pm = probability of m-CNT■ ps = 1 - pm
■ Ngs = number of grown s-CNTs■ Ngm = number of grown m-CNTs■ N = total number of CNTs
Probability of grown CNT count
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Conditional probability after removal techniques
■ Ns = number of surviving s-CNTs■ Nm = number of surving m-CNTs■ prs = conditional probability that a CNT is removed given that it is s-CNT ■ prm = conditional probability that a CNT is removed given that it is m-CNT■ qrs = 1 - prs
■ qrm = 1 -prm
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P൛Ns = ns|Ngs = ngsൟ= ngsCnsqrsnsprs
(ngs-ns) P൛Nm = nm|Ngm = ngmൟ= ngmCnmqrm
(ngm-nm)prmnm
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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters:
ION / IOFF tuning ratio Gate delay Noise Margin
Conclusion
04/29/2014 22
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Effect of CNT count variation on ION / IOFF tuning ratio
■ ION / IOFF is indicator of transistor leakage
■ Improper ION / IOFF → slow output transition or low output swing
■ Target value of ION / IOFF = 104
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Current of a single CNT
ICNT = ps Is + pmIm
µ(ICNT) = psµ( Is )+ pmµ(Im )
■ ICNT = drive current of single CNT (type unknown)■ Is = drive current of single s-CNT■ Im = drive current of single m-CNT
■ ps = probability of s-CNT■ pm = probability of m-CNT
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■ Ns = count of s-CNT■ Nm = count of m-CNT
■ Is,on = s-CNT current, Vgs = Vds = Vdd
■ Is,off = s-CNT current, Vgs = 0 and Vds = Vdd
■ Im = m-CNT current, Vds = Vdd
ION / IOFF ratio of CNTFET
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µ (Ns) = ps (1 - prs) N
µ (Nm) = pm (1 - prm) N
ION / IOFF ratio of CNTFET
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Effect of various processing parameters on the ratio µ(ION) / µ(IOFF)
■ µ(ION) / µ(IOFF) is more sensitive to prm
■ µ(ION) / µ(IOFF) = 104 for prm > 1 – 10 -4 = 99.99 % for pm = 33.33%
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1- prm
𝜇 (𝐼 𝑜𝑛)𝜇(𝐼 𝑜𝑓𝑓 )
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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters:
ION / IOFF tuning ratio Gate delay Noise Margin
Conclusion
04/29/2014 28
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Effect of CNT count variation on Gate delay
delay=C load ∆V
I drive
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3004/29/2014
= =
σ (delay )≈ μ (delay)σ ( I drive)
¿¿σ (delay )≈
Cload V dd
μ2¿¿
μ(delay)≈C load V dd
¿¿
¿𝑝𝑠 σ 2 ( 𝐼 𝑠 )+𝑝𝑚 σ 2 ( 𝐼𝑚 )+𝑝𝑚𝑝𝑠 [ μ ( 𝐼 𝑠 )− μ ( 𝐼𝑚 ) ] 2
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Plot of v/s
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= 0.3σ (delay )μ(delay )
𝜎 𝑠
𝜇𝑠
N = 10
N = 20
N = 30N = 40
N = 50
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3204/29/2014
Plot of v/s N
σ (delay )μ(delay )
N
0.2 0.4 0.60.8
0.9
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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters:
ION / IOFF tuning ratio Gate delay Noise Margin
Conclusion
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Noise Margin of CNTFET
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VIL and VIH
■ Substituting = Vin, , and
■ =
■ Differentiating with respect to Vin and substituting -1
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nFET
pFET
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For CNTFET, For CMOS,
VIL and VIH
NML = VIL - 0
NMH = VDD – VIH
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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters:
ION / IOFF tuning ratio Gate delay Noise Margin
Conclusion
04/29/2014 37
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CONCLUSION
■ Modeled count variations and hence device current as a probabilistic function
■ Studied the affect of these faults on tuning ratio and gate delay■ Inferred some design guidelines that could be used to judge the correctness
of a process■ Mathematically derived noise margin based on current equations – better
noise margin than a CMOS
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