probabilistic logic in cmos (pcmos) - rice universitykvp1/isscc-talk-noanimate.pdf · validation of...

Probabilistic Logic in

CMOS (PCMOS)‡

Krishna V. Palemϯ

Kenneth and Audrey Kennedy Professor

Rice University

Director, Institute for Sustainable Nanoelectronics (ISNE)

Nanyang Technological University(NTU), Singapore

PCMOS Fabrication and Measurement Collaborators:

Pinar Korkmaz*, Kiat-Seng Yeo §, Zhi-Hui Kong §

* Intel Corporation, §School of Electrical and Electronic Engineering, Nanyang Technological University‡ This work was supported in part by DARPA under seedling Contract F30602-02-2-0124 and an award from Intel Corporation to

Georgia Institute of Technology and by ISNE at NTU, SingaporeϮ This author was supported in part by the Moore distinguished faculty fellow program at the California Institute of Technology (2008)

and by the VISEN center at Rice University

* The work of this author was done as part of her PhD research at the Georgia Institute of Technology.

Outline

Device variations and perturbations

Current-day (deterministic) logics are no longer adequate

─ Designing computing systems using current day design methodologies based on traditional logics are no longer possible

The role of probability

Expressiveness and succinctness

─ Probabilistic Boolean Logic(PBL)

─ Probabilistic CMOS(PCMOS) Technology

The value of probabilistic design

Exploit property of PCMOS

In conjunction with value of information

─ Trade “quality” for “cost”

Future directions

2

Impact

A novel Probabilistic Boolean Logic(PBL)

Validation of PBL through 0.18 μm CHRT(Chartered Semiconductor)

technology fabrication.

Using PBL to implement a ultra-low energy Hyper-Encryption system

in CHRT

205 times more efficient through the energy-performance product metric

over a conventional design

Probabilistic arithmetic for ultra low energy signal processing

A FIR used in H-264 realized with half the energy and negligible

performance degradation

─ Simulated using HSPICE and software models

3

Outline




4

The Impediments to Moore’s Law

Decreasing feature size

Shrinking design margins

Static variations

Channel length, width

Threshold voltage

Interconnect (depth of focus)

Dopant fluctuation

Gate Length Variations*

Variations*

*Courtesy Dr Keith Bowman, Intel Corporation5

Dynamic Variations as Impediments to Moore’s Law

Supply voltage variations*

Temperature variations Other dynamic variations*

Thermal noise (amplified)

*Courtesy Dr Keith Bowman, Intel Corporation6

Abstractions have been used to design and automate the design of

complex systems

Abstraction in Design

Input Output

0 1

1 0

Transistors

Gates

Truth tables

Boolean

Formulae

cbay ).(

Logic circuits

Technology Structural Abstraction Behavioral

Abstraction

7

An Ideal CMOS Inverter

Corner case for an ideal deterministic inverter

If Vin < Vdd/2, Vout = Vdd

If Vin > Vdd/2, Vout = 0

Vdd

An Ideal Inverter

Vout

“Digital 0”

0 Vdd

“Digital 1”

Vdd

2

VoutVin

Corner case as a ―rule of thumb‖

•Is invariant as the output is observed over time

•Strictly depends on the input

8

Vdd

Vin

Vdd

Vin

Vdd

VinVin

Effect of Dynamic Variations on the “Rule of Thumb”

Input Output

0 1

1 0

Vdd

Vin

Vdd

Vin

Vdd

VinVin

Transistors

Gates

Truth tables

Boolean

Formulae

cbay ).(

Logic circuits

TechnologyStructural Abstraction

Behavioral

Abstraction

If Vin < Vdd/2, Vout = Vdd

If Vin > Vdd/2, Vout = 0Rule of Thumb

+

Noise

Input Output

0 1

1 0

Transistors

Gates

Truth tables

Boolean

Formulae

cbay ).(

Logic circuits

? ???

In the presence of dynamic variations

What is the rule of thumb in this case ?

9

Effect of Dynamic Variations on the “Rule of Thumb”(Contd.)

What is the rule of thumb ?

Therefore, a single rule of thumb with

two cases does not capture essential

information

At T1, If Vin + 0.40 <Vdd/2, Vout = Vdd

If Vin + 0.40 >Vdd/2, Vout = 0





Dropping many of these

cases can lead to loss of

essential information

T1 T2 T3

Inefficient/Incorrect design

Nois

e V

olta

ge

Noise from the Dynamic variations

Vdd

Vin

Vdd

Vin

Vdd

VinVin

+

Need to list many rules of thumb due to

―uncertainty‖ in the behavior of noise

10

How do we model this uncertain behavior?

Rule of thumb that allows a probabilistic parameter is a

path to succinctness, which is a central part of achieving

efficiency for human designers







Model noise succinctly as a

probabilistic parameter

Vdd

Vin

Vdd

Vin

Vdd

VinVin

+

Noise

Input Output

0 1

1 0

Transistors

Probabilistic

Gates

Truth tables

Probabilistic

Boolean

Formulae

cbay ).(

Probabilistic

Boolean Logic

circuits

X ?XX

Structural Abstraction

Thermal noise

Supply voltage

variations.

Temperature

Variations

11a





11b

Vdd

Vin

Vdd

Vin

Vdd

VinVin

+

Noise

Input Output

0 1

1 0

Transistors

Probabilistic

Gates

Truth tables

Probabilistic

Boolean

Formulae

cbay ).(

Probabilistic

Boolean Logic

circuits

X ?XX


Thermal noise

Supply voltage

variations.

Temperature

Variations

Influenced only by the statistics

of noise





11c

Vdd

Vin

Vdd

Vin

Vdd

VinVin

+

Noise

Input Output

0 1

1 0

Transistors

Probabilistic

Gates

Truth tables

Probabilistic

Boolean

Formulae

cbay ).(

Probabilistic

Boolean Logic

circuits

X ?XX


Thermal noise

Supply voltage

variations.

Temperature

Variations

Specification of PBL independent of the

particular physical perturbation

•Captured through the

probabilistic parameter

Outline







Lakshmi N. B. Chakrapani and Krishna V. Palem, "A Probabilistic Boolean Logic and its Meaning",

Rice University, Department of Computer Science Technical Report, No. TR08-05, June 2008.

Lakshmi N. B. Chakrapani, “Probabilistic Boolean Logic, Arithmetic and Architectures”,PhD Thesis,

Georgia Institute of Technology, August 2008.

12

Probabilistic Boolean Logic

Boolean Logic captures ―rules of thumb‖ on input and output behaviors

(functionality)

Probability captures ―uncertainty‖

Operators are “correct” with a probability p Operators are subscripted with p

“Incorrect” with probability (1-p)

Thermal noise, power supply noise and other dynamic perturbations Does not depend on the source of perturbation

Only on statistics of the source which determines p

x

x x x

x x ?

Λp (0≤p≤1)

Input Output

x Λp y

x y 0 1

0 0 p 1-p

0 1 p 1-p

1 0 p 1-p

1 1 1-p p

13

Each probabilistic Boolean formula

Is associated with a set of classical(deterministic) Boolean formulae

The probability that F behaves like one of these Boolean formula

The meaning of Probabilistic Boolean Logic

0

1

0

1

0

1

2/3

0

1

Formula F

Behaves like this 2 out of

3 times.

And like this 1 out of

3 times.Probabilistic Conjunction

Associated set of Boolean formulae

14

Considering More Complex Formulae For two probabilistic Boolean formulae F and G

If the underlying family of deterministic Boolean formulae F and G and their

probabilities are equivalent

─ F is equivalent to G

AND NOT P(OUT)

Correct Correct 2/3* 3/4

Wrong Wrong 1/3*1/4

Correct Wrong 2/3*1/4

Wrong Correct 1/3*3/4

7/12

5/12

OR P(OUT)

Correct 7/12

Wrong 5/12

2/33/4

Formula F7/12

Formula G

Probabilistic De-Morgan‟s Law

Consider the circuit representation of a probabilistic Boolean formula

1/2

1/6

1/4

1/121/12

1/2

1/6

1/4

The obvious simplification

15

Properties of PBL

Probabilistic Distributivity

X

y

z

p1p2

z

x

z

y

a

c

b

≡

Theorem: Probabilistic Boolean Logic is not distributive

Vp

Vp

Vp

x1 x2

x3

x4

( ( (x1Vp x2) Vp x3) Vp x4 ) ( (x1Vp x2) Vp ( x3Vp x4 ) )

Vp

x3

Vp

x1 x2

Vp

x4

Probabilistic Associativity

≡

Theorem: Probabilistic Boolean Logic is not associative

Identities Preserved

16

Outline








S. Cheemalavagu, P. Korkmaz, K. Palem, “Ultra low-energy computing via probabilistic algorithms and devices: CMOS device primitives and the energy-probability relationship,” Proc. Int. Conf. Solid State Devices and Materials (SSDM), 2004.

P. Korkmaz, B. Akgul, K. Palem, L. Chakrapani, “Advocating noise as an agent for ultra-low energy

computing: probabilistic complementary metal-oxide-semiconductor devices and their characteristics,”

Japanese J. of App. Phys., April 2006.

Pinar Korkmaz, "Probabilistic CMOS (PCMOS) in the Nanoelectronics Regime", PhD Thesis, Georgia

Institute of Technology, December 2007

17

Effect of Dynamic Variations on the “Rule of thumb”

Vdd

Vin

Vdd

Vin

Vdd

VinVin

+

NoiseInput Output

0 1

0 1-p p

1 p 1-p

Transistors

Probabilistic

Gates

Truth tables

Probabilistic

Boolean

Formulae

cbay qp ).(

Probabilistic

Logic circuits

X XXX

Consider the design flow again.


The previous sectionThis section

Technology Behavioral

Abstraction

What do we have so far ?

18

19a

CMOS Inverter as a Probabilistic Object Noise induced (energy) fluctuations

Thermal noise*

Derive probability of error as a function of supply voltage

and noise magnitude

Vout

“Digital 0”

Vdd

“Digital 1”

Vdd

2

*Projected to be a significant concern in future technology generations

*N. Sano, “Increasing importance of electronic thermal noise in sub-0.1m Si-MOSFETs,” IEICE Transactions on

Electronics, vol. E83-C, pp. 1203–1211, Aug.2000.

*L. B. Kish, “End of Moore‟s law: thermal (noise) death of integration in micro and nano electronics”, Phys. Letters A, Vol.

305, 2002.

*H. Li, J. Mundy, W. Paterson, D. Kazazis, A. Zaslavsky, R.I Bahar, “Thermally-induced soft errors in nanoscale CMOS

circuits”, IEEE International Symposium on Nanoscale Architectures, 2007, pages 62—69

0

VoutVin

Ideal case

Vdd

Thermal noise

Vn*

Thermal noise distribution

Probabilistic case

19b

CMOS Inverter as a Probabilistic Object Noise induced (energy) fluctuations

Thermal noise*

Derive probability of error as a function of supply voltage

and noise magnitude

Vout

“Digital 0”

Vdd

“Digital 1”

Vdd

2

Probability of 1

being treated as 0

*Projected to be a significant concern in future technology generations

*N. Sano, “Increasing importance of electronic thermal noise in sub-0.1m Si-MOSFETs,” IEICE Transactions on

Electronics, vol. E83-C, pp. 1203–1211, Aug.2000.

*L. B. Kish, “End of Moore‟s law: thermal (noise) death of integration in micro and nano electronics”, Phys. Letters A, Vol.

305, 2002.

*H. Li, J. Mundy, W. Paterson, D. Kazazis, A. Zaslavsky, R.I Bahar, “Thermally-induced soft errors in nanoscale CMOS

circuits”, IEEE International Symposium on Nanoscale Architectures, 2007, pages 62—69

0

VoutVin

Vdd

Thermal noise

Vn*

Sum of areas

is equal to

the probability

of error = p(say)

22erf

2

1

2

11 ddV

ppProbability of correctness

Probability of 0

being treated as 1

Validation through fabrication of a CMOS inverter

CMOS 0.18 m 1-Poly 6-Metal technology from Chartered

Semiconductor (CHRT)

Fabricated noise source: different values of resistors (60k, 600k, and

2M ohm)

Measurement methodology

Agilent Technologies IC-CAP device modeling software

HP 4142 source monitor unit

Probabilistic CMOS inverter

output

R Output

swing

Area

(m2)

60K 1.4 V 645

600K 1.7 V 6225

2M 1.8 V 12403

For all three cases:

P= 0.5

Power = 665 uW at VDD = 1.8 V and CL = 20 pF

20

Varying probability of correctness

Vout

V20

Reduce error probability by

increasing Vdd

321 VVV

321ˆˆˆ ppp

Vout

V10

Vout

V30

Can we control the probability of error ?

p1

p3

p2

Law of Invariance: NSR uniquely determines the probability

parameter p independent of the Moore‟s Law technology generation

NSR and p relationship from fabricated data

0

0.5

1

1.5

2

0.6 0.7 0.8 0.9 1pN

SR

Meas. Sim.

AMI 0.5 0.5

(yellow)

TSMC 0.25 0.25

IBM 65nm, 90nm

21

Outline




The role of probability in device abstraction

Expressive and succinct





22

List L of length , of n-bit Boolean functions

─ Such that Fi(0n) ≠ Fi(0

n-11), where (only last bit is different)

Encoded bit c = Fk(0n-1m) and transmit c, L (m is the last bit)

Choose the kth function Fk randomly

─ Shared secret key k, 1 k , exists between both A & B

Efficient Designs Using Properties of PBL

Yan Zong Ding, Michael O. Rabin, "Hyper-Encryption and Everlasting Security", Lecture Notes In Computer Science; Vol. 2285, Proceedings of the 19th Annual Symposium on Theoretical Aspects of Computer Science, 2002

m

k

List of Boolean functions L

cA

BAttacker can listen to traffic

Only B knows which

function A used to

generate c from m

most resource-

intensive step of

the algorithm

L

cSender

Receivern-ary gate00

0

One bit message m to be transmitted from A(sender) to B(receiver)

Li

F

Compute Fk(0n), Fk(0

n-11) compare with c

─ Retrieve m

Encryption framework

Sender

Receiver

Sender &

Receiver

23


Compressing the Size of the Circuit through the Power of PBL

24a

can be made less

resource-intensive

using PBL



α Boolean

functions

0

0

0

00

A single PBL formula can be a compact representation of a family of Boolean functions



24b

can be made less

resource-intensive

using PBL



0

0

0

00

A single PBL formula can be a compact representation of a family of Boolean functions

0

0

0

0

0

A useful transformation:

A circuit with probabilistic gates can be replaced with a family

of probabilistic inverters as inputs to a deterministic circuit.



can be made less

resource-intensive

using PBL



0

0

0

0

0

1

01

10

1

11

11

0

00

11

A deterministic circuit with many random inputs

α inputs

A deterministic circuit with

probabilistic inverters as its inputs

25

The Hyper-Encryption Circuit

Series of

2n-to-1

Multiplexers

Probabilistic

Inverters

0

0

0

m

Tree of XOR gatesEncoding the „m‟ bit

c

Basic blocks for the hyper-encryption algorithm using Probabilistic inverters

0

0

0

0

0

Secret Key „k‟

Different sets

of inverters

Depending on the key choose an appropriate set

of inverters to the tree of XOR gates.

Corresponds to a subset

26

32 Probabilistic Inverters as

Random Number Generators

Implementing Hyper-encryption

Output = one encrypted bit per cycle

Technology Used: CMOS 0.18 m, 1-Poly 6-Metal technology from Chartered Semiconductor

Block B

64 5-bit

Serial to

parallel

shift

registers

(secret

Key)

32-to-1

Multiplexer

to XOR

32 bits

Other 63

32-to-1

Multiplexers

5 bits

64-bit XORto XOR

32 PCMOS Inverters

Block B

Probabilistic Inverter = Noise Source

+Noise Amplifier + CMOS inverter

m

27

Value of Probabilistic Design

28a

PRNG based: (Energy * Performance )

Gain = PCMOS based: (Energy * Performance )

≥ ~ 10X*

*Simulated using TSMC 250nm technologyFor producing one

encrypted bit

*Preliminary measurement results

≥ ~ 205X*

Value of Probabilistic Design

28b

PRNG based: (Energy * Performance )

Gain = PCMOS based: (Energy * Performance )

A1 A2

B1 B2

Methodology

A1 A2 B1 B2

9.56 x10-8 Joules 3.13x10-6 sec 3.664 x 10-9 Joules 4x10-7 sec

PRNG + HE Block

Simulated =0

• Everything else measured

For producing one

encrypted bit

Outline












29

Trading probability of correctness

Vout

Vdd20

Reduce error probability by

increasing Vdd

321 dddddd VVV

ppp321

Vout

Vdd10

Vout

Vdd30

Can we control the probability of error ?

p1

p3

p2

Does it cost us ? If so, how much ?

30

The E-p relationship

Reduce error probability

through higher Vdd 321 dddddd VVV

2

2

1ddCVE

321 EEE

This relationship between Energy consumption and the probability of correctness can be

summarized as follows:

The First Law of PCMOS: In any technology generation (C) and constant noise magnitude (σ) the

switching energy (E) grows with p. The order of growth of E in p is asymptotically bounded below by an

exponential in p

Pinar Korkmaz, Bilge E. S. Akgul, Krishna V. Palem and Lakshmi N. Chakrapani, Advocating Noise as an Agent for Ultra Low-

Energy Computing: Probabilistic CMOS Devices and Their Characteristics Japanese Journal of Applied Physics, SSDM Special Issue

Part 1, April 2006.

Stein, K.-U., “Noise-induced error rate as a limiting factor for energy per operation in digital ICs,” IEEE J. Solid-State Circuits, vol. 12,

pp. 527–530, Oct. 1977.

ppp321

C

R

Vdd

Thermal noise

Vn*

VoutVin

22

2ddsw

dd

1p2Cσ4E

CV2

1EE

22

V

2

1

2

1p

inverf

erf

31

0

2

4

6

8

10

12

14

16

18

0.7 0.75 0.8 0.85 0.9 0.95 1

En

erg

y p

er

sw

itch

ing

ste

p,

fJ

p

CHRT 180 nm-analytical

The Analytical E-p relationship

Use the analytical model to develop a relationship between Energy and Probability of correctness

Energy-probability of correctness relationship (E-p) for an inverter

in 180nm CHRT technology

E(fJ) p

1 0.84

2.2 0.9

4.5 0.98

A “Rule of thumb”

supporting a tradeoff

32

0

2

4

6

8

10

12

14

16

18

20

0.773 0.841 0.933 0.977 0.994 0.998 0.999 0.999 1

En

erg

y p

er

sw

itc

hin

g s

tep

(f

J)

p

180nm-Analytical

180nm-Simulated

PTM 32nm Analytical

PTM 32-nm Simulated

Validation of the First Law

Energy-probability of correctness relationship (E-p) for an inverter in CHRT 0.18m technology and Arizona

State University PTM 32 nm technology

1. CMOS 0.18 m 1-Poly 6-Metal

technology from Chartered

Semiconductor (CHRT)

2. Supply voltage is varied from 0.3V

to 1.8V

3. Inverter Load Capacitance = 286fF

p Energy Vdd

0.999 11 1.0

0.976 1.61 0.4

0.889 0.9 0.3

33

Modeling the Filtering Effect of the Noise by

the PCMOS Inverter

When the sampling frequency (or the maximum frequency component)

of the noise > the maximum switching frequency of the inverter

Noise is filtered by the inverter

The analytically found p values are smaller than those that of the simulation results

C

Vdd

Vout*

Vin

Noise

Vn

eq

ddVerfp

225.05.0

22erf

2

1

2

11 ddV

ppBasic Model

5.0

21

thdd

ddnneq

VV

VKTKT

The new model

K1, K2, : parameters fitted using simulations

Tn: maximum frequency component of noise

Pinar Korkmaz, Bilge E. S. Akgul and Krishna V. Palem ,Analysis of Probability and Energy of Nanometre CMOS Circuits in

Presence of Noise, Electronics Letters, Vol. 43, Issue 17, Aug. 2007.

34

Extending To Other Gates

The Energy-probability relationship of a CMOS-based switch can be

extended

Consider XOR gate

Measured, Modeled Energy-probability of correctness relationship for a XOR gate

Vdd P

0.4 0.854

0.8 0.975

1.2 0.998

35

Effect of Parameter Variations

Effect of channel length variation

10% variation

0

5

10

15

20

25

0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05p

En

erg

y p

er

sw

itch

ing

ste

p,

fJ

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0.18u-L

0.18u-L+10%

32nm-L

32nm-L+10%

Energy-probability of correctness relationship (E-p) for an inverter

for varying channel lengths

36

Outline












• The value of probabilistic design

Jason George, Bo Marr, Bilge E. S. Akgul and Krishna V. Palem, “Probabilistic Arithmetic and Energy Efficient Embedded Signal Processing” Proceedings of the Intl. Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), Seoul, Korea, October 23-25, 2006

Lakshmi N. B. Chakrapani, Kirthi Krishna, Lingamneni Avinash, Jason George and Krishna Palem, "Highly Energy and Performance Efficient Embedded Computing through Approximately Correct Arithmetic", International conference on Compilers, Architectures, and Synthesis for Embedded Systems, 2008.

Lakshmi N. B. Chakrapani, and Krishna Palem, “Probabilistic Arithmetic", Rice University, Department of Computer Science Technical Report, TR08-85, October 2008.

Best Paper

CASES 2006

37


Image Processing

FFT

Building Blocks delay adder multiplier

Primitives FIR

Applications Video decoding

Switches and basic gatesDevices

f(x,y)

9

18

Lossy Adder

a

b

carry-in

a

b

carry-in

sum

carry-

out

p

p

Even a slight sacrifice of

probability of correctness

yields energy savings

p 0.99 to p 0.85 for

XOR gate

─ 10.6x reduction in

energy

Use the First law to guide

the tradeoff

10 117 8

38

H.264 Image Decoding using Probabilistic Design

Uniform voltage scaling

AdderS11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

MSB LSB

Probabilistic Biased Voltage Scaling or

BiVoS

Vdd

Bit E

rro

r R

ate

11 10 9 8 7 6 5 4 3 2 1 0

Bit Position

11 10 9 8 7 6 5 4 3 2 1 0

Bit Position

2.5

0

0

0.18

0.9

Normal operation

Uniform Voltage Scaling

Normal operation

BIVOS

BIVOS

FIR

Adders

MultipliersFIR

123

39

Outline












• The value of probabilistic design

Future Directions

40

Probabilistic Design for Ultra-low energy devices

Mobile Embedded

Devices

Education Medical Prosthetics

Cell Phone “Lite”

Collaborators:

1. Al Barr, Caltech

Auditory and Visual

Prosthetic Design

Collaborators:

1. Al Barr, Caltech

2. Danny Petrasek,Caltech

A low power solar powered

visual device for educating in

rural areas with limited access

to electricity

Collaborators:

1. Jayanthi Sivaswamy

2. NGO - VIDAL

Collaborators:

1. Yeo Kiat Seng, NTU

2. Vincent Mooney, NTU

Perceptual

limitations

Perception based

design with a

neuro-biological

basis.

High-Fidelity Video

and Graphics

41

Putting It All Together - An Architectural Vision

Substantial within-die variation is

expected in future architectures

Threshold Vth voltage variation is an

example

─ Variation is known only post manufacturing

─ Could result in upto 30% variation in speed1

Ameliorate the effects of variations

Design independent techniques (e.g Vth

variations)

─ Test “blocks” for speed and leakage

• Use bidirectional adaptive body-biasing circuits to

compensate2

Design specific techniques (e.g ripple carry

adder)

─ Use faster blocks for most significant bits

What is an architecture amenable to such

techniques ?

1S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Kesha varzi, and V. De. “Parameter variations and impact on circuits

and microarchitecture.” In ACM/IEEE 40th Design Automation Conference (DAC-03), pages 338–342, Anaheim, CA, June

2-6 2003.

2Tschanz, J.W.; Kao, J.T.; Narendra, S.G.; Nair, R.; Antoniadis, D.A.; Chandrakasan, A.P.; De, V. “Adaptive body bias

for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage”, In IEEE

Journal of Solid State Circuits, pages 1396–1402, November 2002.

Block 1 Block 2 Block 3

Storage for

variation

information

Configurable Interconnect

Logic blocks

which comprise

a FIR filter

Slowest Fastest Slow

Blocks are

tested to

determine their

behaviors

Store

information

about

variation

Use

information for

design

independent

techniques

like adaptive

body biasing

Use

information for

design

dependent

techniques

like mapping

design on to

reconfigurable

fabric

Reconfigured

chain of blocks to

implement FIR

Least

SignificantMost

Significant

Collaborators:

1. Jim Meindl, Georgia Tech

2. Raghu Murali, Georgia Tech

42

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