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Principles Of Principles Of Digital Digital Design Design Chapter 3 Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology ASICs ASICs Gate Arrays Gate Arrays

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Page 1: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Principles OfPrinciples Of

Digital DesignDigital Design

Chapter 3Chapter 3

Boolean Algebra and Logic Design

Boolean Algebra Logic Gates Digital Design Implementation Technology

ASICsASICsGate ArraysGate Arrays

Page 2: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine2

A set is a collection of objects with a common property IfIf S S is a set and is a set and x x is a member of the set is a member of the set SS, then , then x x S S

A = A = {1, 2, 3, 4} {1, 2, 3, 4} denotes the set denotes the set AA, whose elements are , whose elements are 1, 2, 3, 41, 2, 3, 4

A binary operator on a set S is a rule that assigns to each pair of elements in S another element that is in S

Axioms are assumption that are valid without proof

Basic Algebraic PropertiesBasic Algebraic Properties

Page 3: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine3

Closure A setA set S S is closed with respect to a binary operator is closed with respect to a binary operator ●● iff for all iff for all x, yx, y SS, ,

((x x ●● y y)) SS ZZ++ == {1, 2, 3, …}{1, 2, 3, …} is closed to addition, because positive numbers are in is closed to addition, because positive numbers are in ZZ++

Associativity A binary operator A binary operator ● defined on a set ● defined on a set S S is associative iff for allis associative iff for all

x, y, zx, y, z SS((x x yy) ) z = x z = x ( (y y zz))

Identity Element A set A set S S has an identity element has an identity element e e for every for every xx SS

e e x = x x = x e = xe = xx +x + 0 0 = = 0 + 0 + x = xx = x

Examples of AxiomsExamples of Axioms

Page 4: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine4

Commutativity A binary operator A binary operator ● is commutative ● is commutative iff for all iff for all x, yx, y SS

x x yy = y = y xx

Inverse Element A A set set S S has an inverse iff for every has an inverse iff for every x x SS , there exists an , there exists an

element element y y SS such thatsuch that

x x yy = e= e

Distributivity If If ● and □ are two binary operators on a ● and □ are two binary operators on a set set SS, , ●● is said to be is said to be

distributive over distributive over □□ if, for all if, for all x, y, zx, y, z SSx x ( (yy □□ zz)) = = ((x x yy)) □□ ( (x x zz))

Examples of AxiomsExamples of Axioms

Page 5: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine5

Axiom 1 (Closure Property): (a) B is closed with respect to the operator +; (b) B is also closed with respect to the operator ∙

Axiom 2 (Identity Element): (a) B has an identity element with respect to +, designated by 0; (b) B also has an identity element with respect ∙ , designated by 1

Axiom 3 (Commutativity Property): (a) B is commutative with respect to +; (b) B is also commutative with respect to ∙

Axiom 4 (Distributivity Property): (a) The operator ∙ is distributive over +; (b) similarly, the operator + is distributive over ∙

Axiom 5 (Complement Element): For every x B, there exists an element x′ B such that (a) x + x′ = 1 and (b) x ∙ x′ = 0 This second element x′, is called the complement of x

Axiom 6 (Lower Cardinality Bound): There are at least two elements x, y B such that x y

Axiomatic Definition of Boolean AlgebraAxiomatic Definition of Boolean AlgebraBoolean algebra is a set of elements Boolean algebra is a set of elements BB with two binary operators, with two binary operators, + + and and ∙∙, which , which satisfies the following six axioms:satisfies the following six axioms:

Page 6: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine6

In ordinary algebra, + is not distributive ∙

Boolean algebra does not have inverses with respect to + and ∙ ; therefore, there are no subtraction or division operations in Boolean algebra

Complements are available in Boolean algebra, but not in ordinary algebra

Boolean algebra applies to a finite set of elements, whereas ordinary algebra would apply to the infinite sets of real numbers

The definition above for Boolean algebra does not include associativity, since it can be derived from the other axioms

Axiomatic Definition of Boolean AlgebraAxiomatic Definition of Boolean Algebra

Differences between Boolean algebra and ordinary algebraDifferences between Boolean algebra and ordinary algebra

Page 7: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine7

Two-valued Boolean AlgebraTwo-valued Boolean Algebra

Set B has two elements: 0 and 1

Algebra has two operators: AND and OR

x y x ∙ y

0 0 0

0 1 0

1 0 0

1 1 1

AND Operator

x y x + y

0 0 0

0 1 1

1 0 1

1 1 1

OR Operator

Page 8: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine8

Two-valued Boolean AlgebraTwo-valued Boolean Algebra

Axiom 1 (Closure Property): Closure is evident in the AND/OR tables, since the result of each operation is an element of B.

Axiom 2 (Identity Element): The identity elements in this algebra are 0 for the operator + and 1 for the operator ∙. From the AND/OR tables, we see that:0 + 0 = 0, 0 + 0 = 0, andand 0 + 1 = 1 + 0 = 1 0 + 1 = 1 + 0 = 11 1 ∙∙ 1 = 1, 1 = 1, andand 1 1 ∙∙ 0 = 0 0 = 0 ∙∙ 1 = 0 1 = 0

Axiom 3 (Commutativity Property): The commutativity laws follow from the symmetry of the operator tables.

Two-valued Boolean algebra satisfies Huntington axiomsTwo-valued Boolean algebra satisfies Huntington axioms

Page 9: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine9

Two-valued Boolean AlgebraTwo-valued Boolean Algebra

Axiom 4 (Distributivity): The distributivity of this algebra can be demonstrated by checking both sides of the equation.

x y z y + z x ∙ (y + z) xy xz (xy) + (xz)

0 0 0 0 0 0 0 0

0 0 1 1 0 0 0 0

0 1 0 1 0 0 0 0

0 1 1 1 0 0 0 0

1 0 0 0 0 0 0 0

1 0 1 1 1 0 1 1

1 1 0 1 1 1 0 1

1 1 1 1 1 1 1 1

Proof of distributivity of ∙

x y z yz x + (yz) x + y x + z (x + y)(x + z)

0 0 0 0 0 0 0 0

0 0 1 0 0 0 1 0

0 1 0 0 0 1 0 0

0 1 1 1 1 1 1 1

1 0 0 0 1 1 1 1

1 0 1 0 1 1 1 1

1 1 0 0 1 1 1 1

1 1 1 1 1 1 1 1

Proof of distributivity of +

x ∙ (y + z) = (x ∙ y) + (x ∙ z) x + (y ∙ z) = (x + y)(x + z).

Page 10: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine10

Two-valued Boolean AlgebraTwo-valued Boolean Algebra

Axiom 5 (Complement): 0 and 1 are complements of each other, since 0 + 0′ = 0 + 1 = 1 and 1 + 1′ = 1 + 0 = 1; furthermore,0 ∙ 0′ = 0 ∙ 1 = 0 and 1 ∙ 1′ = 1 ∙ 0 = 0.

Axiom 6 (Cardinality): The cardinality axiom is satisfied, since this two-valued Boolean algebra has two distinct elements, 1 and 0, and 1 0.

x x′

0 1

1 0

NOT Operator

Page 11: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine11

Boolean Operator ProcedureBoolean Operator Procedure

Boolean operators are applied in the following order.

ParenthesesParentheses ( )( ) NOTNOT ′′ ANDAND ∙∙ OROR ++

Example: Evaluate expressionExample: Evaluate expression ((xx + + xyxy))′′ for for xx = 1 = 1 andand yy = 0 = 0::

(1 + 1(1 + 1∙∙0)0)′ = ′ = (1 + 0)(1 + 0)′ = ′ = (1)(1)′ = 0′ = 0

Page 12: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine12

Duality PrincipleDuality PrincipleAny algebraic expression derived from axioms stays valid

when OROR and and ANDAND 00 and and 11

are interchanged.

Example: Example:

IfIf

XX + 1 + 1 = 1 = 1

thenthen

X X ∙ 0 = 0∙ 0 = 0

by the duality principleby the duality principle

Page 13: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine13

Theorem of Boolean AlgebraTheorem of Boolean Algebra

Theorem 1 (a) x + x = x

(Idempotency) (b) xx = x

Theorem 2 (a) x + 1 = 1

(b) x ∙ 0 = 0

Theorem 3 (a) yx + x = x

(Absorption) (b) (y + x)x = x

Theorem 4 (x′)′ = x

(Involution)

Theorem 5 (a) (x + y) + z = x + (y + z)

(Associativity) (b) x(yz) = (xy)z

Theorem 6 (a) (x + y)′ = x′y′

(De Morgan’s Law) (b) (xy)′ = x′ + y′

Basic Theorems of Boolean Algebra

Page 14: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine14

Theorem Theorem Proofs in Boolean AlgebraProofs in Boolean Algebra Theorems can be proved by transformations based on axioms

and theorems

Duality

Example: Example: Theorem 1(a) Idempotency:Theorem 1(a) Idempotency: xx + + x = x = xx..

Proof:Proof:x + xx + x == ((x + xx + x) ∙ 1) ∙ 1 by identity (Ax. 2b)by identity (Ax. 2b)

== ((x + xx + x) () (x + x′x + x′)) by complement (Ax. 5a)by complement (Ax. 5a)== x + xx′x + xx′ by distributivity (Ax. 4b)by distributivity (Ax. 4b)== x + x + 00 by complement (Ax. 5b)by complement (Ax. 5b)== xx by identity (Ax. 2a)by identity (Ax. 2a)

Example: Example: Theorem 1(b) Idempotency:Theorem 1(b) Idempotency: xx ∙∙ x = x = xx..

Proof:Proof:x + xx + x == xx by Theorem 1(a)by Theorem 1(a) x ∙ xx ∙ x == xx by Duality principleby Duality principle

Page 15: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine15

Theorem Theorem Proofs in Boolean AlgebraProofs in Boolean Algebra

Checking theorems for every combinations of variable valueExample: Example:

Theorem 6(a) DeMorgan’s Law: Theorem 6(a) DeMorgan’s Law: ((xx + + yy))′ = ′ = x′y′x′y′

x y x + y (x + y)′ x′ y′ x′y′

0 0 0 1 1 1 1

0 1 1 0 1 0 0

1 0 1 0 0 1 0

1 1 1 0 0 0 0

Proof of Demorgan’s First Theorem

Page 16: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine16

Note 1: When we evaluate Boolean expressions, we must follow a Note 1: When we evaluate Boolean expressions, we must follow a specific order of operations, namely, (1) parentheses, (2) NOT, (3) AND, specific order of operations, namely, (1) parentheses, (2) NOT, (3) AND, (4) OR.(4) OR.

Note 2: A primed or unprimed variable is usually called a literal.Note 2: A primed or unprimed variable is usually called a literal.

Boolean FunctionsBoolean Functions

Algebraic expression, which are formed from binary variables and Boolean operators AND, OR and NOT.

Example: Example: FF11 = = xyxy + + xyxy′′zz + + x′yzx′yz

This function would be equal to This function would be equal to 1 1 if if x x == 1 1 andand y y == 11, or, orif if x x == 1 1 andand y y == 0 0 andand z z == 11, or, or if if x x == 0 0 andand y y == 1 1 andand z z == 11;;

otherwise, otherwise, FF11 = 0 = 0..

Page 17: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine17

Boolean FunctionsBoolean Functions

Truth tables which list the functional value for all combinations of variable values.

Example: Example: FF11 = = xyxy + + xyxy′′zz + + x′yzx′yz

Row Numbers

Variable Values

Function Values

x y z F1

0 0 0 0 0

1 0 0 1 0

2 0 1 0 0

3 0 1 1 1

4 1 0 0 0

5 1 0 1 1

6 1 1 0 1

7 1 1 1 1

Page 18: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine18

Complement of a FunctionComplement of a FunctionComplement of function F is function F′, where F′ can be

obtained by: Interchanging Interchanging 00 and and 11 in the truth table.in the truth table.

Row Numbers

Variable Values

Function Values

x y z F1 F1′

0 0 0 0 0 1

1 0 0 1 0 1

2 0 1 0 0 1

3 0 1 1 1 0

4 1 0 0 0 1

5 1 0 1 1 0

6 1 1 0 1 0

7 1 1 1 1 0

Example: Example: FF11 = = xyxy + + xyxy′′zz + + x′yzx′yz

Page 19: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine19

Complement of a FunctionComplement of a Function

Complement of function F is function F′, where F′ can be obtained by:Repeatedly applying DeMorgan’s theoremsRepeatedly applying DeMorgan’s theorems..

Duality PrincipleDuality Principle

Example:Example: FF11′′ == ((xyxy + xy′z + x′yz + xy′z + x′yz))′′ by definition of by definition of

FF== ((xyxy))′ ′ ((xy′zxy′z))′ ′ ((x′yzx′yz))′′ by DeMorgan’s by DeMorgan’s

Th.Th.== ((xx′′ + y + y′′)()(x′ + y + z′x′ + y + z′)()(x + y′ + z′x + y′ + z′)) by DeMorgan’s by DeMorgan’s

Th.Th.Example:Example: FF11 == ((x x ∙ ∙ yy)) + + ((x ∙ y′ ∙ zx ∙ y′ ∙ z)) + + ((x′ ∙ y ∙ zx′ ∙ y ∙ z))

FF11′′ == ((xx′′ + y + y′′) ) ∙ ∙ ((x′ + y + z′x′ + y + z′) ) ∙ ∙ ( (x + y′ + z′x + y′ + z′))

Page 20: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine20

Graphic Representation of Graphic Representation of Boolean FunctionsBoolean Functions

′ ′

++

++

++

+

′ ′ ′

∙∙

∙∙

AND-OR Expression OR-AND Expression

FF size size == 5 ANDs5 ANDs2 ORs2 ORs2 NOTs2 NOTs

FF size size == 2 ANDs2 ANDs5 ORs5 ORs4 NOTs4 NOTs

zz

FF FF

FF′′

yyxx zzyyxx

Two different expressions have different sizes

Page 21: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine21

We can prove expression equivalence by algebraic manipulation in which each transformation uses an axiom or a theorem of Boolean algebra.

Expression EquivalenceExpression Equivalence

xy + xy′z + x′yz requires 5 ANDs 2 ORs 2 NOTs

xy + xz + yz requires 3 ANDs 2 ORs

Difference: 2 ANDs and 2 NOTs

Example:Example: FF11 == xyxy + xy′z + x′yz + xy′z + x′yz

== xyxy + xz + yz + xz + yzProof:Proof: xyxy + xy′z + x′yz + xy′z + x′yz == xyxy + xyz + xy′z + x′yz + xyz + xy′z + x′yz by absorptionby absorption

== xyxy + x + x((y + y′y + y′))z + xz + x′yz′yz by distributivityby distributivity == xyxy + x + x11z z

+ x′yz+ x′yz by complementby complement == xyxy + xz + xz

+ x′yz+ x′yz by identity by identity == xyxy + xyz + xyz

+ xz + x′yz+ xz + x′yz by absorption by absorption == xyxy + xz + xz

+ + ((x + x′x + x′))yzyz by distributivityby distributivity == xyxy + xz + xz

+ + 11yzyz by complementby complement == xyxy + xz + xz

+ yz+ yz by identityby identity

Page 22: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine22

MintermsMinterms

Minterms for Three Binary Variables

Minterm definitionIf If ii = = bbnn – 1 – 1……bb00 is a binary number between is a binary number between 00 and and 22nn – 1 – 1, then a minterm , then a minterm

of of nn variables variables xxn n – 1– 1, , xxnn – 2 – 2…,…,xx00, could be represented as:, could be represented as:

mmii ((xxn n – 1– 1, , xxnn – 2 – 2…,…,xx00) = ) = yynn – 1 – 1……yy00

where for all where for all kk such that such that 0 0 ≤ ≤ kk ≤ ≤ n – n – 11,,

yykk == {{xxkk ifif bbk k = =

11xxkk′′ ifif bbk k = =

00

x y z Minterms Designation

0 0 0 x′y′z′ m0

0 0 1 x′y′z m1

0 1 0 x′yz′ m2

0 1 1 x′yz m3

1 0 0 xy′z′ m4

1 0 1 xy′z m5

1 1 0 xyz′ m6

1 1 1 xyz m7

Page 23: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine23

Sum-of-MintermsSum-of-MintermsAny Boolean function can be expressed as a sum (OR) of

its 1-minterms:F(list of variables) = Σ(list of 1-minterm indices)

Row Numbers

Variable Values

Function Values

x y z F1 F1′

0 0 0 0 0 1

1 0 0 1 0 1

2 0 1 0 0 1

3 0 1 1 1 0

4 1 0 0 0 1

5 1 0 1 1 0

6 1 1 0 1 0

7 1 1 1 1 0

Example: Example:

Equation TableF1 = xy + xy′z + x′yz

F1′ = (x′ + y′)(x′ + y + z′)(x + y′ + z′)

FF11((x, y, zx, y, z)) == ΣΣ(3, 5, 6, 7) (3, 5, 6, 7)

== mm33 + + mm55 + + mm66 + + mm77

== x′yz + xy′z + xyz′ + xyzx′yz + xy′z + xyz′ + xyz

FF11′′((x, y, zx, y, z)) == ΣΣ(0(0, 1, 2, 4), 1, 2, 4)

== mm00 + + mm11 + + mm22 + + mm44

== x′y′z′ + x′y′z + x′yz′ + xyx′y′z′ + x′y′z + x′yz′ + xy ′′z′z′

Page 24: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine24

Expansion to Sum-of-MintermsExpansion to Sum-of-Minterms

Any Boolean function can be expanded into a sum-of-minterms form be expanding each term with (x + x′) for each missing variable x.

Example:Example: F F = = x + yzx + yz

== xx((y + y′y + y′)()(z + z′z + z′)) + + ((x + x′x + x′))yz yz == xyz + xy′z + xyz′ + xy′z′ + xyz + x′yzxyz + xy′z + xyz′ + xy′z′ + xyz + x′yz

After removing duplicates and rearranging the minterms in After removing duplicates and rearranging the minterms in ascending order:ascending order:

F F = = x′yzx′yz + xy′z′ + xy′z′ + + xy′z + xyz′ + xyzxy′z + xyz′ + xyz== mm33 + m + m44 + m + m55 + m + m66 + m + m77

== ΣΣ(3, 4, 5, 6, 7)(3, 4, 5, 6, 7)

Page 25: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine25

Conversion to Sum-of-MintermsConversion to Sum-of-Minterms

FF = = mm33 + + mm44 + + mm55 + + mm66 + + mm77

Each Boolean function can be converted into a sum-of-minterms form by generating the truth table and identifying 1-minterms.

Example: Example: FF = = xx + + yzyz

x y z F

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 1

Page 26: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine26

MaxtermsMaxterms

Maxterms can be defined as the complement of minterms:MMii == mmii′′ and and MMii′′ = = mmii

Maxterms for Three Binary Variables

x y z Maxterms Designation

0 0 0 x + y + z M0

0 0 1 x + y + z′ M1

0 1 0 x + y′ + z M2

0 1 1 x + y′ + z′ M3

1 0 0 x′ + y + z M4

1 0 1 x′ + y + z′ M5

1 1 0 x′ + y′ + z M6

1 1 1 x′ + y′ + z′ M7

Page 27: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine27

Product-of-MaxtermsProduct-of-MaxtermsAny Boolean function can be expressed as a product (AND)

of its 0-maxterms:F(list of variables) = Π(list of 0-maxterm indices)

Row Numbers

Variable Values

Function Values

x y z F1 F1′

0 0 0 0 0 1

1 0 0 1 0 1

2 0 1 0 0 1

3 0 1 1 1 0

4 1 0 0 0 1

5 1 0 1 1 0

6 1 1 0 1 0

7 1 1 1 1 0

Example: Example:

Equation TableF1 = xy + xy′z + x′yz

F1′ = (x′ + y′)(x′ + y + z′)(x + y′ + z′)

FF11((x, y, zx, y, z)) == ΠΠ(0(0, 1, 2, 4), 1, 2, 4)

== MM0 0 MM1 1 MM2 2 MM44

== ((x + y + zx + y + z))((x + y + z′x + y + z′))((x + y′ + zx + y′ + z))((x′ + y + zx′ + y + z))

FF11′′((x, y, zx, y, z)) == ΠΠ(3, 5, 6, 7)(3, 5, 6, 7)

== MM3 3 MM5 5 MM6 6 MM77

== ((x + y′ + z′x + y′ + z′))((x′x′ + y + z′+ y + z′))((x′ + y′ + zx′ + y′ + z))((x′ + y′ + z′x′ + y′ + z′))

Product-of-maxterms can also be obtained by Product-of-maxterms can also be obtained by complementing the sum-of-minterms complementing the sum-of-minterms

((FF11))′′ == ((x′yz + xy′z + xyz′ + xyzx′yz + xy′z + xyz′ + xyz))′′

== ((x + y′ + z′x + y′ + z′))((x′x′ + y + z′+ y + z′))((x′ + y′ + zx′ + y′ + z))((x′ + y′ + z′x′ + y′ + z′))== MM3 3 MM5 5 MM6 6 MM77

FF11 == ((FF11′′))′′

== ((x′y′z′ + x′y′z + x′yz′ + xyz′x′y′z′ + x′y′z + x′yz′ + xyz′))′′== ((x + y + zx + y + z))((x + y + z′x + y + z′))((x + y′ + zx + y′ + z))((x′ + y′ + zx′ + y′ + z))== MM0 0 MM1 1 MM2 2 MM4 4

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Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine28

Expansion to Product-of-MaxtermsExpansion to Product-of-Maxterms Any Boolean function can be expanded into a product-of-maxterms

form be expanding each term with xx′ for each missing variable x.Example: Example: ConvertConvert

F F == x′y′ + xzx′y′ + xz== ((x′y′ + xx′y′ + x)()(x′y′ + zx′y′ + z))== ((x′ + xx′ + x)()(y′ + xy′ + x)()(x′ + zx′ + z)()(y′ + zy′ + z))== ((xx ++ y′y′)()(x′ + zx′ + z)()(y′ + zy′ + z))

ExpandExpandxx ++ y′y′ == x + y′x + y′ + + zz′zz′ == ((x + y′x + y′ + + zz)()(x + y′x + y′ + + z′z′))x′ + zx′ + z == x′ + z + yy′x′ + z + yy′ == ((x′ + y x′ + y + + zz)()(x′ + y′x′ + y′ + + zz))y′ + zy′ + z == y′ + z + xx′y′ + z + xx′ == ((x + y′ x + y′ + + zz)()(x′ + y′x′ + y′ + + zz))

CombineCombineFF == ((x + y′x + y′ + + zz)()(x + y′x + y′ + + z′z′)()(x′ + y x′ + y + + zz)()(x′ + y′ x′ + y′ + + zz))

== MM2 2 MM3 3 MM4 4 MM66 == (2, 3, 4, 6)(2, 3, 4, 6)

missingmissingxxii

missingmissingyyii

missingmissingccii

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Conversion to Product-of-Maxterms Conversion to Product-of-Maxterms Any Boolean expression can be converted into a sum-of-

maxterms by generating the truth table and listing all the 0-maxterms.Example: Example: FF = = xx′′yy′′ + + xzxz

x y z F

0 0 0 1

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

FF((x, y, zx, y, z)) == ΣΣ(0, 1, 5, 7)(0, 1, 5, 7)

FF((x, y, zx, y, z)) == ΠΠ(2, 3, 4, 6)(2, 3, 4, 6)

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Canonical FormsCanonical Forms

Two canonical forms: Sum-of-minterms Sum-of-minterms PProduct-of-maxtermsroduct-of-maxterms

Canonical forms are unique.

Conversion between canonical forms is achieved by: Exchanging Exchanging ΣΣ and and ΠΠ Listing all the missing indicesListing all the missing indices

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Standard FormsStandard Forms

Two standard forms Sum-of-products Sum-of-products Product-of-sums Product-of-sums

Standard forms are not unique.

Sum-of-products is an OR expression with product terms that may have less literals than minterms

Example: Example: F = F = xy + x′yz + xy′z xy + x′yz + xy′z

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Standard FormsStandard FormsProduct-of-sums is an AND expression with sum terms that

may have less literals than maxterms

Standard forms have fewer operators (literals) than canonical forms

Standard forms can be derived from canonical forms by combining terms that differ in one variable (this is, terms at distance 1)

Example: Example: F = F = ((x′ + y′x′ + y′))((x + y′ + z′x + y′ + z′))((x′ + y + z′x′ + y + z′))

Example: Example: FF11 == xyz + xyz′ + xy′z + x′yzxyz + xyz′ + xy′z + x′yz

== xyz + xyz′ + xyz + xy′z + xyz + x′yzxyz + xyz′ + xyz + xy′z + xyz + x′yz== xyxy((z + z′z + z′)) + x + x((y + y′y + y′))z + z + ((x + x′x + x′))yzyz== xy + xz + yzxy + xz + yz

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Non-standard FormsNon-standard Forms

Non-standard forms have fewer operators (literals) than standard forms.

They are obtained by factoring variables.

Example: Example: xyxy + xy′z + xy′w + xy′z + xy′w == xx((yy + y′z + y′w + y′z + y′w))

== xx((yy + y′ + y′((z + wz + w))))

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Strategy for Operator (Literal) Strategy for Operator (Literal) Reduction in Boolean ExpressionsReduction in Boolean Expressions

Algebraic Expression

Generate canonical form

Expand into truth table

Find functional subcubes

Factor sub-expressions

Non-standard form

Truth table

Canonical form

Standard form

Page 35: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

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Binary Logic OperationsBinary Logic Operations There are 22n

Boolean functions for n binary variables Therefore, 16 Boolean functions for n = 2. They are

NameOperator Symbol

Functional Values for x,y = Algebraic

ExpressionComment

00 01 10 11

Zero 0 0 0 0 F0 = 0 Binary constant 0AND x ∙ y 0 0 0 1 F1 = xy x and yInhibition x / y 0 0 1 0 F2 = xy′ x but not yTransfer 0 0 1 1 F3 = x xInhibition y / x 0 1 0 0 F4 = x′y y but not xTransfer 0 1 0 1 F5 = y yXOR x y 0 1 1 0 F6 = xy′ + x′y x or y but not both

OR x + y 0 1 1 1 F7 = x + y x or yNOR x ↓ y 1 0 0 0 F8 = (x + y)′ Not-OREquivalence x y 1 0 0 1 F9 = xy + x′y′ x equals yComplement y′ 1 0 1 0 F10 = y′ Not yImplication x y 1 0 1 1 F11 = x + y′ If y, then xComplement x′ 1 1 0 0 F12 = x′ Not xImplication x y 1 1 0 1 F13 = x′ + y If x, then yNAND x ↑ y 1 1 1 0 F14 = (xy)′ Not-ANDOne 1 1 1 1 F15 = 1 Binary constant 1

There are two functions that generate constants: Zero and One. For every combination of variable values, the Zero function will return to 0, whereas the One function will return to 1.

There are four functions of one variable, which indicate Complement and Transfer operations. Specifically, the Complement function will produce the complement of one of the binary variables. The Transfer functions by contrast will reproduce one of the binary variables at the output.

There are ten functions that define eight specific binary operations: AND, Inhibition, XOR, OR, NOR, Equivalence, Implication, and NAND.

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Digital Logic GatesDigital Logic Gates

NameGraphic Symbol

Functional Expression

Number of transistors

Delay in ns

Inverter F = x′ 2 1

Driver F = x 4 2

AND F = xy 6 2.4

OR F = x + y 6 2.4

NAND F = (xy)′ 4 1.4

NOR F = (x + y)′ 4 1.4

XOR F = x y 14 4.2

XNOR F = x y 12 3.2

xx FF

xx FF

xxyy

xxyy

FF

FF

FF

FF

FF

FF

Basic Logic Library(CMOS Technology Implementations)

xxyy

xxyy

xxyy

xxyy

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Multiple-Input GatesMultiple-Input Gates

NameGraphic Symbol

Functional Expression

Number of transistors

Delay in ns

3–input AND F = xyz 8 2.8

4–input AND F = xyzw 10 3.2

3–input OR F = x + y + z 8 2.8

4–input OR F = x + y + z + w 10 3.2

3–input NAND F = (xyz)′ 6 1.8

4–input NAND F = (xyzw)′ 8 2.2

3–input NOR F = (x + y + z)′ 6 1.8

4–input NOR F = (x + y + z + w)′ 8 2.2

xxyyzz FF

xxyyzz

FFww

xxyyzz

xxyyzz

ww

xxyyzz

xxyyzz

ww

xxyyzz

xxyyzz

ww

FF

FF

FF

FF

FF

FF

Multiple-Input Standard Logic Gates

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Multiple-Operator (Complex) GatesMultiple-Operator (Complex) GatesName

Graphic Symbol

Functional Expression

Number of transistors

Delay in ns

2–wide, 2–inputAOI

F = (wx + yz)′ 8 2.0

3–wide, 2–inputAOI

F = (uv + wx + yz)′ 12 2.4

2–wide, 3–inputAOI

F = (uvw + xyz)′ 12 2.2

2–wide, 2–inputOAI

F = ((w + x)(y + z))′ 8 2.0

3–wide, 2–inputOAI

F = ((u + v)(w + x)(y + z))′ 12 2.2

2–wide, 3–inputOAI

F = ((u + v + w)(x + y + z))′ 12 2.4

FF

FF

xxyyzz

ww

FF

FF

FF

FF

Multiple-Operator Standard Logic Gates

xxyyzz

ww

xx

yyzz

ww

uuvv

xx

yyzz

ww

uuvv

xxyyzz

uuvvww

xxyyzz

uuvvww

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Full-adder Design Using XOR GatesFull-adder Design Using XOR Gates

xi yi ci ci + 1 si

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1Truth table

ssii == xxii′y′yii′c′cii + + xxii′y′yiiccii′ ′ + + xxiiyyii′c′cii′′ + + xxiiyyiiccii

== ((xxii′y′yii + + xxiiyyii′′))ccii′′ + ( + (xxii′y′yii′′ + + xxiiyyii))ccii

== ((xxii yyii))ccii′′ + ( + (xxii yyii))ccii

= = ((xxii yyii))ccii′′ + ( + (xxii yyii))′c′cii

== ((xxii yyii)) ccii

cci i + 1+ 1 = = xxiiyyiiccii′′ + + xxiiyyiiccii + + xxii′y′yiiccii + + xxiiyyii′c′cii

== xxiiyyii((ccii′′ + + ccii) + ) + ccii((xxii′y′yii + + xxiiyyii′′))

== xxi i yyii + + ccii((xxii y yii))Full–adder equation

xxii yyii

ccii

si

cci i + 1+ 1

2.4 4.2

4.2

2.42.4

Logic Schematic (46 Transistors)

Input/OutputPath

Delay(ns)

ci to ci + 1 4.8 ns

ci to si 4.2 ns

xi, yi to ci + 1 9.0 ns

xi, yi to si 8.4 ns

Full–adder delays

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Full-adder Design Using Fast GatesFull-adder Design Using Fast Gates

xxi i yyii == xxi i yyii + + xxii′y′yii′ ′

== ((((xxi i yyii))′ ′ ((xxii′y′yii′′))′ ′ ))′′

== ((((xxi i yyii))′ ′ ((xxii ++ y yii))))′′

ssii == ((xxii yyii))ccii′′ + ( + (xxii yyii))ccii

== ((xxii yyii))′c′cii′′ + ( + (xxii yyii))ccii

== ((xxii yyii)) ccii

cci i + 1+ 1 = = xxi i yyii + + ccii((xxii ++ y yii))

== ((((xxi i yyii))′ ′ ((ccii((xxii ++ y yii))′)′))′)′Full–adder equation

xi yi ci ci + 1 si

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1Truth table

Logic Schematic (36 Transistors)

Input/OutputPath

Delay(ns)

ci to ci + 1 2.8 ns

ci to si 3.8 ns

xi, yi to ci + 1 5.2 ns

xi, yi to si 7.6 ns

Full–adder delays

xxii

yyii

ccii

ssii cci i + 1+ 1

2.4

1.41.41.4

1.4

1.4

2.4

1.4

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Full-adder Design with Full-adder Design with Multiple-input GatesMultiple-input Gates

xi yi ci ci + 1 si

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1Truth table

Full–adder equation

Logic Schematic (56 Transistors)

xxii

yyii

ccii

ssiicci i + 1+ 1

2.21.8

1.4 1.4 1.4 1.8 1.8 1.8 1.8

Input/OutputPath

Delay(ns)

ci to ci + 1 3.2 ns

ci to si 5.0 ns

xi, yi to ci + 1 4.2 ns

xi, yi to si 5.0 ns

Full–adder delays

ssii == xxii′y′yii′c′cii + + xxii′y′yiiccii′ ′ + + xxiiyyii′c′cii′′ + + xxiiyyiiccii

== ((((xxii′y′yii′c′cii))′ ′ ((xxii′y′yiiccii′′))′ ′ ((xxiiyyii′c′cii′′))′ ′ ((xxiiyyiiccii)’))’)′′

cci i + 1+ 1 = = xxiiyyii + + cciixxii + + cciiyyii

== ((((xxiiyyii))′ ′ ((cciixxii))′ ′ ((cciiyyii))′′))′′

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Full-adder Design with Complex GatesFull-adder Design with Complex Gates

Full–adder equation

xi yi ci ci + 1 si

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1Truth table

Input/OutputPath

Delay(ns)

ci to ci + 1 3.4 ns

ci to si 4.4 ns

xi, yi to ci + 1 3.4 ns

xi, yi to si 4.4 ns

Full–adder delays

Logic Schematic (46 Transistors)ssiicci i + 1+ 1

xxii

yyii

ccii

1.4

2.4 2.0 2.0

ssii == xxii′y′yii′c′cii + + xxii′y′yiiccii′ ′ + + xxiiyyii′c′cii′′ + + xxiiyyiiccii

== ((((xxii′y′yii′c′cii++ x xii′y′yiiccii′′))′ ′ ((xxiiyyii′c′cii′ ′ ++ x xiiyyiiccii))′′))′′

cci i + 1+ 1 = = xxiiyyii + + cciixxii + + cciiyyii

== ((((xxiiyyii))′ ′ ((cciixxii))′ ′ ((cciiyyii))′′))′′

== ((((xxii′′ + + yyii′′)()(ccii′′ + + xxii′′)()(ccii′′ + + yyii′′))))′′

== ((xxii′′ yyii′′ + + ccii′′ xxii′′ + + ccii′′ yyii′′ ))′′

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VLSI TechnologyVLSI Technology

Small-scale integration (SSI) 10 gates/package10 gates/package

Medium-scale integration (MSI) 10 – 100 gates/package (2 – 4 bit slices)10 – 100 gates/package (2 – 4 bit slices)

Large-scale integration (LSI) 100 – 1000 gates/package (controllers, datapaths, bit slices)100 – 1000 gates/package (controllers, datapaths, bit slices)

Very-large-scale integration (VLSI) 1000+ gates/package (systems on a chip)1000+ gates/package (systems on a chip)

Custom designs (Standard cells) Gate arrays (GAs) Field-programmable (FPGAs)

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Custom DesignCustom Design

Each designed by hand

Standard cells Same height, different widthsSame height, different widths Routing in channels and over the cellsRouting in channels and over the cells Two or more metal layersTwo or more metal layers

Standard Cell Approach

Standard Cells

Routing Channel

Page 45: Principles Of Digital Design Chapter 3 Boolean Algebra and Logic Design Boolean Algebra Logic Gates Digital Design Implementation Technology  ASICs

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Example of Custom DesignExample of Custom Design

Full-Adder Implementation with Standard Cells

ssii

cci i + 1+ 1xxiiyyiiccii

yyii c ciicci i + 1+ 1xxi i cci i xxi i yyii

xxii′′ y yii′′ c cii′′yyii′′ccii′′ xxii′′

ssi i xxii′′ y yii c cii′′xxii y yii′′ c cii′′xxi i yyii c cii

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Semi-Custom Approach withSemi-Custom Approach withGate Arrays Gate Arrays

Gate arrays are prefabricated arrays of interconnected gates

All gates are the same type (3–input NAND, for example)

Two or more metal layers used to connect gates

Full-Adder Implementation in a Gate Array

xxii

yyii

ccii

ssii

cci i + 1+ 1

((xxii y yii))′′

yyii′′ ccii′′

xxii′′ ((yyii c cii))′′

((xxii c cii))′′((xxii y yi i ccii))′′

((xxii y yii′′ccii′′))′′

((xxii′′yyi i ccii′′))′′

((xxii′′yyii′′ccii))′′

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Field–Programmable Approach with Field–Programmable Approach with FPGAFPGA

FPGAs are programmed by loading data into internal memory

Excellent for rapid prototyping

Low density and low speed

4-variable Boolean function

GQGQ

GG

HQHQ

HH

gg11

gg22

gg33

gg44

hh11

hh22

hh33

hh44

4-variable Boolean function

SM SM SM

SM SM

SMSMSM

PLB

PLBPLB

PLB

SM

Array Structure Programmable Logic Blocks (PLB)

Interconnect Point (IP)

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Full-adder Implemented with FPGAFull-adder Implemented with FPGA1 programmable logic block for each full-adder3 out of 4 inputs are used for each Boolean function

h1 h2 h3 h4 H

0 0 0 X 00 0 1 X 10 1 0 X 10 1 1 X 01 0 0 X 11 0 1 X 01 1 0 X 01 1 1 X 1

g1 g2 g3 g4 G

X 0 0 0 0X 0 0 1 0X 0 1 0 0X 0 1 1 1X 1 0 0 0X 1 0 1 1X 1 1 0 1X 1 1 1 1

cci i + 1+ 1

GQGQ

GG

HQHQ

HHssii

gg11

gg22

gg33

gg44

hh11

hh22

hh33

hh44

UnusedUnused

UnusedUnused

ccii

xxii

yyii

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Chapter SummaryChapter Summary Boolean Algebra

AxiomsAxioms Basic Basic ttheoremsheorems

Boolean Functions Specification of Boolean Functions

Truth tablesTruth tables Algebraic expressionsAlgebraic expressions

Canonical forms Standard forms Non-standard forms

Algebraic Manipulation of Boolean Expressions Logic Gates

Simple gatesSimple gates Multiple-input gatesMultiple-input gates Complex gatesComplex gates

Implementation Technology SSI (Small-scale integration)SSI (Small-scale integration) MSI (Medium-scale integration)MSI (Medium-scale integration) LSI (Large-scale integration)LSI (Large-scale integration) VLSI (Very-large-scale integration)VLSI (Very-large-scale integration)

Custom designs Semi-custom designs Field-programmable