presenting: itai avron supervisor: chen koren final presentation spring 2005 implementation of...
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Presenting: Itai Avron
Supervisor: Chen Koren
Final Presentation
Spring 2005
Implementation of ArtificialIntelligence System on FPGA
Project Goals
• Creating a VHDL design of a Neural Network
• Comparison Vs. software implementation (Matlab)
Background• Neural Network is a Learning Machine
• It is build from Neurons (Perceptrons), which holds the knowledge of the system within their inter-connection strength
• Every Neuron Implement the Active Function:
0
1
wxw i
n
i
Ti
System Interface
• Input: - Image (16x16 pixels) - Weights
• Output: - A number between 0-9 (4 bit vector)
System Architecture
Net Architecture
Controller – Flow Diagram
Neuron Architecture
Hardware Requirements
• Neuron : ROM – 2^15*20 bit = 80KB 257 Multipliers (20 bit input)
256 Adders (40-48 bit input)
• Network : Memory – Used : 17*(256+1)*20 bit = 10.7KBIn Reality : 32 Lines => 20.1KB
• System : Image registers – 20*256 bit = 640B
Simulations
Neuron:
Neural Network
Neural Network (Cont.)
System
System (Cont.)
Synthesis
• Synthesis on 3 different FPGA
1. xc2v1000-5-bg575 -> 67.128MHz
2. xc2v1000-6-fg256 -> 80.540MHz
3. xc2vp20-6-fg676 -> 75.603MHz
Frequency = 80MHz
Comparison
• Matlab : 114 errors out of 1000 pictures
Calculation time: 0.5970 sec
• VHDL : 114 errors out of 1000 pictures
Calculation time:
1000*43/80MHz = 0.5373 msec
The hardware is about 1000 times faster!!
Improvement Suggestion
• Change numbers resolution to less than 18 bit(max input bits in Xilinx components)
• Implement learning is HW