presentation on multiplication

8/4/2019 Presentation on Multiplication

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By.ShrishtyShrishty DeorariDeorari

Btech 3rd year..

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Introduction

Multiplication is an arithmetic operation in which twonumbers are used to produce there product.

These two numbers are called multiplicand and multiplier.

When multiplier and multiplicand get multiplied together

theygenerate the PRODUCT.


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A simplemultiplicationisasshown below:-

1) 2 x 3 = 6Here 2 is the multiplicand.

and 3 is the multiplier.

2) 23 x 12 = 23

x 12

4 6

+ 2 3

2 7 6-----answer


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Digitalmultiplicationprocess

y Digital multiplication is not the most fundamentallycomplex operation, but is the most extensivelyusedoperation (especiallyin signal processing).

y Digital multiplication entails a sequence ofadditionscarried out on partial products.

y The method bywhich this partial product arrayis summedto give the final product is the keydistinguishing factoramongst the numerous multiplication schemes .


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Basics of Digital Multiplication


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Binarymultiplication


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1. TestMultiplier0

32threpetition?

3. Shift the Mplier register right 1 bit

2. Shift the Mcand register left 1 bit

1a. Add multiplicand to product &place the result in Product register

Multiply Algorithm Version 1

Done

Yes: 32repetitions

No: < 32 repetitions

Multiplier0 = 0Multiplier0 = 1


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Exampleof4 bitmultiplication

x3 x2 x1 x0

x y3 y2 y1 y0

y3x0 y2x0 y1.x0 x0.y0

y3x1 y2x1 y1x1 y0x1

y3x2 y2x2 y1x2 y0x2

y3x3 y2x3 y1x3 yox3

s7 s6 s5 s4 s3 s2 s1 s0

o In this example whenX3 X2 X1 X0 bitsare multiplied with Y3 Y2 Y1 Y0

Produces the output S7 S6 S5 S4 S3 S2 S1 S0 . This has beenimplemented in the next slide.


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Parrallel adder

Input x3 x2 x1 x0

Inputy3y2y1y0

Output S7 S6 S5 S4 S3 S2 S1 S0


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Arraymultiplier

y Is the another method of multiplication process.

y

In this the unit element is made whose arrayis formedin order to produce the result.

y Each unit cell consist ofan AND gate and a FULLadder.

y Worst case delayin this multiplication process wouldbe (2n+1)td


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unitelementofarraymultiplier


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Where:

y Sin : is the input from previous unit element.

yX in: is the bit of multiplicand.

y

Yin: is the bit of multiplier.y Cin: is the carryfrom the previous bit product.

y Sout: output of the adderwhich is either passed to thenext unit or taken as the product as per case.

y

Cout: is the carrygenerated from the unit which ispassed to the next bit product.

yXout: is the xin which is passed to the diagonal unitelement.


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A general block diagram ofarraymultiplier is as shown above.


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Multiplicationalgorithms:

y Multiplication can be done in different ways which can begiven bythere algorithms.

y At each step we multiplythe multiplicand bya single digit

from the multiplier. In binary, we multiplybyeither 1 or 0 (much simplerthan decimal)

y The algorithm is different than the repeated addition

algorithm we used in our MIPS multiplysubroutine.

y We take advantage ofpositional representation. feweradditions (manyfewer)


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1. TestMultiplier0

32threpetition?

3. Shift the Mplier register right 1 bit

2. Shift the Mcand register left 1 bit

1a. Add multiplicand to product &place the result in Product register


Done

Yes: 32 repetitions


Multiplier0 = 0Multiplier0 = 1


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Multiplication Hardware 1

64-bit product

32-bit ALU

Shift_left

Shift_right

WriteControl

32 bits

32bits

64 bits

32-bit multiplicand

lsb

32-bit multiplier


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Betterand newalgorithmChanges can be made:

y -instead of shifting multiplicand left, shift product right

y

-adder can be shortened to length of the multiplier &multiplicand(8 bits in our example)

y -place multiplier in right half of the productregister(multiplier will disappearas product is shifted right

y

-add multiplicand to left half of product


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1. TestProduct00

32threpetition?

2. Shift the Product register right 1 bit.

1a.Add multiplicand to the left half ofproduct &place the result in the left half ofProduct

register

Done

Yes: 32 repetitions


Product = 0Product = 1


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Multiplication Hardware for version 2

product

16-bit ALU

Shift_left

Shift_right

WriteControl Test

16 bits

32 bits

multiplicand


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Boothsmultiplication

y Booth's multiplication algorithm multiplies two signedbinarynumbers in two's complement notation.

y The algorithm was invented byAndrew Donald Booth in1951 while doing research on crystallographyat BirkbeckCollege in Bloomsbury, London.

y Booth used desk calculators that were fasterat shifting

than adding and created the algorithm to increase theirspeed.

y Booth's algorithm is of interest in the studyof computerarchitecture.


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y In booths algorithm the multiplicand is stored in oneregister.

y The multiplier is combined with equal numberofzeros which after the completion of the process givethe product.

y If besides addition we also use subtraction, we canreduce the number of consecutives additions andtherefore we can make the multiplication faster.


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c ar r oo sa gor


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Example:


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y The upper half of the final result is in register [A]while the lower half is in register [Q].

y The product is given in signed 2's complement and itsactual value is negative of the 2's complement:


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Continued..yAs the operands are in signed 2's complement form,

the arithmeticshift is used for the right shifts above,

i.e., the MSB bit (sign bit) is always repeated while allother bits are shifted to the right. This guarantees theproper sign extension for both positive and negative

values represented in signed 2's complement.


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Implementation

16-bit ALU

Shift_right

WriteControl

16 bits

32 bits

multiplicand

Initially00| multiplier

Add /submultcnd to theleft halfOf theProduct.


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Programmablelogicdevices

yAprogrammable logic device or PLD isan electronic component used to

build reconfigurable digital circuits.

y Unlike a logic gate, which has a fixed function, a PLDhas an undefined function at the time of manufacture.

y Before the PLD can be used in a circuit it must beprogrammed, that is, reconfigured.


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PLDsfamily:


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y The first type of user-programmable chip that could

implement logic circuits was the Programmable Read-OnlyMemory(PROM), in which address lines can beused as logic circuit inputs and data lines as outputs.

y It uses a decoder at input to select the logic.

y

The first device developed later specificallyforimplementing logic circuits was the Field-Programmable Logic Array(FPLA), or simplyPLA forshort.

y

PLA

a Programmable Logic Array (PLA) is arelativelysmall FPD that contains two levels of logic,an AND-plane and an OR-plane, where both levels areprogrammable ( are user-programmable).


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y PAL a Programmable Array Logic (PAL) is arelativelysmall FPD that has a programmable AND-

plane followed bya fixed OR-plane.

y SPLD refers to anytype of Simple PLD, usuallyeithera PLA or PAL.

y CPLD a more Complex PLD that consists ofanarrangement of multiple SPLD-like blocks on a single

chip. Alternative names (that will not be used in thispaper) sometimes adopted for this style of chip areEnhanced PLD (EPLD), Super PAL, Mega PAL, andothers.


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y FPGA a Field-Programmable Gate Arrayis an FPDfeaturing a general structure that allows veryhigh logiccapacity.

y Whereas CPLDs feature logic resources with a widenumber of inputs (AND planes), FPGAs offer more narrowlogic resources. FPGAs also offera higherratio of flip-flopsto logic resources than do CPLDs.

y The FPGA configuration is generallyspecified usinga hardware description language (HDL), similar to thatused foran application-specific integrated circuit (ASIC).

y FPGAs contain programmable logic components called"logic blocks", and a hierarchyofreconfigurableinterconnects that allow the blocks to be "wired together.


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Advantages

y Standard off the shelf products

y Programmable byuser several times

y Fast time to market

y High flexibility

Disadvantages

y Slower than ASIC i.e. higher delays Unpredictabledelays.

y More power

y Volatile memorynecessitates the use ofan EEPROM tohold the program.

presentation on multiplication

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