presentation given at pcb europe '98 - design for manufacture

PCB Design for Manufacture in anAdvanced Military Avionics Application

Neil WhitehallEric FergusonBill BradshawPeter Dalglish

Jack AlexanderAndrew BarkerBruce Wilkinson

With the explosion of products in today’s markets with significant electronics content, PCBDesign for Manufacture has become a vital competence.This presentation will take an item of advanced avionics equipment as a case study to show howthe requirements from multiple disciplines are treated throughout the product designverification and validation cycle.The presentation will highlight the techniques and infrastructure that are required to deliversufficient organisational capability. We will discuss how the requirements from the differentdisciplines involved are explored, managed and flowed down to the PCB design itself. Thefollowing disciplines will be considered:i) The Product Design Process.ii) Thermal Management.iii) Thermal Simulation, Assessment and Solder Joint Reliability.iv) PCB Assembly and the Soldering Process.v) PCB Fabrication.vi) PCB Design.

PCB Design for Manufacture in an AdvancedMilitary Avionics Application.

1. Design Process - Neil Whitehall.2. Thermal Management - Eric Ferguson.3. Thermal Simulation, Assessment & Solder Joint Reliability

- Bill Bradshaw.4. PCB Assembly - Peter Dalglish.5. PCB Fabrication - Jack Alexander.6. PCB Design - Andrew Barker.7. Convection Reflow Soldering Profiles - Bruce Wilkinson.

PCB Europe : Design for ManufactureRadar and Countermeasures Systems

07/06/99

‹#›Page

PCB Design for Manufacture in an Advanced Military Avionics

ApplicationNeil WhitehallEric FergusonBill BradshawPeter Dalglish

Jack AlexanderAndrew Barker

GEC Marconi Avionics,Radar and Countermeasures Systems.


07/06/99

‹#›Page

Session Themes Theme 1 : The Design Process. Theme 2 : Thermal Management. Theme 3 : Thermal Simulation, PCB Stress &

Solder Joint Reliability. Theme 4 : PCB Assembly & Soldering Process. Theme 5 : PCB Fabrication. Theme 6 : PCB Design. Panel Questions & Answer Session.


07/06/99

‹#›Page

The Design Process

Neil Whitehall,Electronics Process Manager,

GMAv RCS-Edinburgh.


07/06/99

‹#›Page

Agenda

Business Drivers Integrated Product and Process Development. A Generic Systems Engineering Process Model. A Tailored Process Model for PCB DFM.


07/06/99

‹#›Page

Business Drivers : Why are we in Business ?

THE GOAL : TO MAKE MONEYBottom line measurements ...

What is the bridge ?

NET PROFIT(Absolute)

CASH FLOW(Survival)

RETURN ON INVESTMENT

(Relative)

ACTIONS


07/06/99

‹#›Page

Our Actions & CompetitivenessTHE COMPETITIVE EDGE IMPACT : OPERATIONAL MEASURES LINKED TO ACTIONS THROUGH THE BRIDGE.

CASH FLOWNET PROFIT RETURN ONINVESTMENT

THROUGHPUT(FUTURE)

OPERATINGEXPENSEINVENTORY

COMPETITIVE EDGE


07/06/99

‹#›Page

The Value ChainCustomer /

Prime

AircraftConsortium

Requirements

Value

RadarConsortium

Requirements

ValueValue PCB

Assembler

PCBFabricator

Requirements

RequirementsValue

Suppliers1 to ‘N’


07/06/99

‹#›Page

Value through Price & Performance

Performance Price

Value


07/06/99

‹#›Page

Performance through Dependability and Features

Dependability Features

Performance


07/06/99

‹#›Page

Enabling & Limiting Constraints

Design ProcessPerformance

LimitingConstraints

EnablingConstraints

Level of Achievement of

the Design Team

AchievementCeiling


07/06/99

‹#›Page

Focussing on Adding Value through Product Features, Product Dependability and Product Price.

CE : Cultural ApproachThe earliest possible

integrationof the overall company’sknowledge, resources andexperience into creatingsuccessful new products.

Integrated Product Teams.People Development.

Process Education & Training.Co-location & Communication.

Continuous ImprovementCMM Phased Improvement Plans

Focused on Key Process Areas& Adoption of Key Practices

CMM Process Assessments :Organization Disconnects& Dysfunctional Links.

Focused Improvement throughBusiness Constraint Identification.

CE : Logistical ApproachGet the Right Data, to the Right

Place, at the Right Time, in the Right Format.

Layer 5 : Decision Support.Layer 4 : WM & Metrics.

Layer 3 : PDM.Layer 2b : Inter-operable Tasks.Layer 2a : Interoperable Tools.

Layer 1 : Interoperable Computing.

SRR FDR

Systems Engineering Generic Activity SequenceRBD FBD SBD PD DD Imp T&I A&C

SDR PDR CDR TRR FCA / PCAProduct Lifecycle Management

Integrated Product & Process Development (IPPD)


07/06/99

‹#›Page

CE : Logistical Focus Concurrent Engineering (CE)

• Definition #1 : Logistical Focus.• “Get the right data, To the Right Place, At the

Right Time, In the Right Format”.• Don Carter & Barbara Stillwell Baker.• ‘Concurrent Engineering - The Product

Development Environment for the 1990s’.• Volume 1 & 2 : ISBN 0-201-56349-5.

Can data be managed in the same way as inventory is managed in production ?

Can people be disciplined enough to change their own working cultures ?


07/06/99

‹#›Page

Carter’s Process Support Layers.

Layer 1 : Inter-operable Network Computing. Layer 2a : Inter-operable Tools. Layer 2b : Inter-operable Tasks. Layer 3 : Product Data Management. Layer 4 : Workflow Management & Metrics. Layer 5 : Requirements & Decision Support.


07/06/99

‹#›Page

Inter-operable Network Computing

User InterfaceLevel

Application DeliveryLevel

Data Management Level

File/Print ServerDatabase Server

UNIX ServerWindowsApplicationsServer


07/06/99

‹#›Page

Inter-operable ToolsAspect CCDBExplore CIS

VIP Database

Library ManagementLMS Manager, PDSAxiom CompliersAspect Integration

Models

Design Architect LMS

SherpaDataVault

Mentor SchematicsDesign Architect

Aspect Client Integration

SherpaPDM

QuickSim IIQuickVHDL

Pro

Saber Template LibrarySaber Component Library

Smartmodel Library

Mentor Simulation

Sherpa Integrator

Mentor LayoutSpectra 65, Quad XTKValor Enterprise 3000

QuickSim IIQuickVHDL Pro

Analogy SimulationSaber

Thermal / Stress SimulationPNC PCB Explorer, VibPlus,

PCB Fatigue & Soldersim


07/06/99

‹#›Page

Inter-operable Tasks

GenerateSymbol

GenerateModel

GenerateGeometry

ThermalModel

GenerateQuad Model

New PCBJobs Buffer

Component Request

Information Gathering New PCBRecognised

EDA Part Assembly and Test

Metrics Analysis

SymbolRequest

ModelRequest

GeometryRequest

ThermalRequest

Quad Model Request

Metrics Input Metrics Database

TO PCBTASKS

EDA LIBRARY SYSTEM TASKS

$DEVLIB$RLSLIB


07/06/99

‹#›Page

Product Data Management

Design Engineering

MRP

CDMPDM

ManufacturingProcurement

PDM = Product Data ManagementMRP = Materials Requirements PlanningCDM = Component Data Management


07/06/99

‹#›Page

Workflow Management & Metrics• 1 - Project Start Date• 2 - LRU Level Plan Released• 3 - PEC Development Plan Released• 4 - LRU Functional Requirement Spec Released• 5 - PEC Functional Requirement Spec Released• 6 - First Component Specification Request• 7 - First EDA Component Request• 8 - Last Component Specification Request• 9 - Last EDA Component Request• 10 - Last PCB Interconnect Change• 11 - Last PCB Component Positional Change• 12 - PCB Outline Finalized• 13 - PCB Technology Type Chosen• 14 - Thermal Strategy Decided• 15 - Preliminary PEC Design Review• 16 - PEC Thermal Assessment Completed• 17 - Advance PIL Issue Date

• 18 - PEC Design Checklist Completed• 19 - PEC Detailed Design Description Issued• 20 - Development Components Ordered• 21 - PIL Issued• 22 - PEC Design Review (Sign Off)• 23 - PCB Manufacturing Data Released• 24 - PCB Delivered• 25 - PEC Prototype Available• 26 - PEC Test Specification Issued• 27 - Development Test Equipment Available• 28 - Development Test Completed• 29 - Development Components Delivered• 30 - Production Components Ordered• 31 - Production Components Delivered• 32 - First Delivery• 33 - Reliability Assessment Completed• 34 - FMEA Completed• 35 - PIL Updated for Obsolescence


07/06/99

‹#›Page

Requirements & Decision Support

Detail Drawings and Plans

BuildingBlocks

Tested andPartially-ProvenBuilding Blocks

Tested andPartially-Proven

Sub System


System

Accept Validated System and

Sub SystemsCustomer Equipment andOperational Environment

Customer'sDevelopment

Activities

SystemEngineering

Activities

Sub SystemEngineering

Activities

DesignBuilding Blocks

ProduceBuilding Blocks

TestBuilding Blocks

TrialsIntegrate with Customer'sEquipment

Integrateand TestSystem

Integrateand Test

Sub Systems

ResponseSpecificationand Drawings


Building Block Reqts Spec


System Reqts Spec

Sub System Reqts Spec



07/06/99

‹#›Page

CE : Cultural Focus Concurrent Engineering (CE)

• Definition #2 : Cultural Focus.• “defined as the earliest possible integration of

the overall company’s knowledge, resources,and experience in design, development,marketing, manufacturing, and sales intocreating successful new products, with highquality and low cost, while meeting customerexpectations.”

• Sammy G. Shina.• Concurrent Engineering and Design for

Manufacture of Electronic Products, 1991.• ISBN 0-442-00616-0.


07/06/99

‹#›Page

Integrated Product Teams

ElectronicDesign Team

Designer

Project Management. ProjectDesign Team

ECAD & PCB Design

MechanicalDesign Team

Thermal & Stress

InterconnectionsEngineering

ConfigurationManagement

Procurement

ComponentEngineering

Production Planning

Printed CircuitAssembly

IntegratedLogistics Support

1,2 3,4

5,15,19,22,26,27,28,35

7,9,1011,13

18

12

14,16

1317,21

20,23,30

6,8

24,2931,32

25,32

33,34


07/06/99

‹#›Page

Co-location & Communication

10m

UsefulInteraction

PCBDesign

StressEngineer

ThermalEngineer

InterconnectionsEngineer

15m 19m

4m

25m

10m

15m

Sum of All Distances = 78m. Average Distance = 13m.Longest Distances = 25m.


07/06/99

‹#›Page

Education & Training from Process Definition

ProcessDefinition

1.

StandardPlans

2.

TailoredPlans

3.

Executed onProjects

4.

SkillIdentification

5.

SkillsAudits

6.Training &

Education Plans

7.

ProcessReview

8.

ImprovementPlans

9.


07/06/99

‹#›Page

A Generic Systems Engineering Process Model : Project View

START

CREATESOLUTION CONCEPTS

C

PROVIDE SPECIALIST SUPPORT GG

PLAN AND MANAGE SYSTEM DEVELOPMENT FF

ANALYSIS MODELLING AND SIMULATION EE

ADJUST EMERGING DESIGN H

SUB SYSTEMENGINEERING

SUB-SYSTEM DESIGNPROCUREMENT

MANUFACTUREINTEGRATION AND TEST

SUB SYSTEM DELIVERY

H

D DESIGN ANDSPECIFY SYSTEM

FUNCTIONALDECOMPOSITION

A DETERMINEREQUIREMENTS

B

I INTEGRATE

AND TESTSYSTEM

INSERVICESUPPORT

L

J PLAN ANDANALYSE

TRIALS

PROTOTYPE

K PROVECOMPLIANCE

SRR

SEGASRBD FBD SBD PD DD Imp T&I A&C

FDR SDR PDR CDR TRR FCA / PCA


07/06/99

‹#›Page

Design Verification & Validation

Detail Drawings and Plans

BuildingBlocks

Tested andPartially-ProvenBuilding Blocks


Sub System


System

Accept Validated System and

Sub SystemsCustomer Equipment andOperational Environment

Customer'sDevelopment

Activities

SystemEngineering

Activities

Sub SystemEngineering

Activities

DesignBuilding Blocks

ProduceBuilding Blocks

TestBuilding Blocks

TrialsIntegrate with Customer'sEquipment

Integrateand TestSystem

Integrateand Test

Sub Systems



Building Block Reqts Spec


System Reqts Spec

Sub System Reqts Spec



07/06/99

‹#›Page

Project View, Process View & TimeSystem Engineering

Process ModelTime

Design ValidationThrough Development

Test & System Integration

Design VerificationThroughout the Product

Hierarchy

Manufacture


07/06/99

‹#›Page

A Tailored Verification Process Model for PCB DFM

Aircraft Platform

Black Box

Cassette

PCB

Thermal & Stress Models

PCB Design

PCB Fabrication

PCBAssembly


07/06/99

‹#›Page

Requirements & Modeling in the PCB DFM Verification Process

EFA Platform Requirements

Black Box

Cassette

PEC

PCB Design

PCB Fabrication

PCBAssembly

Sea HarrierPlatform Requirements &

Measurements from Validation

Sup

porte

d by

Rea

d A

cros

s Fr

om P

rior P

roje

cts Platform Thermal & Stress Requirements

Enclosure Thermal & Stress Requirements

Cassette Thermal & Stress Requirements

Assemblers Capability &Our Requirements

Fabricators Capability &Our Requirements

Constraints on PCB Design


07/06/99

‹#›Page

Black Box

Cassette

PECThermal

Management -E.Ferguson

1.

Aircraft

Speakers by PCB DFM Theme

ThermalAnalysis -

B.Bradshaw

2.

PCB Design -A.Barker

5.

PCB Fabrication -J.Alexander

4.

PCBAssembly -P.Dalglish

3.


07/06/99

‹#›Page

Design Process : Bibliography ‘The Theory of Constraints’

- Eli Goldratt.- ISBN 0-88427-085-8.

‘Information Integration for CE (IICE)’.- Wright Patterson Air Force Base, 1995.

‘CE - The Product Development Environment for the 1990s’.- Don Carter & Barbara Stillwell Baker.- Volume 1 & 2 : ISBN 0-201-56349-5.

‘Concurrent Engineering and Design for Manufacture of Electronic Products’.- Sammy G. Shina, 1991.- ISBN 0-442-00616-0.

‘Developing Products in Half the Time’.- Preston G. Smith & Donald G. Reinertsen.- ISBN 0-471-292-524.

‘Managing the Design Factory - The Product Developer’s Toolkit’.- Donald G. Reinertsen.- ISBN 0-684-83991-1.

‘Optimizing Quality in Electronics Assembly’.- James Allen Smith & Frank B. Whitehall.- ISBN 0-07-059229-2.


07/06/99

‹#›Page

Speaker Biography

Neil Whitehall (Electronics ProcessManager).

After studying for a degree in Electronicsand a Masters in Digital SystemsEngineering Neil joined Ferranti DefenseSystems in 1988. He is now responsiblefor Design Process Infrastructure /Support, Improvement Plans and Budgetsand for managing the ECAD, PCB andHybrid Design Groups. This wasproceeded by technical roles usingSilicon MCM-D & WSI, Signal Processingsystems using DSP and FPGAtechnologies and ASIC design makinguse of RISC processor cores andadvanced DFT techniques such as L-BIST, MBIST and BSCAN.


07/06/99

‹#›Page

Summary - Session Themes

Theme 1 : The Design Process. Theme 2 : Thermal Management, Simulation & Assessment. Theme 3 : Stress Analysis of PCBs & Solder Joint Reliability. Theme 4 : PCB Assembly & Soldering Process. Theme 5 : PCB Fabrication. Theme 6 : PCB Design. Questions & Answers.


07/06/99

‹#›Page

Panel Questions & Answer Session


07/06/99

1Page

Thermal Management

Eric Ferguson,Chief Thermal Engineer, GMAv RCS-Edinburgh.


07/06/99

2Page

Thermal Engineering

A MEANS OF IMPROVING RELIABILITY


07/06/99

3Page

Failures Caused By Environmental Stress Screening (ESS)

THERMAL %Temperature Cycling 20.8High Temperature 10.2Thermal Shock 6.9Low Temperature 6.7Environment 5.8Humidity 2.8

MECHANICAL %Random Vibration 19.1Fixed Vib Frequency 6.8Sweep Vib Frequency 6.1Mech Shock 4.5Acceleration 1.7Altitude 1

ELECTRICAL %Electrical Stress 7.6

THERMAL (53%)

ELECTRICAL (8%)

MECHANICAL (39%)


07/06/99

4Page

Gripen

Avionics Cooling Air Parameters•Inlet Temperature: 0°C ±10•Mass Flow: 20 g/s per kW•Pressure Potential: 3 kPa


07/06/99

5Page

Sea Harrier (MLU)

Avionics Cooling Air Parameters•Inlet Temperature: 30°C•Mass Flow: 35 g/s per kW•Pressure Potential: 1.5 kPa


07/06/99

6Page

Eurofighter Typhoon

Avionics Cooling Air Parameters•Inlet Temperature: 54°C•Mass Flow: 58 g/s per kW•Pressure Potential: 0.5 kPa


07/06/99

7Page

SUPPLY PRESSURE

0

0.5

1

1.5

2

2.5

3

kPa

TEMPERATUREINLET OUTLET

10

20

30

40

50

60

70

-10

0

5055

71

1985

1990

1995

19951985

Radar Cooling Air

1990


07/06/99

8Page

Avionics Cooling Air

25 kW2.3 MW

ECS

MAIN

ENGINE

NAVIGATION & CONTROL AVIONICS

RADAR

COCKPIT

COCKPIT BYPASS VALVE

COOLING AIR

1 % EFFICIENCY


07/06/99

9Page

Component Temperatures: Design Aim

THERMAL DESIGN WORKING RANGE

Future Offensive Aircraft2000

85 °C

120 °C

100 °C

0 °C

Component Obsolescence

Customers Demand Improved Reliability

Increased Transparencies

Datum

Coolant Pressure

Coolant Temperature

Recommended MAXIMUMJUNCTION TEMPERATURE

Component Case Temperature

Component Temperature Penalty

1985 1990 1995


07/06/99

10Page

Cooling Technique

Air Outlet

Cooling Air Inlet

Heat Exchangers


07/06/99

11Page

Typical PSUCFD Analysis


07/06/99

12Page

Cooling Air Inlets

Heat Exchanger Frame

Internal Serrated Finning

PCB Cooling TechniqueSurface Mount PCB


07/06/99

13Page

Heat Exchanger

Power Hybrid @ 87°C

Heat Exchanger Inlets

Air Inlet @ 54°C

CFD Analysis

PCB Substrate Temperatures

Air Outlet@ 71°C


07/06/99

14Page

Power Hybrid Component

CFD AnalysisHeat Load = 18 Watts


07/06/99

15Page

Summary Thermal Engineering: A Means of Improving

Reliability

Environmental Conditions on Aircraft are getting worse for avionic systems

Mitigated by investment in CFD and specialised thermal software

Future Offensive Aircraft: Non-traditional cooling techniques will be utilised …..


07/06/99

‹#›Page

Thermal Analysis of PCBs & Solder Joint Reliability

Bill Bradshaw,Senior Thermal Engineer,

GMAv RCS-Edinburgh.


07/06/99

‹#›Page

Thermal Analysis of PCBsand Solder Joint Reliability

Agenda Computer thermal modelling of PCB assemblies Interpretation of results Verification using IR camera Solder joint fatigue parameters Calculation and measurement of PCB CTE


07/06/99

‹#›Page

Computer modelling

Two types of analysis

Steady state Transient

Target: ensure reliability is not compromised by thermal environment


07/06/99

‹#›Page

Computer Modelling Input

PCB outline and construction Component layout Component thermal data: JC and power

dissipation Component lead geometries Component masses Operating environment (worst case)


07/06/99

‹#›Page

Thermal Analysis Results

Component temperatures- Junction- Case

PCB temperatures- Top surface- Centre- Bottom surface

Coloured thermal contour map


07/06/99

‹#›Page

Table of temperatures***** TEMPERATURE(C) INFORMATION ***** APPLIED COMPONENT BOARD LAYER U-NAME PART NAME POWER JUNC TOP BOTTOM FRONT MID BACK -------- ---------------- -------- -------------------- -------------------- R1 RN 0.025 66.87 66.64 65.41 64.55 64.48 63.83 R2 RN 0.025 65.15 64.92 63.69 63.17 63.12 62.55 U1 UPX 1.000 78.26 75.75 75.82 73.26 72.93 71.81 U2 UPX 1.000 77.51 75.00 75.07 72.43 72.11 71.13 U3 UPX 1.000 69.02 66.51 66.57 64.02 63.70 62.50 U4 SILC 0.075 58.45 58.18 57.97 57.16 57.13 56.71 U5 SILC 0.075 59.91 59.64 59.44 58.73 58.70 58.35 U6 TCON 0.100 65.31 64.96 64.68 63.87 63.83 63.38 U7 22V10 0.250 76.59 73.19 65.17 62.18 61.88 60.98 U8 512K8 0.375 86.38 83.69 77.53 75.60 75.37 74.47 U9 512K8 0.375 86.57 83.87 77.71 75.53 75.26 73.72 U10 512K8 0.375 85.33 82.64 76.48 74.02 73.80 72.51 U11 512K8 0.375 82.45 79.76 73.60 71.05 70.76 69.37 U12 512K8 0.375 86.54 83.85 77.69 75.51 75.30 74.42 U13 512K8 0.375 86.80 84.10 77.94 75.46 75.22 73.68


07/06/99

‹#›Page

Colour contour thermal map


07/06/99

‹#›Page

Create thermal report containing:

Assumptions including boundary conditions Predicted component and PCB temperatures Colour thermal contour map Requirements

• thermal vias• changes to PCB construction• relocation of hot components


07/06/99

‹#›Page

Infra-red scanning

Used for- verifying thermal analysis- fault finding faulty components short circuits in PCBs


07/06/99

‹#›Page

Typical Infra-red image


07/06/99

‹#›Page

Infra-red image of fault in PCB


07/06/99

‹#›Page

Solder joint reliability

Some factors affecting the fatigue life of solder joints Stand off height Lead shape Component size Crystalline structure of solder joint Type of solder Conformal coating Temperature extremes Dwell time at temperature extremes Temperature ramp rate Shape of the solder joint Difference in CTE between components and PCB


07/06/99

‹#›Page

PCB coefficient of thermal expansion

CTE is affected by: dielectric material copper thickness constraining layers heat ladder PCB mounting


07/06/99

‹#›Page

Good leadless componentsolder joints


07/06/99

‹#›Page

Fatigued leadless componentsolder joints

Cracks


07/06/99

‹#›Page

Spreadsheet calculation of CTE

Performed before thermal analysis

Require: Exact PCB layer construction Material physical properties

Young’s Modulus or tensile modulusCTE


07/06/99

‹#›Page

CTE spreadsheet calculationA B C D E F

SSPE, AB side PCB, 3990/09871CTE Y Mod psi ThicknessC*D E*B

copper track 16 17 1.54 26.18 418.88Invar 1 21FR4 16 2.5polyimide/glas 14 3.5polyimide film 70 1.7Carbon 3.4 5.3PI/aramid 7.5 2.26 22.2 50.172 376.29Cu core 16 17 1.4 23.8 380.8molybdenum 4.9 47Epoxy/Kevlar 6.5 4.4Aluminium 23 10Ablefilm 100 1.9

25.14 100.152 1175.97

Overall CTE 11.74


07/06/99

‹#›Page

Measuring CTE

Use strain gauges- first gauge bonded on sample of known CTE- second gauge bonded on test PCB

Construct Wheatstone Bridge circuit Measure voltage offset across bridge at set

temperatures Calculate CTE


07/06/99

‹#›Page

Wheatstone Bridge circuit

Test Gauge

Reference Gauge

V out

120 Ohms

V in

120 Ohms

Temperature cyclingChamber

CTE sample = 4(Vout (high temp) - V out (low temp)) + CTE reference Vin * * T


07/06/99

‹#›Page

CTE: measured v calculated

Measured value- X axis 9.9 ppm- Y axis 10.6 ppm

Calculated value- Both axes 11.7 ppm


07/06/99

‹#›Page

Solder joint fatigue calculations

Fatigue life of LCCC solder joints

0

500

1000

1500

2000

2500

3000

0 2 4 6 8 10 12

CTE PCB minus CTE component (ppm)

Num

ber o

f cyc

les

68 pin lcc

44 pin lcc

32 pin lcc

Design aim200 cycles


07/06/99

‹#›Page

Finally:

When the following checks are deemed to be satisfactory, we can proceed with the design:

computer thermal modelling CTE calculations and measurements fatigue life calculations temperature cycling tests


07/06/99

‹#›Page

Speaker Biography

Bill Bradshaw (Senior ThermalEngineer).

Bill joined Ferranti in 1975 afterstudying Applied Physics. He workedinitially as a Gyro Design Engineer andlater moved to Radar Systems wherehe joined the InterconnectionsEngineering Group where he definedthe Static Handling Procedures andquality standards for solderingprocesses. For the last 18 months Billhas worked in the ThermalEngineering Group, where heperforms Thermal Modelling ofhardware designs and thermalassessments of hardware using IRcamera techniques.


07/06/99

1Page

PCB Assembly & Soldering Process

Peter Dalglish,Chief Interconnections Engineer,

GMAv RCS-Edinburgh.


07/06/99

2Page

Agenda

PCB Assembly and Soldering Process- PCB Assembly Process

Solder Paste Measurements Component Pick and Place Placement of Fine Pitch Components Convection Reflow

- Cassette Assembly Process Assembly Process Vacuum Process Adhesive Curing Process

- DFSSM Scorecard


07/06/99

3Page

The Example Assembly


07/06/99

4Page

PCB Assembly Process

Pre-Assembly

&Inspection.

5

De-gold& Tin

Components

2

LoadComponents

LoadDrive Tape,Inspection.

3

DessicantCabinet,ScreenPrint

Boards.

6

Pick & Place,Convection

Re-flow,Inspection.

7

Boardsin PreBakeOven.

4

PrioritizeBoards &

SplitKit.

1

PCBs

Components : De-gold & tinning required.

Components : De-gold & tinning not required.


07/06/99

5Page

Solder Paste Measurements


07/06/99

6Page

Component Pick and Place


07/06/99

7Page

SMT Hot Gas Workstation


07/06/99

8Page

Convection Reflow


07/06/99

9Page

Convection Reflow Set Points

PCBTopBottom

Set °C 180°C 200°C 300°C

170°C 180°C 200°C 295°CActual

Set 170°C 180°C 200°C 300°C

170°C 180°C 200°C 295°CActual

Conveyor Speed SettingConveyor Speed Actual

28.0

27.1

cm/min.cm/min.

Conveyor Belt

170


07/06/99

10Page

Convection Reflow Thermal Profile


07/06/99

11Page

Cassette Assembly Process

ReceiveBuilds from

Stores

Start1

Prioritizeand Placein Queue

2

Screen Printwith

Adhesive

3

Path for Brazed Skinned Cassettes

ApplyPre-formedAdhesive &

VacuumBag

6

Path for Brazed Skinnless Cassettes

Cure Boardsand

MeasureAdhesiveThickness

4

AssembleCassette& Cure

5

CureCassette

7 Inspection

8


07/06/99

12Page

Skinless Cassette Structure


07/06/99

13Page

Cassette Assembly Drawing


07/06/99

14Page

DFSSM ScorecardDSSM SCORECARD FOR PCB ASSEMBLIESThis Scorecard is not a rule checker and assumes that the design adheres to GM5-01-M1

PRODUCT ECR 90 Radar PCB THICKNESS mmASSY DESC RGC SSPE (A/B SIDE) (Microwire) PCB NO OF LAYERSPART NO 390/02762 THERMAL PLANES Y/NDATE 17/02/99 Heavy Hitters contributing mo

ITEM DESCRIPTION CCT QTY PIN/ COMPONENT Thermal SM SM PROCESSNo REF LEAD TYPE Bonding LEAD CHIP WAVE

COUNT SURFACE Presolder PITCH SIZE REFLOWEACH THROUGH Yes, No mm e.g. 1206 HAND

optional optional mandatory mandatory mandatory mandatory mandatory mandatory mandatory mandatory1 QBS U1-4 4 66 s n 0.65 r3 QBC U5 1 66 s n 0.65 r5 SILC U6-10 5 66 s n 0.65 r7 EC u11 1 192 s n 0.65 r9 UPX U13 1 192 s n 0.65 r

11 TCON U14 1 66 s n 0.65 r13 EMID U15 1 24 s n 1.25 r15 HAU U12 1 192 s n 0.65 r17 Microcircuit Digital U87 1 20 s n 1.25 r21 ICD CMOS U16-31 16 28 s n 1.25 r23 ICD CMOS U32-35 4 32 s n 1.25 r25 ICD CMOS U36-39 4 68 s n 0.65 r28 ICD CMOS U40-43 4 32 s n 1.25 r29 ICD CMOS U48-49 2 32 s n 1.25 r31 ICD Hex U50-51 2 20 s n 1.25 r33 ICD Hex U52-53 2 20 s n 1.25 r35 U54 1 20 s n 1.25 r

37 ICD Buffer U55-58 4 20 s n 1.25 r39 ICD Buffer U59-70 12 20 s n 1.25 r41 ICD Buffer U71-76 6 20 s n 1.25 r43 ICD Shift Register U77 1 20 s n 1.25 r45 ICD Octal Register U78-84 7 20 s n 1.25 r47 ICD Buffer U85 1 28 s n 1.25 r49 ICD Buffer U86 1 28 s n 1.25 r51 Capacitor C1-5 5 2 s n 2412 r53 Capacitor c6 1 2 s n 2412 r55 Capacitor c 95 2 s n 805 r56 Capacitor c 8 2 s n 1206 r57 Resistor R1 1 2 s n 1206 r

ICD Hex

T A R G E T S I G M A L E V E L I N P U T

O F D 3 6 3 3

D P U p r e s o l d e r t o u c h - u p / i n s p 9 5 . 4 8 4 1F T Y r o l l e d t o u c h - u p / i n s p & t e s t 0 . 0 0 %P E C D P M O 2 6 2 8 2

S i g m a L e v e l 3 . 4 4

D P U p o s t in s p 0 . 1 6 2 5F T Y r o l le d t e s t o n ly 8 5 . 0 1 %P E C D P M O 4 5

S ig m a L e v e l 5 . 4 2

H I S T O R YP r e - t o u c h - u p , i n s p e c t i o n & t e s t

D A T E D P U S I G M A F T Y D a t e C a p S h t .1 8 / 0 2 / 9 9 9 5 . 4 8 4 1 4 1 3 . 4 4 0 . 0 0 % 0 4 / 0 8 / 9 8

D u e t o t h e s p a c e r e q u i r e d o n l y o n e l i n e o f c a l c u l a t i o n s

i s a v a i l a b l e . T o i n s e r t f u r t h e r c a l c u l a t i o n s o n e o f t h e t h e s e b u t t o n s m u s t b e c l i c k e d t o s u i t r e q u i r e m e n t s : -

1 0 l i n e i t e m sr e q u i r e d



1 0 0 l i n e i t e m sr e q u i r e d


07/06/99

15Page

Summary

Change in board material gives substantial weight saving.

Removal of constraining layers. Makes the reflow process easier. Reduces overall board thickness. Increases the choice of board supplier. Rework easier to control. More cassette in box i.e. reduce pitch. Manufacturing window easier to

control/standardize.


07/06/99

16Page

Speaker Biography

Peter Dalglish (Chief InterconnectionsEngineer).

Peter began his career as a MechanicalDesign Engineer in the machine toolindustry. For the last 27 years he hasspecialised in electronic packaging formilitary avionics. Since 1989 he has beenresponsible for the InterconnectionsEngineering Group within the RadarSystems Division in Edinburgh. Latelyhis role has been expanded to managethe Thermal and Stress EngineeringGroups in Edinburgh and act as Head ofDiscipline for Mechanical Engineeringacross Radar and CountermeasuresSystems.


07/06/99

‹#›Page

DESIGN FOR MANUFACTUREPCB Fabrication

Jack Alexander,Senior Interconnections Engineer,

GMAv RCS-Edinburgh.


07/06/99

‹#›Page


07/06/99

‹#›Page

Layout &Routing

ManufacturingData Package

PCBFabricator

PCBFabrication

ManufacturingRules

PCBTechnologies

FabricatorComments

InterconnectionEngineer

Data PackageEdit

PCB DesignChecklist

Design RulesDatabase

DesignConcept

DesignReview

PCB DesignRequirements


DesignChecklist

ManufacturingCapability

BoardTechnology


DESIGN FOR MANUFACTUREManufacturing Data Package Generation


07/06/99

‹#›Page

DESIGN FOR MANUFACTURABILITY8 Layer Multilayer

Buried Via Inner Layers


07/06/99

‹#›Page

DESIGN FOR MANUFACTURABILITY8 Layer Multilayer

PlatedBuried

Via Holes

Plane Clearance

Polyimide Non-Woven Aramid

Copper Foil + Plating

Plane Connection

OverallThru' Plated

Hole

Split Plane Division

Polyimide Non-Woven Aramid Pre-Preg


07/06/99

‹#›Page

DESIGN FOR MANUFACTURABILITYKEY PROCESS ROUTE

Data PackageEdit

DrillingProcess

T.P HoleConditioning& Electro-lessCopper Plate

Inner LayerImage Transfer

Complete

1 2

5 6

Inner LayerEtch

3BondingProcess

4

OuterLayer Etch

9

ClearanceHole Profile

10Final

Inspection

11

Outer LayerImage Transfer

7

Electroplating

8

Start


07/06/99

‹#›Page

DESIGN FOR MANUFACTURABILITYFront End Edit

Order and Data received from customer, is

processed.

•Drawings & specifications examined

•Customer liaison

•Tooling instructions prepared

•Data is checked to manufacturing capabilities

•Production route & materiel's are planned

•Job sheet raised & loaded to production


07/06/99

‹#›Page

DESIGN FOR MANUFACTURABILITYPLATED BURIED VIA HOLES

PlatedBuried

Via Holes

Polyimide Non-Woven Aramid

Copper Foil + Plating

Polyimide Non-Woven Aramid Pre-Preg


07/06/99

‹#›Page

DESIGN FOR MANUFACTURABILITYINNER LAYER EXPOSURE

The laminated boards are exposed to strong Ultra-Violet light through an appropriate

artwork for the job. Where the light shines through the clear parts of the artwork, the blue resist underneath is hardened. The areas of the artwork shown as brown, will block the light

and the blue resist underneath will remain soft

PhototoolEtch resist

U/V LIGHT SOURCE


07/06/99

‹#›Page

DESIGN FOR MANUFACTUREINNER LAYER ETCH

Printed feature after etching & stripping •After stripping, the printed circuit features can be seen as copper conductors.

Copper track


07/06/99

‹#›Page

DESIGN FOR MANUFACTURABILITYDRILLING

High speed spindle machines are used for high accuracy & hole quality, which is confirmed by Laser during drilling. 4 & 5 spindle machines also work on a similar principle

960 Tool magazineStack of boards being drilled (Aluminum entry and Techboard exit materials)

Each spindle is capable ofdrilling small holes at speeds of110,000 R.P.M


07/06/99

‹#›Page

DESIGN FOR MANUFACTURABILITYDRILLING

If the boards are multilayers, then it isimportant that the holes are in alignment withthe inner layer features (pads), as shown in thecross section.

Exit material

Entry material

To prevent burrs during drilling Stack of boards

to be drilled

INNER LAYER

Hole drilled

through laminate

Base copper


07/06/99

‹#›Page

DESIGN FOR MANUFACTURABILITYELECTROPLATING

Boards are jigged onto flight bars (above) which are automatically carriedthrough a sequence of cleaning tanks, and then electrolytically plated withCopper.The plating window is 1.4 square metres (15 square feet) x2A pair of flight bars of plated work is completed every 16 to 20 minutes

RectifiersTransporter


07/06/99

‹#›Page

DESIGN FOR MANUFACTURABILITYELECTROPLATING

This process is to build up enough thickness of copper in the holes to carry thesignals of the circuit when finished. This copper is plated onto the carbon depositleft from the direct plating (Black Hole). There is a top coat of Tin plated asprotection during etching

Cross section view

Plated Through

Holes (PTH)

. ...

.

.

. .. . ..

.. ...

...

Tin plating

Plating resist

Plating resist

Base copper

Base copperPlated copper

Plated Tin

CarbonCopper plating Plating resist


07/06/99

‹#›Page

DESIGN FOR MANUFACTURABILITYCLEARANCE HOLES AND PROFILE

On a 3 spindle C.N.C machine, boards are routed in stacks using high speed carbide cutters (shown below).

With 18 tool positions, non- PTH holes can be drilled at the same operation.

Air bearing spindlesrotating at 24.000r.p.m, cut a stack ofthree boards to size,and to within a 0.10mm tolerance

Carbide Routing cutter


07/06/99

‹#›Page

DESIGN FOR MANUFACTURABILITYFINAL INSPECTION

Chemical analysis and product testing

Product Testing

Video assisted Microscopy


07/06/99

‹#›Page

DESIGN FOR MANUFACTURABILITYIn Conclusion

PARTNERSHIP

DESIGN RULES DATABASE

MANUFACTURING RULES DATABASE

JOINT DATABASE REVIEW

RIGHT FIRST TIME


07/06/99

‹#›Page

Speaker Biography

Jack Alexander (Senior InterconnectionsEngineer).

Jack has worked in the electronicsindustry for the past 38 years. After a briefspell in NC part programming formachined components, he transferred toan in-house unit manufacturing printedcircuit boards for a period of 20 years.Latterly he held the position of DeputyManager for the PCB Fabrication Group.This covered all aspects of designrequirements for the manufacture ofspecialised, complex CTE controlledmulti-layer PCBs for the AvionicsIndustry. For the last 9 years he hasworked in the InterconnectionsEngineering Group, advising on designfor manufacture and acting as a point ofliaison with the company supplier base.

PCB Europe : Design for Manufacture

Radar and Countermeasures Systems07/06/99

‹#›Page

PCB Design

Andrew Barker,Physical Design Team Leader,

GMAv RCS-Edinburgh.



‹#›Page

Agenda High Level PCB Design Process.

- EDA Library Process Receive Package

- Design Checklist- MCAD Interaction

PCB Layout- Methodology and Design Example

Interaction with Thermal Engineering PCB Routing

- Methodology and Design Example Post Processing PCB Design Process - Summary Conclusions



‹#›Page

Our Goal !



‹#›Page

PCB Design Process - High Level

ReceivePackage

ThermalSimulation

PCBRouting

PostProcessing

PCBLayout

DesignStart

DesignComplete

1 2 3 4 5

i) Functionii) Checksiii) Sign Off

‘n’

Data Input Data Output

Requirements foreach Discipline

Each step is represented by



‹#›Page

EDA Library ProcessThe Requirement

An ECAD Library Entry will haveSchematic SymbolSimulation Models

e.g. SaberQuadSmartmodels

Geometry e.g. Outlines

FootprintsAttributes



‹#›Page

Library Design for AssemblyGoal - Fully Assembled, No Rework

RequirementsPlacement MachineFiducialsSolder ResistsSolder ScreensModification Capability

Design ImpactsComponent DensityPlacement MachinesSolderibilityRework



‹#›Page

Library Design for FabricationGoal - Manufacturable PCB, High Yield

RequirementsEtchingPad and Track SizesPlated Hole SizesClearancesResists

Design ImpactsComponent DensityTracking DensityBoard Thickness / Number of Layers



‹#›Page

Library Design for TestGoal - Fully Assembled, Testable Board

RequirementsTest Point Access

Design ImpactsComponent DensityBreakout Via Pattern / Size



‹#›Page

Library Design for Thermal/Stress

Goal - Reliability

RequirementsThermal ModelsLayout Info - Build, Layers, Copper Coverage

Design ImpactsFootprint SizesTV Geometries (Number of Holes)



‹#›Page

Stage 1 : Receive PackageReceivePackage

ThermalSimulation

PCBRouting

PostProcessing

DesignStart

DesignComplete

1PCB

Layout

2 4 53

MCAD Drawings / DataData Sheets

Checklist

Any Additional Information

Contents

Board Build - TechnologyGeometry Library Shortfall

Create Board Geometry

Enter into Progress System



‹#›Page

PCB Design ChecklistPRINTED WIRING BOARD (PCB) DESIGN CHECK LISTAT DESIGNER -- EDPG INTERFACE

Ref.No.RMS/0170Issue.8

PRODUCT CODENO.

BOARD TITLE PCB DETAIL DRG NO ISSUE CU ISSUE

LRU TITLE SUB - UNIT TITLE

DESIGN DATA LOCATIONDesign Soft Path NameDesign Data Storage/Archive Location.CURRENT REQUIREMENTS :

VOLTAGE REQUIREMENTS:

OTHER SPECIAL FEATURES:

FURTHER INFORMATION MAY BE REQUIRED BY EDPG ON FINAL BOARD BUILDELECTRICAL DESIGN ENGINEERNAME (BLOCK CAPITALS): SIGNATURE.........................................DATETEL. NO.

1 SYSTEM QUESTIONS REPLY1.1 Have standard connector pins been used ? ?1.2 Have sufficient ground and power pins been used ? ?1.3 Is each sub function a complete entity ? ?1.4 Has expansion contingency been specified ? ?1.5 Has a preliminary design review been held ? ?1.6 Does the circuit design require mixed technology ? ?1.6 Are the circuit symbols / references in accordance with BS, MIL, RSD local

procedures ??

1.7 Comments:--

2 COMPONENT QUESTIONS2.1 Has the printed wiring board thermal coefficient of expansion (TCE) been considered. ?2.2 Has cognisance of this been made in connection with the largest component. ?2.3 If applicable, what is the perceived T.C.E. value required ?.2.4 Are all components PCB mountable ? ?2.5 Have approved components been used ? ?2.6 Are all components specified by their generic type ? ?2.7 Are all components suitable for automatic placement ? ?2.8 Are all discrete components available on tape ? ?2.9 Are all components suitable for vapour phase soldering and able to withstand 215°C

for 30 - 40 seconds ??

2.10 Are all components suitable for wave soldering and able to withstand 255°C for 3seconds on solder side and 180°C approx on component side ?

?

2.11 Convection reflow soldering. State temperature window for the lowest temperaturerated component.

2.12 Can fully loaded PCB withstand oven preheat of 100°C for 2 hours ? ?2.14 Are all heavy components identified/adequately supported ? ?2.15 How many (with details) of single source components ? ?2.16 Where the circuit design requires mixed technology, has the PCB assembly

department been consulted ??

PRINTED WIRING BOARD (PCB)Design Approval Status

Ref.No.RMS/0170Issue.8

PRODUCT CODENO.

BOARD TITLE PCB DETAIL DRG NO ISSUE CU ISSUE

ADDITIONAL INFORMATION TO BE SUPPLIED BY IDO TO EDPG.DRG NO ISSUE DATE SUPPLIED

BOARD PROFILE LAYOUTPIL PARTS LISTECAD NET LISTCIRCUIT DIAGRAMUSED ON ASSEMBLYAD NO IF APPLICABLE

DEPARTMENT AUTHORITY

INTEGRATED DESIGN OFFICE

Name (Block capitals)Signature........................................................................Date:

DESIGN ENGINEERMECHANICAL


DESIGN ENGINEERTESTABILITY


DESIGN ENGINEER INTERCONNECTIONSBOARD TECHNOLOGY


DESIGN ENGINEERTHERMAL


On completion of the above signatory list, the following to be completed / signed by Engineer or LRI Engineer.

SCHEMATIC / CIRCUIT DIAGRAMAPPROVAL


NET LISTAPPROVAL


COMPONENT LAYOUTAPPROVAL


DESIGN ROUTINGAPPROVAL


DATA PACKAGE RELEASEDFOR MANUFACTURE. EDPG.


Section headers onsheets 1 to 5 are -

SYSTEM

COMPONENTS

ELECTRICAL

SOFTWARE

TEST

B.I.T.

TECHNOLOGY

THERMAL

Sheet 5Sheet 1



‹#›Page

MCAD InteractionMCAD Drawing data

is Imported to ECAD library

ECAD Design data is Exported to

MCAD Drawings



‹#›Page

PCB Layout - MethodologyReceivePackage

ThermalSimulation

PCBRouting

PostProcessing

DesignStart

DesignComplete

1PCB

Layout

2 4 5

COMPROMISE

3

Component

LibraryFixingsRestrictions - HeightConnector PositionsMECHANICAL

FiducialsProximityASSEMBLY

Near cold edgeHot Components - more than 50mWTHERMAL

Components near ConnectorsASICS - Components around ASICS

Remainder filled in

Connectors

Memory

ELECTRICAL



‹#›Page

PCB Layout - Example Design



‹#›Page

Interaction with Thermal GroupReceivePackage

ThermalSimulation

PCBRouting

PostProcessing

DesignStart

DesignComplete

1PCB

Layout

2 4 53

Data Transferred to Thermal Engineering

Thermal Analysis

Report Prepared

Sign OffRecommendations(TV’s or Changes)



‹#›Page

Routing - MethodologyReceivePackage

ThermalSimulation

PCBRouting

PostProcessing

DesignStart

DesignComplete

1PCB

Layout

2 4 53

Breakout PatternsSubstitute Via type

Manual or Autoroute

DRC Checks• Spectra CCT• BoardStation• Valor

Design RequirementsSpecial InstructionsRouting Rules - Crosstalk

Net Classes• Critical Nets• Busses• Long Nets• Short Nets• Remainder



‹#›Page

Routing - Example Design8 Layers -1 - Footprints1 - Plane layer2 x 2 Buried Vias1 - Plane layer1 - Pads for Tph’s

Connections - 2841Tph’s - 4028B/Vias - 3303Components - 218Track - 0.005Gap - 0.006Pad - 0.024-0.018Via - 0.018Hole - 0.008

Board size -230 x 160 mm

Thickness - 1 mm



‹#›Page

DRC Checking with Valor



‹#›Page

Post ProcessingReceivePackage

ThermalSimulation

PCBRouting

PostProcessing

DesignStart

DesignComplete

1PCB

Layout

2 4 53

DFM ChecksCompleted

BoardDrawings

TestData

PlacementData

AssemblyDrawings

GerberData

ScreenData

DrillingData

HeatplateData



‹#›Page

High Level Process - Reprise

ReceivePackage

ThermalSimulation

PCBRouting

PostProcessing

PCBLayout

DesignStart

DesignComplete

1 2 3 4 5

Checklist

MCAD

GeometryLibrary

Assembly

Fabrication

TestECADLibrary

Data Sheets& Standards



‹#›Page

Summary

Multi Disciplinary Library Parts A Structured Logical Approach Consider Each Process Stage (Data In versus Data Out) Checklists Be Prepared to Compromise Bi-directional Communications

USING

WILL ACHIEVE A COMPLETE WELL THOUGHT OUT DESIGN



‹#›Page

Conclusion

PCBDESIGN

THERMALENGINEERING

TEST

ELECTRICALENGINEERING

PCBFABRICATION

PCBASSEMBLY

STRESSENGINEERING

MCAD

INTERCONNECTIONSENGINEERING



‹#›Page

Speaker Biography

Andrew Barker (Physical Design Team Leader). Andrew completed an apprenticeship at Rosyth

Royal Naval Dockyard before joining Ferranti’sPCB Design Group in 1979 to work on Thin FilmHybrid designs. PCB design followed in the early‘80s using Digitised Colour Masters - he missedout on taped masters by a few days ! - to designDIL, Double Sided and 8 layer PCBs. He wasIntroduced to ECAD in 1983 which extended layercounts and via types thus enabling SurfaceMount, Depth Drilled and Hybrid techniques. In1984 Andrew completed his first Surface Mount0.006” track and gap multi-layer metal cored PCB.By 1993 he had moved on to Microvia PCBs with0.003” track and gap. His current role is PhysicalDesign Team Leader with 7 PCB & HybridDesigners using Mentor Graphics, Valor, InterceptPantheon, Zuken Redac and Spectra CCT.

Prediction of Convection Reflow Soldering Profiles

Speaker

Bruce Wilkinson, Thermal Engineer

BAE Systems

Crewe Toll

Edinburgh

Introduction

• Small Batch Size

• High Unit Cost

• Heavy PCB assembly difficult to solder

• Evaluated / measured process - not up to it!

• Evaluated other machines

• Computer modelled process

• Result - successfully soldered assembly

• Questions will be answered at the end

History

• Unable to effectively solder large surface mount hybrids to heavy PCB in convection reflow soldering oven

• Largest hybrid weighed 35 grams, it was 75mm long, 40mm wide, 8 mm high

• PCB was 2.0 mm thick, 10 copper layers, 2 Cu/In/Cu layers, non-woven aramid construction

Assembly Photograph

Measured Process Parameters

• Measured heat transfer coefficient of our convection reflow oven

• Measured heat transfer coefficient of subcontractor’s convection reflow ovens

• Used slab of aluminium fitted with thermocouples

Plate used to Measure HTC

Measured Heat Transfer Coefficients

Zone 1Zone 2

Zone 3Zone 4

Zone 5Zone 6

Zone 7

Sub-Contractor CRO 1

BAE Systems CRO

Sub-Contractor CRO 20

10

20

30

40

50

60

70

80

90

Heat Transfer Coefficient (W/m^2K)

Heating Zones

Oven

Comparison of Heat Transfer Coefficients

Convection Reflow Oven Model Requirements

• “Soldersim” from ANSOFT

• Number of zones and their lengths

• Gaps between zones (if applicable)

• Heat transfer coefficient of all zones

• Recommended solder profile

• Best estimate oven settings– Zone temperatures– Conveyor speed

Model Oven Settings

Temp. Settings

h1 = 230Ch2 = 170Ch3 = 170Ch4 = 210Ch5 = 260Ch6 = 280Ch7 = 315Cc1 = 109Cc2 = 86Cc3 = 77C

PCB Assembly Model Requirements

• “PCB Explorer” by ANSOFT

• Two ways of collecting data:

• Transfer of data from PCB Design Group

• Build PCB data from scratch– PCB layer construction and shape– PCB and component material physical properties– Component layout– Component masses

Model Output

• Temperatures of all components on the PCB at any moment in time throughout the soldering process

• Temperatures at any position on the PCB at any moment in time throughout the soldering process

• Plots of temperatures against time for components and PCB

After 60 seconds

After 90 seconds

After 120 seconds

After 150 seconds

After 180 seconds

After 210 seconds

After 240 seconds

After 300 seconds

Thermal Contour Plot (210 seconds)

Temperature Plot

Model Adjustment

If the resulting temperature plots do not match the required solder paste profile, we can change:

– belt speed– zone temperatures

Trial & Error - Using Skilled Judgement and Experience

The required adjustment is usually obvious

Soldering Results

•PCB assembly soldered satisfactorily FIRST TIME

Picture of Solder Joints

Summary

• We need to model the soldering process due to:

small batch sizes

high unit cost

• We have successfully characterised the convection reflow soldering process

• We have used this information to computer model the soldering process

• The software modelling is especially useful for heavy PCBs and large components

• Most recently, the soldering process was successfully modelled for a large thick motherboard

Q = m Cp (Tpcbhot - Tpcbcold) / t

h = Q / A (Theater - Tpcbave)

Q = Heat Load

m = Mass

Cp = Specific Heat Capacity

Tpcbhot = PCB Hot Temperature

Tpcbcold = PCB Cold Temperature

Tpcbave = PCB Average Temperature

Theater = Zone Heater Temperature

h = Heat Transfer Coefficient

A = Area Being Heated

t = time


07/06/99

‹#›Page

Panel Questions & Answer Session