presentation available at front end card › doc › cer_apr-02 › fec.pdf · 1 roberto campagnolo...
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1Roberto Campagnolo – CERN EP-ED
Front End Card Front End Card -- status reportstatus report
Alice TPC Meeting, C.E.R.N. Alice TPC Meeting, C.E.R.N. -- 29/30 April 200229/30 April 2002
Roberto Campagnolo – CERN Ep-Ed
presentation available at http://cern.ch/ep-ed-alice-tpc/
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2Roberto Campagnolo – CERN EP-ED
• The New Front End Card
• Related Interfaces- new 40-bit Mezzanine ,- Termination/ Service card ,- Analog Test card
• Test and Measurements
• Conclusions
OUTLINE
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3Roberto Campagnolo – CERN EP-ED
Why a New Front End Card ?
The Old FEC Integrates :
• 8 PASA from CERES
• 64 discrete dual-channel ADC
• 16 ALTRO chip (4 channels prototype)
• 32 bit Read Out BUS
The New FEC Integrates :
• 8 Newest PASA
• 8 ALTRO –16 channels each
• 40 bit Read Out BUS
}
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4Roberto Campagnolo – CERN EP-ED
FEC - Circuit Board layout : The Ground plane
PASA
ALTRO Analog section
BC, Transceiversand ALTRO Digital
PASA to ALTRO connection in
differential mode
FRONT END CONNECTORS
ALTRO bus - RCU side
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5Roberto Campagnolo – CERN EP-ED
The New Front End Card: TOP view
HARWIN connectors
Read Out busconnectors
control busconnector
power supplyconnector
voltageregulators
current monitoring& supervision
ALTROs
ShapingAmplifiers
GTL/ PECL Read Out-Clock fan out
Board Controller
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6Roberto Campagnolo – CERN EP-ED
ALTROs
ShapingAmplifiers
GTLtransceivers
GTL/ PECL Sampling-Clock fan out
The New Front End Card:Bottom view
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7Roberto Campagnolo – CERN EP-ED
FECs – dimensional comparison
155
mm 24
0 m
m
190 mm 300 mm
New Front End Card Previous functional prototype
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8Roberto Campagnolo – CERN EP-ED
Front End Card - Test Set Up
PLDaPCI
PMC40 bitGTL
Interf.
GTLService/Termin.
Card
ALTRO – Bus ( 1m. length)
Logic St.Analyser
WaveformGenerator
F E C
AnalogTest-Card
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9Roberto Campagnolo – CERN EP-ED
The new Mezzanine for PCI-based RCU
New 40-bit Mezzanine card
DDL-SIU CONNECTORNew Picture !
NIM CONNECTORs( L1, L2, RDOCLK, ADCCLK)
GTL Transceivers
PCI CARD (PLDa)
PMC connectors
FPGA with PCI-core
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10Roberto Campagnolo – CERN EP-ED
The service card layout
ALTRO / GTL – bus Power supply
Logic State Analyzer probes
ALTRO-bus Power Supply
TerminationsResistor
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11Roberto Campagnolo – CERN EP-ED
Analog Test Card layout
Capacitors for the injection of the charge into the PASA
Capacitors to simulate thedetector Pad capacitance
Kapton cables to the FEC
Power Supply
From the Waveform Generator
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12Roberto Campagnolo – CERN EP-ED
Complete system overview
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13Roberto Campagnolo – CERN EP-ED
Self Test results : variable pattern on 128 channels
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14Roberto Campagnolo – CERN EP-ED
Communications with the FEC
Access to an Altro Register
( Write and Read )
Event download( Transfer )
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15Roberto Campagnolo – CERN EP-ED
GTL and internal bus Overall signal quality
GTL+ bus noise margin( more than 700 mV )
FEC internal data bus
Under-shoot : -1.22 V Over-shoot : 0.26 V
Channel cross-talk(less than 100mV)
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16Roberto Campagnolo – CERN EP-ED
FEC Power Consumption
• Board Controller : 140 mW
• Slow control circuitry : 5 mW
• ADC and Read Out Clock fan-out :~ 500 mW
• GTL transceivers : 60 mW
• 8 ALTRO : ~ 2060 mW
• 8 PASA : ~ 1530 mW
• Polarization circuitry: 7mW
• Power Regulators (20% avg. drop):~ 860 mW
TOTAL POWER CONSUMPTION : ~ 5200 mW => 40.5 mW / channel
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17Roberto Campagnolo – CERN EP-ED
Conclusions
Preliminary tests shown that the present version of Front end Card fully satisfiesthe requirements for the interface of the ALTRO chip to the read out bus.
Nevertheless the design features related to the analog section of the card ( PASA chips and related signals routing ) have still to be verified because of
the logic for the read-out of events by the RCU is still under construction.