presentation affarii rrhsolution

1 © Affarii Technologies Limited, 2010

June 2010


cellular network evolution

Macro Base Station   Central: RF, Baseband and Transport

Layer in the same cabinet near base of transmission tower.

 High site costs, inflexible upgrades.

“Remote Radio” Network  Distributed: Remote baseband connected to

Radio Head (RRH) located near the antenna using high speed optical link.

 Lower site costs, flexible upgrades.

Macro Base Station

Electrical cable

WAN backhaul

Baseband

Transport Layer

RF RRH

Distributed Base Station

= Remote Radio Head(RRH)

Optical Fiber/

Baseband Data

RRH RRH

Baseband

Transport Layer

WAN backhaul

U.E.

RRH

2G 4G

  Cellular Networks have evolved from a macro to distributed BTS architecture.   The key component in this new architecture is the Remote Radio Head (RRH).


remote radio head

  The RRH is responsible for converCng digital data on the opCcal link to RF carriers for radio transmission and recepCon.

  The RRH includes signal processing for Digital Up/Down Conversion (DUC/DDC), Crest Factor ReducCon (CFR) and Digital PredistorCon (DPD).

  By using an FPGA with DSP cells, SERDES, and soS processor blocks all digital funcConality can be included in a single reconfigurable FPGA device.

CPRI/OSBAI INTERFACE

RRH DIGITAL PROCESSING

GPIO/USER IO

RRH CONTROL PROCESSOR

ADAPTION

SY

NC

DDC

DPD

DUC+CFR

PA DAC

ADC

LOTX/DPD

LNA ADC

LORX

Optical link to baseband processing network.


RRH processor solution LaVce and Affarii provide all blocks necessary to build an RRH on ECP3.


RRU PROCESSOR

RX ADC

TX DAC

FBK ADC GPIO/USER IO

SDRAM INTERACE

GENERAL PURPOSE PROCESSOR (GPP)

ETHERNET MAC

SYN

C

DATA PROCESSOR

ADAPTION ENGINE

DIGITAL UP CONVERSION (DUC)

DIGITAL DOWN CONVERSION (DDC)

DIGITAL PRE-DISTORTION (DPD)

DUC CFR

DPD

DDC SERDES

PHY

SDRAM

I/O

Lattice Affarii

  Includes CFR and DPD blocks for peak reducCon and amplifier linearizaCon.

  Low resource DUC and DDC designs for common standards such as WCDMA, LTE and WiMAX.


crest factor reduction (cfr)

CFR CLIP

SAMPLE

FILTER GEN

AGC PAPR

Crest Factor ReducCon:

  Reduces signal peak level to reduce amplifier size and cost.

  Supports mulC-‐carrier waveforms up to 20MHz bandwidth.

  Allows configuraCon of number of stages, elements and effecCve filter length.

  Automated training algorithm requires no knowledge of the channel configuraCon.

  Provides input and output signal scaling to minimise noise and use full DAC range.


digital predistortion (dpd)

QMC EQU DPD

ADAPTION MEASURE Digital PredistorCon:

  Corrects analog distorCon in the PA device, reducing size, power consumpCon and cost.

  Supports mulC-‐carrier waveforms up to 20MHz bandwidth @ 122.88Msps.

  Provides 20-‐30dB of ACLR correcCon with memory effect.

  CompaCble with Class AB and Doherty amplifiers using LDMOS and GaN transistors.

  Configurable memory and equaliser lengths for design opCmisaCon.

dBm

30 20 10

0 -10 -20 -30 -40 -50 -60

40 Unlinearised Linearised (Memory)

Start: 2.0550 GHz Stop: 2.1450 GHz Res BW: 100 kHz Window: 66.66 uS 9 .00 MHz/Div

LDMOS 20W CLASS AB - 4CH WCDMA Burst Measurement


DPD power advantage

commercial in confidence

DPD CORE – POWER CONSUMPTION ESTIMATE

DEVICE CONDITION STATIC DYNAMIC TOTAL

LFE3-‐70E-‐8FN484 Typical @ 25C 270mW 300mW 570mW

High End SoluAon 25C -‐ 800mW -‐

  DPD soluCon integrates both adapCon and correcCon funcConal onto the FPGA device; no external processor is required.

  DPD block offers best dynamic power consumpCon per antenna for a programmable logic soluCon:

  SoluCon use less than half the dynamic power of compeCng high end devices.

50% LESS POWER


RRH signal path solution

  WCDMA reference design implements DSP signal path for 4 channel RRH .

  Device technology is ECP3-‐150-‐8 device.

  Includes 64 tap 4CH DUC and DDC channel filters.

  Supports CFR and DPD operaCon up to 20MHz bandwidth at 122.88Msps.

  Including CPRI and control processor funcConal blocks adds ~4K extra slices.

RRH : LFE3-‐150E-‐FPBGA1156-‐8 RESOURCE SLICES EBR MULT MHz

VALUE 27K 136 132 184MHz

RX ADC

TX DAC

FBK ADC


RRU PROCESSOR

GPIO/USER IO

SDRAM INTERACE


ETHERNET MAC

ADAPTION ENGINE

DIGITAL UP CONVERSION

SYN

C

DIGITAL PRE DISTORTION

SERDES

ETHERNET PHY

SDRAM

I/O

DIGITAL DOWN CONVERSION

CREST FACTOR REDUCTION

Signal path Components


production & test support   High speed serial interface for

development and product test.

  Supports test and analysis functions: –  Signal generation and playback. –  Real time signal measurement.

  Allows in-circuit monitoring and debug of TRX operation.

  Test Development Kit: –  USB interface module. –  Windows TM USB driver and C/C+

+ interface library. –  Octave/Matlab TM interface for

signal generation and analysis.

  Product demonstration and production test examples.

commercial in confidence

affarii digitalTRX

TCK TDI TDO TDS


development tools •  Development tool uses DPD

test interface to analyse data from live or test sources.

•  Tools support measurement of waveform to check standard conformance.

•  Contribution of analog and digital components to transmit quality can be measured.

•  Characterisation of PA linearity including thermal and reactive effects can be performed.


  SoluCon supports integraCon of all RHH processing into a single device.

  Includes high performance CFR and DPD soluCon:   20 MHz ModulaCon Bandwidth.

  Up to 30dB ACLR CorrecCon.   Lowest dynamic power for

programmable logic DPD soluCon:   570mW per antenna.

  Fully supported soluCon with PC based design analysis tools.

  End applicaCons: WCDMA, LTE, WiMAX/WiBro, DVB-‐T/S/H.

RRH soluCon summary RX ADC

TX DAC

FBK ADC


RRU PROCESSOR

GPIO/USER IO

SDRAM INTERACE


ETHERNET MAC

ADAPTION ENGINE

DIGITAL UP CONVERSION

SYN

C

DIGITAL PRE DISTORTION

SERDES DIGITAL DOWN CONVERSION

CREST FACTOR REDUCTION


Thank you

presentation affarii rrhsolution

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signal generation

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