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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor 9

    1.2 Pinout ListTable 1 provides the pinout listing for the P4080 by bus.Table 1. P4080 Pins List by BusSignal Signal DescriptionPackagePin NumberPinTypePower

    SupplyNotesDDR SDRAM Memory Interface 1

    D1_MDQ00Data A17I/O GVDDD1_MDQ01Data D17I/O GVDDD1_MDQ02Data C14 I/O GVDDD1_MDQ03Data A14 I/O GVDDD1_MDQ04Data C17I/O GVDDD1_MDQ05Data B17I/O GVDDD1_MDQ06Data A15I/O GVDDD1_MDQ07Data B15I/O GVDDD1_MDQ08Data D15I/O GVDDD1_MDQ09 Data G15I/O GVDDD1_MDQ10Data E12I/O GVDDD1_MDQ11Data G12I/O GVDD

    D1_MDQ12Data F16I/O GVDDD1_MDQ13Data E15I/O GVDDD1_MDQ14Data E13 I/O GVDDD1_MDQ15Data F13 I/O GVDDD1_MDQ16Data C8I/O GVDDD1_MDQ17Data D12I/O GVDDD1_MDQ18Data E9 I/O GVDDD1_MDQ19 Data E10I/O GVDDD1_MDQ20Data C11 I/O GVDDD1_MDQ21Data C10I/O GVDDD1_MDQ22Data E6I/O GVDDD1_MDQ23Data E7I/O GVDDD1_MDQ24Data F7I/O GVDDD1_MDQ25Data F11 I/O GVDDD1_MDQ26Data H10I/O GVDD

    D1_MDQ27Data J10I/O GVDDD1_MDQ28Data F10I/O GVDDD1_MDQ29 Data F8I/O GVDDD1_MDQ30Data H7I/O GVDD

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    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 10SemiconductorD1_MDQ31Data H9 I/O GVDDD1_MDQ32Data AC7I/O GVDDD1_MDQ33Data AC6I/O GVDDD1_MDQ34Data AF6I/O GVDDD1_MDQ35Data AF7I/O GVDDD1_MDQ36Data AB5I/O GVDDD1_MDQ37Data AB6I/O GVDDD1_MDQ38Data AE5I/O GVDDD1_MDQ39 Data AE6I/O GVDDD1_MDQ40Data AG5I/O GVDDD1_MDQ41Data AH9 I/O GVDDD1_MDQ42Data AJ9 I/O GVDDD1_MDQ43Data AJ10I/O GVDDD1_MDQ44Data AG8I/O GVDDD1_MDQ45Data AG7I/O GVDDD1_MDQ46Data AJ6I/O GVDDD1_MDQ47Data AJ7I/O GVDDD1_MDQ48Data AL9 I/O GVDDD1_MDQ49 Data AL8I/O GVDDD1_MDQ50Data AN10I/O GVDDD1_MDQ51Data AN11 I/O GVDDD1_MDQ52Data AK8I/O GVDDD1_MDQ53Data AK7I/O GVDDD1_MDQ54Data AN7I/O GVDD

    D1_MDQ55Data AN8I/O GVDDD1_MDQ56Data AT9 I/O GVDDD1_MDQ57Data AR10I/O GVDDD1_MDQ58Data AT13 I/O GVDDD1_MDQ59 Data AR13 I/O GVDDD1_MDQ60Data AP9 I/O GVDDD1_MDQ61Data AR9 I/O GVDDD1_MDQ62Data AR12I/O GVDDD1_MDQ63Data AP12I/O GVDDD1_MECC0Error Correcting Code K9 I/O GVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor11D1_MECC1 Error Correcting Code J5I/O GVDDD1_MECC2Error Correcting Code L10I/O GVDDD1_MECC3 Error Correcting Code M10I/O GVDDD1_MECC4 Error Correcting Code J8I/O GVDDD1_MECC5Error Correcting Code J7I/O GVDDD1_MECC6Error Correcting Code L7I/O GVDDD1_MECC7Error Correcting Code L9 I/O GVDDD1_MAPAR_ERR Address Parity Error N8I GVDD4D1_MAPAR_OUT Address Parity Out Y7O GVDDD1_MDM0Data Mask A16O GVDDD1_MDM1Data MaskD14 O GVDDD1_MDM2Data MaskD11 O GVDDD1_MDM3Data Mask G11 O GVDDD1_MDM4Data Mask AD7O GVDDD1_MDM5Data Mask AH8O GVDDD1_MDM6Data Mask AL11 O GVDDD1_MDM7Data Mask AT10O GVDDD1_MDM8Data Mask K8O GVDDD1_MDQS0Data Strobe C16I/O GVDDD1_MDQS1Data Strobe G14 I/O GVDDD1_MDQS2Data Strobe D9 I/O GVDDD1_MDQS3Data Strobe G9 I/O GVDDD1_MDQS4Data Strobe AD5I/O GVDDD1_MDQS5Data Strobe AH6I/O GVDD

    D1_MDQS6Data Strobe AM10I/O GVDDD1_MDQS7Data Strobe AT12I/O GVDDD1_MDQS8Data Strobe K6I/O GVDDD1_MDQS0Data Strobe B16I/O GVDDD1_MDQS1Data Strobe F14 I/O GVDDD1_MDQS2Data Strobe D8I/O GVDDD1_MDQS3Data Strobe G8I/O GVDDD1_MDQS4Data Strobe AD4 I/O GVDDD1_MDQS5Data Strobe AH5I/O GVDDD1_MDQS6Data Strobe AM9 I/O GVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor13D1_MCK2Clock V8O GVDDD1_MCK3 Clock W9 O GVDDD1_MCK4 Clock F1 O GVDDD1_MCK5Clock AL1 O GVDDD1_MCK0Clock Complements W5O GVDDD1_MCK1 Clock Complements V5O GVDDD1_MCK2Clock Complements V9 O GVDDD1_MCK3 Clock Complements W8O GVDDD1_MCK4 Clock Complements F2O GVDDD1_MCK5Clock Complements AL2O GVDDD1_MODT0On Die Termination AD10O GVDDD1_MODT1 On Die Termination AG10O GVDDD1_MODT2On Die Termination AD8O GVDDD1_MODT3 On Die Termination AF10O GVDDD1_MDIC0Driver Impedance Calibration T6I/O GVDD16D1_MDIC1Driver Impedance Calibration AA5I/O GVDD16DDR SDRAM Memory Interface 2

    D2_MDQ00Data C13 I/O GVDDD2_MDQ01Data A12I/O GVDDD2_MDQ02Data B9 I/O GVDDD2_MDQ03Data A8I/O GVDDD2_MDQ04Data A13 I/O GVDDD2_MDQ05Data B13 I/O GVDDD2_MDQ06Data B10I/O GVDD

    D2_MDQ07Data A9 I/O GVDD

    D2_MDQ08Data A7I/O GVDDD2_MDQ09 Data D6I/O GVDDD2_MDQ10Data A4 I/O GVDDD2_MDQ11Data B4 I/O GVDDD2_MDQ12Data C7I/O GVDDD2_MDQ13Data B7I/O GVDDD2_MDQ14Data C5I/O GVDDD2_MDQ15Data D5I/O GVDDD2_MDQ16Data B1 I/O GVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 14 SemiconductorD2_MDQ17Data B3 I/O GVDDD2_MDQ18Data D3 I/O GVDDD2_MDQ19 Data E1 I/O GVDDD2_MDQ20Data A3 I/O GVDDD2_MDQ21Data A2I/O GVDDD2_MDQ22Data D1 I/O GVDDD2_MDQ23Data D2I/O GVDDD2_MDQ24Data F4 I/O GVDDD2_MDQ25Data F5I/O GVDDD2_MDQ26Data H4 I/O GVDDD2_MDQ27Data H6I/O GVDDD2_MDQ28Data E4 I/O GVDDD2_MDQ29 Data E3 I/O GVDDD2_MDQ30Data H3 I/O GVDDD2_MDQ31Data H1 I/O GVDDD2_MDQ32Data AG4 I/O GVDDD2_MDQ33Data AG2I/O GVDDD2_MDQ34Data AJ3 I/O GVDDD2_MDQ35Data AJ1 I/O GVDDD2_MDQ36Data AF4 I/O GVDDD2_MDQ37Data AF3 I/O GVDDD2_MDQ38Data AH1 I/O GVDDD2_MDQ39 Data AJ4 I/O GVDDD2_MDQ40Data AL6I/O GVDD

    D2_MDQ41Data AL5I/O GVDDD2_MDQ42Data AN4 I/O GVDDD2_MDQ43Data AN5I/O GVDDD2_MDQ44Data AK5I/O GVDDD2_MDQ45Data AK4 I/O GVDDD2_MDQ46Data AM6I/O GVDDD2_MDQ47Data AM7I/O GVDDD2_MDQ48Data AN1 I/O GVDDD2_MDQ49 Data AP3 I/O GVDDD2_MDQ50Data AT1 I/O GVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor15D2_MDQ51Data AT2I/O GVDDD2_MDQ52Data AM1 I/O GVDDD2_MDQ53Data AN2I/O GVDDD2_MDQ54Data AR3 I/O GVDDD2_MDQ55Data AT3 I/O GVDDD2_MDQ56Data AP5I/O GVDDD2_MDQ57Data AT5I/O GVDDD2_MDQ58Data AP8I/O GVDDD2_MDQ59 Data AT8I/O GVDDD2_MDQ60Data AR4 I/O GVDDD2_MDQ61Data AT4 I/O GVDDD2_MDQ62Data AR7I/O GVDDD2_MDQ63Data AT7I/O GVDDD2_MECC0Error Correcting Code J1 I/O GVDDD2_MECC1 Error Correcting Code K3 I/O GVDDD2_MECC2Error Correcting Code M5I/O GVDDD2_MECC3 Error Correcting Code N5I/O GVDDD2_MECC4 Error Correcting Code J4 I/O GVDDD2_MECC5Error Correcting Code J2I/O GVDDD2_MECC6Error Correcting Code L3 I/O GVDDD2_MECC7Error Correcting Code L4 I/O GVDDD2_MAPAR_ERR Address Parity Error N2I GVDD4D2_MAPAR_OUT Address Parity Out Y1 O GVDDD2_MDM0Data Mask B12O GVDD

    D2_MDM1Data Mask B6O GVDDD2_MDM2Data Mask C4 O GVDDD2_MDM3Data Mask G3 O GVDDD2_MDM4Data Mask AG1 O GVDDD2_MDM5Data Mask AL3 O GVDDD2_MDM6Data Mask AP2O GVDDD2_MDM7Data Mask AP6O GVDDD2_MDM8Data Mask K2O GVDDD2_MDQS0Data Strobe A10I/O GVDDD2_MDQS1Data Strobe A5I/O GVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 16SemiconductorD2_MDQS2Data Strobe C2I/O GVDDD2_MDQS3Data Strobe G6I/O GVDDD2_MDQS4Data Strobe AH2I/O GVDDD2_MDQS5Data Strobe AM4 I/O GVDDD2_MDQS6Data Strobe AR1 I/O GVDDD2_MDQS7Data Strobe AR6I/O GVDDD2_MDQS8Data Strobe L1 I/O GVDDD2_MDQS0Data Strobe A11 I/O GVDDD2_MDQS1Data Strobe A6I/O GVDDD2_MDQS2Data Strobe C1 I/O GVDDD2_MDQS3Data Strobe G5I/O GVDDD2_MDQS4Data Strobe AH3 I/O GVDDD2_MDQS5Data Strobe AM3 I/O GVDDD2_MDQS6Data Strobe AP1 I/O GVDDD2_MDQS7Data Strobe AT6I/O GVDDD2_MDQS8Data Strobe K1 I/O GVDDD2_MBA0Bank Select AA3 O GVDDD2_MBA1 Bank Select AA1 O GVDDD2_MBA2Bank Select M1 O GVDDD2_MA00Address Y4 O GVDDD2_MA01 Address U1 O GVDDD2_MA02Address U4 O GVDDD2_MA03 Address T1 O GVDDD2_MA04 Address T2O GVDD

    D2_MA05Address T3 O GVDDD2_MA06Address R1 O GVDDD2_MA07Address R4 O GVDDD2_MA08Address R2O GVDDD2_MA09 Address P1 O GVDDD2_MA10Address AA2O GVDDD2_MA11 Address P3 O GVDDD2_MA12Address N1 O GVDDD2_MA13 Address AC4 O GVDDD2_MA14 Address N3 O GVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor17D2_MA15Address M2O GVDDD2_MWE Write Enable AB2O GVDDD2_MRAS Row Address Strobe AB1 O GVDDD2_MCAS Column Address Strobe AC3 O GVDDD2_MCS0Chip Select AC1 O GVDDD2_MCS1 Chip Select AE1 O GVDDD2_MCS2Chip Select AB3 O GVDDD2_MCS3 Chip Select AE2O GVDDD2_MCKE0Clock Enable R5O GVDDD2_MCKE1 Clock Enable T5O GVDDD2_MCKE2Clock Enable P4 O GVDDD2_MCKE3 Clock Enable M4 O GVDDD2_MCK0Clock W3 O GVDDD2_MCK1 Clock V3 O GVDDD2_MCK2Clock V1 O GVDDD2_MCK3 Clock W2O GVDDD2_MCK4 Clock G1 O GVDDD2_MCK5Clock AK2O GVDDD2_MCK0Clock Complements W4 O GVDDD2_MCK1 Clock Complements V4 O GVDDD2_MCK2Clock Complements V2O GVDDD2_MCK3 Clock Complements W1 O GVDDD2_MCK4 Clock Complements G2O GVDDD2_MCK5Clock Complements AK1 O GVDD

    D2_MODT0On Die Termination AD2O GVDDD2_MODT1 On Die Termination AF1 O GVDDD2_MODT2On Die Termination AD1 O GVDDD2_MODT3 On Die Termination AE3 O GVDDD2_MDIC0Driver Impedance Calibration AA4 I/O GVDD16D2_MDIC1Driver Impedance Calibration Y6I/O GVDD16Local Bus Controller Interface

    LAD00MuxedData/Address K26I/O BVDD3LAD01 MuxedData/Address L26I/O BVDD3LAD02MuxedData/Address J26I/O BVDD3Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 18SemiconductorLAD03 MuxedData/Address H25I/O BVDD3LAD04 MuxedData/Address F25I/O BVDD3LAD05MuxedData/Address H24 I/O BVDD3LAD06MuxedData/Address G24 I/O BVDD3LAD07MuxedData/Address G23 I/O BVDD3LAD08MuxedData/Address E23 I/O BVDD3LAD09 MuxedData/Address D23 I/O BVDD3LAD10MuxedData/Address J22I/O BVDD3LAD11 MuxedData/Address G22I/O BVDD3LAD12MuxedData/Address F19 I/O BVDD3LAD13 MuxedData/Address J18I/O BVDD3LAD14 MuxedData/Address K18I/O BVDD3LAD15MuxedData/Address J17I/O BVDD3LDP0Data Parity J24 I/O BVDDLDP1Data Parity K23 I/O BVDDLA16Address J25O BVDD35LA17Address G25O BVDD35LA18Address H23 O BVDD35LA19 Address F22O BVDD35LA20Address H22O BVDD35LA21 Address E21 O BVDD35LA22Address F21 O BVDD35LA23 Address H21 O BVDD3,4LA24 Address K21 O BVDD3,4,38

    LA25Address G20O BVDD35LA26Address J20O BVDDLA27Address K20O BVDDLA28Address G19 O BVDDLA29 Address H19 O BVDDLA30Address J19 O BVDDLA31 Address G18O BVDDLCS0Chip Selects D19 O BVDD5LCS1 Chip Selects D20O BVDD5LCS2Chip Selects E20O BVDD5Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor19LCS3 Chip Selects D21 O BVDD5LCS4 Chip Selects D22O BVDD5LCS5Chip Selects B23 O BVDD5LCS6Chip Selects F24 O BVDD5LCS7Chip Selects G26O BVDD5LWE0Write Enable D24 O BVDDLWE1 Write Enable A24 O BVDDLBCTL Buffer Control C22O BVDDLALE Address Latch Enable A23 I/O BVDDLGPL0UPM General Purpose Line 0/LFCLEFCMB25O BVDD3,4LGPL1 UPM General Purpose Line 1/LFALEFCME25O BVDD3,4LGPL2UPM General Purpose Line 2/LOE_BOutput EnableD25O BVDD3,4LGPL3 UPM General Purpose LIne 3/LFWP_BFCMH26O BVDD3,4LGPL4 UPM General Purpose Line 4/LGTA_BFCMC25I/O BVDD

    LGPL5UPM General Purpose Line 5/ Amux E26O BVDD3,4LCLK0Local Bus Clock C24 O BVDDLCLK1 Local Bus Clock C23 O BVDDDMA

    DMA1_DREQ0/GPIO18DMA1 Channel0Request AP21 I OVDD26DMA1_DACK0/GPIO19 DMA1 Channel0Acknowledge AL19 O OVDD26DMA1_DDONE0DMA1 Channel0Done AN21 O OVDD4,27DMA2_DREQ0/GPIO20/ALT_MDVAL DMA2Channel0Request AJ20I OVDD26DMA2_DACK0/EV7/ALT_MDSRCID0DMA2Channel0Acknowledge AG19 O OVDD26DMA2_DDONE0/EVT8/ALT_MDSRCID1DMA2Channel0Done AP20O OVDD26USB Host Port 1

    USB1_D7/EC1_TXD3 USB1Data bits AP36I/O LVDD35USB1_D6/EC1_TXD2USB1Data bits AT34 I/O LVDD35USB1_D5/EC1_TXD1 USB1Data bits AR34 I/O LVDD35USB1_D4/EC1_TXD0USB1Data bits AT35I/O LVDD35

    USB1_D3/EC1_RXD3 USB1Data bits AM33 I/O LVDD27Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinTypePowerSupplyNotes

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    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 20SemiconductorUSB1_D2/EC1_RXD2USB1Data bits AN34 I/O LVDD27USB1_D1/EC1_RXD1 USB1Data bits AN35I/O LVDD27USB1_D0/EC1_RXD0USB1Data bits AN36I/O LVDD27USB1_STP/EC1_TX_EN USB1 Stop AR36O LVDDUSB1_NXT/EC1_RX_DV USB1 Next data AM34 I LVDD27USB1_DIR/EC1_RX_CLK USB1Data Direction AM36I LVDD27USB1_CLK/EC1_GTX_CLK USB1 bus clock AP35I LVDD26USB Host Port 2

    USB2_D7/EC2_TXD3 USB2Data bits AT31 I/O LVDD35USB2_D6/EC2_TXD2USB2Data bits AP30I/O LVDD35USB2_D5/EC2_TXD1 USB2Data bits AR30I/O LVDD35USB2_D4/EC2_TXD0USB2Data bits AT30I/O LVDD35USB2_D3/EC2_RXD3 USB2Data bits AP33 I/O LVDD27USB2_D2/EC2_RXD2USB2Data bits AN32I/O LVDD27USB2_D1/EC2_RXD1 USB2Data bits AP32I/O LVDD27USB2_D0/EC2_RXD0USB2Data bits AT32I/O LVDD27USB2_STP/EC2_TX_EN USB2Stop AR31 O LVDDUSB2_NXT/EC2_RX_DV USB2Next data AR33 I LVDD27USB2_DIR/EC2_RX_CLK USB2Data Direction AT33 I LVDD27USB2_CLK/EC2_GTX_CLK USB2bus clock AN31 I LVDD26Programmable Interrupt Controller

    IRQ00External Interrupts AJ16I OVDDIRQ01 External Interrupts AH16I OVDDIRQ02External Interrupts AK12I OVDD

    IRQ03

    /GPIO21

    External Interrupts AJ15

    I OVDD26

    IRQ04/GPIO22External Interrupts AH17I OVDD26IRQ05/GPIO23 External Interrupts AJ13 I OVDD26IRQ06/GPIO24 External Interrupts AG17I OVDD26IRQ07/GPIO25External Interrupts AM13 I OVDD26IRQ08/GPIO26External Interrupts AG13 I OVDD26IRQ09/GPIO27External Interrupts AK11 I OVDD26IRQ10/GPIO28External Interrupts AH14 I OVDD26IRQ11/GPIO29 External Interrupts AL12I OVDD26IRQ_OUT/EVT9 Interrupt Output AK14 O OVDD1,2,26Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinTypePowerSupplyNotes

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor21TMP_DETECT TamperDetect AN19 I OVDD27eSDHC

    SDHC_CMD Command/Response AG23 I/O OVDDSDHC_DAT0Data AP24 I/O OVDDSDHC_DAT1Data AT24 I/O OVDDSDHC_DAT2Data AM23 I/O OVDDSDHC_DAT3Data AG22I/O OVDDSDHC_DAT4/SPI_CS0Data AN29 I/O CVDD26,37SDHC_DAT5/SPI_CS1Data AJ28I/O CVDD26,37SDHC_DAT6/SPI_CS2Data AR29 I/O CVDD26,37SDHC_DAT7/SPI_CS3Data AM29 I/O CVDD26,37SDHC_CLK Host to Card Clock AL23 O OVDDSDHC_CD/IIC3_SCL/GPIO16CardDetection AK13 I OVDD26,27SDHC_WP/IIC3_SDA/GPIO17Card Write Protection AM14 I OVDD26,27eSPI

    SPI_MOSI Master Out Slave In AT29 I/O CVDDSPI_MISO Master In Slave Out AH28I CVDDSPI_CLK eSPI clock AK29 O CVDDSPI_CS0/SDHC_DAT4 eSPI chip select AN29 O CVDD26SPI_CS1/SDHC_DAT5eSPI chip select AJ28O CVDD26SPI_CS2/SDHC_DAT6eSPI chip select AR29 O CVDD26SPI_CS3/SDHC_DAT7eSPI chip select AM29 O CVDD26IEEE Std 1588

    TSEC_1588_CLK_IN Clock In AL35I LVDDTSEC_1588_TRIG_IN1 Trigger In 1 AL36I LVDDTSEC_1588_TRIG_IN2Trigger In 2AK36I LVDDTSEC_1588_ALARM_OUT1 Alarm Out1 AJ36O LVDDTSEC_1588_ALARM_OUT2/GPIO30Alarm Out2AK35O LVDD26TSEC_1588_CLK_OUT Clock Out AM30O LVDDTSEC_1588_PULSE_OUT1 Pulse Out1 AL30O LVDDTSEC_1588_PULSE_OUT2/GPIO31 Pulse Out2AJ34 O LVDD26Ethernet MII Management Interface 1

    EMI1_MDC ManagementData Clock AJ33 O LVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinTypePowerSupplyNotes

    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. H

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    Freescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 22SemiconductorEMI1_MDIO ManagementData In/Out AL32I/O LVDDEthernet MII Management Interface 2

    EMI2_MDC ManagementData Clock AK30O 1.2V2,18,22EMI2_MDIO ManagementData In/Out AJ30I/O 1.2V2,18,22Ethernet Reference Clock

    EC_GTX_CLK125Reference Clock AK34 I LVDD27Ethernet External Timestamping

    EC_XTRNL_TX_STMP1 External Timestamp Transmit1 AM31 I LVDDEC_XTRNL_RX_STMP1 External Timestamp Receive 1 AK32I LVDDEC_XTRNL_TX_STMP2External Timestamp Transmit2AJ31 I LVDDEC_XTRNL_RX_STMP2External Timestamp Receive 2AK31 I LVDDThree-Speed Ethernet Controller 1

    EC1_TXD3/USB1_D7TransmitData AP36O LVDD26,35EC1_TXD2/USB1_D6TransmitData AT34 O LVDD26,35EC1_TXD1/USB1_D5TransmitData AR34 O LVDD26,35EC1_TXD0/USB1_D4 TransmitData AT35O LVDD26,35EC1_TX_EN/USB1_STP Transmit Enable AR36O LVDD15EC1_GTX_CLK/USB1_CLK Transmit Clock Out AP35O LVDD26EC1_RXD3/USB1_D3 ReceiveData AM33 I LVDD26,27EC1_RXD2/USB1_D2ReceiveData AN34 I LVDD26,27EC1_RXD1/USB1_D1 ReceiveData AN35I LVDD26,27EC1_RXD0/USB1_D0ReceiveData AN36I LVDD26,27EC1_RX_DV/USB1_NXT Receive Data Valid AM34 I LVDD27EC1_RX_CLK/USB1_DIR Receive Clock AM36I LVDD27Three-Speed Ethernet Controller 2

    EC2_TXD3/USB2_D7TransmitData AT31 O LVDD26,35EC2_TXD2/USB2_D6TransmitData AP30O LVDD26,35EC2_TXD1/USB2_D5TransmitData AR30O LVDD26,35EC2_TXD0/USB2_D4 TransmitData AT30O LVDD26,35EC2_TX_EN/USB2_STP Transmit Enable AR31 O LVDD15EC2_GTX_CLK/USB2_CLK Transmit Clock Out AN31 O LVDD26

    EC2_RXD3/USB2_D3 ReceiveData AP33 I LVDD26,27Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinTypePowerSupplyNotes

    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor23EC2_RXD2/USB2_D2ReceiveData AN32I LVDD26,27EC2_RXD1/USB2_D1 ReceiveData AP32I LVDD26,27EC2_RXD0/USB2_D0ReceiveData AT32I LVDD26,27

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    EC2_RX_DV/USB2_NXT Receive Data Valid AR33 I LVDD27EC2_RX_CLK/USB2_DIR Receive Clock AT33 I LVDD27DUART

    UART1_SOUT/GPIO8TransmitData AL22O OVDD26UART2_SOUT/GPIO9 TransmitData AJ22O OVDD26UART1_SIN/GPIO10Receive Data AR23 I OVDD26UART2_SIN/GPIO11 Receive Data AN23 I OVDD26

    UART1_RTS/UART3_SOUT/GPIO12Ready to Send AM22O OVDD26UART2_RTS/UART4_SOUT/GPIO13 Ready to Send AK23 O OVDD26UART1_CTS/UART3_SIN/GPIO14 Clear to Send AP22I OVDD26UART2_CTS/UART4_SIN/GPIO15Clear to Send AH23 I OVDD26I2C Interface

    IIC1_SCL Serial Clock AH15I/O OVDD2,14IIC1_SDA SerialData AN14 I/O OVDD2,14IIC2_SCL Serial Clock AM15I/O OVDD2,14IIC2_SDA SerialData AL14 I/O OVDD2,14IIC3_SCL/GPIO16/SDHC_CD Serial Clock AK13 I/O OVDD2,14IIC3_SDA/GPIO17/SDHC_WP SerialData AM14 I/O OVDD2,14IIC4_SCL/EVT5Serial Clock AG14 I/O OVDD2,14IIC4_SDA/EVT6SerialData AL15I/O OVDD2,14SerDes (x18) PCIe, sRIO, Aurora, 10GE, 1GE

    SD_TX17TransmitData (positive) AG31 O XVDD

    SD_TX16TransmitData (positive) AE31 O XVDDSD_TX15TransmitData (positive) AB33 O XVDDSD_TX14 TransmitData (positive) AA31 O XVDDSD_TX13 TransmitData (positive) Y29 O XVDDSD_TX12TransmitData (positive) W31 O XVDDSD_TX11 TransmitData (positive) T30O XVDDSD_TX10TransmitData (positive) P31 O XVDDSD_TX09 TransmitData (positive) N33 O XVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinTypePower

    SupplyNotes

    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 24 SemiconductorSD_TX08TransmitData (positive) M31 O XVDDSD_TX07TransmitData (positive) K31 O XVDDSD_TX06TransmitData (positive) J33 O XVDDSD_TX05TransmitData (positive) G33 O XVDDSD_TX04 TransmitData (positive) D34 O XVDDSD_TX03 TransmitData (positive) F31 O XVDDSD_TX02TransmitData (positive) H30O XVDDSD_TX01 TransmitData (positive) F29 O XVDDSD_TX00TransmitData (positive) H28O XVDDSD_TX17TransmitData (negative) AG32O XVDDSD_TX16TransmitData (negative) AE32O XVDD

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    SD_TX15TransmitData (negative) AB34 O XVDDSD_TX14 TransmitData (negative) AA32O XVDDSD_TX13 TransmitData (negative) Y30O XVDDSD_TX12TransmitData (negative) W32O XVDDSD_TX11 TransmitData (negative) T31 O XVDDSD_TX10TransmitData (negative) P32O XVDDSD_TX09 TransmitData (negative) N34 O XVDD

    SD_TX08TransmitData (negative) M32O XVDDSD_TX07TransmitData (negative) K32O XVDDSD_TX06TransmitData (negative) J34 O XVDDSD_TX05TransmitData (negative) F33 O XVDDSD_TX04 TransmitData (negative) E34 O XVDDSD_TX03 TransmitData (negative) E31 O XVDDSD_TX02TransmitData (negative) G30O XVDDSD_TX01 TransmitData (negative) E29 O XVDDSD_TX00TransmitData (negative) G28O XVDDSD_RX17Receive Data (positive) AG36I XVDDSD_RX16Receive Data (positive) AF34 I XVDDSD_RX15Receive Data (positive) AC36I XVDDSD_RX14 Receive Data (positive) AA36I XVDDSD_RX13 Receive Data (positive) Y34 I XVDDSD_RX12Receive Data (positive) W36I XVDD

    SD_RX11 Receive Data (positive) T34 I XVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinTypePowerSupplyNotes

    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor25SD_RX10Receive Data (positive) P36I XVDDSD_RX09 Receive Data (positive) M36I XVDDSD_RX08Receive Data (positive) L34 I XVDDSD_RX07Receive Data (positive) K36I XVDDSD_RX06Receive Data (positive) H36I XVDDSD_RX05Receive Data (positive) F36I XVDDSD_RX04 Receive Data (positive) D36I XVDDSD_RX03 Receive Data (positive) A31 I XVDDSD_RX02Receive Data (positive) C30I XVDDSD_RX01 Receive Data (positive) A29 I XVDDSD_RX00Receive Data (positive) C28I XVDDSD_RX17Receive Data (negative) AG35I XVDDSD_RX16Receive Data (negative) AF33 I XVDDSD_RX15Receive Data (negative) AC35I XVDDSD_RX14 Receive Data (negative) AA35I XVDDSD_RX13 Receive Data (negative) Y33 I XVDDSD_RX12Receive Data (negative) W35I XVDDSD_RX11 Receive Data (negative) T33 I XVDD

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    SD_RX10Receive Data (negative) P35I XVDDSD_RX09 Receive Data (negative) M35I XVDDSD_RX08Receive Data (negative) L33 I XVDDSD_RX07Receive Data (negative) K35I XVDDSD_RX06Receive Data (negative) H35I XVDDSD_RX05Receive Data (negative) F35I XVDDSD_RX04 Receive Data (negative) C36I XVDD

    SD_RX03 Receive Data (negative) B31 I XVDDSD_RX02Receive Data (negative) D30I XVDDSD_RX01 Receive Data (negative) B29 I XVDDSD_RX00Receive Data (negative) D28I XVDDSD_REF_CLK1 SerDes Bank1 PLL Reference Clock A35I XVDDSD_REF_CLK1 SerDes Bank1 PLL Reference ClockComplementB35I XVDDSD_REF_CLK2SerDes Bank2Reference Clock V34 I XVDDSD_REF_CLK2SerDes Bank2Reference ClockComplementV33 I XVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackage

    Pin NumberPinTypePowerSupplyNotes

    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 26SemiconductorSD_REF_CLK3 SerDes Bank2and3 PLL ReferenceClock

    AC32I XVDD36SD_REF_CLK3 SerDes Bank2and3 PLL ReferenceClock Complement

    AC31 I XVDD36General-Purpose Input/Output

    GPIO00General Purpose Input / Output AL21 I/O OVDDGPIO01 General Purpose Input / Output AK22I/O OVDDGPIO02General Purpose Input / Output AM20I/O OVDDGPIO03 General Purpose Input / Output AN20I/O OVDDGPIO04 General Purpose Input / Output AH21 I/O OVDDGPIO05General Purpose Input / Output AJ21 I/O OVDDGPIO06General Purpose Input / Output AK21 I/O OVDDGPIO07General Purpose Input / Output AG20I/O OVDDGPIO08/UART1_SOUT General Purpose Input / Output AL22I/O OVDDGPIO09/UART2_SOUT General Purpose Input / Output AJ22I/O OVDDGPIO10/UART1_SIN General Purpose Input / Output AR23 I/O OVDDGPIO11/UART2_SIN General Purpose Input / Output AN23 I/O OVDDGPIO12/UART1_RTS/UART3_SOUT General Purpose Input / Output AM22I/O OVDDGPIO13 /UART2_RTS/UART4_SOUT General Purpose Input / Output AK23 I/O OVDDGPIO14/UART1_CTS/UART3_SIN General Purpose Input / Output AP22I/O OVDD

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    GPIO15/UART2_CTS/UART4_SIN General Purpose Input / Output AH23 I/O OVDDGPIO16/IIC3_SCL/SDHC_CD General Purpose Input / Output AK13 I/O OVDDGPIO17/IIC3_SDA/SDHC_WP General Purpose Input / Output AM14 I/O OVDDGPIO18/DMA1_DREQ0General Purpose Input / Output AP21 I/O OVDDGPIO19/DMA1_DACK0General Purpose Input / Output AL19 I/O OVDDGPIO20/DMA2_DREQ0/ALT_MDVAL General Purpose Input / Output AJ20I/O OVDDGPIO21/IRQ3 General Purpose Input / Output AJ15I/O OVDD

    GPIO22/IRQ4 General Purpose Input / Output AH17I/O OVDDGPIO23/IRQ5General Purpose Input / Output AJ13 I/O OVDDGPIO24/IRQ6General Purpose Input / Output AG17I/O OVDDGPIO25/IRQ7General Purpose Input / Output AM13 I/O OVDDGPIO26/IRQ8General Purpose Input / Output AG13 I/O OVDDGPIO27/IRQ9 General Purpose Input / Output AK11 I/O OVDDGPIO28/IRQ10General Purpose Input / Output AH14 I/O OVDDGPIO29/IRQ11 General Purpose Input / Output AL12I/O OVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinTypePowerSupplyNotes

    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor27GPIO30/TSEC_1588_ALARM_OUT2General Purpose Input / Output AK35I/O LVDD25

    GPIO31/TSEC_1588_PULSE_OUT2General Purpose Input / Output AJ34 I/O LVDD25System Control

    PORESET Power On Reset AP17I OVDDHRESET Hard Reset AR17I/O OVDD1,2RESET_REQ Reset Request AT16O OVDD35CKSTP_OUT Checkstop Out AM19 O OVDD1,2Debug

    EVT0Event0AJ17I/O OVDD20EVT1 Event1 AK17I/O OVDDEVT2Event2AN16I/O OVDDEVT3 Event3 AK16I/O OVDDEVT4 Event4 AM16I/O OVDDEVT5/IIC4_SCL Event5AG14 I/O OVDDEVT6/IIC4_SDA Event6AL15I/O OVDDEVT7/DMA2_DACK0/ALT_MSRCID0Event7AG19 I/O OVDDEVT8/DMA2_DDONE0/ALT_MSRCID1 Event8AP20I/O OVDDEVT9/IRQ_OUT Event 9 AK14 I/O OVDDMDVAL Debug Data Valid AR15O OVDDMSRCID0Debug Source ID0AH20O OVDD4,20MSRCID1Debug Source ID1 AJ19 O OVDD35MSRCID2Debug Source ID2AH18O OVDD35

    ALT_MDVAL/DMA2_DREQ0/GPIO20Alternate Debug Data Valid AJ20O OVDD26ALT_MSRCID0/DMA2_DACK0/EVT7Alternate Debug Source ID0AG19 O OVDD26ALT_MSRCID1/DMA2_DDONE0/EVT8AlternateDebug Source ID1 AP20O OVDD26CLK_OUT Clock Out AK20O OVDD6

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    Clock

    RTC Real Time Clock AN24 I OVDDSYSCLK System Clock AT23 I OVDDJTAG

    TCK Test Clock AR22I OVDDTDI TestData In AN17I OVDD7TDO TestData Out AP15O OVDD6T

    able 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinTypePowerSupplyNotes

    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 28SemiconductorTMS Test Mode Select AR20I OVDD7TRST Test Reset AR19 I OVDD7DFT

    SCAN_MODE Scan Mode AL17I OVDD12TEST_SEL Test Mode Select AT21 I OVDD12,28Power Management

    ASLEEP Asleep AR21 O OVDD35Input / Output Voltage Select

    IO_VSEL0I/O Voltage Select AL18I OVDD30

    IO_VSEL1 I/O Voltage Select AP18I OVDD30IO_VSEL2I/O Voltage Select AK18I OVDD30IO_VSEL3 I/O Voltage Select AM18I OVDD30IO_VSEL4 I/O Voltage Select AH19 I OVDD30Power and Ground Signals

    GND Ground C3 GND Ground B5 GND Ground F3 GND Ground E5 GND GroundD7 GND Ground C9 GND Ground B11 GND Ground J3 GND Ground H5 GND Ground G7

    GND Ground F9 GND Ground E11 GND GroundD13 GND Ground C15 GND Ground K19 GND Ground B20 GND Ground B22 GND Ground E19 GND Ground L22 Table 1. P4080 Pins List by Bus (continued)

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    Signal Signal DescriptionPackagePin NumberPinTypePowerSupplyNotes

    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor29GND Ground J23 GND Ground A22

    GND Ground L20 GND Ground A26 GND Ground A18 GND Ground E17 GND Ground F23 GND Ground J27 GND Ground F27 GND Ground G21 GND Ground K25 GND Ground B18 GND Ground L18 GND Ground J21 GND Ground M27 GND Ground G13 GND Ground F15

    GND Ground H11 GND Ground J9 GND Ground K7 GND Ground L5 GND Ground M3 GND Ground R3 GND Ground P5 GND Ground N7 GND Ground M9 GND Ground V25 GND Ground R9 GND Ground T7 GND Ground U5 GND Ground U3 GND Ground Y3 GND Ground Y5 GND Ground W7 Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinTypePowerSupply

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    Notes

    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 30SemiconductorGND Ground V10 GND Ground AA9 GND Ground AB7 GND Ground AC5 GND Ground AD3 GND Ground AD9 GND Ground AE7 GND Ground AF5 GND Ground AG3 GND Ground AG9 GND Ground AH7 GND Ground AJ5 GND Ground AK3 GND Ground AN3 GND Ground AM5 GND Ground AL7 GND Ground AK9 GND Ground AJ11 GND Ground AH13 GND Ground AR5 GND Ground AP7 GND Ground AN9 GND Ground AM11

    GND Ground AL13 GND Ground AK15 GND Ground AG18 GND Ground AR11 GND Ground AP13 GND Ground AN15 GND Ground AM17 GND Ground AK19 GND Ground AF13 GND Ground AR18 GND Ground AB27 Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin Number

    PinTypePowerSupplyNotes

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor31GND Ground AP19 GND Ground AH22 GND Ground AM21 GND Ground AL29 GND Ground AR16 GND Ground AT22 GND Ground AP23 GND Ground AR32 GND Ground AK28 GND Ground AE27 GND Ground L16 GND Ground AP34 GND Ground AJ32 GND Ground AN30 GND Ground AH34 GND Ground AT36 GND Ground AL34 GND Ground AM32 GND Ground AE26 GND Ground AC26 GND Ground AA26 GND Ground W26 GND Ground U26 GND Ground R26

    GND Ground N26 GND Ground M11 GND Ground P11 GND Ground T11 GND Ground V11 GND Ground Y11 GND Ground AB11 GND Ground AD11 GND Ground AE12 GND Ground AC12 Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 32SemiconductorGND Ground AA12 GND Ground W12 GND Ground U12 GND Ground R12 GND Ground N12 GND Ground M13 GND Ground P13 GND Ground T13 GND Ground V13 GND Ground Y13 GND Ground AB13 GND Ground AD13 GND Ground AE14 GND Ground AC14 GND Ground AA14 GND Ground W14 GND Ground U14 GND Ground R14 GND Ground N14 GND Ground L14 GND Ground M15 GND Ground P15 GND Ground T15 GND Ground V15

    GND Ground Y15 GND Ground AB15 GND Ground AD15 GND Ground AF15 GND Ground W16 GND Ground AC16 GND Ground AA16 GND Ground AE16 GND Ground U16 GND Ground R16 Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor33GND Ground N16 GND Ground M17 GND Ground P17 GND Ground T17 GND Ground N18 GND Ground R18 GND Ground U18 GND Ground Y17 GND Ground AB17 GND Ground AD17 GND Ground AF17 GND Ground W18 GND Ground AC18 GND Ground AA18 GND Ground AE18 GND Ground AF19 GND Ground AD19 GND Ground AB19 GND Ground Y19 GND Ground V19 GND Ground T19 GND Ground P19 GND Ground M19 GND Ground N20

    GND Ground R20 GND Ground U20 GND Ground AE20 GND Ground AA20 GND Ground AC20 GND Ground W20 GND Ground AF21 GND Ground AD21 GND Ground AB21 GND Ground Y21 Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 34 SemiconductorGND Ground V21 GND Ground T21 GND Ground P21 GND Ground M21 GND Ground AE22 GND Ground AC22 GND Ground AA22 GND Ground W22 GND Ground U22 GND Ground R22 GND Ground N22 GND Ground AF23 GND Ground AD23 GND Ground AB23 GND Ground Y23 GND Ground V23 GND Ground T23 GND Ground P23 GND Ground M23 GND Ground L24 GND Ground N24 GND Ground R24 GND Ground U24 GND Ground W24

    GND Ground AA24 GND Ground AC24 GND Ground AE24 GND Ground AF25 GND Ground AD25 GND Ground AB25 GND Ground Y25 GND Ground P27 GND Ground V17 GND Ground T25 Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor35GND Ground P25 GND Ground M25 GND Ground T27 GND Ground V27 GND Ground Y27 GND Ground AD27 GND Ground L12

    XGND SerDes Transceiver GND AA30 XGND SerDes Transceiver GND AB32 XGND SerDes Transceiver GND AC30 XGND SerDes Transceiver GND AC34 XGND SerDes Transceiver GND AD30 XGND SerDes Transceiver GND AD31 XGND SerDes Transceiver GND AF32 XGND SerDes Transceiver GND AG30 XGND SerDes Transceiver GNDD33 XGND SerDes Transceiver GND E28 XGND SerDes Transceiver GND E30 XGND SerDes Transceiver GND F32 XGND SerDes Transceiver GND G29 XGND SerDes Transceiver GND G31 XGND SerDes Transceiver GND H29 XGND SerDes Transceiver GND H32 XGND SerDes Transceiver GND H34

    XGND SerDes Transceiver GND J29 XGND SerDes Transceiver GND J31 XGND SerDes Transceiver GND K28 XGND SerDes Transceiver GND K29 XGND SerDes Transceiver GND L29 XGND SerDes Transceiver GND L32 XGND SerDes Transceiver GND M30 XGND SerDes Transceiver GND N29 XGND SerDes Transceiver GND N30 XGND SerDes Transceiver GND N32 Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 36SemiconductorXGND SerDes Transceiver GND P29 XGND SerDes Transceiver GND P34 XGND SerDes Transceiver GND R30 XGND SerDes Transceiver GND R32 XGND SerDes Transceiver GND U29 XGND SerDes Transceiver GND U31 XGND SerDes Transceiver GND V29 XGND SerDes Transceiver GND V31 XGND SerDes Transceiver GND W30 XGND SerDes Transceiver GND Y32 XGND SerDes Transceiver GND AH31 SGND SerDes Core Logic GND A28 SGND SerDes Core Logic GND A32 SGND SerDes Core Logic GND A36 SGND SerDes Core Logic GND AA34 SGND SerDes Core Logic GND AB36 SGND SerDes Core Logic GND AD35 SGND SerDes Core Logic GND AE34 SGND SerDes Core Logic GND AF36 SGND SerDes Core Logic GND AG33 SGND SerDes Core Logic GND B30 SGND SerDes Core Logic GND B34 SGND SerDes Core Logic GND C29 SGND SerDes Core Logic GND C33

    SGND SerDes Core Logic GNDD31 SGND SerDes Core Logic GNDD35 SGND SerDes Core Logic GND E35 SGND SerDes Core Logic GND G34 SGND SerDes Core Logic GND G36 SGND SerDes Core Logic GND J35 SGND SerDes Core Logic GND K33 SGND SerDes Core Logic GND L36 SGND SerDes Core Logic GND M34 SGND SerDes Core Logic GND N35 Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor37SGND SerDes Core Logic GND R33 SGND SerDes Core Logic GND R36 SGND SerDes Core Logic GND T35 SGND SerDes Core Logic GND U34 SGND SerDes Core Logic GND V36 SGND SerDes Core Logic GND W33 SGND SerDes Core Logic GND Y35 SGND SerDes Core Logic GND AH35 SGND SerDes Core Logic GND AH33

    AGND_SRDS1 SerDes PLL1 GND B33 AGND_SRDS2SerDes PLL2GND T36 AGND_SRDS3 SerDes PLL3 GND AE36 SENSEGND_PL1 Platform GND Sense 1 AF12 8SENSEGND_PL2Platform GND Sense 2K27 8SENSEGND_CA Core Group A GND Sense K17 8SENSEGND_CB Core Group B GND Sense AG16 8OVDD General I/O Supply AN22 OVDDOVDD General I/O Supply AJ14 OVDDOVDD General I/O Supply AJ18 OVDDOVDD General I/O Supply AL16 OVDDOVDD General I/O Supply AJ12 OVDDOVDD General I/O Supply AN18 OVDDOVDD General I/O Supply AG21 OVDDOVDD General I/O Supply AL20 OVDD

    OVDD General I/O Supply AT15 OVDDOVDD General I/O Supply AJ23 OVDDOVDD General I/O Supply AP16 OVDDOVDD General I/O Supply AR24 OVDDCVDD eSPI Supply AJ29 CVDDCVDD eSPI Supply AP29 CVDDGVDDDDR Supply B2 GVDDGVDDDDR Supply B8 GVDDGVDDDDR Supply B14 GVDDGVDDDDR Supply C18 GVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 38SemiconductorGVDDDDR Supply C12 GVDDGVDDDDR Supply C6 GVDDGVDDDDR SupplyD4 GVDDGVDDDDR SupplyD10 GVDDGVDDDDR SupplyD16 GVDDGVDDDDR Supply E14 GVDDGVDDDDR Supply E8 GVDDGVDDDDR Supply E2 GVDDGVDDDDR Supply F6 GVDDGVDDDDR Supply F12 GVDDGVDDDDR Supply AR8 GVDDGVDDDDR Supply G4 GVDDGVDDDDR Supply G10 GVDDGVDDDDR Supply G16 GVDDGVDDDDR Supply H14 GVDDGVDDDDR Supply H8 GVDDGVDDDDR Supply H2 GVDDGVDDDDR Supply J6 GVDDGVDDDDR Supply K10 GVDDGVDDDDR Supply K4 GVDDGVDDDDR Supply L2 GVDDGVDDDDR Supply L8 GVDDGVDDDDR Supply M6 GVDDGVDDDDR Supply N4 GVDD

    GVDDDDR Supply N10 GVDDGVDDDDR Supply P8 GVDDGVDDDDR Supply P2 GVDDGVDDDDR Supply R6 GVDDGVDDDDR Supply T10 GVDDGVDDDDR Supply T4 GVDDGVDDDDR Supply J12 GVDDGVDDDDR Supply U2 GVDDGVDDDDR Supply U8 GVDDGVDDDDR Supply V7 GVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor39GVDDDDR Supply AK10 GVDDGVDDDDR Supply W10 GVDDGVDDDDR Supply AA6 GVDDGVDDDDR Supply AR2 GVDDGVDDDDR Supply Y2 GVDDGVDDDDR Supply Y8 GVDDGVDDDDR Supply AC2 GVDDGVDDDDR Supply AD6 GVDDGVDDDDR Supply AE10 GVDDGVDDDDR Supply AE4 GVDDGVDDDDR Supply AF2 GVDDGVDDDDR Supply AF8 GVDDGVDDDDR Supply AB4 GVDDGVDDDDR Supply AB10 GVDDGVDDDDR Supply AC8 GVDDGVDDDDR Supply AG6 GVDDGVDDDDR Supply AH10 GVDDGVDDDDR Supply AH4 GVDDGVDDDDR Supply AJ2 GVDDGVDDDDR Supply AJ8 GVDDGVDDDDR Supply AR14 GVDDGVDDDDR Supply AK6 GVDDGVDDDDR Supply AL4 GVDDGVDDDDR Supply AL10 GVDD

    GVDDDDR Supply AM2 GVDDGVDDDDR Supply AM8 GVDDGVDDDDR Supply AP10 GVDDGVDDDDR Supply AN12 GVDDGVDDDDR Supply AN6 GVDDGVDDDDR Supply AP4 GVDDBVDD Local Bus Supply B24 BVDDBVDD Local Bus Supply K22 BVDDBVDD Local Bus Supply F20 BVDDBVDD Local Bus Supply F26 BVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 40SemiconductorBVDD Local Bus Supply E24 BVDDBVDD Local Bus Supply E22 BVDDBVDD Local Bus Supply K24 BVDDBVDD Local Bus Supply H20 BVDDBVDD Local Bus Supply H18 BVDDSVDD SerDes Core Logic Supply A30 SVDDSVDD SerDes Core Logic Supply A34 SVDDSVDD SerDes Core Logic Supply AA33 SVDDSVDD SerDes Core Logic Supply AB35 SVDDSVDD SerDes Core Logic Supply AD36 SVDDSVDD SerDes Core Logic Supply AE33 SVDDSVDD SerDes Core Logic Supply AF35 SVDDSVDD SerDes Core Logic Supply AG34 SVDDSVDD SerDes Core Logic Supply B28 SVDDSVDD SerDes Core Logic Supply B32 SVDDSVDD SerDes Core Logic Supply B36 SVDDSVDD SerDes Core Logic Supply C31 SVDDSVDD SerDes Core Logic Supply C34 SVDDSVDD SerDes Core Logic Supply C35 SVDDSVDD SerDes Core Logic SupplyD29 SVDDSVDD SerDes Core Logic Supply E36 SVDDSVDD SerDes Core Logic Supply F34 SVDDSVDD SerDes Core Logic Supply G35 SVDDSVDD SerDes Core Logic Supply J36 SVDD

    SVDD SerDes Core Logic Supply K34 SVDDSVDD SerDes Core Logic Supply L35 SVDDSVDD SerDes Core Logic Supply M33 SVDDSVDD SerDes Core Logic Supply N36 SVDDSVDD SerDes Core Logic Supply R34 SVDDSVDD SerDes Core Logic Supply R35 SVDDSVDD SerDes Core Logic Supply U33 SVDDSVDD SerDes Core Logic Supply V35 SVDDSVDD SerDes Core Logic Supply W34 SVDDSVDD SerDes Core Logic Supply Y36 SVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor41SVDD SerDes Core Logic Supply AH36 SVDD

    XVDD SerDes Transceiver Supply AA29 XVDDXVDD SerDes Transceiver Supply AB30 XVDDXVDD SerDes Transceiver Supply AB31 XVDDXVDD SerDes Transceiver Supply AC33 XVDDXVDD SerDes Transceiver Supply AD32 XVDDXVDD SerDes Transceiver Supply AE30 XVDDXVDD SerDes Transceiver Supply AF31 XVDDXVDD SerDes Transceiver Supply E32 XVDDXVDD SerDes Transceiver Supply E33 XVDDXVDD SerDes Transceiver Supply F28 XVDDXVDD SerDes Transceiver Supply F30 XVDDXVDD SerDes Transceiver Supply G32 XVDDXVDD SerDes Transceiver Supply H31 XVDDXVDD SerDes Transceiver Supply H33 XVDDXVDD SerDes Transceiver Supply J28 XVDDXVDD SerDes Transceiver Supply J30 XVDDXVDD SerDes Transceiver Supply J32 XVDDXVDD SerDes Transceiver Supply K30 XVDDXVDD SerDes Transceiver Supply L30 XVDDXVDD SerDes Transceiver Supply L31 XVDDXVDD SerDes Transceiver Supply M29 XVDDXVDD SerDes Transceiver Supply N31 XVDDXVDD SerDes Transceiver Supply P30 XVDD

    XVDD SerDes Transceiver Supply P33 XVDDXVDD SerDes Transceiver Supply R29 XVDDXVDD SerDes Transceiver Supply R31 XVDDXVDD SerDes Transceiver Supply T29 XVDDXVDD SerDes Transceiver Supply T32 XVDDXVDD SerDes Transceiver Supply U30 XVDDXVDD SerDes Transceiver Supply V30 XVDDXVDD SerDes Transceiver Supply V32 XVDDXVDD SerDes Transceiver Supply W29 XVDDXVDD SerDes Transceiver Supply Y31 XVDDTable 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 42SemiconductorXVDD SerDes Transceiver Supply AH32 XVDDLVDD Ethernet Controller1 and2Supply AK33 LVDDLVDD Ethernet Controller1 and2Supply AP31 LVDDLVDD Ethernet Controller1 and2Supply AL31 LVDDLVDD Ethernet Controller1 and2Supply AN33 LVDDLVDD Ethernet Controller1 and2Supply AJ35 LVDDLVDD Ethernet Controller1 and2Supply AR35 LVDDLVDD Ethernet Controller1 and2Supply AM35 LVDDPOVDD Fuse Programming Override Supply AT17 POVDD39VDD_PL Platform Supply M26 VDD_PL VDD_PL Platform Supply P26 VDD_PL VDD_PL Platform Supply T26 VDD_PL VDD_PL Platform Supply V26 VDD_PL VDD_PL Platform Supply Y26 VDD_PL VDD_PL Platform Supply AB26 VDD_PL VDD_PL Platform Supply AD26 VDD_PL VDD_PL Platform Supply N11 VDD_PL VDD_PL Platform Supply R11 VDD_PL VDD_PL Platform Supply W11 VDD_PL VDD_PL Platform Supply AA11 VDD_PL VDD_PL Platform Supply AE11 VDD_PL VDD_PL Platform Supply M12 VDD_PL VDD_PL Platform Supply P12 VDD_PL VDD_PL Platform Supply T12 VDD_PL

    VDD_PL Platform Supply V12 VDD_PL VDD_PL Platform Supply Y12 VDD_PL VDD_PL Platform Supply AB12 VDD_PL VDD_PL Platform Supply AD12 VDD_PL VDD_PL Platform Supply AE13 VDD_PL VDD_PL Platform Supply AE15 VDD_PL VDD_PL Platform Supply V16 VDD_PL VDD_PL Platform Supply AE17 VDD_PL VDD_PL Platform Supply L11 VDD_PL VDD_PL Platform Supply AE19 VDD_PL Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor43VDD_PL Platform Supply U11 VDD_PL VDD_PL Platform Supply AC11 VDD_PL VDD_PL Platform Supply V20 VDD_PL VDD_PL Platform Supply AE21 VDD_PL VDD_PL Platform Supply V22 VDD_PL VDD_PL Platform Supply U13 VDD_PL VDD_PL Platform Supply R27 VDD_PL VDD_PL Platform Supply U23 VDD_PL VDD_PL Platform Supply W23 VDD_PL VDD_PL Platform Supply AA27 VDD_PL VDD_PL Platform Supply AC27 VDD_PL VDD_PL Platform Supply AE23 VDD_PL VDD_PL Platform Supply M24 VDD_PL VDD_PL Platform Supply P24 VDD_PL VDD_PL Platform Supply T24 VDD_PL VDD_PL Platform Supply V24 VDD_PL VDD_PL Platform Supply Y24 VDD_PL VDD_PL Platform Supply AB24 VDD_PL VDD_PL Platform Supply AD24 VDD_PL VDD_PL Platform Supply N25 VDD_PL VDD_PL Platform Supply R25 VDD_PL VDD_PL Platform Supply U25 VDD_PL VDD_PL Platform Supply W25 VDD_PL VDD_PL Platform Supply AA25 VDD_PL

    VDD_PL Platform Supply AC25 VDD_PL VDD_PL Platform Supply N27 VDD_PL VDD_PL Platform Supply U27 VDD_PL VDD_PL Platform Supply W28 VDD_PL VDD_PL Platform Supply AE25 VDD_PL VDD_PL Platform Supply AF24 VDD_PL VDD_PL Platform Supply AF22 VDD_PL VDD_PL Platform Supply AF20 VDD_PL VDD_PL Platform Supply AF16 VDD_PL VDD_PL Platform Supply W13 VDD_PL Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 44 SemiconductorVDD_PL Platform Supply AF18 VDD_PL VDD_PL Platform Supply V14 VDD_PL VDD_PL Platform Supply V18 VDD_PL VDD_PL Platform Supply L13 VDD_PL VDD_PL Platform Supply L15 VDD_PL VDD_PL Platform Supply L17 VDD_PL VDD_PL Platform Supply L19 VDD_PL VDD_PL Platform Supply L21 VDD_PL VDD_PL Platform Supply L23 VDD_PL VDD_PL Platform Supply L25 VDD_PL VDD_PL Platform Supply AF14 VDD_PL VDD_PL Platform Supply N23 VDD_PL VDD_PL Platform Supply R23 VDD_PL VDD_PL Platform Supply AA23 VDD_PL VDD_PL Platform Supply AC23 VDD_PL VDD_PL Platform Supply U21 VDD_PL VDD_PL Platform Supply W21 VDD_PL VDD_PL Platform Supply U15 VDD_PL VDD_PL Platform Supply AC21 VDD_PL VDD_PL Platform Supply AD22 VDD_PL VDD_PL Platform Supply M22 VDD_PL VDD_PL Platform Supply N13 VDD_PL VDD_PL Platform Supply AC13 VDD_PL VDD_PL Platform Supply P22 VDD_PL

    VDD_PL Platform Supply T22 VDD_PL VDD_PL Platform Supply Y22 VDD_PL VDD_PL Platform Supply AB22 VDD_PL VDD_PL Platform Supply AA13 VDD_PL VDD_PL Platform Supply R13 VDD_PL VDD_PL Platform Supply M14 VDD_PL VDD_PL Platform Supply U17 VDD_PL VDD_PL Platform Supply U19 VDD_PL VDD_PL Platform Supply T14 VDD_PL VDD_PL Platform Supply AD14 VDD_PL Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor45VDD_PL Platform Supply AD16 VDD_PL VDD_PL Platform Supply AD18 VDD_PL VDD_PL Platform Supply AD20 VDD_PL VDD_PL Platform Supply Y14 VDD_PL VDD_CA Core/L2Group A (0-3) Supply T20 VDD_CA VDD_CA Core/L2Group A (0-3) Supply P20 VDD_CA VDD_CA Core/L2Group A (0-3) Supply R21 VDD_CA VDD_CA Core/L2Group A (0-3) Supply R19 VDD_CA VDD_CA Core/L2Group A (0-3) Supply P14 VDD_CA VDD_CA Core/L2Group A (0-3) Supply N19 VDD_CA VDD_CA Core/L2Group A (0-3) Supply M20 VDD_CA VDD_CA Core/L2Group A (0-3) Supply N21 VDD_CA VDD_CA Core/L2Group A (0-3) Supply M16 VDD_CA VDD_CA Core/L2Group A (0-3) Supply N15 VDD_CA VDD_CA Core/L2Group A (0-3) Supply P16 VDD_CA VDD_CA Core/L2Group A (0-3) Supply T16 VDD_CA VDD_CA Core/L2Group A (0-3) Supply R17 VDD_CA VDD_CA Core/L2Group A (0-3) Supply T18 VDD_CA VDD_CA Core/L2Group A (0-3) Supply R15 VDD_CA VDD_CA Core/L2Group A (0-3) Supply N17 VDD_CA VDD_CA Core/L2Group A (0-3) Supply M18 VDD_CA VDD_CA Core/L2Group A (0-3) Supply P18 VDD_CA VDD_CB Core/L2Group B (4-7) Supply W15 VDD_CB 29VDD_CB Core/L2Group B (4-7) Supply W19 VDD_CB 29

    VDD_CB Core/L2Group B (4-7) Supply AA19 VDD_CB 29VDD_CB Core/L2Group B (4-7) Supply Y20 VDD_CB 29VDD_CB Core/L2Group B (4-7) Supply AB14 VDD_CB 29VDD_CB Core/L2Group B (4-7) Supply AA21 VDD_CB 29VDD_CB Core/L2Group B (4-7) Supply Y16 VDD_CB 29VDD_CB Core/L2Group B (4-7) Supply AA15 VDD_CB 29VDD_CB Core/L2Group B (4-7) Supply AC15 VDD_CB 29VDD_CB Core/L2Group B (4-7) Supply AA17 VDD_CB 29VDD_CB Core/L2Group B (4-7) Supply AC17 VDD_CB 29VDD_CB Core/L2Group B (4-7) Supply W17 VDD_CB 29Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 46SemiconductorVDD_CB Core/L2Group B (4-7) Supply Y18 VDD_CB 29VDD_CB Core/L2Group B (4-7) Supply AB18 VDD_CB 29VDD_CB Core/L2Group B (4-7) Supply AB16 VDD_CB 29VDD_CB Core/L2Group B (4-7) Supply AC19 VDD_CB 29VDD_CB Core/L2Group B (4-7) Supply AB20 VDD_CB 29

    AVDD_CC1 Core Cluster PLL1 Supply A20 13AVDD_CC2Core Cluster PLL2Supply A21 13AVDD_CC3 Core Cluster PLL3 Supply AT18 13AVDD_CC4 Core Cluster PLL4 Supply AT19 13AVDD_PLAT Platform PLL Supply AT20 13AVDD_DDR DDR PLL Supply A19 13AVDD_SRDS1 SerDes PLL1 Supply A33 13AVDD_SRDS2SerDes PLL2Supply U36 13AVDD_SRDS3 SerDes PLL3 Supply AE35 13SENSEVDD_PL1 Platform Vdd Sense AF11 8SENSEVDD_PL2Platform Vdd Sense L27 8SENSEVDD_CA Core Group A Vdd Sense K16 8SENSEVDD_CB Core Group B Vdd Sense AG15 8Analog Signals

    MVREF SSTL_1.5/1.8Reference Voltage B19 I GVDD/2SD_IMP_CAL_TX SerDes Tx Impedance Calibration AF30I200;1to

    XVDD23

    SD_IMP_CAL_RX SerDes Rx Impedance Calibration B27I200;1toSVDD24TEMP_ANODE Temperature Diode Anode C21 internaldiode9TEMP_CATHODE Temperature Diode Cathode B21 internaldiode9No Connection Pins

    NC01 No Connection J13 11NC02No Connection AB28 11NC03 No Connection E16 11NC04 No Connection AC29 11

    NC05No Connection K14 11Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinTypePowerSupplyNotes

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor47NC06No Connection C26 11NC07No Connection E27 11NC08No Connection AE29 11NC09 No Connection AG26 11NC10No Connection AF26 11NC11 No Connection AC28 11NC12No Connection AA28 11NC13 No Connection J15 11NC14 No Connection J14 11NC15No Connection AD29 11NC16No Connection J16 11NC17No Connection AG28 11NC18No Connection AE28 11NC19 No Connection AF28 11NC20No Connection H27 11NC21 No Connection H12 11NC22No Connection H13 11NC23 No Connection H16 11NC24 No Connection AH30 11NC25No Connection AH29 11NC26No Connection Y28 11NC27No Connection AN13 11NC28No Connection J11 11NC29 No Connection AB29 11

    NC30No Connection K11 11NC31 No Connection AD28 11NC32No Connection A27 11NC33 No Connection K15 11NC34 No Connection H15 11NC35No Connection K13 11NC36No Connection K12 11NC37No Connection G17 11NC38No Connection H17 11NC39 No Connection C20 11Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

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    PRELIMINARYPin Assignments and Reset StatesP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without Notice

    Freescale Semiconductor49Reserve11 AH27 11Reserve12 AR26 11Reserve13 AT27 11Reserve14 AH26 11Reserve15 AJ27 11Reserve16 AT26 11Reserve17 AN26 11Reserve18 AJ26 11Reserve19 AG25 11Reserve20 AP27 11Reserve21 AM25 11Reserve22 AP28 11Reserve23 AL28 11Reserve24 AG24 11Reserve25 AP26 11Reserve26 AJ24 11Reserve27 AM28 11Reserve28 AR25 11Reserve29 AM24 11Reserve30 AL27 11Reserve31 AT28 11Reserve32 AT25 11Reserve33 AL24 11Reserve34 AL26 11

    Reserve35 AK24 11Reserve36 AN25 11Reserve37 AK27 11Reserve38 AP25 11Reserve39 AM26 11Reserve40 AN27 11Reserve41 AL33 11Reserve42 C32 11Reserve43 U35 11Reserve44 AD34 11Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinT

    ypePowerSupplyNotes

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    PRELIMINARYP4080 QorIQ Integrated Processor Hardware Specifications, Rev. HFreescale Confidential Proprietary, NDA RequiredPreliminarySubject to Change Without NoticePin Assignments and Reset States

    Freescale 50SemiconductorReserve45 D32 11Reserve46 U32 11Reserve47 AD33 11Reserve48 N28 GND21Reserve49 AG11 GND21Reserve50 L28 GND21Reserve51 AG12 GND21Reserve52 M28 GND21Reserve53 AH12 GND21Reserve54 P28 GND21Reserve55 AH11 GND21Reserve56 A25 11Table 1. P4080 Pins List by Bus (continued)Signal Signal DescriptionPackagePin NumberPinTypePowerSupplyNotes