practice problem set 3 eem16

UCLA | EEM16/CSM51A | Winter 2015 Prof. Mani Srivastava

Practice Problem Set #3 Problem #1 Please show your work. Just writing the answer without show intermediate steps on the way to coming up with the answer will get zero credit. a. Convert the decimal number 59491 into a hexadecimal number. b. Represent 59491 as a BCD number using the minimum number of bits. c. Represent 59491 as a 2’s complement number using the minimum number of bits. d. Represent 59491 as a 2’s complement number using the minimum number of bits. e. Represent 59491 as a 1’s complement number using the minimum number of bits.

Problem #2: Arithmetic operations on a digital computers are done using arithmetic modules that are designed to represent inputs and outputs using the same number of bits. While this has the nice property that result of one operation can be used as input for the next one, it creates the problem of overflow and underflow, i.e. the output may be too large or too small to be representable by the number of bits available. One way to combat this is to make arithmetic modules that do saturation arithmetic instead of modular arithmetic (wrap around) which the arithmetic modules we discussed in the class do. In saturation arithmetic, the output values are clamped to a maximum value in the case of an overflow, and to a minimum value in the case of underflow. The Wikipedia article on this topic at http://en.wikipedia.org/wiki/Saturation_arithmetic has an excellent description. While properties like associativity and distributivity are no longer hold true in saturation arithmetic, it offers the tremendous advantage that the results are numerically closer to reality, e.g. adding two large positive numbers may yield a negative number due to overflow in modular arithmetic, but in the case of saturated arithmetic would yield the largest positive number that can be represented. Your task is to design an arithmetic module which takes as input two 8bit 2’s complement numbers DIN0 and DIN1, and a 1bit control signal CNTL, and outputs an 8bit t 2’s complement result DOUT such that when CNTL is 0 then DOUT is the saturated sum of DIN0 and DIN1 (i.e. DIN0+DIN1 saturated), and when CNTL is 1 then DOUT is the saturated subtraction of DIN1 from DIN0 (i.e. DIN0DIN1 saturated). You may use halfadders, fulladders, NAND gates, and inverters.

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Problem #3:

a. Draw the FSM for a multimodel counter with 3bit states 000, 001, 010, … 111 and an input M such that

● If M=0, then the counter cycles through the states in binary order … 000, 001, 010, 011, 100, 101, 110, 111, 000 …

● If M=1, then the counter cycles through the states in gray coded order … 000, 001, 011, 010, 110, 111, 101, 100, 000 …

b. Implement the counter using D flipflops, NAND gates, and inverters only. Write expressions for the next state logic and output logic, and show supporting steps (e.g. Karnaugh maps if you use them). Both correctness and efficiency of implementation would be considered during grading. Give the cost of your implementation, assuming that an ninput NAND gate has a cost of n, and a 1bit D flipflop has a cost of 10.

Note: For part (b), you might want to try out your solution in Logisim to make sure it works correctly. If so, you are welcome to include printouts of Logisim schematics and Karnaugh maps. However, please do things manually as otherwise you would have a hard time in the finals.

Problem #4:

a. You have to design a synchronous digital sequential system which has one input X and output Z such that Z is asserted to be 1 whenever the input sequence 010 is observed, as long as the input sequence 100 has never been seen. Draw a finite state machine (i.e. the state diagram) for the system. Note that for 30% reduced credit you could instead design the system as more than one concurrent finite state machine.

b. Modify the finite state machine so that Z is asserted to be 1 whenever either of the following two input sequences are observed 01101+0 or 011101+0, as long as the input sequence 100 has never been seen. Here 1+ means “one or more 1”. Note that for 30% reduced credit you could instead design the system as more than one concurrent finite state machine.

c. Implement the FSM of step (a) [or for extra credit, implement instead the FSM from step (b)] using D flipflops, NAND gates, and inverters only. Write expressions for the next state logic and output logic, and show supporting steps (e.g. Karnaugh maps if you use them). Give the cost of your implementation, assuming that an ninput NAND gate has a cost of n, and a 1bit D flipflop has a cost of 10. Both correctness and efficiency of implementation would be considered during grading.

Note: For part (c), you might want to try out your solution in Logisim to make sure it works correctly. If so, you are welcome to include printouts of Logisim schematics and Karnaugh

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maps. However, please do things manually as otherwise you would have a hard time in the finals.

Problem #5:

In the class we discussed D flipflops which at the clock edge read and stored the value present at their data input pin. There are other types of flipflops that behave slightly differently. One such flipflop is called the T flipflop, whose behavior is that at the clock edge if the input is 1 then it toggles the stored value (i.e. if the stored value was 0 then it is changed to 1, and vice versa), and if the input is 0 then the stored value is left untouched.

a. Derive the nextstate and output equations (in terms of boolean logic operators for and, or, not, and xor) for the circuit shown below that is made using T flipflops.

b. Show the state table for the circuit, making sure to show all possible states that the circuit can be in.

c. Draw the state diagram for the circuit, making sure to show all possible states that the circuit can be in.

d. Complete the timing diagram below by drawing the waveform for Z assuming current state right after t=0 is S[0]=S[1]=0.

e. From the state diagram you would see that the circuit has an isolated state. What state is that? This state should not occur in normal operation. What happens if the circuit happens to start in this state? What circuit modifications can you make to prevent the system from ever entering this illegal state or cause it to leave this illegal state once entered?

Please fill the timing diagram for part (d) here:

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Problem #6:

Draw the state diagram of the following circuit with input x and outputs z0 and z1, and made using JK flips flops. The two state bits are qA and qB. These flipflops operate according to the following equation: .J Q) ¬K )Qnext = ( ⋀¬ ⋁( ⋀Q

Problem #7:

Often time signals from realworld, such as audio, images, sensor data etc., are noisy and need to be “smoothed” to remove noise. The goal of this problem is to design a very simple system to do this. Your system receives an 8bit 2’s complement signed data sample on input X on every clock cycle, and outputs on each clock cycle an 8bit 2’s complement signed data value Y such that Y[n] = 0.25X[n] + 0.5X[n1] + 0.25X[n2] where X[n] and Y[n] indicate the nth input and output data sample. Assume that the first valid sample that you receive on X is for n=0, and that all the previous X[n] for n<0 were 0.

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Clearly show the steps in your design. Your design may use any standard combinational combinational (simple gates, mux, demux, encoder, decoder, arithmetic functions etc., except multipliers) or sequential modules (flipflop, registers, counters etc.) discussed in the lectures. Note again: you do not have a multiplier module available to you.

Note: You might want to try out your solution in Logisim to make sure it works correctly. If so, you are welcome to include printouts of Logisim schematics. However, please do things manually as otherwise you would have a hard time in the quiz and finals.

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practice problem set 3 eem16

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