practicalelectronicsnat5_tcm4-719530

8/10/2019 PracticalElectronicsNat5_tcm4-719530

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NATIONAL QUALIFICATIONS CURRICULUM SUPPORT

Practical Electronics

Circuit Design

Combinational Logic

NATIONAL !"


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T#is a$%ice an$ gui$ance #as been &ro$uce$ to su&&ort t#e &ro'ession (it# t#e $eli%er) o'

courses (#ic# are eit#er ne( or (#ic# #a%e as&ects o' signi'icant c#ange (it#in t#e ne(

national *uali'ications +NQ, 'rame(or-.

T#e a$%ice an$ gui$ance &ro%i$es suggestions on a&&roac#es to learning an$ teac#ing.

Practitioners are encourage$ to $ra( on t#e materials 'or t#eir o(n &art o' t#eir continuing

&ro'essional $e%elo&ment in intro$ucing ne( national *uali'ications in (a)s t#at matc# t#e

nee$s o' learners.

Practitioners s#oul$ also re'er to t#e course an$ unit s&eci'ications an$ su&&ort notes (#ic#

#a%e been issue$ b) t#e Scottis# Quali'ications Aut#orit).

#tt&/00(((.s*a.org.u-0s*a012342.#tml

Acknowledgement

5 Cro(n co&)rig#t 6746.8ou ma) re9use t#is in'ormation +e:clu$ing logos, 'ree o' c#arge inan) 'ormat or me$ium; un$er t#e terms o' t#e O&en #ere (e #a%e i$enti'ie$ an) t#ir$ &art) co&)rig#t in'ormation )ou (ill nee$ to obtain

&ermission 'rom t#e co&)rig#t #ol$ers concerne$.

An) en*uiries regar$ing t#is $ocument0&ublication s#oul$ be sent to us at

en*uiries=e$ucationscotlan$.go%.u-.

T#is $ocument is also a%ailable 'rom our (ebsite at(((.e$ucationscotlan$.go%.u-.

6 PRACTICAL CRAFT S?ILLS +NATIONAL 1,

5 Cro(n co&)rig#t 6746
http://www.sqa.org.uk/sqa/34714.htmlhttp://www.nationalarchives.gov.uk/doc/open-government-licence/http://www.nationalarchives.gov.uk/doc/open-government-licence/mailto:[email protected]:[email protected]:[email protected]://www.educationscotland.gov.uk/http://www.educationscotland.gov.uk/http://www.educationscotland.gov.uk/http://www.sqa.org.uk/sqa/34714.htmlhttp://www.nationalarchives.gov.uk/doc/open-government-licence/mailto:[email protected]:[email protected]://www.educationscotland.gov.uk/


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Contents

Teaching and learning approaches 2

Basic logic functions @

Combinational logic circuits 27

Converting logic circuits to Boolean expressions and truth tables !6

Converting Boolean expressions to logic circuits 1

Converting truth tables to logic circuits 37

Appendix 1 @4

PRACTICAL CRAFT S?ILLS +NATIONAL 1, 1



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TEACHI! A" #EA$I! A%%$&ACHE'

Teaching and learning approaches

Introduction

T#is gui$e &ro%i$es suggestions; i$eas an$ acti%ities 'or &ractitioners on t#e

$eli%er) o' combinational logic; (#ic# 'orms one learning outcome o' t#e

Circuit Design unit in National ! Practical Electronics.

T#e content also co%ers all t #e combinational logic to&ics re*uire$ in Circuit

Design at National 2 so t#is gui$e can also be use$ 'or t#is le%el but t#is (ill

re*uire more tutorial e:ercises to be $e%elo&e$.

Aims and ob(ectives

T#is gui$ance is inten$e$ to su&&ort t#e &ractitioner in t#e $eli%er) Practical

Electronics/ Circuit Design; Combinational Logic.

T#e materials &ro%i$e gui$ance on t#e 'ollo(ing t#ree &arts/

4. basic logic 'unctions

6. con%erting trut# tables to logic circuits an$ con%erting Boolean

e:&ressions to logic circuits

1. con%erting logic circuits to Boolean e:&ressions.

Learners coul$ be encourage$ to (or- t#roug# t#e e:ercises bot# in$i%i$uall)

an$ in &airs.

Once t#e basic conce&ts #a%e been learne$; simulation &ac-ages an$ logic

tutor boar$s coul$ be use$ to en#ance t#e learning an$ &ro%i$e &ractical#an$s9on e:&erience.

T#e gui$ance (ill su&&ort &ractitioners in gi%ing t#e learners t#e o&&ortunit)

to gain an un$erstan$ing o' t#e basic gates use$ in combinational logic; t#eir

trut# tables an$ Boolean e:&ression.

T#e) coul$ also be able to con%ert trut# tables an$ Boolean e:&ressions to

logic circuits an$ con%ert logic circuits to Boolean e:&ressions.

2 PRACTICAL ELECTRONICS +NATIONAL !,



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Introduction

T#e 'irst &art o' t#e a$%ice an$ gui$ance co%ers t#e basic logic gates an$&ro%i$es t#e ANSI 6 an$ t#e BS EN 743 logic s)mbols; trut# table an$

Boolean e:&ression 'or eac# gate.

T#e secon$ &art $escribes #o( trut# tables an$ Boolean e:&ressions are

con%erte$ into logic circuits.

T#e t#ir$ &art $escribes #o( logic circuits are con%erte$ into Boolean

e:&ressions.

Learners sometimes cannot see t#e rele%ance to real9li'e situations o'

combinational logic; so &ractitioners ma) ma-e re'erence to #o( logic is use$

e%er)$a); ie I (ill bu) )ou a co''ee not is an e:am&le o' t#e NOT or

in%ert logic 'unction.

Practical e:am&les o' (#ere logic is use$ coul$ also be inclu$e$; eg/

Com&uters nee$ combinational logic circuits to (or-.

Mo$ern cars #a%e electronic control units +ECUs,. T#ese are small;

&o(er'ul com&uters t#at control %arious 'unctions (it#in t#e car; suc# as

t#e 'uel management s)stem.

Tele%isions can #a%e Free%ie(; (#ic# is a $igital tele%ision signal t#atuses combinational logic.

Practitioners ma) (is# to &ro%i$e some ot#er e:am&les.

'uggested learning and teaching approaches

T#e s-ills an$ -no(le$ge re*uire$ (ill be gaine$ as t#e learner &rogresses

t#roug# eac# to&ic.

)onitoring progress

As eac# to&ic buil$s on t#e &re%ious one; it is im&ortant t#at t#e learner is

con'i$ent be'ore mo%ing on.

Learners t#ere'ore s#oul$ be encourage$ to ta-e res&onsibilit) 'or t#eir o(n

&rogress so t#at t#e) can (or- at t#eir o(n &ace an$ $i''iculties are i$enti'ie$

as earl) as &ossible.

PRACTICAL ELECTRONICS +NATIONAL !, !



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Suggeste$ Learning an$ Teac#ing A&&roac#es

T#ese (ill be $e&en$ent on t#e 'acilities an$ e:&ertise a%ailable in t#e centrebut t#e 'ollo(ing are suggeste$/

(or-e$ e:am&les 'or eac# to&ic

tutorials to buil$ u& -no(le$ge an$ un$erstan$ing

learner9centre$ buil$ing an$ testing on simulation so't(are

logic tutor9t)&e boar$s in$i%i$uall) an$0or in &airs.

$esources

Some use'ul (ebsites 'or basic combinational logic are/

#tt&/00(((.&la)9#oo-e).com0$igital0basicgates.#tml

#tt&/00com&uter.#o(stu''(or-s.com0boolean4.#tm

#tt&/00(((.(isc9online.com0obGects0Hie(ObGect.as&:IDJDIor-benc#; MultiSim etc.

T#ere are also a number o' logic tutor s)stems a%ailable; 'or e:am&le t#e

Fee$bac- Logic tutor s)stem.

It is suggeste$ t#at learners use so't(are simulation &ac-ages to buil$ an$

test circuits. T#is is a sa'e met#o$ to use be'ore t#e) go on to use t#e more

#an$s9on logic tutor s)stems.

Learners using simulation so't(are can (or- eit#er in$i%i$uall) or in &airs.

Circuits can be built an$ teste$ t#en sa%e$. T#e) can t#en be $emonstrate$ at

a later time.

T#e Po(erPoint Presentation contains all t#e basic logic s)mbols an$ t#ese

can be use$ to ma-e u& 'urt#er e:ercises i' re*uire$.

PRACTICAL ELECTRONICS +NATIONAL !,

http://www.play-hookey.com/digital/basic_gates.htmlhttp://computer.howstuffworks.com/boolean1.htmhttp://www.wisc-online.com/objects/ViewObject.aspx?ID=DIG1302http://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/combi.htmlhttp://www.kpsec.freeuk.com/gates.htmhttp://www.play-hookey.com/digital/basic_gates.htmlhttp://computer.howstuffworks.com/boolean1.htmhttp://www.wisc-online.com/objects/ViewObject.aspx?ID=DIG1302http://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/combi.htmlhttp://www.kpsec.freeuk.com/gates.htm


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Once t#e learners #a%e gaine$ e:&erience using t#e simulation so't(are; t#e

circuits coul$ be built an$ %eri'ie$ using logic tutor boar$s or (#ate%er

&ractical s)s tem t#e centre em&lo)s.

Because t#is is a &ractical learning en%ironment; t#e rele%ant sa'et)

&recautions must be obser%e$.

A list o' $e%ice numbers an$ &in connections 'or all t#e basic gates is

&ro%i$e$ in A&&en$i: 4.

PRACTICAL ELECTRONICS +NATIONAL !, 3



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Basic logic functions

T#is section &ro%i$es an intro$uction to t#e %arious logic gates AND; OR;

NOT; OR; NAND an$ NOR.

For eac# gate t#e logic s)mbol is &ro%i$e$ along (it# t#e trut# t able an$

Boolean e:&ression.

Bot# t#e ANSI 6 an$ t#e EN BS 743 logic s)mbols are &ro%i$e$. o(e%er;

a'ter t#e tutorial *uestions in t#e 'irst &art o' t#e $ocument; onl) t#e ANSI 6

s)mbols (ill be use$ as t#e) are more commonl) use$.

A s#ort e:&lanation o' trut# tables an$ Boolean algebra #as also been

inclu$e$ but (ill nee$ 'urt#er e:&lanation or e:&an$ing $uring t#e lesson.

Learners o'ten $ont un$erstan$ (#ere t#e logic 4s an$ 7s 'or t#e in&uts come

'rom. A s#ort re'res#er on binar) arit#metic mig#t be a&&ro&riate #ere so

learners un$erstan$ #o( to count 'rom 7 to 1 an$ 7 to 3 in binar).

Anot#er met#o$ sometimes use$ is to ta-e t#e %alue o' t#e binar) column; @;

2; 6; 4 etc; to $etermine t#e number o' 7s t#en 4s toget#er; ie starting 'rom

t#e to&; t#e @ column (ill #a%e eig#t 7s 'ollo(e$ b) eig#t 4s; t#e 2 column

(ill #a%e 'our 7s 'ollo(e$ b) 'our 4s etc.

T#is is an eas) met#o$ 'or &ro$ucing t#e trut# tables an$ allo(s t#e learner to

concentrate on t#e out&ut o' t#e table rat#er t#an #o( to &ro$uce t#e in&ut

%alues.

In or$er to ai$ t#e learners un$erstan$ing; t#e conce&t 'or eac# logic gate;(#ere &ossible; #as been intro$uce$ using a sim&le electrical circuit using

s(itc#es as t#e in&uts an$ a lig#t as t#e out&ut. It (oul$ be bene'icial to t#e

learner i'; $uring teac#ing; more e:am&les coul$ be gi%en so rein'orcing t#e

i$ea t#at logic is use$ in all sorts o' areas.

For e:am a t(o9(a) lig#ting circuit use$ on staircases (it# one s(itc# at

t#e to& an$ one at t#e bottom is an e:am&le o' t#e OR 'unction.

@ PRACTICAL ELECTRONICS +NATIONAL !,



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T#e Po(erPoint Presentation contains all t#e logic s)mbols use$ in t#ese

notes an$ t#ese can be use$ to $e%elo& more tutorial e:ercises i' re*uire$.

An internet searc# (ill &ro%i$e a number o' e:am&les o' sim&le uses o'

combinational logic circuits.

A'ter t#e learners #a%e gone t#roug# t#e tutorial e:ercises; t#e basic logic

'unctions s#oul$ be rein'orce$ using simulation so't(are suc# as Electronic

(or-benc#; MultiSim or (#ate%er so't(are &ac-age t#e centre uses to test

logic 'unctions.

T#is (ill &ro%i$e a$$e$ %alue to t#e learners -no(le$ge.

Tutorial

4. I$enti') t#e logic gate 'rom t#e logic s)mbol

AND OR

NOT OR




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NOR NAND




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AND OR

OR NAND

Learners coul$ also be as-e$ to (rite t#e Boolean e:&ression 'or eac# gate.

6. Dra( t#e logic gate an$ (rite t#e Boolean e:&ression $escribe$ b) t#e

'ollo(ing trut# tables.

B A O0P B A O0P

7 7 7 7 7 7

7 4 4 7 4 4

4 7 4 4 7 4

4 4 7 4 4 4

OR OR

OR logic s)mbol OR logic s)mbol

O0P J A B O0P J A B

B A O0P B A O0P

7 7 7 7 7 4



J4

J4

4


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7 4 7 7 4 4

4 7 7 4 7 4

4 4 4 4 4 7AND NAND




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AND logic s)mbol NAND logic s)mbol

O0P J A.B O0P J A.B

B A O0P A O0P

7 7 4 7 7

7 4 7 4 4

4 7 7

4 4 7NOR NOT

NOR logic s)mbo l NOT logic s)mbol

O0P J A B O0P J A




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1. Determine t#e logic 'unction re&resente$ b) t#e 'ollo(ing Boolean

e:&ressions/

O0P J P O0P J A.B.C

NOT AND

O0P J P Q O0P J A.B

OR NAND

O0P J A B O0P J P Q

NOR OR

Learners coul$ also be as-e$ to &ro$uce t#e trut# table 'or eac# e:&ression.

Converting from truth tables to logic circuits

T#is section buil$s on t#e -no(le$ge o' t#e basic gates b) 'irst ta-ing t#e

trut# table an$ e:&laining t#at onl) lines on t#e trut# table (#ere t#e out&ut is

a logic 4 are re*uire$ to $esign t#e logic circuit. T#is is because t#e circuit

#as to &ro$uce a logic 4 out&ut 'or onl) t#ese in&ut con$itions.

It coul$ be #ig#lig#te$ t#at t#e in&uts to t#e circuit are tie$ toget#er on a

trut# table b) t#e Boolean AND 'unction. It coul$ also be mentione$; t#at t#is

AND 'unction is calle$ t#e &ro$uct o' sums 'orm.

Follo(ing on 'rom t#is; all t#e lines on a trut# table t#at #a%e a logic 4 out&ut

are tie$ to eac# ot#er b) t#e Boolean OR 'unction. T#is is calle$ t#e sum o'

&ro$ucts 'orm. Boolean e:&ressions &ro$uce$ 'rom a trut# table (ill al(a)s

be in t#e sum o' &ro$ucts 'orm.




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T#e &ractitioner coul$ emasise t#e 'ollo(ing/

Because t#e circuit #as onl) one out&ut; t#ere can onl) be one logic

gate &ro$ucing t#is out&ut. Because t#e Boolean e:&ression is in t#e sum

o' &ro$ucts 'orm; t#e out&ut gate (ill be an OR gate i' more t#an one line

on t#e trut# table is a logic 4. o(e%er; i' onl) one line on t#e trut# table

is a logic 4 t#en t#e out&ut gate (ill be an AND gate.

T#e number o' &ro$uct terms; ie t#e number o' lines on t#e trut# table

(#ose out&ut is logic 4; also $etermines #o( man) in&uts t#ere (ill be

into t#e out&ut gate.

It $oesnt matter (#at or$er t#e in&uts are (ritten in/ A.B.C is e:actl)

t#e same as C.A.B or B.C.A.

A B C is t#e also same as B A C etc.

Practitioners s#oul$ emasise to learners t#at an) t)&e o' electrical circuit

$iagram 'lo(s 'rom le't to rig#t on t#e &age; ie signals in&ut on t#e le't an$

out&ut on t#e rig#t. Also; (#en $ra(ing logic circuits or an) -in$ o' electrical

$iagram; (iring must al(a)s be $ra(n eit#er #oriontall) or %erticall); ne%er

at an angle.

Once t#e learners #a%e &rogresse$ t#roug# t#e course t#e circuits coul$ t#en

be constructe$ an$ teste$ 'irst using a simulation &ac-age; t#en (it# a logictutor.

>#en using t#e logic tutor s)stem; learners s#oul$ be instructe$ to al(a)s

connect all unuse$ in&uts to logic 4. T#is &re%ents &roblems occurring an$ is

also goo$ &ractice.

E:am&le

Design a logic circuit 'or t#e 'ollo(ing trut# table.

R P Q O0P

7 7 7 7

7 7 4 7

7 4 7 7

7 4 4 4

4 7 7 7

4 7 4 4

4 4 7 7

4 4 4 7

PRACTICAL ELECTRONICS +NATIONAL !, 4!



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T#e t(o lines t#at #a%e t#e out&ut at logic 4 are R.P.Q an$ R.P.Q.

T#ese are t#e t(o &ro$ucts o' sum e:&ressions.

T#e out&ut is t#ere'ore O0P J R.P.Q R.P.Q

T#e out&ut gate is an OR gate (it# t(o in&uts. One in&ut is R.P.Q an$ t#e

ot#er is R.P.Q.

T#e circuit can no( be built u& 'rom t#e out&ut gate bac- to t#e in&ut.

Alt#oug# t#e com&lete logic circuit is s#o(n belo(; it s#oul$ be built u& in

stages 'rom t#e out&ut gate bac- to $emonstrate #o( it is constructe$.



O0P J R.P.Q R.P.Q

R

R

P

P

RQ

R.P.Q

R.P.Q


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Tutorial* #ogic circuits from truth tables

Dra( t#e logic circuit $escribe$ b) t#e trut# tables belo(/

4.

B A O0P

7 7 7

7 4 7

4 7 7

4 4 4

AND trut# table

O0P J A.B

6.

C B A O0P

7 7 7 7

7 7 4 4

7 4 7 4

7 4 4 4

4 7 7 4

4 7 4 4

4 4 7 4

4 4 4 4

OR trut# table

O0P J A B C



A

B

O0P

ABC

O0P


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1.

B A O0P

7 7 77 4 4

4 7 4

4 4 7

O0P J A B

2.

C B A O0P

7 7 7 7

7 7 4 7

7 4 7 77 4 4 7

4 7 7 7

4 7 4 7

4 4 7 4

4 4 4 7

O0P J A.B.C

4@ PRACTICAL ELECTRONICS +NATIONAL !,


A

B

O0P J A B

An OR gate

A

B

C

O0P J A.B.C

A


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!.

C B A O0P

7 7 7 77 7 4 4

7 4 7 7

7 4 4 7

4 7 7 7

4 7 4 7

4 4 7 7

4 4 4 7

O0P J A.B.C



A

B

C

B

C

O0P J A.B.C


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.

C B A O0P

7 7 7 47 7 4 7

7 4 7 7

7 4 4 7

4 7 7 7

4 7 4 7

4 4 7 7

4 4 4 7

O0P J A.B.C

B) loo-ing at t#e trut# table it can be seen t#at it is 'or a t#ree9in&ut NOR

gate an$ coul$ #a%e been (ritten as/

It s#oul$ be &ointe$ out t#at bot# circuits are correct but t#e NAND gate is

use$ in a &ractical circuit as it uses 'e(er $e%ices.

Alt#oug# it is not &art o' t#is course; t#e abo%e $iagram illustrates one o' De

Morgans t#eorems in a &ractical circuit; ie mo%e t#e in%ersion+s, 'rom t#e

in&ut to t#e out&ut an$ c#ange t#e gate 'rom AND to OR.



A

B

C

O0P J A.B.C

A

B

C

O0P J A B C


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3.

C B A O0P

7 7 7 77 7 4 7

7 4 7 4

7 4 4 7

4 7 7 7

4 7 4 7

4 4 7 7

4 4 4 4

O0P J A.B.C A.B.C



A

B

C

O0P


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@.

C B A O0P

7 7 7 77 7 4 7

7 4 7 7

7 4 4 4

4 7 7 4

4 7 4 7

4 4 7 7

4 4 4 7

O0P J A.B.C A.B.C



A

B

C

O0P


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.

C B A O0P

7 7 7 77 7 4 4

7 4 7 7

7 4 4 7

4 7 7 7

4 7 4 7

4 4 7 4

4 4 4 7

O0P J A.B.C A.B.C



A

B

C

O0P J A.B.C A.B.C


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47.

R Q P O0P

7 7 7 47 7 4 4

7 4 7 4

7 4 4 4

4 7 7 4

4 7 4 4

4 4 7 4

4 4 4 7

O0P J A.B.C

Note / It mig#t be a$%isable to tell t#e learners to loo- closel) at t#e trut#

table be'ore $esigning t#e logic circuit.



A

B

C

O0P J A.B.C


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44.

8 O0P

7 7 7 77 7 4 4

7 4 7 4

7 4 4 7

4 7 7 4

4 7 4 7

4 4 7 7

4 4 4 7

O0P J .8. .8. .8.



8

.8.

.8.

.8.

O0P J .8. .8. .8.


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46.

C B A O0P

7 7 7 77 7 4 7

7 4 7 7

7 4 4 4

4 7 7 7

4 7 4 4

4 4 7 4

4 4 4 7

O0P J A.B.C A.B.C A.B.C



A

B

C

O0P J A.B.C A.B.C A.B.C


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#ogic circuits from Boolean expressions

T#is tec#ni*ue is #ar$er 'or learners as t#e out&ut gate can be an) o' t#e basicgates. Learners o'ten 'in$ $i''icult) in $eci$ing (#at t#e out&ut gate s#oul$

be an$ t#e e:&ression $oesnt nee$ to be %er) com&le: 'or t#is to #a&&en.

Anal)sing e:&ressions to $e$uce t#e out&ut gate; (it#out $ra(ing t#e logic

circuit; is goo$ &ractice 'or learners an$ centres coul$ &ro$uce a range o'

e:am&les 'or t#is &ur&ose.

Encouraging learners to use brac-ets; as t#e) (oul$ 'or or$inar) algebra; also

greatl) #el&s t#em to $etermine t#e out&ut gate.

Again; learners s#oul$ be taug#t to (or- bac- 'rom t#e out&ut gate; (or-ing

out t#e logic 'or eac# branc# bac- to t#e in&ut. >it# &ractice; t#e logic

$iagrams (ill get ti$ier an$ clearer.

T#e learners s#oul$ buil$ an$ test t#e circuits using a simulation &ac-age.

Logic tutor s)stems s#oul$ t#en be use$ to buil$ an$ test t#e circuits.




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#ogic circuits from Boolean expressions

Dra( t#e logic circuit 'or eac# o' t#e Boolean e:&ressions gi%en belo(.

4. A.B.C

6. A B



A

B

A B

A.B.CA

B

C


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1. A.B C

2. A.B.C



A

B

C

A.B.C

A

B

C

A.B C


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!. A.B C

. P Q

T#is is a t(o9in&ut NOR gate; in$icate$ b) t#e bar abo%e t#e (#ole

e:&ression.

3. A B C

T#e out&ut gate in t#is case is a NOR. T#e bar abo%e t#e A B grou&s

t#em toget#er as one in&ut to t#e NOR gate.



A

B

C

A.B C

P

Q

P Q


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A

A

C

A B C


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@. A.B C

. +P Q,.+P R,

T#e out&ut gate is NAND.

47. +A.B, C



A

A

C

A .B C

P

Q

R

+P Q,.+P R,


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A

B

C

A.B

A.B C


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Boolean expressions and truth tables from logic circuits

Con%ersion o' a logic circuit into a Boolean e:&ression is %er)straig#t'or(ar$. Sim&l) start at t#e in&ut to t#e circuit an$ at t#e out&ut o'

e%er) gate (rite $o(n on t#e logic $iagram t#e logic e:&ression 'or t#at gate

base$ on t#e in&uts.

Continue t#is until t#e e:&ression 'or t#e out&ut gate #as been $eri%e$.

Common mista-es/

Learners $o not &a) attention to t#e t)&e o' gate.

T#e) mi: u& AND an$ OR 'unctions.

T#e) o'ten 'orget t#at a circle on t#e out&ut o' a gate means t#at t#ere #as

been an in%ersion an$ t#ere s#oul$ be a bar o%er t#e (#ole o' t#e out&ut o'

t#at gate.

T#e) recognise t#at t#e gate #as an in%ersion but &ut t#e bar on eac# o' t#e

in&uts in$i%i$uall).

T#e) correctl) $eri%e t#e out&ut o' a gate but $o not use t#e com&lete

e:&ression as t#e in&ut to t#e ne:t gate; ie t#e) miss out t#e bar abo%e an

e:&ression.

T#e im&ortance o' trut# tables in $etermining t#e o&eration o' logic circuits

cannot be un$erstate$. It is o'ten %er) $i''icult to un$erstan$ t#e 'unction o' alogic circuit 'rom t#e $iagram or t#e Boolean e:&ression. o(e%er; a trut#

table can #el& greatl) in clari')ing t#e 'unction o' t#e circuit.

For e:am ta-e t#e 'ollo(ing logic circuit/

T#e out&ut e:&ression 'or t#is circuit is A.B A.B.



A

B

O0P


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An)one (#o #as logic e:&erience (ill recognise t#is as an OR 'unction; but

learners ma) struggle to see t#is.

o(e%er; t#e trut# table 'or t#e circuit is/

B A O0P

7 7 7

7 4 4

4 7 4

4 4 7

Learners s#oul$ no( be able to see t#at t#is is t#e trut# table 'or t#e OR

gate stu$ie$ earlier.

T#e circuit in t#e $iagram belo( uses t(o9in&ut AND gates to &ro%i$e a

t#ree9in&ut AND gate.



A

B

C

T#is is one met#o$ o' &ro$ucing a t#ree9in&ut AND gate.

A

B

C


36/89


A trut# table $ra(n 'or bot# circuits (ill s#o( t#e logic 'unction clearl)/

C B A O0P

7 7 7 7

7 7 4 7

7 4 7 7

7 4 4 7

4 7 7 7

4 7 4 7

4 4 7 7

4 4 4 4

T#is is t#e trut# table 'or bot# circuits abo%e.

Similarl); a t#ree9 or 'our9in&ut gate can be use$ as a t(o9in&ut $e%ice b)

using t(o o' t#e in&uts an$ t)ing t#e ot#er t(o &ermanentl) to logic 4.

Alternati%el); it coul$ be use$ b) t)ing t(o in&uts toget#er as one in&ut an$

$oing t#e same (it# t#e ot#er t(o/

All t#e circuits in t#is section s#oul$ be built an$ teste$ using t#e logic tutor

boar$s.

Questions 6; 2 an$ 44 in t#e tutorial can be sim&li'ie$. T#is s#oul$ be

#ig#lig#te$ to t#e learner.



AB

Logic 4

A

B

T)ing t(o in&uts to logic 4 Using t(o in&uts tie$ toget#er 'or eac# in&ut


37/89


Conversion of logic circuits to Boolean expressions

Deri%e t#e trut# table an$ Boolean e:&ression 'or t#e out&ut o' t#e 'ollo(inglogic circuits.

4.

C B A +A.B, +A.B, C

7 7 7 7 7

7 7 4 7 7

7 4 7 7 7

7 4 4 4 4

4 7 7 7 4

4 7 4 7 4

4 4 7 7 4

4 4 4 7 4

6.

C B A +A.B, +A.B,. C7 7 7 7 7

7 7 4 7 7

7 4 7 7 7

7 4 4 4 7

4 7 7 7 7

4 7 4 7 7

4 4 7 7 7

4 4 4 4 4

T#is circuit can be re&lace$ b) a t#ree in&ut AND gate



A

B

C

+A.B, C

+A.B,

A

B

C

+A.B,.C

+A.B,

C


38/89


1.

C B A +A.B, +B.C, +A.B,

+B.C,

7 7 7 7 7 7

7 7 4 7 7 7

7 4 7 7 7 7

7 4 4 4 7 4

4 7 7 7 7 7

4 7 4 7 7 7

4 4 7 7 4 4

4 4 4 4 4 4

2.

C B A +A B, +A. B,

C7 7 7 7 7

7 7 4 4 4

7 4 7 4 4

7 4 4 4 4

4 7 7 7 4

4 7 4 4 4

4 4 7 4 4

4 4 4 4 4

T#is circuit can be re&lace$ b) a t#ree9in&ut OR gate.



A

B

C

+A B,

C

+A B, C

A

B

C

+A.B, +B.C,

+A.B,

+B.C,


39/89


!.

C B A

B

A.B.C

A.B.C

7 7 7 4 7 4

7 7 4 4 7 4

7 4 7 7 7 4

7 4 4 7 7 4

4 7 7 4 7 4

4 7 4 4 4 7

4 4 7 7 7 4

4 4 4 7 7 4

.

R Q P

P.Q

R

P.Q R

7 7 7 4 4 77 7 4 4 4 7

7 4 7 4 4 7

7 4 4 7 4 7

4 7 7 4 7 7

4 7 4 4 7 7

4 4 7 4 7 7

4 4 4 7 7 4

It is #ar$ to see 'rom t#e logic $iagram or t#e Boolean e:&ression; but t#e

trut# table s#o(s t#at t#is circuit can be re&lace$ b) a t#ree9in&ut AND gate.



P

Q

R

+P.Q, R

+P.Q,

R

A

B

C

+A.B.C,

B

+A.B.C,


40/89


3.

C B A +A.B,

C

+A.B, C

7 7 7 7 4 4

7 7 4 7 4 4

7 4 7 7 4 4

7 4 4 4 4 4

4 7 7 7 7 7

4 7 4 7 7 7

4 4 7 7 7 7

4 4 4 4 7 4

@.

B A

A

A B

+A B, B

+A B, B

7 7 4 7 7 4

7 4 7 4 4 7

4 7 4 7 4 7

4 4 7 7 4 7

T#is circuit can be re&lace$ b) a t(o9in&ut NOR gate.



A

B

+A B,.B

A

+A B,

A

B

C

+A.B, C

+A.B,

R


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.

C B A

A

+A B,

+A .B, C

+A .B,

C

7 7 7 4 4 4 7

7 7 4 7 7 7 4

7 4 7 4 7 7 4

7 4 4 7 4 4 7

4 7 7 4 4 4 7

4 7 4 7 7 4 7

4 4 7 4 7 4 7

4 4 4 7 4 4 7



A

B

C

+A B, C

A

+A B,


42/89


47.

D C B A

B

D

A.B

C.D

+A.B,.+C.D,

7 7 7 7 4 4 7 7 7

7 7 7 4 4 4 4 7 7

7 7 4 7 7 4 7 7 7

7 7 4 4 7 4 7 7 7

7 4 7 7 4 4 7 4 7

7 4 7 4 4 4 4 4 4

7 4 4 7 7 4 7 4 7

7 4 4 4 7 4 7 4 7

4 7 7 7 4 7 7 7 7

4 7 7 4 4 7 4 7 7

4 7 4 7 7 7 7 7 7

4 7 4 4 7 7 7 7 7

4 4 7 7 4 7 7 7 7

4 4 7 4 4 7 4 7 7

4 4 4 7 7 7 7 7 7

4 4 4 4 7 7 7 7 7



A

B

C

D

+A.B,.+C.D,

B

D

+A.B,

+C.D,


43/89


44.

C B A +A B, +A B,

C

+A B, C

7 7 7 7 7 4

7 7 4 4 4 7

7 4 7 4 4 7

7 4 4 4 4 7

4 7 7 7 4 7

4 7 4 4 4 7

4 4 7 4 4 7

4 4 4 4 4 7

T#is circuit can be re&lace$ b) a t#ree9in&ut NOR gate.



A

B

C

+A B,+A B, C

+A B, C


44/89


46.

C B A

B

C

+A.B.C,

+A.B.C, +A.B.C,

+A.B.C, +A.B.C,

+A.B.C, +A.B.C,

+A.B.C,

7 7 7 4 4 7 7 7 7 77 7 4 4 4 7 7 7 7 7

7 4 7 7 4 7 7 7 7 7

7 4 4 7 4 7 4 7 4 4

4 7 7 4 7 7 7 7 7 7

4 7 4 4 7 4 7 7 4 4

4 4 7 7 7 7 7 7 7 7

4 4 4 7 7 7 7 4 7 4



A

B

C

+A.B.C,+A.B.C,+A.B.C,

+A.B.C,

+A.B.C,

+A.B.C,

+A.B.C, +A.B.C,

B

C


45/89

C&)BIATI&A# #&!IC CI$C+IT'

Combinational logic circuits

#ogic functions

Logical o&erations are use$ in e%er)$a) li'e. Statements suc# as I (ill bu)

)ou a co''ee not are common. In t#is statement t#e &erson is sa)ing

somet#ing &ositi%e t#en ma-ing it into t#e o&&osite (it# t#e not at t#e en$

o' t#e sentence. Ot#er logical o&erations are t#ings suc# as/

To use )our com&uter s)stem t#e com&uter must be s(itc#e$ on andt#e

monitor must be s(itc#e$ on.

To get out o' t#e #ouse )ou can e:it b) t#e 'ront $oor ort#e bac- $oor.

Logic s)stems #a%e onl) t(o st ates an$ t#e) can be re&resente$ b) %arious

met#o$s; ie #ig# or lo(; u& or $o(n; 4 or 7; on or o''; true or 'alse etc.

Com&uter s)stems use logical o&erations an$ electrical circuits are use$ to

&ro$uce t#ese logic 'unctions. I$enti'ication o' t#e 'unction is b) a s)mbol

an$ t#ere are $i''erent s)mbols use$ 'or eac# o' t#e basic logic 'unctions.

T(o sets o' s)mbols are use$/ ANSI s)mbols an$ IEC s)mbols. Bot# (ill be

s#o(n 'or t#e basic gates t#en t#e ANSI s)mbols (ill be use$ 'or t#e rest o'

t#e mo$ule.

All logic gates use electrical signals being eit#er on or o'' to re&resent t#e

logic states 4 an$ 7; ie a signal &resent is re&resente$ b) logic 4 an$ a s ignal

not &resent b) logic 7.

T#e basic logic 'unctions are terme$ gates; an$ gates are combine$ toget#er

to &ro$uce logic circuits.

T#e basic logical 'unctions +gates, are AND; OR; NOT; OR; NAND an$

NOR.

T#e) can #a%e one or more in&uts but onl) one out&ut.




46/89


All logical 'unctions or circuits; 'rom t#e sim&lest to t#e more com&le:; canbe re&resente$ in %arious 'orms. Trut# tables are one 'orm; Boolean algebra is

anot#er.

Bot# o' t#ese $escribe t#e be#a%iour o' t#e logic circuit.

Truth tables

A trut# table is a table t#at lists all combinations o' in&uts along (it# t#eir

corres&on$ing out&ut. In combinational logic an in&ut combination (ill

al(a)s &ro$uce t#e same out&ut con$ition irres&ecti%e o' (#at #as been

&resent be'ore; ie i' an in&ut o' logic 4 on in&ut A an$ logic 7 on in&ut B

&ro$uce$ an out&ut o' 4 it (ill al(a)s &ro$uce t#at out&ut 'or t#at logic

'unction.

An e:am&le o' a trut# table 'or a t(o9in&ut logic circuit is s#o(n belo(/

In&ut A In&ut B Out&ut

7 7 7

7 4 4

4 7 7

4 4 4

T#e in&uts 'or trut# tables are sim&l) a binar) count 'rom 7 to all 4s; 'or

e:am&le t#e abo%e trut# table starts at in&ut A J 7 an$ in&ut B J 7 an$ counts

u& b) one on e%er) l ine until bot# in&uts are at logic 4. T#e count in binar) is

t#ere'ore 77; 74; 47; 44 an$ t#e count in $ecimal is 7; 4; 6; 1.

I' t#e logic 'unction #a$ t#ree in&uts t#en t#e count (oul$ start at 777 an$ go

u& to 444. In $ecimal t#is (oul$ be 7 to 3.



Logic 'unction

A

B

In&utsOut&ut

O0P

A t(o9in&ut logic 'unction


47/89


Boolean algebra

Boolean algebra is a mat#ematical met#o$ o' re&resenting logic 'unctions an$can be mani&ulate$ in a similar (a) to or$inar) algebra.

It uses letters or names 'or t#e in&uts A; B; C or P;Q etc. t#at are connecte$ to

t#e gate an$ connects t#em using s&ecial s)mbols to re&resent t#e logic

'unction.

T#e basic logic gates are &ro%i$e$ in t#e 'ollo(ing &ages (it# t#eir trut#

tables an$ Boolean e:&ressions.

A" gate

T#e easiest (a) to s#o( t#e AND logic gate o&eration is b) using an

electrical circuit/

As can be seen; t#e lam& (ill onl) lig#t (#en bot# s(itc#es are on.

T#e trut# table belo( s#o(s t#at t#e out&ut ) (ill be at logic 4 onl) (#en

bot# t#e in&uts are at logic 4.



A B

Lam&

O'' J 7On J 4

4 J s(itc# on 7 J s(itc# o''

O0PA

B

ANSI t(o9in&ut AND gate

s)mbol

A

B

O0

P

BS EN 743 s)mbol 'or a t(o9in&ut

AND gate


48/89


A B O0P

7 7 77 4 7

4 7 7

4 4 4

Trut# table 'or a t(o9in&ut AND gate

Boolean expression

T#e ot#er met#o$ to s#o( t#e 'unction o' t#e circuit is to use Boolean

algebra. T#is uses t#e names o' t#e in&uts connecte$ (it# s)mbols t#at

re&resent t#e 'unction.

In t#e case o' t#e AND 'unction t#e Boolean o&erator is a 'ull sto&.

T#e Boolean e:&ression 'or t#e t(o9in&ut AND gate abo%e is/

O0P J A.B

T#e out&ut is logic 4 (#en A is at logic 4 andB is at logic 4.

&$ gate

T#e easiest (a) to s#o( t#e OR logic 'unction is b) an electrical circuit.



A

B

9

4 J s(itc# on 7 J s(itc# o''

Lam&

+O0P,


49/89


As can be seen; t#e lam& (ill lig#t (#en eit#er or bot# s(itc#es are on.

A B O0P

7 7 7

7 4 4

4 7 4

4 4 4

Trut# table 'or a t(o9in&ut OR 'unction +gate,

Boolean expression

T#e ot#er met#o$ to s#o( t#e 'unction o' t#e circuit is to use Boolean

algebra.

T#e s)mbol 'or t#e OR o&erator is a &lus +, sign; not to be con'use$ (it# t#e

a$$ition sign.

T#e Boolean e:&ression 'or t#e t(o9in&ut OR gate abo%e is/

O0P J A B

T#is is rea$ as O0P J 4 (#en A is 4 orB is 4 orbot# are 4.

T#is is more correctl) terme$ t#e inclusi%e OR 'unction as it inclu$es all t#e

con$itions/ A or B or bot#.



ANSI s)mbol 'or a t(o9in&ut OR

gate

A

B

O0P 4O0PA

B

BS EN 743 s)mbol 'or a t(o9in&ut

OR gate


50/89


&T gate

T#e electrical circuit 'or t#e NOT 'unction is s#o(n belo(. It is also calle$ anin%erter gate.

>#en t#e s(itc# is o'' +logic 7, t#e lam& is on; ie logic 4.

>#en t#e s(itc# is on +logic 4, t#e lam& is o''; ie logic 7.

T#e out&ut is t#ere'ore t#e o&&osite o' t#e in&ut.

Notice t#e bubble on t#e out&ut o' t#e NOT gate. T#is bubble signi' ies t#at an

in%ersion #as ta-en &lace +ie a logic 7 becomes a logic 4 an$ a logic 4

becomes a logic 7,.

!7 PRACTICAL ELECTRONICS +NATIONAL !,


A

Resistor

Lam&

A O0P

ANSI s)mbol 'or a NOT

gate

4A O0

P

BS EN 743 s)mbol 'or a NOT

gate


51/89


A O0P

7 44 7

Trut# table 'or a NOT gate

Boolean expression

T#e Boolean e:&ression 'or a NOT o&erator is obtaine$ b) &lacing a line

calle$ a bar abo%e t#e 'unction/

O0P J A

T#is is rea$ as t#e out&ut J not A; ie t#e out&ut is t#e o&&osite o' t#e in&ut A.

Exclusive &$ function ,-&$.

As can be seen; t#e lam& (ill lig#t (#en s(itc# A is in &osition 4 ands(itc#

B is in &osition 7 or(#en s(itc# A is in &osition 7 ands(itc# B is in

&osition 4.

PRACTICAL ELECTRONICS +NATIONAL !, !4


A

4

B

7

Lam& +O0P,

7 4


52/89


A B O0P

7 7 7

7 4 4

4 7 4

4 4 7

Trut# table 'or a OR 'unction +gate,

Boolean expression

In t#e case o' t#e OR 'unction t#e Boolean o&erator is a &lus sign insi$e a

circle/

O0P J A B

The &T A" or A" gate

T#is is an AND gate (it# t#e out&ut in%erte$.

Note t#e bubble; (#ic# in$icates an in%ersion.



A

B

O0P

ANSI s)mbol 'or an

e:clusi%e +OR, OR

gate

J4A

B

O0P

BS EN 743 s)mbol 'or an

e:clusi%e +OR, OR gate

A

BO0P A

B

O0P

ANSI s)mbol 'or a t(o9in&ut

NAND gateBS EN 743 s)mbol 'or a t(o9in&ut

NAND gate


53/89


54/89


T#e abo%e logic gates #a%e been s#o(n as #a%ing onl) t(o in&uts. o(e%er;

gates are a%ailable (it# more t#an t(o in&uts; but t#e 'unction remains t#e

same. For e:am an AND gate (it# t#ree in&uts (ill onl) &ro$uce a logic 4out&ut (#en all t#ree in&uts are at logic 4; as s#o(n belo(.

T#e Boolean e:&ression 'or t#is gate is ) J P.Q.R.

'ummar0 of logic gates

An AND gate (ill onl) &ro$uce a logic 4 out&ut (#en

all t#e in&uts are at logic 4.

An OR gate (ill &ro$uce an out&ut o' logic 4 (#en an) or all t#e in&uts are at

logic 4.

A NOT gate &ro$uces an out&ut t#at is t#e o&&osite o' its in&ut.

An OR gate (ill onl) &ro$uce an out&ut o' logic 4 (#en bot# in&uts are

$i''erent.

A NAND gate (ill onl) &ro$uce a logic 7 out&ut (#en all t#e in&uts are at

logic 4.

A NOR gate (ill onl) &ro$uce a logic 4 out&ut (#en all t#e in&uts are at logic

7.



P Q R O0P

7 7 7 7

7 7 4 7

7 4 7 7

7 4 4 7

4 7 7 7

4 7 4 74 4 7 7

4 4 4 4

PQ

R O0P


55/89


Tutorial #ogic !ates

4. I$enti') t#e logic gate 'rom t#e logic s)mbol.

9999999999999999 999999999999999999

9999999999999999 999999999999999999

9999999999999999 999999999999999999

PRACTICAL ELECTRONICS +NATIONAL !, !!


J 4

4

999999999

999999999999

999999999

999999999999


56/89


6. Dra( t#e logic gate an$ (rite t#e Boolean e:&ression $escribe$ b) t#e

'ollo(ing trut# tables.

B A O0P B A O0P

7 7 7 7 7 7

7 4 4 7 4 4

4 7 4 4 7 4

4 4 7 4 4 4

B A O0P B A O0P

7 7 7 7 7 4

7 4 7 7 4 4

4 7 7 4 7 4

4 4 4 4 4 7

B A O0P A O0P

7 7 4 7 7

7 4 7 4 4

4 7 7

4 4 7

1. Determine t#e logic 'unction re&resente$ b) t#e 'ollo(ing Boolean

e:&ressions/

O0P J P O0P J A.B.C

O0P J P Q O0P J A.B

O0P J A B O0P J P Q

! PRACTICAL ELECTRONICS +NATIONAL !,



57/89

#&!IC CI$C+IT' T& B&EA E-%$E''I&' A" T$+TH TAB#E'

Converting logic circuits to Boolean expressions and

truth tables

Con%erting trut# tables or Boolean e:&ressions to logic circuits in%ol%e$ 'irst

i$enti')ing t#e out&ut gate an$ t#e number o' in&uts to t#at gate; t#en

(or-ing eac# o' t#ese in&uts in turn bac- to t#e in&ut signals using t#e

Boolean e:&ression 'or t#e out&ut o' eac# gate.

T#is time t#e logic circuit is -no(n an$ t#e Boolean e:&ression must be

$eri%e$ 'rom t#is logic circuit.

T#e tec#ni*ue 'or $oing t#is is t #e o&&osite o' t#at use$ to $etermine t#e

logic circuit. Instea$ o' (or-ing 'rom t#e out&ut bac- to t#e in&ut; t#e

Boolean e:&ression is $eri%e$ b) (or-ing 'rom t#e in&ut to t#e out&ut.

T#is is $one 'or eac# logical &at# in t#e circuit.

Example 1

Deri%e t#e Boolean e:&ression 'or t#e 'ollo(ing logic circuit.

B) loo-ing at t#e circuit; it can be seen t#at t#ere are t(o logical &at#s 'rom

t#e in&ut signals to t#e out&ut.

One &at# is t#roug# t#e to& AND gate an$ t#e ot#er &at# is t#roug# t#e

bottom OR gate.

>or- out 'or one o' t#ese gates; eg t#e AND gate; (#at its in&uts are an$

(#at t#e out&ut e:&ression is.

PRACTICAL ELECTRONICS +NATIONAL !, !3


A

B

C

A

A

B

C


58/89


T#e in&uts are A an$ B; an$ it is an AND gate so t#e out&ut is +A.B,.

No( re&eat t#is 'or t#e OR gate.

T#e in&uts are A an$ C; an$ it is an OR gate so t#e out&ut is +A C,.

>rite t#e out&ut e:&ression 'or t#e t(o gates on t#e res&ecti%e out&uts; as

s#o(n in t#e $iagram belo(.

It is sometimes a goo$ i$ea to enclose t#e in&uts to a logic gate in brac-ets.

T#is -ee&s t#e out&ut e:&ression eac# gate lin-e$ toget#er.

Use t#ese t(o out&uts; (#ic# are also t#e in&uts to t#e last AND gate; to$etermine t#e out&ut e:&ression 'or t#e AND gate. T#is is also t#e Boolean

'unction 'or t#e com&lete circuit.

!@ PRACTICAL ELECTRONICS +NATIONAL !,


A

B

C

A

A

B

C

+A.B,

+A C,

A

B

C

A

A

B

C

+A.B,

+A C,

+A.B,.+A C,


59/89


It is o'ten use'ul to &ro$uce t#e trut# table 'or t#e circuit as t#e 'unction o'

t#e circuit can t#en be $etermine$.

To ma-e t#ings a bit easier; t#e out&uts 'rom all t#e logic gates s#oul$ be

s#o(n on t#e trut# table; as $emonstrate$ belo(.

C B A A.B A C O0P J +A.B,.+A C,

7 7 7 7 7 7

7 7 4 7 4 7

7 4 7 7 7 7

7 4 4 4 4 4

4 7 7 7 4 7

4 7 4 7 4 74 4 7 7 4 7

4 4 4 4 4 4



In&uts A; B an$

C to t#e circuit.

T#is is t#e out&ut o' t#e

circuit. T#e in&uts are t#e

out&uts o' t#e AND an$

OR gates gi%en in t#e

&re%ious t(o columns.

T#is is t#e out&ut'rom t#e AND gatet#at #as A an$ B as itsin&uts.Remember; (it# an

AND gate all t#ein&uts nee$ to be atlogic 4 to &ro$uce alogic 4 on t#e out&uto' t#e gate.

T#is is t#e out&ut'rom t#e OR gate t#at#as A an$ C as itsin&uts.Remember (it# an

OR gate an) in&ut atlogic 4 &ro$uces alogic 4 on t#e out&uto' t#e gate.


60/89


Example

Deri%e t#e trut# table an$ Boolean e:&ression 'or t#e 'ollo(ing logic circuit/

T#is circuit is %er) similar to t#e one in E:am&le 4 but is being use$ to s#o(

#o( an out&ut (it# a bar abo%e it is #an$le$.

First i$enti') all t#e &at#s 'rom t#e in&ut to t#e out&ut an$ 'or eac# gate in

t#e &at#. Deri%e its out&ut e:&ression; remembering to enclose t#e out&uts o'

eac# gate in brac-ets.

T#e to& gate is a NOR gate; ie an OR gate (it# its out&ut in%erte$ so t#e

(#ole o' t#e out&ut (ill #a%e a bar abo%e it to s#o( t#is in%ersion.

T#e out&ut (ill be +A B,

T#e out&ut 'or t#e bottom NOR gate (ill be +A C,.

T#e out&ut o' t#e last AND gate (ill be +A B,.+A C,



A

B

C

A

A

B

C

A

B

C

A

A

B

C

+A B,

+A C,


61/89


T#e trut# table 'or t#e circuit is/

C B A

AB

A C

O0P J +AB,.+A C,

7 7 7 4 4 4

7 7 4 7 7 7

7 4 7 7 4 7

7 4 4 7 7 7

4 7 7 4 7 7

4 7 4 7 7 7

4 4 7 7 7 7

4 4 4 7 7 7

Remember A B an$ A C are NOR gates so t#e out&ut (ill onl) be logic 4

(#en bot# t#e in&uts are logic 7.

T#e out&ut is an AND gate so t#e out&ut (ill be logic 4 (#en all in&uts are

logic 4.



A

B

C

A

A

B

C

+A B,

+A C,

+A B,.+A C,


62/89


Example 2

Deri%e t#e trut# table an$ Boolean e:&ression 'or t#e 'ollo(ing logic circuit/

>rite t#e Boolean e:&ression 'or t#e out&ut o' t#e NAND gate/

As t#ere is onl) one gate connecte$ to t#e out&ut NOR gate; t#e out&ut

$iagram can no( be (ritten as/

3333333333

333

T#e out&ut e:&ression is t#ere'ore +A.B, C

T#e trut# table 'or t#is circuit is gi%en belo(/



A

B

C

A

B

C

+A.B,

A

B

C

+A.B,

+A.B, C


63/89


64/89


65/89


Tutorial* Conversion of logic circuits to Boolean expressions

Deri%e t#e trut# table an$ Boolean e:&ression 'or t#e out&ut o' t#e 'ollo(inglogic circuits.

4.

6.

1.



A

B

C

O0P

A

B

C

O0P

A

B

C

O0P


66/89


2.

!.

.



A

B

C

O0P

A

B

C

O0P

PQ

R

O0P


67/89


68/89


47.

44.

46.



A

B

C

D

O0P

O0P

A

B

C


69/89




A

B

C

A

B

C

O0P


70/89

B&EA E-%$E''I&' T& #&!IC CI$C+IT'

Converting Boolean expressions to logic circuits

Logic circuits can also be $esigne$ 'rom Boolean e:&ressions.

O'ten $esigners (or- out #o( t#e circuit s#oul$ &er'orm using Boolean

algebra. T#is (ill &ro$uce a Boolean e:&ression t#at $escribes t#e o&eration

o' t#e logic circuit.

As (as seen earlier (it# trut# tables; t#e out&ut gate is eit#er an OR gate or

an AND gate; an$ t#e Boolean e:&ression is al(a)s in t#e sum o' &ro$ucts

'orm.

>it# Boolean e:&ressions; #o(e%er; its not so sim&le. T#e out&ut gate coul$

be an) o' t#e basic gates an$ t#e out&ut coul$ be in t#e sum o' &ro$ucts +OR

or NOR gate, 'orm or it coul$ be in t#e &ro$uct o' sums 'orm. T#is 'orm is

(#ere eac# in&ut to t#e 'inal gate is connecte$ (it# an AND gate +or NAND,

so t#e out&ut gate is an AND gate +or NAND,; eg/

O0P J A B.A C

T#is is not %er) clear. o(e%er; i' brac-ets are use$; e:actl) t#e same as in

or$inar) algebra; t#e e:&ression becomes muc# clearer/

O0P J +A B,.+A C,

In t#is case t#e out&ut gate is an AND gate (it# t(o in&uts/ +A B, an$ +A

C,.

T#e circuit $iagram is $ra(n using e:actl) t#e same met#o$ as 'or t#e trut#tables; ie $ra( t#e out&ut gate t#en (or- eac# in&ut o' t#at gate bac- to t#e

in&ut o' t#e circuit.




71/89


'tep 1

Dra( t#e out&ut gate.

'tep

Ta-e eac# in&ut in turn an$ $etermine t#e gate an$ its in&uts.

First com&lete +A B,.



+A B,.+A C,

+A B,

+A C,

+A B,.+A C,

+A B,

+A C,

A

B


72/89


'tep 2

Com&lete +A C,.

Example 1

Design t#e logic circuit 'or t#e 'ollo(ing Boolean e:&ression.

O0P J +P Q,.R

T#e out&ut gate in t#is e:am&le is an AND gate (it# t(o in&uts/ +P Q, an$

R.

'tep 1

Dra( t#e out&ut gate an$ s#o( its in&uts.



+P Q,

R

O0P J +P Q,.R

+A B,.+A C,

+A B,

+A C,

A

B

C

Final circuit 'or +A B,.+A C,


73/89


'tep


Example

Design t#e logic circuit 'or t#e 'ollo(ing Boolean e:&ression.

O0P J +A B,. +A C,

At 'irst glance; t#is loo-s li-e an AND gate out&ut; but a closer ins&ections#o(s t#at t#ere is a bar abo%e t#e (#ole e:&ression. T#is means t#at t#e

out&ut gate is a NAND gate (it# t(o in&uts/

+A B,; ie a NOR gate; an$ +A C,; ie an OR gate.

'tep 1

Dra( t#e out&ut gate s#o(ing its in&uts.



+P Q,

O0P J +P Q,.R

R

R

Q

P

+A B,

+A C,

+A B,.+A C,


74/89


'tep




+A B,

+A C,

+A B,.+A C,

A

B

C

A

A

B

C


75/89


76/89


3. A B C

@. A.B C

. +P Q,.+P R,

47. +A.B, O C




77/89

T$+TH TAB#E' T& #&!IC CI$C+IT'

Converting truth tables to logic circuits

Logic gates can be use$ eit#er in$i%i$uall) or combine$ (it# ot#er logic

gates to &ro$uce circuits t#at &ro%i$e some 'unction.

For e:am a circuit is re*uire$ t#at (ill soun$ an alarm i' t#e (ater in a

tan- $ro&s to a le%el t#at acti%ates t#e lo( (ater le%el alarm an$ t#e $rain

%al%e is o&en. T#is is a sim&le AND 'unction (it# one in&ut 'rom t#e lo((ater alarm an$ t#e ot#er 'rom t#e $rain %al%e.

T#e lo( (ater le%el alarm signal is at logic 4 (#en t#e alarm is acti%ate$. T#e

$rain %al%e signal (ill be at logic 4 (#en t#e $rain %al%e is o&en.

T#e trut# table is/

Lo( (ater

le%el

Drain

%al%e

Buer

7 7 77 4 7

4 7 7

4 4 4

T#e Boolean e:&ression 'or t#is circuit is/

alarm J lo( (ater le%el 4 $rain %al%e

ie t#e alarm (ill soun$ (#en t#e (ater tri&s t#e lo( le%el alarm andt#e $rain

%al%e is o&en.



Lo( le%el

alarm

Drain %al%eBue

r


78/89


Example 1

A mac#ine 'or cutting metal (ill onl) acti%ate t#e cutter (#en t#e sa'et)guar$ is in &osition; t#e o&erator #ol$s t#e sa'et) #an$le an$ t#e 'oots(itc# is

acti%ate$.

T#is is anot#er AND 'unction; (it# t#e sa'et) guar$ as one in&ut; t#e sa'et)

#an$le as anot#er in&ut an$ t#e 'oots(itc# as t#e t#ir$ in&ut.

T#e trut# table is/


79/89


o(e%er; i' t#e in&ut to a logic gate is A +or P; or R etc., t#en t#is is t#e

o&&osite o' t#e in&ut signal an$ is &ro$uce$ b) using an in%erter gate in t#e

circuit to c#ange A to A.

Example

Consi$er t#e 'ollo(ing trut# table.

B A O0P

7 7 7

7 4 4

4 7 7

4 4 7

T#ere is onl) one con$ition (#ere t#e out&ut is at logic 4/ (#en in&ut A is at

logic 4 an$ in&ut B is at logic 7.

It is im&ortant to note t#at t#e in&uts to t#e circuit are A an$ B; an$ t#e out&ut

is O0P.

In&ut A is A but in&ut B; because it is at logic 7; is B. ie B not B.A.

B A O0P

7 7 7

7 4 4

4 7 7

4 4 7

In algebra 6 1 is t#e same as 1 6 an$ t#is is also true in Boolean algebra/

B.A is e:actl) t#e same as A.B

As t#ere is onl) one out&ut in t#e trut# table at logic 4; t#e Boolean

e:&ression 'or t#e trut# table is/

3

O0P J B.A

3

T#is coul$ also #a%e been (ritten as O0P J A.B.

All t#e in&uts 'or a &articular out&ut are connecte$ toget#er using an AND

'unction; as s#o(n abo%e.




80/89


All t#e circuits (e (ill loo- at in t#is course (ill #a%e t(o or more in&uts;

but onl) one out&ut. T#is means t#ere (ill be a single logic gate &ro$ucing

t#e out&ut.

T#is logic gate brings all t#e &arts o' eit#er t#e trut# table or t#e Boolean

e:&ression toget#er to a single out&ut.

I' (e are &ro$ucing a logic circuit 'rom a trut# table; t#en t#e out&ut gate (ill

al(a)s be an OR gate +or NOR, i' t#ere is more t#an one line in t#e trut#

table at logic 4.

I' t#ere is onl) one line on t#e trut# table at logic 4 t#en t#e out&ut gate (ill

be an AND gate +or NAND,.

Consi$er t#e e:am&le abo%e. T#e out&ut is gi%en b) A.B. T#is is calle$ t#e

&ro$uct o' sums 'orm; ie all in&uts are connecte$ b) an AND gate.

B) loo-ing at t#e e:&ression (e can see t#e t#ere are t(o in&uts; A an$ B;

an$ t#e gate is an AND gate; signi'ie$ b) t#e 5 o&erator.

T#e circuit (ill consist o' an AND gate (it# t(o in&uts; A an$ B.

B is sim&l) in&ut B &asse$ t#roug# an in%erter gate as s#o(n belo(/

T#is is t#e logic circuit $escribe$ b) t#e trut# table.

@7 PRACTICAL ELECTRONICS +NATIONAL !,


B

B

A

O0P J A.B


81/89


82/89


No( ta-e eac# in&ut in turn an$ $etermine t#e gate an$ its in&uts.

T#e in&ut R.P.Q is anot#er AND gate (it# in&uts R; P an$ Q as s#o(n belo(.

In&ut R is &ut t#roug# an in%erter gate to &ro$uce t#e re*uire$ in&ut to t#e

AND gate.

@6 PRACTICAL ELECTRONICS +NATIONAL !,


R.P.Q

R.P.Q

R.P.Q R.P.Q

R.P.Q

R.P.Q

R.P.Q R.P.Q

P

Q

R

R

Q

P


83/89


No( com&lete t#e circuit 'or R.P.Q.

T#e circuit is s#o(n belo( (it#out an) labels 'or clarit).

PRACTICAL ELECTRONICS +NATIONAL !, @1


R.P.Q

R.P.Q

R.P.Q R.P.Q

P

Q

P

R

Q

P

R

R.P.Q R.P.Q

R

Q

P


84/89


85/89


2.

C B A O0P7 7 7 7

7 7 4 7

7 4 7 7

7 4 4 7

4 7 7 7

4 7 4 7

4 4 7 4

4 4 4 7

!.

C B A O0P

7 7 7 7

7 7 4 4

7 4 7 7

7 4 4 7

4 7 7 7

4 7 4 7

4 4 7 74 4 4 7

.

C B A O0P

7 7 7 4

7 7 4 7

7 4 7 7

7 4 4 7

4 7 7 7

4 7 4 7

4 4 7 7

4 4 4 7

PRACTICAL ELECTRONICS +NATIONAL !, @!



86/89


3.

C B A O0P

7 7 7 77 7 4 7

7 4 7 4

7 4 4 7

4 7 7 7

4 7 4 7

4 4 7 7

4 4 4 4

@.

C B A O0P

7 7 7 7

7 7 4 7

7 4 7 7

7 4 4 4

4 7 7 4

4 7 4 7

4 4 7 7

4 4 4 7

.

C B A O0P

7 7 7 7

7 7 4 4

7 4 7 7

7 4 4 7

4 7 7 7

4 7 4 7

4 4 7 4

4 4 4 7




87/89


47.

R Q P O0P

7 7 7 47 7 4 4

7 4 7 4

7 4 4 4

4 7 7 4

4 7 4 4

4 4 7 4

4 4 4 7

44.

8 O0P

7 7 7 7

7 7 4 4

7 4 7 4

7 4 4 7

4 7 7 4

4 7 4 7

4 4 7 7

4 4 4 7

46.

C B A O0P

7 7 7 7

7 7 4 7

7 4 7 7

7 4 4 4

4 7 7 7

4 7 4 4

4 4 7 4

4 4 4 7

PRACTICAL ELECTRONICS +NATIONAL !, @3



88/89

A%%E"I- 1

Appendix 1

@@ PRACTICAL ELECTRONICS +NATIONAL !,


4

6

1

2

!

3

42

41

46

44

477

77

@

Pinout 'or

t#e

'ollo(ing

$e%ices

6788

6789

672

679:

I0P4

I0P4

O0P4

I0P6

I0P6

O0P6

7 H

Hcc

I0P2

I0P2

O0P2

I0P1

I0P1

O0P1

T)&ical

$e%ice

I0P 4

I0P 6

O0P

3277 *ua$ 6 I0P NAND gate

327@ *ua$ 6 I0P AND gate

3216 *ua$ 6 I0P OR gate

32@ *ua$ 6 I0P OR gate


89/89

A%%E"I- 1

4

6

1

2

!

3

42

41

46

44

47777

@

Pinout 'or

t#e

'ollo(ing

$e%ices

678Qua$ 6

I0P NOR

gate

O0P4

I0P4

I0P4

O0P6

I0P6

40P6

7 H

Hcc

O0P2

I0P2

I0P2

O0P1

I0P1

I0P1

4

6

1

2

!

3

42

41

46

44

47777

@

Pinout 'or

t#e

'ollo(ing$e%ices

6787

e:

In%erter

I0P4

O0P4

I0P6

O0P6

I0P1

O0P1

7 H

Hcc

I0P

O0P

I0P!

O0P!

I0P2

O0P2

practicalelectronicsnat5_tcm4-719530

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