7/28/2019 PPT on MOSFETs

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THE ROLE OF HIGH-K GATE DIELECTRIC MATERIALS OVER

SHORT CHANNEL PARAMETERS UNDER SUB-100 NM MOSFETSP K Agarwal ESC M.TECH ROLL NO: 211EE1323

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IntroductionThe major limitation in scaling of CMOS devices is the gate dielectric thickness [1-3]. The conventional silicon dioxide as

gate dielectric has reached the point where film thickness is only a few atomic layers thick. At these dimensions or below 1.5

nm, the direct tunnelling dramatically increases the leakage current which, consequently increases the static power and hence

affect the circuit operation [4-5]. To get rid of this critical problem, high-k dielectrics have been introduced by taking directly

on the silicon wafer or on the silicon dioxide layer. While keeping the equivalent oxide thickness (EOT) constant, high-k

dielectrics permits the increase in physical thickness (a factor of k/kSiO2) of the gate oxide to inhibit gate tunnelling [5-6].

However, it has been verified by device simulation that the use of high-k gate dielectrics directly on silicon wafer would

degrade the short channel performance. This degradation is mainly caused by the fringing fields either from the gate to the

source/drain regions or from the source/drain to the channel region which weakens the gate control[7]. But these shortcomings

to some extent can be overcome by taking the gate stack (GS) configuration i.e. high-k dielectrics over silicon dioxide layer [8-

11]. By taking a thick layer of dielectric material over a thin SiO 2 layer keeping EOT constant significantly reduces the gate

tunnelling current. In addition, there are various limitations with the use of high-k gate dielectrics as discussed: 1) the use of

high-k dielectrics results in polysilicon gate depletion effects and finite inversion layer (FIL) capacitance [6]. Gate depletion in

current polysilicon gate technology increases the effective gate thickness and degrades the device performance. Therefore, to

mitigate this problem, it is desirable to replace the polysilicon gate with mid-gap gates or metal gates. 2) Another challenge for

integrating high-k is the threshold voltage stability during operation. The shift in threshold voltage (V th) known as hysteresis

phenomenon is attributed to trapping of charges in the pre-existing traps without creation of additional traps. This problem is

somewhat mitigated by considering the Hafnium (Hf)-based dielectrics [4].

In this work, extensive simulations have been carried out to study the performance degradation due to fringing fields in

high-k dielectrics and its minimization by considering gate stack concept. Different gate stack configurations are simulated to

optimize the device performance by integrating high-k dielectrics into various structures.

Device Design

The schematic structure of DG MOSFET is shown in Fig. 1. In this structure the channel length (L) and Source/Drain

length (LS/LD) is fixed as 40nm, the silicon thickness (tSi) as 10nm and a uniform density of ND as 1020 cm-3 is taken. The

channel is doped with (NA) 1016 cm-3. Two different types of structural models have been considered. The first model isstructured considering single oxide layer and the second with gate stack. In each case the effective oxide thickness is fixed at

1.1nm. To maintain a constant capacitance for k=7.5, k=24 and k=50, the corresponding high-k thicknesses are 2.1nm, 6.8nm

and 14.1nm respectively in order to maintain a constant EOT=1.1nm for single layer configurations. Further for gate stack

configurations SiO2 layer thickness is fixed at 0.6nm and above this layer 0.5nm equivalent thickness of high-k layer is

deposited, so that the EOT reaches 1.1nm. This work considers the high-k dielectrics as Si3N4, HfO2 and Ta2O5 and the work

function for the gate material is assumed to be 4.8ev.

Result Analysis

The Sub threshold Slope (SS) is the major parameter for calculating the off state current. Furthermore, SS is calculated as:

(1)

The typical value for the SS of Multigate MOSFET is 60 mV /decade. The SS is extracted by calculating the inverse of

maximum slope of VG versus log (ID) curve as shown in the TABLE 1. It is clear that with increasing high-k dielectric

permittivity for single layer, the SS value also increases and reaches a value 75.53 mV/dec. But, while considering gate stack

configuration the SS value nearly approaches the ideal value. The threshold voltage (Vth) is also a very important parameter for

higher on state current which improves the circuit speed. The Vth is extracted by calculating the maximum slope of the ID-VG

curve, finding the intercept with the x-axis and then subtracting half of the applied drain bias as given in Table 1. However,with single layer for k=50 gives higher drive current (Ion). But, at the same time it also offers a high leakage current (Ioff) of the

order of 59pA which is undesirable. The gate stack configurations are showing higher values of gm which is required for analog

application. The DIBL calculation is performed for Vth at VD=0.1 V and VD=1.0 V. The GS structures predict better values of

DIBL as compared to single layer structures as shown in the TABLE 1. Again the off-state current (I off) is extracted by

calculating the drain current (ID) at VGS=0 and VDS=VDD. It is important to keep Ioffvery small in order to minimize the static

power dissipation when the device is in off state. The Ioff is very low for GS configuration which is our requirement. Fig.6

shows the potential distributions of different device structures by considering various gate dielectric materials to investigate the

effect of the fringing fields from source and drain through the gate insulator. A comparison is made between the single layer

and double layer gate oxide structures. By comparing the structures shown in Fig. 6 (b), (c) and (d) of single layer with

increasing k value (i.e. for k=7.5, 24 and 50), the electric fields from the source to the drain spread into the channel area. This

results in lowering of the channel barrier potential and induces the short channel effects. However, from the structures shown in

Fig. 6 (e), (f) and (g) with double layer/gate stack, the electric field lines gradually decreases from the channel. Therefore, the

potential barrier in the channel is not lowered.

Fig.1. (a) Schematic structure of Double Gate N-MOSFET Fig 2. Behaviour of ID as a function of VGS at VDS=0.1V and 1.0V

Fig3. ID as a function of VGS in log scale, Fig.4. Variation of transconductance (gm) with VGS at VDS=0.1V and 1.0V for different configurations.

Models of

DG

Vt(V) at

Vd=0.1V

Vt(V) at

Vd=1V

SS(mV/dec)

at Vd=0.1V

SS(mV/dec)

at Vd=1V

Ion(mA/um)

at Vd=0.1V

Ion(mA/um)

at Vd=1V

Ioff(pA)at

Vd=0.2V

Gm (mS)

at Vd=0.1V

Gm (mS)

at Vd=1V

DIBL

(mV/V)

(k=3.9) 0.49 0.11 62.01 62.22 0.64 1.41 0.393 1.81 3.63 341.54

(k=7.5) 0.49 0.11 62.15 62.32 0.64 1.42 0.397 1.82 3.64 342.00

(k=24) 0.48 0.09 65.13 65.37 0.65 1.48 0.845 1.81 3.66 347.93

(k=50) 0.44 0.03 75.53 76.34 0.67 1.73 59.028 1.71 3.65 375.46

GS-(k=7.5) 0.49 0.11 62.06 62.25 0.64 1.40 0.394 1.80 3.58 342.11

GS-(k=24) 0.49 0.11 61.80 61.94 0.66 1.49 0.390 1.90 3.84 341.26

GS-(k=50) 0.48 0.10 63.42 63.67 0.64 1.44 0.430 1.81 3.63 344.82

Table 1. Extracted Parameters

Fig 5. Variation of DIBL, Threshold Voltage and SS as a function of

gate dielectric permittivity (k) for different configurations

Fig. 6.The simulated results of the potential distribution in the gate

insulator for different configurations keeping EOT as 1.1nm in each case (a)

& (h) for single layer k=3.9 (b) for single layer k=7.5 (c) for single layer

k=24 (d) for single layer k=50 (e) for double layer/gate stack k=7.5 (f) for

double layer/gate stack k=24 (g) for double layer/gate stack k=50

ConclusionThe impact of high-k gate dielectrics on short channel effects in both single and double layer gate oxide structures have been studied. The degradation in short channel performance is

investigated by using ATLAS device simulator. This paper investigates the effect of fringing fields from the source and drain to the channel region in different structures with varying

permittivity. It is found that the degradation in short channel performance using high-k dielectrics is mainly due to the fringing fields from the gate to the source/drain regions. This work

also shows that superb short channel performance can be achievable by taking gate stack/double layer configurations. It is possible to suppress the fringing fields, leakage current (Ioff), SS

and DIBL by considering a thin layer of SiO2 with a thick layer of high-k dielectric material above it.

Abstract

The impact of dielectric materials with different dielectric permittivities as gate oxide on various short channel device parameters using a two

dimensional (2-D) device simulator are studied in this paper. It is found that the use of high-k dielectrics directly on the silicon wafer would degrade

the short channel performance. This degradation is mainly due to the fringing field effect developed from gate to source/drain. This fringing field willfurther generate electric field into the channel region from source/drain which weakens the gate control. Therefore, by taking the gate stack

engineering into account (i.e one thick layer of high-k dielectric taken over one thin layer of low-k dielectric) it is shown in this paper that we can

minimize the electric field as well as enhance the device performance. We also examined the variations of other short channel parameters like potential

distribution from source and drain, threshold voltage (Vth), drain induced barrier lowering (DIBL), subthreshold slope (SS), on-current (Ion), off-current

(Ioff) and Transconductance (gm) by taking different dielectric materials SiO2(=3.9), Si3N4 (=7.5), HfO2 (=24) and Ta2O5 (=50) as gate oxide.