Scheduler for ARM processor

By,Biju DanielJennis ThomasLinju Baby JohnNibas P PTony Lijo Jose

Government Engineering CollegeSreekrishnapuram

4th July 2011

Contents

I Introduction

I General view of an OS

I ARM Architecture

I Implementation and Design

I Conclusion

I Future Scope

I References

INTRODUCTION

I Embedded System and its Components.Three main components are there.

1. It has a hardware.2. It has a main application software.3. It has a real time operating system that supervises the

application software.

I Advantages of embedded systems.

I ARM Processor

Project work flow

Real Time Operating Sysyem

I A real-time operating system (RTOS) is an operatingsystem (OS) intended to serve real-time applicationrequests

I A key characteristic of a RTOS is the level of itsconsistency concerning the amount of time it takes toaccept and complete an application’s task

I A real-time OS has an advanced algorithm forscheduling

I A variant of OS that operates in constrainedenvironment in which computer memory and processingpower is limited

Scheduling

Two types of scheduling:I Non Preemptive

I First come first serve:–Assigns the priority in the order in which they requestthe processor.

I Shortest job next:–Scheduling algorithm chooses the process requiringminimum service time as its next one.

I PreemptiveI Round Robin:

–Distribution of processing time equitably among allprocesses requesting the processor.

InterruptsSteps in handling Interrupts

1. Disable further interrupts.

2. Store current state of program.

3. Execute appropriate interrupt handling routine.

4. Restore state of program.

5. Enable interrupts.

6. Resume program execution.

ARM Architecture

I Architectural simplicity of ARM processors (RISC)

I Low power consumption

I Load store architecture

I Uniform and fixed length instruction fields to simplifydecode instructions

ARM Register set

I ARM has 31 general-purpose 32-bit registers

I Only 16 registers are visible at a timeI Two registers in the visible set have special functions

I Link Register r14I Program Counter r15

Registers in the ARM set

ARM Architecture contd..ARM architecture data path

ARM Architecture contd..ARM instruction set

I Data processing instructions.

I Branch instructions.

I Load store instructions.

I Software interrupt instruction.

I Program status register instruction.

Implementation and Design 1The LPC2148 has the following memory regions

1. 512kb on-chip flash memory.This is where the load image of the program resides,including instructions and a read-only copy of the datasection

2. 32kB SRAM.This is where the user stack, data, and bss are located.Each thread gets its own stack.

3. 8kB USB DMA SRAM.The LPC2148 contains an additional 8kB of SRAMwhich can be used by the USB DMA engine, or if DMAis not used, can be used as general purpose RAM.We use this memory region for thebootloader/supervisor.

4. Peripheral address space.On-chip hardware peripherals, such as timers, SPIinterface, UART interface, USB interface, PWM block,and A/D converter are controlled through registerswhich are mapped to this region of memory

TCB

I The task array resides in the memory.

I TCB is a structure having an array of registers(unsigned int reg[16]), a CPSR(unsigned int), and tid(int).

I Static number of tasks,eg: define MAXTASKS 10

I Then the structure TCB is called.,TCB threadtab[MAXTASKS];

I Current index value is kept volatile.volatile int currindex;

Implementation and Design 1

Implementation and Design 2when an interrupt occurs the arm core does the following.

I (2)The current value of pc is copied to r14 irq

I The current value of cpsr is copied to spsr irq

I pc is loaded with the address 0x18 and the processormode is changed to irq mode with irq interruptsdisabled (to prevent interrupt from the interrupt.)

Implementation and Design 2

Implementation and Design 3

1. The IRQ vector at address 0x18 contains an LDRinstruction that causes the PC to jump to the IRQwrapper routine, called ARM irq, which is defined in thesupervisor.

2. The IRQ wrapper routine saves registers r0-r3 and r12to the IRQ scratch area. Remember that if a subroutinewants to use any of r4-r11, it must first push theexisting value to the stack.

3. The IRQ wrapper routine manually switches from IRQmode to SYS mode.

4. The IRQ wrapper routine saves lr to the IRQ scratcharea because it calls a subroutine. Recall that calling asubroutine, also called ”branch and link,” modifies thelr register, and that lr is a callee save register.Therefore the IRQ wrapper routine must save lr beforecalling any subroutines.

Implementation and Design 3

Implementation and Design 4

(6) The IRQ wrapper routine loads the address of theinterrupt service routine from the vectored interruptcontroller (VIC) and executes a branch and link to thisaddress. We have provided code thatconfigures the VIC to associatemythreadISRwiththetimer0interrupt.(7) timer isr() needs to save the state of task 0 tothreadtab[0] before it can load the state of thread 1.The state of a thread consists of the values of r0-r15 andcpsr BEFORE the processor was interrupted by the IRQexception. When timer isr() is called, the values ofr4-r11,r13 have not been modified since beforethe interrupt occurred, so you may save these values directlyto memory in the threadtab[0] structure.Also the r0-r3 and r12 is loaded to threadtab[0] from the irqscratch area.

Implementation and Design 4

(8) At this point, registers r0-r14 have been saved to thethreadtab[0] structure. You still need to save pcand cpsr to memory. How do we do this? Recall that whenthe exception occurred, the ARM hardware copied pcto r14 irq and cpsr to SPSR irq.(9) Now that you’re in IRQ mode, you can save the values ofr14 and spsr to memory. The state of task0 isnow saved to memory.

Implementation and Design 5

(10) Now you need to load the state of task1. Note thatwe’re still in IRQ mode, so load the values of pc and cpsrfrom memory into registers.(11) Switch back to SYS(12) Load r4-r11,r13 from memory into registers, and copyr0-r3,r12,lr from memory to the IRQ scratch area.

Implementation and Design 6

(13) return from the subroutine so that the execution willcontinue in the irq wrapper function.(14) The IRQ wrapper routine loads lr from the scratch areainto r14.(15) The IRQ wrapper routine switches from SYS mode toIRQ mode.(16) The IRQ wrapper routine loads r0-r3,r12 from thescratch area to registers.(17) The IRQ wrapper routine executes the return frominterrupt instruction (movs pc,lr), which resumes executionwhere task1 left off and copies spsr into cpsr in a single step.

Implementation and Design 7

CONCLUSION

I Familiarized ARM architecture

I Studied how to develop a realtime operating system

I Studied the functions of a scheduler and its workingalso familiarized with the routines inside the operatingsystem

I Major constraint- inside the ISR.

FUTURE SCOPE

I Apart from task scheduling, process scheduling can beimplemented if we have a better processor with memorymanagement unit

I File system can be developed

I Device drivers for different real time applications can bedeveloped

I Project can be extended to other platforms like atmel,avr, pic other arm platforms like arm cortex M 3, armcortex A 8, stellaris etc..

REFERENCES1. ARM System Developers guide.

Designing and Optimizing System Software By AndrewN. Sloss, Dominic Symes and Chris Wright.

2. User manual of LPC 214X3. ARM Assembly Language

Fundamentals and Techniques. By William Hohl4. µC/OS”TheRealTimeKernal”,ByJeanJ.Labrosse5. Embedded Systems. By Raj Kamal6. http://en.kioskea.net/contents/pc/ on june 20117.

http://infocenter.arm.com/help/topic/com.arm.doc.prd29-genc-009492c/

8. http://freertos.org ,on november 20109. http://linuxkernalcrossreference.com on november 2010

10. http://www.codesourcery.com/sgpp/lite/arm onJanuary 2011

11. http://qemu.org on January 201112. https://sites.google.com/a/eng.ucsd.edu/ece30/lab-6

on June 2011

THANK YOU