powerpoint presentationmoshovos/ece352-2016/adders.pdf · ppp c 2 1 0 in 21 (j ppp pc. + ppp g +...

16
Addition 1 0 1 1 0 1 1 0 0 1 1 0 1 1 1 1 FA A i B i S i C i-1 C i

Upload: others

Post on 18-Jun-2020

2 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

Addition

1 0 1 1 0

1 1 0 0 1

1 0 1 1 1 1

FA

Ai Bi

Si

Ci-1 Ci

Page 2: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

Full-Adder • s = A + B + Cin • Cout = A . Cin + B

FA

x y

S

Cin Cout

Page 3: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

N-Bit Ripple-Carry Adder

Page 4: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

Ripple-Carry Addition • Let’s add 0111 + 1001

Page 5: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

Subtraction • Note that -x = inverse of x + 1

Page 6: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

Delay through the Ripple-Carry Adder

• Two gates (AND and OR) Cin • Delay ~ 2 x N • N bits

Page 7: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

A Faster Adder • Each Stage either:

– Generates a Carry : 1 + 1 – Propagates a Carry: 1 + 0, 0 + 1, 0 + 0

Propagate Generate

Page 8: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

Carry-Lookahead Adder

Page 9: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

4-Bit CLA Adder

Page 10: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

CLA Adder Delay Analysis

Page 11: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

CLA Adder Delay Analysis

Page 12: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

Compound CLA Adder

Page 13: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

16-bit CLA Adder

Page 14: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

Delay of 16-bit CLA Adder

Page 15: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

Carry Select Adder • Say you wanted to calculate a 64-bit add • But you cannot fit it in a cycle • But you can fit 32-bit adds • What can you do?

Page 16: PowerPoint Presentationmoshovos/ECE352-2016/adders.pdf · PPP c 2 1 0 in 21 (J PPP Pc. + PPP G + PPG 321 The delay for all carry signals is 3 gate delays: 1. 1 OR for the P terms

Carry Select Adder • Calculate three sums in parallel • Lower 32-bit sum

– This produces a carry out at the 32-bit position

• Two Upper 32-bit sums – One that uses a 0 carry in – Another that uses a 1 carry in

• Once the Lower completes – Select which upper result is right