powerpc 74101163609326
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Features 22.8SPECint95(estimated),17SPECfp95at500MHz(estimated) 917MIPSat500MHz SelectableBusClock(14CPUBusDividersUpTo9x) SevenSelectableCore-to-L2FrequencyDivisors Selectable603InterfaceVoltageBelow3.3V(1.8V,2.5V)
SelectableL2interfaceof1.8Vor2.5V PDTypical5.3Wat500MHz,FullOperatingConditions Nap,DozeandSleepModesforPowerSaving Superscalar(FourInstructionsfetchedperClockCycle) 4GBDirectAddressingRange VirtualMemory:4hexabytes(252) 64-bitDataand32-bitAddressBusInterface 32KBInstructionandDataCache EightIndependentExecutionUnitsandThreeRegisterFiles Write-backandWrite-throughOperations fINTMax=450MHz(500MHztobeconfirmed) fBUSMax=133MHz
DescriptionThePC7410isthesecondmicroprocessorthatusesthefourth(G4)fullimplementa-tionofthePowerPCReducedInstructionSetComputer(RISC)architecture.ItisfullyJTAG-compliant.
ThePC7410maintainssomeofthecharacteristicsofG3microprocessors:
Thedesignissuperscalar,capableofissuingthreeinstructionsperclockcycleintoeightindependentexecutionunits
Themicroprocessorprovidesfoursoftwarecontrollablepower-savingmodesandathermalassistunitmanagement
Themicroprocessorhasseparate32-Kbyte,physically-addressedinstructionanddatacacheswithdedicatedL2cacheinterfacewithon-chipL2tags
Inaddition,thePC7410integratesfullhardware-basedmultiprocessingcapability,includinga5-statecachecoherencyprotocol(4MESIstatesplusafifthstateforsharedintervention)andanimplementationofthenewAltiVectechnologyinstruc-tionset.
Newfeatureshavebeendevelopedtomakelatencyequalfordouble-precisionandsingle-precisionfloating-pointoperationsinvolvingmultiplication.Additionally,inmem-orysubsystem(MSS)bandwidth,thePC7410offersanoptional,high-bandwidthMPXbusinterface.
UnlikethePC7400,thePC7410doesnotsupportthe3.3VI/OontheL2cacheinterface.
Screening CBGAUpscreeningsBasedonAtmelStandards
FullMilitaryTemperatureRange(Tj=-55C,+125C),IndustrialTemperatureRange(Tj=-40C,+110C)
CI-CGAPackageVersions
PowerPC7410
RISC
Microprocessor
Preliminary
Specification-site
PC7410
Rev.2141AHIREL03/02
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BlockDiagram
Figure1.PC7410MicroprocessorBlockDiagram
Fetcher
BranchProcessingUnit
Instruction
Queue
6-word
DispatchUnit
Instructio
nUnit
DataMMU
SRs
(
Original)
1
28-entry
DTLB
DBAT
Array
InstructionMMU
SRs
(
Shadow)
1
28-entry
ITLB
IBAT
Array
Reservat
ion
Station
Vector
Permute
Unit
Vector
ALU
Integer
Unit1
Integer
Unit2
System
Register
Unit
Reservation
Station
Reservation
Station
Reservation
Station
Reservation
Station
Reservation
Station
2-entry
Reserv
ation
Station
VR
File
6Rename
Buffers
GPR
File
6Rename
Buffe
rs
FPR
File
6Rename
Buffers
Load/Store
Unit
Floating
PointU
nit
Com
pletionUnit
8-entry
ReorderBuffer
VSIU
VCIU
VFPU
Tags
32-Kbyte
iCache
Tags
32-K
byte
DCa
che
6
4-entryBTIC/512-entryBHT
LR/CTR
Add-Multip
ly-
divide
-Add-
V
SCR
-Add-
Add-Multiply-
divid
e
FPSC
R
EACalculation
FinishedStores
Completed
Stores
128-bit
3
2-bit
128-bit
2Instructions
32-bit
64-bit
(2Instructions)
32-bitAddressBus
64-or32-bitL2DataBus
19-bitL2AddressBus
64-bitDataBus
32-bit
EA
PA
64-bit
64-bit
DataReload
Buffer
DataReload
Table
Instruction
ReloadBuffer
Instruction
ReloadTable
MemorySubsystem
L2Miss
Data
Transa
ction
Que
ue
L2Castout
BusInterfaceUnit
L2Data
Transaction
Queue
L2Co
ntroller
L2Tags
L2CR
L2PMCR
Additionalfeatures
TimeBase
Counter/Decre
menter
ClockMultiplie
r
JTAG/COPInt
erface
Thermal/Powe
rManagement
PerformanceM
onitor
128bits
128bits
(4instructions)
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GeneralParameters Table1providesasummaryofthegeneralparametersofthePC7410.
Note: 1. 3.3VI/Obusnotsupportedfor1.5Vcorepowersupplyprocessorversion.
Features ThissectionsummarizesfeaturesofthePC7410simplementationofthePowerPCarchitecture.MajorfeaturesofthePC7410areasfollows:
BranchProcessingUnit
Fourinstructionsfetchedperclock
Onebranchprocessedpercycle(plusresolvingtwospeculations)
Uptoonespeculativestreaminexecution,oneadditionalspeculativestreaminfetch
512-entrybranchhistorytable(BHT)fordynamicprediction
64-entry,4-waysetassociativebranchtargetinstructioncache(BTIC)foreliminatingbranchdelayslots
DispatchUnit
Fullhardwaredetectionofdependencies(resolvedintheexecutionunits)
Dispatchtwoinstructionstoeightindependentunits(system,branch,load/store,fixed-pointunit1,fixed-pointunit2,floating-point,AltiVecpermute,AltiVecALU)
Serializationcontrol(predispatch,postdispatch,executionserialization)
Decode
Registerfileaccess
Forwardingcontrol
Partialinstructiondecode
Completion
8-entrycompletionbuffer
Instructiontrackingandpeakcompletionoftwoinstructionspercycle
Completionofinstructionsinprogramorderwhilesupportingout-of-orderinstructionexecution,completionserializationandallinstructionflowchanges
Fixed-pointUnits(FXUs)thatShare32GPRsforIntegerOperands
Fixed-pointunit1(FXU1)multiply,divide,shift,rotate,arithmetic,logical
Table1.DeviceParameters
Parameter Description
Technology 0.18mCMOS,six-layermetal
Diesize 6.32mmx8.26mm(52mm2)
Transistorcount 10.5million
Logicdesign Fully-static
Packages Surface-mount,ceramic360-ballor-columngridarray
(CBGA/CI-CGA)
Corepowersupply 1.8V100mVdcor1.5V50mVdc(nominal;seeTable4for
RecommendedOperatingConditions)
I/Opowersupply 1.8V100mVdcor
2.5V100mVdc(inputthresholdsareconfigurationpinselectable)or3.3V100mV(603busonly)(1)
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Fixed-pointunit2(FXU2)shift,rotate,arithmetic,logical
Single-cyclearithmetic,shifts,rotates,logical
Multiplyanddividesupport(multi-cycle)
Earlyoutmultiply
Three-stageFloating-pointUnitanda32-entryFPRFile
SupportforIEEE-754standardsingle-anddouble-precisionfloating-pointarithmetic
Three-cyclelatency,one-cyclethroughput(singleordoubleprecision)
Hardwaresupportfordivide
Hardwaresupportfordenormalizednumbers
Timedeterministicnon-IEEEmode
SystemUnit
ExecutesCRlogicalinstructionsandmiscellaneoussysteminstructions
Specialregistertransferinstructions
AltiVecUnit
Full128-bitdatapaths Twodispatchableunits:vectorpermuteunitandvectorALUunit
Containsitsown32-entry128-bitvectorregisterfile(VRF)withsixrenames
ThevectorALUunitisfurthersub-dividedintothevectorsimpleintegerunit(VSIU),thevectorcomplexintegerunit(VCIU)andthevectorfloating-pointunit(VFPU).
Fullypipelined
Load/StoreUnit
One-cycleloadorstorecacheaccess(byte,half-word,word,double-word)
Two-cycleloadlatencywithone-cyclethroughput
Effectiveaddressgeneration Hitsundermisses(multipleoutstandingmisses)
Single-cycleunalignedaccesswithindouble-wordboundary
Alignment,zeropadding,signextendforintegerregisterfile
Floating-pointinternalformatconversion(alignment,normalization)
Sequencingforload/storemultiplesandstringoperations
Storegathering
ExecutesthecacheandTLBinstructions
Big-andlittle-endianbyteaddressingsupported
Misalignedlittle-endiansupported
SupportsFXU,FPU,andAltiVecload/storetraffic CompletesupportforallfourarchitectureAltiVecDSTstreams
Level1(L1)CacheStructure
32K32-byteline,8-waysetassociativeinstructioncache(iL1)
32K32-byteline,8-waysetassociativedatacache(dL1)
Single-cyclecacheaccess
Pseudoleast-recently-used(LRU)replacement
DatacachesupportsAltiVecLRUandtransientinstructionsalgorithm
Copy-backorwrite-throughdatacache(onapage-per-pagebasis)
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SupportsallPowerPCmemorycoherencymodes
Non-blockinginstructionanddatacache
Separatecopyofdatacachetagsforefficientsnooping
NosnoopingofinstructioncacheexceptforICBIinstruction
Level2(L2)CacheInterface
InternalL2cachecontrollerandtags;externaldataSRAMs
512K,1Mand2-Mbyte2-waysetassociativeL2cachesupport
Copybackorwrite-throughdatacache(onapagebasisorforallL2)
32-byte(512K),64-byte(1M),or128-byte(2M)sectoredlinesize
Supportspipelined(register-register)synchronousburstSRAMsandpipelined(register-register)late-writesynchronousburstSRAMs
Supportsdirectmappedmodefor256K,512K,1Mor2MbytesofSRAM(eitherall,halfornoneofL2SRAMmustbeconfiguredasdirectmapped.
Core-to-L2frequencydivisorsof1,1.5,2,2.5,3,3.5,and4supported
64-bitdatabuswhichalsosupport32-bitsbusmode Selectableinterfacevoltagesof1.8Vand2.5V
MemoryManagementUnit
128entry,2-waysetassociativeinstructionTLB
128entry,2-waysetassociativedataTLB
HardwarereloadforTLBs
FourinstructionBATsandfourdataBATs
Virtualmemorysupportforuptofourpetabytes(252)ofvirtualmemory
Realmemorysupportforuptofourgigabytes(232)ofphysicalmemory
SnoopedandinvalidatedforTLBIinstructions
EfficientDataFlow AlldatabusesbetweenVRF,load/storeunit,dL1,iL1,L2andthebusare
128bitswide
dL1isfullypipelinedtoprovide128bitspercycleto/fromtheVRF
L2isfullypipelinedtoprovide128bitsperL2clockcycletotheL1s
Uptoeightoutstandingout-of-ordercachemissesbetweendL1andL2/bus
Uptosevenoutstandingout-of-ordertransactionsonthebus
LoadfoldingtofoldnewdL1missesintoolderoutstandingloadandstoremissestothesameline
Storemissmergingformultiplestoremissestothesameline.Onlycoherencyactiontaken(i.e.,addressonly)forstoremissesmergedtoall32
bytesofacacheline(nodatatenureneeded). Two-entryfinishedstorequeueandfour-entrycompletedstorequeue
betweenload/storeunitanddL1
Separateadditionalqueuesforefficientbufferingofoutbounddata(castouts,writethroughs,etc.)fromdL1andL2
BusInterface
MPXbusextensionto60Xprocessorinterface
Mode-compatiblewith60xprocessorinterface
32-bitaddressbus
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64-bitdatabus
Bus-to-corefrequencymultipliersof2x,2.5x,3x,3.5x,4x,4.5x,5x,5.5x,6x,6.5x,7x,7.5x,8x,9xsupported
Selectableinterfacevoltagesof1.8V,2.5Vand3.3V
PowerManagement
Low-powerdesignwiththermalrequirementsverysimilartoPC740andPC750
Lowvoltage1.8Vor1.5Vprocessorcore
Selectableinterfacevoltagesof1.8Vcanreducepowerinoutputbuffers
Threestaticpowersavingmodes:doze,nap,andsleep
Dynamicpowermanagement
Testability
LSSDscandesign
IEEE1149.1JTAGinterface
Arraybuilt-inselftest(ABIST)factorytestonly
RedundancyonL1dataarraysandL2tagarrays ReliabilityandServiceability
Paritycheckingon60xandL2cachebuses
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SignalDescription Figure2.PC7410MicroprocessorSignalGroups
PCX7410
VDD OVDD AVDD
L2OVDD
L2AVDD
13 49 1
GND
TS
CHK
GBL
ARTRY
WT
CI
DBG
D[0:63]
DP[0:7]
TA
DTI1
TEA
BR
BG
ABB/AMON[0]
A[0:31]
AP[0:3]
TT[0:4]
TBST
TSIZ[0:2]
AACK
DBWO, DTI(0)
DBB, DMON(0)
DTI(2)
L2CE
L2WE
SRESET
HRESET
HIT
L2ADDR[0:18]
L2DATA[0:63]
L2DP[0:7]
L2CLKOUTA,L2CLKOUTB
L2SYNC_OUT
L2SYNC_IN
L2ZZ
INT
SMI
MCP
CKSTP_IN
CKSTP_OUT
SHDO, SHD1
RSRV
1
1
1
1
32
4
5
1
3
1
1
1
1
1
1
1
1
1
64
8
1
1
1
1
19
64
8
1
1
1
2
1
1
1
1
1
1
1
1
1
1
TBEN
EMODE
QREQ
QACK
DRDY
SYSCLK
PLL_CFG[0:3]
CLK_OUT
JTAG:COP
Factory Test
L1_TSTCLK,L2_TSTCLK
BVSEL
L2VSEL
1
2
1
1
1
1
1
1
1
4
1
5
3
1
112 20 1
L2 CacheAddress/Data
AddressArbitration
AddressBus
AddressStart
TransferAttribute
AddressTermination
DataArbitration
DataTransfer
DataTermination
L2 CacheClock/Control
InterruptsReset
ProcessorStatusControl
ClockControl
Test Interface
LSSD_MODE
I/O VoltageSelection
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DetailedSpecification
Scope ThisdrawingdescribesthespecificrequirementsforthemicroprocessorPC7410incompliancewithAtmel-Grenoblestandardscreening.
Applicable
Documents
1. MIL-STD-883:Testmethodsandproceduresforelectronics
2. MIL-PRF-38535:AppendixA:Generalspecificationsformicrocircuits
Requirements
General Themicrocircuitsareinaccordancewiththeapplicabledocumentsandasspecifiedherein.
DesignandConstruction
TerminalConnections Dependingonthepackage,theterminalconnectionsareasshowninTable15,Table4andFigure2.
AbsoluteMaximumRatings
Notes: 1. FunctionalandtestedoperatingconditionsaregiveninTable4.Absolutemaximum
ratingsarestressratingsonly.Stressesbeyondthoselistedmayaffectdevicereli-
abilityorcausepermanentdamagetothedevice.
2. Caution:VINmustnotexceedOVDDorL2OVDDbymorethan0.2Vatanytimeinclud-ingduringpower-onreset.
3. Caution:L2OVDD/OVDDmustnotexceedVDD/AVDD/L2AVDDbymorethan2.0Vatany
timeincludingduringpower-onreset.
4. Caution:VDD/AVDD/L2AVDDmustnotexceedL2OVDD/OVDDbymorethan0.4Vatany
time including during power-on reset. In addition, operation at nominal
VDD/AVDD/L2AVDDgreaterthannominalL2OVDDorOVDDinthe1.8Vinputthreshold
selectmodecancauseerraticoperationandACtimingvaluesworsethandescribed
inthisspecification.
5. VINmayovershoot/undershoottoavoltageandforamaximumdurationasshownin
Figure3.
Table2.AbsoluteMaximumRatings(1)
Symbol Characteristic Value Unit
VDD Coresupplyvoltage -0.3to2.1(4) V
AVDD PLLsupplyvoltage -0.3to2.1(4) V
L2AVDD L2DLLsupplyvoltage -0.3to2.1(4) V
OVDD 60xbussupplyvoltage -0.3to3.465(3)
V
L2OVDD L2bussupplyvoltage -0.3to2.6(3) V
VIN Processorbusinputvoltage -0.3toOVDD+0,2V(2)(5) V
VINL2businputvoltage -0.3toL2OVDD+0,2V(2)(5) V
VIN JTAGsignalinputvoltage -0.3toOVDD+0,2V V
TSTG Storagetemperaturerange -55to150 C
Reworktemp 260 C
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Figure3.Overshoot/UndershootVoltage
ThePC7410providesseveralI/Ovoltagestosupportbothcompatibilitywithexistingsystemsandmigrationtofuturesystems.ThePC7410corevoltagemustalwaysbeprovidedatnominalvoltage(seeTable4foractualrecommendedcorevoltage).Volt-agetotheL2I/OsandprocessorinterfaceI/Osareprovidedthroughseparatesetsofsupplypinsandmaybeprovidedatthevoltagesshownin Table3.TheinputvoltagethresholdforeachbusisselectedbysamplingthestateofthevoltageselectpinsatthenegationofthesignalHRESET.TheoutputvoltagewillswingfromGNDtothemaxi-
mumvoltageappliedtotheOVDDorL2OVDDpowerpins.
Notes: 1. Caution:TheinputthresholdselectionmustagreewiththeOVDD/L2OVDDvoltages
supplied.2. Toselectthe2.5Vthresholdoption,L2VSEL/BVSELshouldbetiedtoHRESETso
thatthetwosignalschangestatetogether.Thisisthepreferredmethodforselecting
thismodeoperation.
3. Defaultvoltagesettingifleftunconnected(internalpull-up).
4. Toovercometheinternalpullupresistance,apulldownresistancelessthan250shouldbeused.
5. Notsupportedfor1.5Vcorepowersupplyprocessorversion.
Table3.InputThresholdVoltageSetting
BVSELSignalProcessorBusInputThresholdisRelativeto: L2VSELSignal
L2BusInputThresholdisRelativeto:
0(1) 1.8V 0 1.8
HRESET(1)(2) 2.5V HRESET 2.5
1(1)(3) 3.3V(5) 1 2.5
HRESET 3.3V(5) HRESET Notsupported
Not to exceed 10% of tSYSCLK
(L2)OVDD + 20%
(L2)OVDD + 5%
(L2)OVDD
VIH
VIL
GND
GND - 0.3V
GND - 0.7V
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RecommendedOperatingConditions
Notes: 1. Thesearetherecommendedandtestedoperatingconditions.Properdeviceoperationoutsideoftheseconditionsisnot
guaranteed.2. Onlyavailableonrev1.4PC7410XXXnnnLEandlaterrevision.
3. OVDD=3.3Vnotsupportedfor1.5Vcorepowersupplyprocessorversions.
ThermalCharacteristics
PackageCharacteristics
TheboarddesignercanchoosebetweenseveralcommerciallyavailableheatsinktypestoplaceonthePC7410.Forexposed-diepackagingtechnologyasinTable5,theintrin-sicconductionthermalresistancepathsareshowninFigure4.
Table4.RecommendedOperatingConditions(1)
Symbol Characteristic
Recommended
ValueUnit
VDD Coresupplyvoltage 1.8100mV
or1.550mV
V
AVDD PLLsupplyvoltage 1.8100mV
or1.550mV
V
L2AVDD L2DLLsupplyvoltage 1.8100mV
or1.550mV
V
OVDD Processorbussupplyvoltageseenote(3) BVSEL=0 1.8100mV V
OVDD BVSEL=HRESET 2.5100mV V
OVDD(2)(3) BVSEL=1or=HRESET 3.3165mV V
L2OVDD L2bussupplyvoltage L2VSEL=0 1.8100mV VL2OVDD L2VSEL=1
(2)orL2VSEL=HRESET 2.5100mV V
VIN Inputvoltage Processorbus GNDtoOVDD V
VIN L2Bus GNDtoL2OVDD V
VIN JTAGSignals GNDtoOVDD V
Tj Die-junctiontemperature -55to125 C
Table5.PackageThermalCharacteristics
Symbol Characteristic Value Rating
JC CBGAandCI-CBGApackagesthermalresistance,diejunction-to-casethermalresistance
(typical)
0.03 C/W
JB CBGApackagethermalresistance,diejunction-to-leadthermalresistance(typical) 3.8 C/W
JB CI-CBGApackagethermalresistance,diejunction-to-leadthermalresistance(typical) 4 C/W
JA CBGApackagethermalresistance,diejunction-to-ambiantresistance(typical) 17.9 C/W
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ThermalManagementInformation
Thissectionprovidesthermalmanagementinformationfortheceramicballgridarray(CBGA)packageforair-cooledapplications.Properthermalcontroldesignisprimarilydependentuponthesystem-leveldesigntheheatsink,airflowandthermalinterfacematerial.Toreducethedie-junctiontemperature,heatsinksmaybeattachedtothepackagebyseveralmethods:adhesive,springcliptoholesintheprinted-circuitboardorpackageandmountingclipandscrewassembly;see Figure5.Thisspringforce
shouldnotexceed5.5poundsofforce.Ultimately,thefinalselectionofanappropriateheatsinkdependsonmanyfactorssuchasthermalperformanceatagivenairvelocity,spatialvolume,mass,attachmentmethod,assemblyandcost.
Figure5.CBGAPackageCross-sectionwithHeatSinkOptions
AdhesivesandThermalInterfaceMaterials
Athermalinterfacematerialisrecommendedatthepackagelid-to-heatsinkinterfacetominimizethethermalcontactresistance.Forthoseapplicationswheretheheatsinkisattachedbyspringclipmechanism,Figure6showsthethermalperformanceofthreethin-sheetthermal-interfacematerials(silicone,graphite/oil,floroetheroil),abarejointandajointwiththermalgreaseasafunctionofcontactpressure.Asshown,theperfor-manceofthesethermalinterfacematerialsimproveswithincreasingcontactpressure.Theuseofthermalgreasesignificantlyreducestheinterfacethermalresistance.Thatis,thebarejointresultsinathermalresistanceapproximatelyseventimesgreaterthanthethermalgreasejoint.
Heatsinksareattachedtothepackagebymeansofaspringcliptoholesintheprinted-circuitboard(seeFigure5).Thisspringforceshouldnotexceed5.5poundsofforce.Therefore,syntheticgreaseoffersthebestthermalperformance,consideringthelowinterfacepressure.
Theboarddesignercanchoosebetweenseveraltypesofthermalinterface.Heatsinkadhesivematerialsshouldbeselectedbaseduponhighconductivity,yetmusthaveadequatemechanicalstrengthtomeetequipmentshock/vibrationrequirements.
Printed-Circuit Board
Adhesive or Thermal Interface Material
Heat Sink ClipHeat Sink
Option
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Figure6.ThermalPerformanceofDifferentThermalInterfaceMaterials
HeatSinkSelectionExample Forpreliminaryheatsinksizing,thedie-junctiontemperaturecanbeexpressedasfollows:
where:
Tj=die-junctiontemperature
Ta=inletcabinetambienttemperature
Tr=airtemperaturerisewithinthecomputercabinet
jc=junction-to-casethermalresistance
int=adhesiveorinterfacematerialthermalresistance
sa=heatsinkbase-to-ambientthermalresistance
Pd=powerdissipatedbythedeviceDuringoperation,thedie-junctiontemperatures(Tj)shouldbemaintainedlessthanthevaluespecifiedin Table4.Thetemperatureoftheaircoolingthecomponentgreatlydependsupontheambientinletairtemperatureandtheairtemperaturerisewithintheelectroniccabinet.Anelectroniccabinetinlet-airtemperature(T a)mayrangefrom30Cto40C.Theairtemperaturerisewithinacabinet(Tr)maybeintherangeof5Cto10C.Thethermalresistanceofthethermalinterfacematerial( int)istypicallyabout1C/W.AssumingaTaof30C,aTrof5C,aCBGApackagejc =0.03,andapowerconsumption(Pd)of5.0watts,thefollowingexpressionforTjisobtained:
0
0.5
1
1.5
2
0 10 20 30 40 50 60 70 80
SiliconeSheet(0.006inch)BareJointFloroetherOilSheet(0.007inch)Graphite/OilSheet(0.005inch)SyntheticGrease
ContactPressure(psi)
SpecificThermalResistance(Kin
2/W)
Tj Ta Tr jc in t sa+ +( ) Pd+ +=
Tj 30C 5C 0.03C W 1.0C W sa+ +( ) 5W+ +=
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ForaThermallyheatsink#2328B,theheatsink-to-ambientthermalresistance(sa)ver-susairflowvelocityisshowninFigure7.
Figure7.Thermalloy#2328BHeatSink-to-ambientThermalResistancevs.AirflowVelocity
Assuminganairvelocityof0.5m/s,theeffectiveRsais7C/W,thus
,
resultinginadie-junctiontemperatureofapproximately75 Cwhichiswellwithinthemaximumoperatingtemperatureofthecomponent.
OtherheatsinksofferedbyChipCoolers,IERC,Thermalloy,WakefieldEngineeringandAavidEngineeringofferdifferentheatsink-to-ambientthermalresistancesandmayormaynotneedairflow.
Thoughthediejunction-to-ambientandtheheatsink-to-ambientthermalresistancesareacommonfigureofmeritusedforcomparingthethermalperformanceofvariousmicroelectronicpackagingtechnologies,oneshouldexercisecautionwhenonlyusing
thismetricindeterminingthermalmanagementbecausenosingleparametercanade-quatelydescribethree-dimensionalheatflow.Thefinaldie-junctionoperatingtemperatureisnotonlyafunctionofthecomponent-levelthermalresistance,butofthesystem-leveldesignanditsoperatingconditions.Inadditiontothecomponent'spowerconsumption,anumberoffactorsaffectthefinaloperatingdie-junctiontemperatureairflow,boardpopulation(localheatfluxofadjacentcomponents),heatsinkefficiency,heatsinkattach,heatsinkplacement,next-levelinterconnecttechnology,systemairtemperaturerise,altitude,etc.
1
3
5
7
8
0 0.5 1 1.5 2 2.5 3 3.5
ApproachAirVelocity(m/s)
HeatSinkT
hermalResistance(C/W)
2
4
6
Thermalloy#2328BPin-finHeatSink
(25x28x15mm)
Tj 30C 5C 0.03C W 1.0C W 7C W+ +( ) 5W+ +=
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Duetothecomplexityandthemanyvariationsofsystem-levelboundaryconditionsfortoday'smicroelectronicequipment,thecombinedeffectsoftheheattransfermecha-nisms(radiation,convectionandconduction)mayvarywidely.Forthesereasons,itisrecommendedtouseconjugateheattransfermodelsfortheboard,aswellassystem-leveldesigns.
Toexpeditesystem-levelthermalanalysis,severalcompactthermal-packagemodelsareavailablewithinFLOTHERM.Theseareavailableuponrequest.
PowerConsideration
PowerManagement ThePC7410providesfourpowermodes,selectablebysettingtheappropriatecontrolbitsintheMSRandHIDOregisters.Thefourpowermodesare:
Full-power:ThisisthedefaultpowerstateofthePC7410.ThePC7410isfullypoweredandtheinternalfunctionalunitsareoperatingatthefullprocessorclockspeed.Ifthedynamicpowermanagementmodeisenabled,functionalunitsthatareidlewillautomaticallyenteralow-powerstatewithoutaffectingperformance,softwareexecutionorexternalhardware.
Doze:AllthefunctionalunitsofthePC7410aredisabledexceptforthetimebase/decrementerregistersandthebussnoopinglogic.Whentheprocessorisindozemode,anexternalasynchronousinterrupt,asystemmanagementinterrupt,adecrementerexception,ahardorsoftresetormachinecheckbringsthePC7410intothefull-powerstate.ThePC7410indozemodemaintainsthePLLinafullypoweredstateandlockedtothesystemexternalclockinput(SYSCLK)soatransitiontothefull-powerstatetakesonlyafewprocessorclockcycles.
Nap:Thenapmodefurtherreducespowerconsumptionbydisablingbussnooping,leavingonlythetimebaseregisterandthePLLinapoweredstate.ThePC7410returnstothefull-powerstateuponreceiptofanexternalasynchronousinterrupt,asystemmanagementinterrupt,adecrementerexception,ahardorsoftresetoramachinecheckinput(MCP).Areturntofull-powerstatefromanapstatetakesonly
afewprocessorclockcycles.Whentheprocessorisinnapmode,ifQACKisnegated,theprocessorisputindozemodetosupportsnooping.
Sleep:Sleepmodeminimizespowerconsumptionbydisablingallinternalfunctionalunits,afterwhichexternalsystemlogicmaydisablethePLLandSYSCLK.ReturningthePC7410tothefull-powerstaterequirestheenablingofthePLLandSYSCLK,followedbytheassertionofanexternalasynchronousinterrupt,asystemmanagementinterrupt,ahardorsoftresetoramachinecheckinput(MCP)signalafterthetimerequiredtorelockthePLL.
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PowerDissipation
Notes: 1. ThesevaluesapplyforallvalidprocessorbusandL2busratios.Thevaluesdonot
includeI/Osupplypower(OVDDandL2OVDD)orPLL/DLLsupplypower(AVDDand
L2AVDD).OVDDandL2OVDDpowerissystemdependent,butistypically
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Electrical
Characteristics
StaticCharacteristics
Notes: 1. Nominalvoltages;seeTable4forRecommendedOperatingConditions.
2. Forprocessorbussignals,thereferenceisOVDDwhileL2OVDDisthereferencefortheL2bussignals.3. Excludestestsignals(LSSD_MODE,L1_TSTCLK,L2_TSTCLK)andIEEE1149.1boundaryscan(JTAG)signals.
4. Capacitanceisperiodicallysampledratherthan100%tested.
5. TheleakageismeasuredfornominalOVDDandVDD,orbothOVDDandVDDmustvaryinthesamedirection(forexample,
bothOVDDandVDDvarybyeither+5%or-5%).
Table8.DCElectricalSpecifications(seeTable4forRecommendedOperatingConditions)
Symbol Characteristic
NominalBus
Voltage(1) Min Max Unit
VIH Inputhighvoltage
(allinputsexceptSYSCLK)(2)(3)1.8 0.65x(L2)OVDD (L2)OVDD+0.2 V
VIH 2.5 1.7 (L2)OVDD+0.2 V
VIH 3.3 2.0 (L2)OVDD+0.3 V
VIL Inputlowvoltage
(allinputsexceptSYSCLK)
1.8 -0.3 0.35xOVDD V
VIL 2.5 -0.3 0.2x(L2)OVDD V
VIL 3.3 -0.3 0.8 V
CVIH SYSCLKinputhighvoltage(2)
1.8 1.5 OVDD+0.2 V
CVIH 2.5 2.0 OVDD+0.2 V
CVIH 3.3 2.4 OVDD+0.3 V
CVIL SYSCLKinputlowvoltage 1.8 -0.3 0.2 V
CVIL 2.5 -0.3 0.4 V
CVIL 3.3 -0.3 0.4 V
IIN Inputleakagecurrent,
VIN=L2OVDD/OVDD(2)(3)
10 A
ITSI High-Z(off-state)leakagecurrent,
VIN=L2OVDD/OVDD(2)(3)(5)
10 A
VOH Outputhighvoltage,
IOH=-6mA
1.8 (L2)OVDD-0.45 V
VOH 2.5 1.7 V
VOH 3.3 2.4 V
VOL Outputlowvoltage,
IOL=6mA
1.8 0.45 V
VOL 2.5 0.4 V
VOL 3.3 0.4 V
CIN Capacitance,VIN=0V,
f=1MHz(3)(4)7.5 pF
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DynamicCharacteristics Afterfabrication,partsaresortedbymaximumprocessorcorefrequencyasshowninClockACSpecificationsandtestedforconformancetotheACspecificationsforthatfrequency.Thesespecificationsareforvalidprocessorcorefrequencies.Theprocessorcorefrequencyisdeterminedbythebus(SYSCLK)frequencyandthesettingsofthePLL_CFG[0:3]signals.Partsaresoldbymaximumprocessorcorefrequency.
ClockACSpecifications Table9providestheclockACtimingspecificationsasdefinedinFigure8.
Notes: 1. Caution:TheSYSCLKfrequencyandPLL_CFG[0:3]settingsmustbechosensuchthattheresultingSYSCLK(bus)fre-
quency,CPU(core)frequencyandPLL(VCO)frequencydonotexceedtheirrespectivemaximumorminimumoperating
frequencies.RefertothePLL_CFG[0:3]signaldescriptioninClockSelectiononpage36forvalidPLL_CFG[0:3]settings
2. RiseandfalltimesfortheSYSCLKinputmeasuredfrom0.4Vto2.4VwhenOVDD=3.3Vnominal.
3. RiseandfalltimesfortheSYSCLKinputmeasuredfrom0.2Vto1.2VwhenOVDD=1.8Vor2.5Vnominal.
4. Timingisguaranteedbydesignandcharacterization.5. Thisrepresentstotalinputjitter,short-termandlong-termcombined,andisguaranteedbydesign.
6. Relocktimingisguaranteedbydesignandcharacterization.PLL-relocktimeis themaximumamountoftimerequiredfor
PLLlockafterastableVDDandSYSCLKarereachedduringthepower-onresetsequence.Thisspecificationalsoapplies
whenthePLLhasbeendisabledandsubsequentlyre-enabledduringsleepmode.AlsonotethatHRESETmustbeheld
assertedforaminimumof255busclocksafterthePLL-relocktimeduringthepower-onresetsequence.
Figure8.SYSCLKInputTimingDiagram
Note: VM=MidpointVoltage(OVDD/2)
Table9.ClockACTimingSpecifications(SeeTable4forRecommendedOperatingConditions)
Symbol Characteristic
MaximumProcessorCoreFrequency
Unit
400MHz 450MHz 500MHz
Min Max Min Max Min Max
fCORE(1) Processorfrequency 350 400 350 450 350 500 MHz
fVCO(1) VCOfrequency 450 800 450 900 450 1000 MHz
fSYSCLK(1) SYSCLKfrequency 33 133 33 133 33 133 MHz
tSYSCLK
SYSCLKcycletime 7.5 30 7.5 30 7.5 30 ns
tKR&tKF(2) SYSCLKriseandfalltime 1.0 1.0 1 ns
tKR&tKF(3) 0.5 0.5 0.5 ns
tKHKL/tSYSCLK(4) SYSCLKdutycyclemeasuredatOVDD/2 40 60 40 60 40 60 %
SYSCLKjitter(5) 150 150 150 ps
InternalPLLrelocktime(6) 100 100 100 s
SYSCLK
VM VM VM CVIL
CVIH
tKHKL
tSYSCLKtKR tKF
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ProcessorBusACSpecifications
Table10providestheprocessorACtimingspecificationsforthePC7410asdefinedinFigure10andFigure11.TimingspecificationsfortheL2busareprovidedinL2BusACSpecificationsonpage24.
Notes: 1. Allinputspecificationsaremeasuredfromthemidpointofthesignalinquestiontothemidpointoftherisingedgeoftheinput
SYSCLK.AlloutputspecificationsaremeasuredfromthemidpointoftherisingedgeofSYSCLKtothemidpointofthesig-
nal inquestion. Alloutput timings assume a purely resistive 50 load (see Figure 10).Inputand output timings are
measuredatthepin;time-of-flightdelaysmustbeaddedfortracelengths,viasandconnectorsinthesystem.
2. Thesymbologyusedfortimingspecificationshereinfollowsthepatternof
t(signal)(state)(reference)(state)forinputsandt(reference)(state)(signal)(state)foroutputs.Forexample,tIVKHsymbolizesthetimeinputsig-
nals(I)reachthevalidstate(V)relativetotheSYSCLKreference(K)goingtothehigh(H)stateorinputsetuptime.And
tKHOVsymbolizesthetimefromSYSCLK(K)goinghigh(H)untiloutputs(O)arevalid(V)oroutputvalidtime.Inputholdtime
canbereadasthetimethattheinputsignal(I)wentinvalid(X)withrespecttotherisingclockedge(KH)-notetheposition
ofthereferenceanditsstateforinputs-andoutputholdtimecanbereadasthetimefromtherisingedge(KH)untiltheout-
putwentinvalid(OX).
3. ThesetupandholdtimeiswithrespecttotherisingedgeofHRESET(seeFigure11).
4. Thisspecificationisforconfigurationmodeselectonly.AlsonotethattheHRESETmustbeheldassertedforaminimumof255busclocksafterthePLLre-locktimeduringthepower-onresetsequence.
5. tSYSCLKistheperiodoftheexternalclock(SYSCLK)innanoseconds(ns).Thenumbersgiveninthetablemustbemultiplied
bytheperiodofSYSCLKtocomputetheactualtimeduration(innanoseconds)oftheparameterinquestion.
6. ModeselectsignalsareBVSEL,EMODE,L2VSEL,PLL_CFG[0:3]
7. Allotheroutputsignalsarecomposedofthefollowing-A[0:31],AP[0:3],TT[0:4],TBST,TSIZ[0:2],GBL,WT,CI,DH[0:31],
DL[0:31],DP[0:7],BR,CKSTP_OUT,DRDY,HIT,QREQ,RSRV.
8. Outputvalidtimeismeasuredfrom2.4Vto0.8VwhichmaybelongerthanthetimerequiredtodischargefromVddto0.8V.
Table10.ProcessorBusACTimingSpecifications(1)atVDD=AVDD=1.8V100mV;-55C Tj 125C,OVDD=1.8V100mV
Symbol(2) Parameter
400,450,500MHz
UnitMin Max
tMVRH(3)(4)(5)(6) ModeselectinputsetuptoHRESET 8 t
SYSCLK
tMXRH(2)(3)(5) HRESETtomodeselectinputhold 0 ns
tIVKH InputSetup 1.0 ns
tIXKH InputHold 0 ns
tKHTSVtKHARV
tKHOV
OutputValidTimes:(7)(8)
TS
ARTRY/SHD0/SHD1
AllOtherOutputs
3.0
2.3
3.0
ns
tKHTSXtKHARXtKHOX
OutputHoldTimes:(7)(12)
TS
ARTRY/SHD0/SHD1
AllOtherOutputs
0.5
0.5
0.5
ns
tKHOE(11) SYSCLKtoOutputEnable 0.5 ns
tKHOZ SYSCLKtoOutputHighImpedance(allexceptABB/AMON[0],ARTRY/SHD,
DBB/DMON[0]),SHD0,SHD1)
3.5 ns
tKHABPZ(5)(9)(11) SYSCLKtoABB/AMON[0],DBB/DMON[0]HighImpedanceafterprecharge 1.0 t
SYSCLK
tKHARP(5)(10)(11) MaximumDelaytoARTRY/SHD0/SHD1Precharge 1 t
SYSCLK
tKHARPZ(5)(10)(11)
SYSCLKtoARTRY/SHD0/SHD1HighImpedanceAfterPrecharge 2 tSYSCLK
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9. Accordingtothe60xbusprotocol,ABBandDBBaredrivenonlybythecurrentlyactivebusmaster.Theyareassertedlow
thenprechargedhighbeforereturningtohigh-ZasshowninFigure9.ThenominalprechargewidthforABBorDBBis0.5x
tSYSCLK,i.e.,lessthantheminimumtSYSCLKperiod,toensurethatanothermasterassertingABB,orDBBonthefollowing
clockwillnotcontendwiththeprecharge.Outputvalidandoutputholdtimingistestedforthesignalasserted.Outputvalid
timeistestedforprecharge.Thehigh-Zbehaviorisguaranteedbydesign.
10. Accordingtothe60xbusprotocol,ARTRYcanbedrivenbymultiplebusmastersthroughtheclockperiodimmediatelyfol-
lowingAACK.BuscontentionisnotanissuesinceanymasterassertingARTRYwillbedrivingitlow.Anymasterasserting
itlowinthefirstclockfollowingAACKwillthengotohigh-Zforoneclockbeforeprechargingithighduringthesecondcycle
aftertheassertionofAACK.ThenominalprechargewidthforARTRYis1.0tSYSCLK;i.e.,itshouldbehigh-Zasshownin
Figure9beforethefirstopportunityforanothermastertoassertARTRY.Outputvalidandoutputholdtimingaretestedfor
thesignalasserted.Outputvalidtimeistestedforprecharge.Thehigh-Zbehaviorisguaranteedbydesign.
11. Guaranteedbydesignandnottested.
12. OutputholdtimecharacteristicscanbealteredbytheuseoftheL2_TSTCKpinduringsystemreset,similartoL2output
holdbeingalteredbytheuseofbits[14-15]intheL2CRregister.InformationontheoperationoftheL2_TSTCLKwillbe
includedinfuturerevisionsofthisspecification.
Figure9.Input/OutputTimingDiagram
tIVKHtIXKH
tKHOVtKHOX
tKHOE tKHOZ
tKHTSV
tKHTSV
tKHABPZ
tKHTSX
tKHARV
tKHARV
tKHARPZ
tKHARP
tKHARX
VM = Midpont Voltage (OVDD/2)
SYSCLK
All Inputs
VM VM VM
All Outputs(except TS, ABB,ARTRY, DBB)
TS,ABB/AMON[0],DBB/DMON[0]
All Outputs(except TS, ABB,ARTRY, DBB)
ARTRY,SHD0,SHD1
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Figure10.ACTestLoadforthe60xInterface
Figure11.ModeInputTimingDiagram
whereVM=MidpointVoltage(OVDD/2)
L2ClockACSpecifications TheL2CLKfrequencyisprogrammedbytheL2configurationregister(L2CR[4:6])core-to-L2divisorratio.SeeTable17forexamplecoreandL2frequenciesatvariousdivi-sors.Table11providesthepotentialrangeofL2CLKoutputACtimingspecificationsasdefinedinFigure12.
TheL2SYNC_OUTsignalisintendedtoberoutedhalfwayouttotheSRAMsandthenreturnedtotheL2SYNC_INinputoftheMPC7410tosynchronizeL2CLKOUTattheSRAMwiththeprocessorsinternalclock.L2CLKOUTattheSRAMcanbeoffsetfor-wardorbackwardintimebyshorteningorlengtheningtheroutingofL2SYNC_OUTtoL2SYNC_IN.SeeMotorolaApplicationNoteAN179/D"PowerPCBacksideL2TimingAnalysisforthePCBDesignEngineer."
TheminimumL2CLKfrequencyofTable11isspecifiedbythemaximumdelayofthe
internalDLL.Thevariable-tapDLLintroducesuptoafullclockperioddelayintheL2CLKOUTA,L2CLKOUTBandL2SYNC_OUTsignalssothatthereturningL2SYNC_INsignalisphasealignedwiththenextcoreclock(dividedbytheL2divisorratio).Donotchooseacore-to-L2divisorwhichresultsinanL2frequencybelowthisminimum,ortheL2CLKOUTsignalsprovidedforSRAMclockingwillnotbephasealignedwiththePC7410coreclockattheSRAMs.
ThemaximumL2CLKfrequencyshowninTable11isthecorefrequencydividedbyone.VeryfewL2SRAMdesignswillbeabletooperateinthismode.Mostdesignswillselectagreatercore-to-L2divisortoprovidealongerL2CLKperiodforreadandwriteaccesstotheL2SRAMs.ThemaximumL2CLKfrequencyforanyapplicationofthePC7410willbeafunctionoftheACtimingsofthePC7410,theACtimingsfortheSRAM,busloadingandprintedcircuitboardtracelength.
AtmelissimilarlylimitedbysystemconstraintsandcannotperformtestsoftheL2inter-faceonasocketedpartonafunctionaltesteratthemaximumfrequenciesof Table11.Therefore,functionaloperationandACtiminginformationaretestedatcore-to-L2divi-sorsof2orgreater.
Z0 = 50 Ohms
RL = 50 Ohms
OVDD/2Output
VM
tMVRH tMXRH
HRESET
MODE SIGNALS
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L2inputandoutputsignalsarelatchedorenabledrespectivelybytheinternalL2CLK(whichisSYSCLKmultiplieduptothecorefrequencyanddivideddowntotheL2CLKfrequency).Inotherwords,theACtimingsof Table12areentirelyindependentofL2SYNC_IN.Inaclosedloopsystem,whereL2SYNC_INisdriventhroughtheboardtracebyL2SYNC_OUT,L2SYNC_INonlycontrolstheoutputphaseofL2CLKOUTAandL2CLKOUTBwhichareusedtolatchorenabledataattheSRAMs.However,since
inaclosedloopsystemL2SYNC_INisheldinphasealignmentwiththeinternalL2CLK,thesignalsofTable12arereferencedtothissignalratherthanthenot-externally-visibleinternalL2CLK.Duringmanufacturingtest,thesetimesareactuallymeasuredrelativetoSYSCLK.
Notes: 1. L2CLKoutputsareL2CLK_OUTA,L2CLK_OUTB,andL2SYNC_OUTpins.TheL2CLKfrequencytocorefrequencyset-
tingsmustbechosensuchthattheresultingL2CLKfrequencyandcorefrequencydonotexceedtheirrespectivemaximum
or minimum operating frequencies. The maximum L2LCK frequency will be system-dependent. L2CLK_OUTA and
L2CLK_OUTBmusthaveequalloading.
2. ThenominaldutycycleoftheL2CLKis50%measuredatmidpointvoltage.
3. TheDLLre-locktimeisspecifiedintermsofL2CLKs.ThenumberinthetablemustbemultipliedbytheperiodofL2CLKtocomputetheactualtimedurationinnanoseconds.Re-locktimingisguaranteedbydesignandcharacterization.
4. TheL2CR[L2SL]bitshouldbesetforL2CLKfrequencieslessthan110MHz.ThisaddsmoredelaytoeachtapoftheDLL.
5. AllowableskewbetweenL2SYNC_OUTandL2SYNC_IN.
6. Guaranteedbydesignandnottested.Thisoutputjitternumberrepresentsthemaximumdelayofonetapforwardoronetap
backfromthecurrentDLLtapasthephasecomparatorseekstominimizethephasedifferencebetweenL2SYNC_INand
theinternalL2CLK.Thisnumbermustbe comprehended in theL2 timing analysis.The inputjitteronSYSCLK affects
L2CLKOUTandtheL2address/data/controlsignalsequallyandthereforeisalreadycomprehendedin theACtimingand
doesnothavetobeconsideredintheL2timinganalysis.
Table11.L2CLKOutputACTimingSpecificationsatRecommendedOperatingConditions(SeeTable4)
Symbol Parameter
400MHz 450MHz 500MHz
UnitMin Max Min Max Min Max
fL2CLK(1)(4) L2CLKfrequency 133 400 133 400 133 400 MHz
tL2CLK L2CLKcycletime 2.5 7.5 2.5 7.5 2.5 7.5 ns
tCHCL/tL2CLK(2)
L2CLKdutycycle 50 50 50 %
InternalDLL-relocktime(3) 640 640 640 - L2CLK
DLLcapturewindow(5) 0 10 0 10 0 10 ns
tL2CSKW L2CLKOUToutput-to-output
skew(6)- 50 - 50 - 50 ps
L2CLKOUToutputjitter(6) - 150 - 150 - 150 ps
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Figure12.L2CLK_OUTOutputTimingDiagram
Note: VM=MidpointVoltage(L2OVDD/2)
tCHCL
tL2CLK
tL2CR tL2CF
L2 Single-Ended Clock Mode
L2CLK_OUTA
L2CLK_OUTB
L2SYNC_OUT
L2CLK_OUTA
L2CLK_OUTB
L2SYNC_OUT
tCHCL
tL2CLK
VM VM VM
VM VM VM
VM VM VM
VM VM VM
VM VM VM
tL2CSKW
VM
L2 Differential Clock Mode
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L2BusACSpecifications Table12providestheL2businterfaceACtimingspecificationsforthePC7410asdefinedinFigure13andFigure14fortheloadingconditionsdescribedinFigure15.
Notes: 1. RiseandfalltimesfortheL2SYNC_INinputaremeasuredfrom20%to80%ofL2OVDD.
2. Allinputspecificationsaremeasuredfromthemidpointofthesignalinquestiontothemidpointvoltageoftherisingedgeof
theinputL2SYNC_IN(seeFigure13).Inputtimingsaremeasuredatthepins.
3. AlloutputspecificationsaremeasuredfromthemidpointvoltageoftherisingedgeofL2SYNC_INtothemidpointofthesig-
nalinquestion.Theoutputtimingsaremeasuredatthepins.Alloutputtimingsassumeapurelyresistive50load(see
Figure15).
4. The outputs are valid for bothsingle-ended and differential L2CLKmodes.For pipelined registered synchronousburst
RAMs, L2CR[14:15] = 00 is recommended. For pipelined late-write synchronous burst SRAMs, L2CR[14:15] = 10 is
recommended.
Figure13.L2BusInputTimingDiagram
Note: VM=MidpointVoltage(L2OVDD/2)
Table12.L2BusInterfaceACTimingSpecificationsatVDD=AVDD=L2AVDD=1.8V100mVor1.5V50mV;-55C Tj125C,L2OVDD=2.5V100mVorL2OVDD=1.8V100mV
Symbol Parameter
400,450,500MHz
UnitMin Max
tL2CR&tL2CF(1) L2SYNC_INriseandfalltime 1.0 ns
tDVL2CH(2)
SetupTimes
Dataandparity 1.5
ns
tDXL2CH(2)
InputHoldTimes
Dataandparity 0.0
ns
tL2CHOV(3)(4) ValidTimes
AlloutputswhenL2CR[14:15]=00
AlloutputswhenL2CR[14:15]=01
AlloutputswhenL2CR[14:15]=10
AlloutputswhenL2CR[14:15]=11
2.5
2.5
2.9
3.5
ns
tL2CHOX(3) OutputHoldTimes
AlloutputswhenL2CR[14:15]=00
AlloutputswhenL2CR[14:15]=01
AlloutputswhenL2CR[14:15]=10
AlloutputswhenL2CR[14:15]=11
0.4
0.8
1.2
1.6
ns
tL2CHOZ L2SYNC_INtohighimpedance
AlloutputswhenL2CR[14:15]=00
AlloutputswhenL2CR[14:15]=01
AlloutputswhenL2CR[14:15]=10
AlloutputswhenL2CR[14:15]=11
2.0
2.5
3.0
3.5
ns
L2SYNC_IN
L2 Data and DataParity Inputs
tL2CR tL2CF
tDVL2CHtDXL2CH
VM
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Figure14.L2BusOutputTimingDiagram
Note: VM=MidpointVoltage(L2OVDD/2)
Figure15.ACTestLoadfortheL2Interface
L2SYNC_IN
All Outputs
tL2CHOVtL2CHOX
VMVM
tL2CHOZ
L2DATA BUS
Z0 = 50 Ohms
RL = 50 Ohms
L2OVDD/2Output
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IEEE1149.1ACTimingSpecifications
Table13providestheIEEE1149.1(JTAG)ACtimingspecificationsasdefinedinFigure16,Figure17,Figure18andFigure19.
Notes: 1. Alloutputsaremeasuredfromthemidpointvoltageofthefalling/risingedgeofTCLK
tothemidpointofthesignalinquestion.Theoutputtimingsaremeasuredatthepins.
Alloutputtimingsassumeapurelyresistive50load(seeFigure16).Time-of-flight
delaysmustbeaddedfortracelengths,viasandconnectorsinthesystem.2. TRSTisanasynchronouslevelsensitivesignal.Thesetuptimeisfortestpurposes
only.
3. Non-JTAGsignalinputtimingwithrespecttoTCK.
4. Non-JTAGsignaloutputtimingwithrespecttoTCK.
5. Guaranteedbydesignandcharacterization
Figure16.AlternateACTestLoadfortheJTAGInterface
Figure17.JTAGClockInputTimingDiagram
Note: VM=MidpointVoltage(OVDD/2)
Table13.JTAGACTimingSpecifications(IndependentofSYSCLK) (1)atRecom-mendedOperatingConditions(seeTable4)
Symbol Parameter Min Max Unit
fTCLK TCKfrequencyofoperation 0 33.3 MHz
tTCLK TCKcycletime 30 ns
tJHJL TCKclockpulsewidthmeasuredatOVDD/2 15 ns
tJR&tJF TCKriseandfalltimes 0 2 ns
tTRST(2) TRSTasserttime 25 ns
tDVJH(3)
tIVJH
InputSetupTimes:
Boundary-scandata
TMS,TDI
4
0
ns
tDXJH(3)
tIXJH
InputHoldTimes:
Boundary-scandataTMS,TDI
2025
ns
tJLDV(4)
tJLOV
ValidTimes:
Boundary-scandata
TDO
4
4
20
25
ns
tJLDZ(4)(5)
tJLOZ(5)
TCKtooutputhighimpedance:
Boundary-scandata
TDO
3
3
19
9
ns
Z0 = 50 Ohms
RL = 50 Ohms
OVDD/2Output
CLK
tJR tJF
tJHJL
tTCLK
VMVM VM
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Figure18.TRSTTimingDiagram
Note: VM=MidpointVoltage(OVDD
/2)
Figure19.Boundary-scanTimingDiagram
Note: VM=MidpointVoltage(OVDD/2)
Figure20.TestAccessPortTimingDiagram
Note: VM=MidpointVoltage(OVDD/2)
TRST
tTRST
VMVM
TCK
tJLDX
VM
Boundary
Data Inputs
BoundaryData Outputs
Boundary
Data Outputs
VM
Input DataValid
tDVJHtDXJH
tJLDV
tJLDZ
Output Data Valid
Output Data Valid
TCK
tJLOX
VM
TDI, TMS
TDO
TDO
VM
Input DataValid
tIVJHtIXJH
tJLOV
tJLOZ
Output Data Valid
Output Data Valid
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Preparationfor
Delivery
CertificateofCompliance Atmel-Grenoblesuppliesacertificateofcompliancewitheachshipmentofparts,con-firmingthepartsareincompliancewithMIL-PRF-38535andguaranteeingthe
parametersnottestedatextremetemperaturesfortheentiretemperaturerange.
Handling MOSdevicesmustbehandledwithcertainprecautionstoavoiddamageduetoaccu-mulationofstaticcharge.Inputprotectiondeviceshavebeendesignedinthechiptominimizetheeffectofstaticbuildup.However,thefollowinghandlingpracticesarerecommended:
Devicesshouldbehandledonbencheswithconductiveandgroundedsurfaces.
Groundtestequipment,toolsandoperator.
Donothandledevicesbytheleads.
Storedevicesinconductivefoamorcarriers.
Avoiduseofplastic,rubberorsilkinMOSareas. Maintainrelativehumidityabove50%ifpractical.
ForCI-CGApackages,usespecifictraytotakecareofthehighestheightofthepackagecomparedwiththenormalCBGA.
PackageMechanicalData
Parameters Thepackageparametersareasprovidedinthefollowinglist.Thepackagetypeis25x25mm,360-leadCBGAandCI-CGA.
ThefollowingremarksapplytoFigure25andFigure26:
DimensionsandtolerancingareasperASMEY14.5M-1994. Alldimensionsareinmillimeters.
TopsideA1cornerindexisametallizedfeaturewithvariousshapes.BottomsideA1cornerisdesignatedwithaballmissingfromthearray.
DimensionBisthemaximumsolderballdiametermeasuredparalleltodatumA.
D2andE2definetheareaoccupiedbythedieandunderfill.Actualsizeofthisareamaybesmallerthanshown.D3andE3aretheminimumclearancefromthepackageedgetothechipcapacitors.
Table14.PackageParameters
Parameter
Packageoutline 25mmx25mm
Interconnects 360(19x19ballarrayminusone)
Pitch 1.27mm(50mil)
Minimummoduleheight 2.65mm(CBGA),3.65mm(CI-CGA)
Maximummoduleheight 3.20mm(CBGA),4.20mm(CI-CGA)
Ballorcolumndiameter 0.89mm(35mil)
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PinAssignment
BGA360Package Figure21,Figure22,Figure23andFigure24showtopviewsofthepackagesavailableforthePC7410.Notethatthesedrawingsarenottoscale.
Figure21.TopViewof360-BallCBGAand360-PinCI-CGAPackages
Figure22.TopViewof360-pinCBGAandCI-CGAPackages
Pin A1 Index
A
B
C
D
E
F
G
H
J
K
L
M
NP
R
T
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
U
V
W
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Figure23.Cross-sectionof360-ballCBGAPackage
Figure24.Cross-sectionof360-columnCI-CGAPackage
Substrate Assembly
Encapsulant
View
Die
View
Die
Substrate Assembly
Encapsulant
Table15.PinoutListingforthePC7410,360-ballCBGAandCI-CGApackages
SignalName PinNumber Active I/O I/FSelect(1)
A[0:31] A13,D2,H11,C1,B13,F2,C13,E5,D13,G7,F12,G3,G6,
H2,E2,L3,G5,L4,G4,J4,H7,E1,G2,F3,J7,M3,H3,J2,
J6,K3,K2,L2
High I/O BVSEL
AACK N3 Low Input BVSEL
ABB(12)
AMON[0](12)
L7 Low Output BVSEL
AP[0:3] C4,C5,C6,C7 High I/O BVSEL
ARTRY L6 Low I/O BVSEL
AVDD A8 Vdd
BG H1 Low Input BVSEL
BR E7 Low Output BVSEL
BVSEL(1)(3)(8)(9)(14) W1 High Input N/A
CHK(4)(8)(9) K11 Low Input BVSEL
CI C2 Low I/O BVSEL
CKSTP_IN B8 Low Input BVSEL
CKSTP_OUT D7 Low Output BVSEL
CLK_OUT E3 High Output BVSEL
DBB(12)
DMON[0](12)K5 Low Output BVSEL
DBG K1 Low Input BVSEL
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DH[0:31] W12,W11,V11,T9,W10,U9,U10,M11,M9,P8,W7,P9,
W9,R10,W6,V7,V6,U8,V9,T7,U7,R7,U6,W5,U5,W4,P7,V5,V4,W3,U4,R5
High I/O BVSEL
DL[0:31] M6,P3,N4,N5,R3,M7,T2,N6,U2,N7,P11,V13,U12,P12,T13,W13,U13,V10,W8,T11,U11,V12,V8,T1,P1,
V1,U1,N1,R2,V3,U3,W2
High I/O BVSEL
DP[0:7] L1,P2,M2,V2,M1,N2,T3,R1 High I/O BVSEL
DRDY(6)(8)(13) K9 Low Output BVSEL
DBWO
DTI[0]
D1 Low Input BVSEL
DTI[1:2](10)(13) H6,G1 High Input BVSEL
EMODE(7)(10) A3 Low Input BVSEL
GBL B1 Low I/O BVSEL
GND D10,D14,D16,D4,D6,E12,E8,F4,F6,F10,F14,F16,G9,
G11,H5,H8,H10,H12,H15,J9,J11,K4,K6,K8,K10,K12,
K14,K16,L9,L11,M5,M8,M10,M12,M15,N9,N11,P4,
P6,P10,P14,P16,R8,R12,T4,T6,T10,T14,T16
N/A
HIT(6)(8) B5 Low Output BVSEL
HRESET B6 Low Input BVSEL
INT C11 Low Input BVSEL
L1_TSTCLK(2) F8 High Input BVSEL
L2ADDR[0:16] L17,L18,L19,M19,K18,K17,K15,J19,J18,J17,J16,H18,
H17,J14,J13,H19,G18
High Output L2VSEL
L2ADDR[17:18](8) K19,W19 High Output L2VSEL
L2AVDD L13 Vdd
L2CE P17 Low Output L2VSEL
L2CLKOUTA N15 High Output L2VSEL
L2CLKOUTB L16 High Output L2VSEL
L2DATA[0:63] U14,R13,W14,W15,V15,U15,W16,V16,W17,V17,U17,
W18,V18,U18,V19,U19,T18,T17,R19,R18,R17,R15,
P19,P18,P13,N14,N13,N19,N17,M17,M13,M18,H13,
G19,G16,G15,G14,G13,F19,F18,F13,E19,E18,E17,
E15,D19,D18,D17,C18,C17,B19,B18,B17,A18,A17,
A16,B16,C16,A14,A15,C15,B14,C14,E13
High I/O L2VSEL
L2DP[0:7] V14,U16,T19,N18,H14,F17,C19,B15 High I/O L2VSEL
L2OVDD(11) D15,E14,E16,H16,J15,L15,M16,K13,P15,R14,R16,
T15,F15
N/A
L2SYNC_IN L14 High Input L2VSEL
L2SYNC_OUT M14 High Output L2VSEL
L2_TSTCLK(2) F7 High Input BVSEL
L2VSEL(1)(3)(8)(9)(14) A19 High Input N/A
Table15.PinoutListingforthePC7410,360-ballCBGAandCI-CGApackages(Continued)
SignalName PinNumber Active I/O I/FSelect(1)
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Notes: 1. OVDDsuppliespowertotheprocessorbus,JTAGandallcontrolsignalsexcepttheL2cachecontrols(L2CE,L2WE,andL2ZZ); L2OVDD supplies power to the L2 cache interface (L2ADDR[0:18], L2ASPARE, L2DATA[0:63], L2DP[0:7] and
L2SYNC_OUT)andtheL2controlsignalsandVDDsuppliespowertotheprocessorcoreandthePLLandDLL(afterfiltering
tobecomeAVDDandL2AVDDrespectively).Thesecolumnsserveasareferenceforthenominalvoltagesupportedona
givensignalasselectedbytheBVSEL/L2VSELpinconfigurationsof Table3andthevoltagesupplied.Foractualrecom-
mendedvalueofVINorsupplyvoltages,seeTable4.
2. ThesearetestsignalsforfactoryuseonlyandmustbepulleduptoOVDDfornormalmachineoperation.
3. ToallowforfutureI/Ovoltagechanges,providetheoptiontoconnectBVSELandL2VSELindependentlytoeitherOVDD(selects2.5V),GND(selects1.8V),ortoHRESET(selects2.5V).ThePC7410Boththe60xprocessorbusandtheL2bus
onlysupportthe1.8and2.5options(seeTable3).thedefaultselectionifBVSELand/orL2VSELisleftunconnectedis2.5V
4. ConnecttoHRESETtotriggerpostpower-on-reset(por)internalmemorytest.
L2WE N16 Low Output L2VSEL
L2ZZ G17 High Output L2VSEL
LSSD_MODE
(2)
F9 Low Input BVSELMCP B11 Low Input BVSEL
OVDD D5,D8,D12,E4,E6,E9,E11,F5,H4,J5,L5,M4,P5,R4,
R6,R9,R11,T5,T8,T12
N/A
PLL_CFG[0:3] A4,A5,A6,A7 High Input BVSEL
QACK B2 Low Input BVSEL
QREQ J3 Low Output BVSEL
RSRV D3 Low Output BVSEL
SHD0(8) B3 Low I/O BVSEL
SHD1(5)(8) B4 Low I/O BVSEL
SMI A12 Low Input BVSEL
SRESET E10 Low Input BVSEL
SYSCLK H9 Input BVSEL
TA F1 Low Input BVSEL
TBEN A2 High Input BVSEL
TBST A11 Low Output BVSEL
TCK B10 High Input BVSEL
TDI(9) B7 High Input BVSEL
TDO D9 High Output BVSEL
TEA J1 Low Input BVSEL
TMS(9) C8 High Input BVSEL
TRST(9)(14) A10 Low Input BVSEL
TS K7 Low I/O BVSEL
TSIZ[0:2] A9,B9,C9 High Output BVSEL
TT[0:4] C10,D11,B12,C12,F11 High I/O BVSEL
WT C3 Low I/O BVSEL
VDD G8,G10,G12,J8,J10,J12,L8,L10,L12,N8,N10,N12 N/A
Table15.PinoutListingforthePC7410,360-ballCBGAandCI-CGApackages(Continued)
SignalName PinNumber Active I/O I/FSelect(1)
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5. Ignoredin60xbusmode.
6. Unusedoutputin60xbusmode.
7. Deasserted(pulledhigh)atHRESETfor60xbusmode.
8. Usesoneof9existingno-connectsinPC750s360-ballBGApackage.
9. Internalpull-upondie.
10. ReusesPC750sDRTRY,DBDISandTLBISYNCpins(DTI1,DTI2andEMODErespectively).
11. TheVOLTDETpinpositiononthePC750360-ballCBGApackageisnowanL2OVDDpinonthePC7410packages.
12. OutputonlyforPC7410,wasI/OforPC750.
13. Enhancedmodeonly.
14. Toovercometheinternalpull-upresistanceandensurethisinputwillrecognizealowsignal,apull-downresistanceless
than250shouldbeused.
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Figure25.MechanicalDimensionsandBottomSurfaceNomenclatureofthe360-ballCBGAPackage
Parameter Min Max Parameter Min Max
A 2.62 3.20 D3 2.75
A1 0.8 1.00 D4 6.32
A2 1.10 1.30 E 25.00BASIC
A3 0.6 E1 22.86BASIC
A4 0.82 0.9 E2 12.6typ
B 0.82 0.93 E3 3.00
D 25.00BASIC E4 8.26
D1 22.86BASIC G 1.27BASIC
D2 10typ
A
A1
A2
A
0.15 A
FT360X
G
1 2 3 4 5 6 7 8 9 10 111213141516
A
B
C
DE
F
G
H
J
K
L
M
N
P
R
T
E0.3
T0.15
B
171819
U
W
V
K
K
DPIN A1
E
D4
0.22X
B
E2
TOP VIEW
INDEX
D3
E
3
0.2
2X
A3
A4
D1
E1
C
D2
E4
BOTTOM VIEW
0.2
2X
360 X
0.35 A
GND : C1.2 C2.2 C3.2 C4.2 C5.2 C6.2
C1.1, C2.1 : L2OVDD
C3.1, C6.1 : OVDD
C4.1, C5.1 : OVDD
C6
C1
C2
C3
C4
C5
2
1
1 2
1 2
12
12
1
2
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Figure26.MechanicalDimensionsandBottomSurfaceNomenclatureofthe360-columnCI-CGAPackage
Parameter Min Max Parameter Min Max
A 3.4 4.20 D3 2.75
A1 1.545 1.695 D4 6.32
A2 1.10 1.30 E 25.00BASICA3 0.6 E1 22.86BASIC
A4 0.82 0.9 E2 15
B 0.82 0.93 E3 3.00
D 25.00BASIC E4 8.26
D1 22.86BASIC G 1.27BASIC
D2 13
A
A1
A2
A
0.15 A
FT360X
G
1 2 3 4 5 6 7 8 9 10 111213141516
A
B
CD
E
F
G
H
J
K
L
M
N
P
R
T
E0.3
T0.15
B
171819
U
W
V
K
K
DPIN A1
E
D4
0.22X
B
E2
TOP VIEW
INDEX
D3
E3
0.2
2X
A3
A4
D1
E1
C
D2
E4
0.2
2X
360 X
0.35 A
GND : C1.2 C2.2 C3.2 C4.2 C5.2 C6.2
C1.1, C2.1 : L2OVDD
C3.1, C6.1 : OVDD
C4.1, C5.1 : OVDD
C6
C1
C2
C3
C4
C5
2
1
1 2
1 2
12
2
1
2
1
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ClockSelection ThePC7410sPLLisconfiguredbythePLL_CFG[0:3]signals.ForagivenSYSCLK(bus)frequency,thePLLconfigurationsignalssettheinternalCPUandVCOfrequencyofoperation.ThePLLconfigurationforthePC7410isshowninTable16forexamplefrequencies.
Notes: 1. PLL_CFG[0:3]settingsnotlistedarereserved.
2. Thesamplebus-to-corefrequenciesshownareforreferenceonly.SomePLLconfigurationsmayselectbus,core,orVCO
frequencieswhicharenotuseful,notsupported,ornottestedforbythePC7410;seeClockACSpecificationsonpage18
forvalidSYSCLK,core,andVCOfrequencies.
3. InPLL-bypassmode,theSYSCLKinputsignalclockstheinternalprocessordirectly,thePLLisdisabled,andthebusmode
issetfor1:1modeoperation.Thismodeisintendedforfactoryuseonly.
Note:TheACtimingspecificationsgiveninthisdocumentdonotapplyinPLL-bypassmode.
4. InPLL-offmode,noclockingoccursinsidethePC7410regardlessoftheSYSCLKinput.
Table16.PC7410MicroprocessorPLLConfiguration
PLL_C
FG[0:3]
ExampleBus-to-CoreFrequencyinMHz(VCOFrequencyinMHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus
33.3MHz
Bus
50MHz
Bus
66.6MHz
Bus
75MHz
Bus
83.3MHz
Bus
100MHz
Bus
133MHz
0100 2x 2x
0110 2.5x 2x
1000 3x 2x 400(800)
1110 3.5x 2x 350(700) 465(930)
1010 4x 2x 400(800)
0111 4.5x 2x 375(750) 450(900)
1011 5x 2x 375(750) 416(833) 500(1000)
1001 5.5x 2x 366(733) 412(825) 458(916)
1101 6x 2x 400(800) 450(900) 500(1000)
0101 6.5x 2x 433(866) 488(967)
0010 7x 2x 350(700) 466(933)
0001 7.5x 2x 375(750) 500(1000)
1100 8x 2x 400(800)
0000 9x 2x 450(900)
0011 PLLoff/bypass PLLoff,SYSCLKclockscorecircuitrydirectly,1xbus-to-coreimplied
1111 PLLoff PLLoff,nocoreclockingoccurs
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ThePC7410generatestheclockfortheexternalL2synchronousdataSRAMsbydivid-ingthecoreclockfrequencyofthePC7410.Thedivided-downclockisthenphase-adjustedbyanon-chipdelay-lock-loop(DLL)circuitandshouldberoutedfromthePC74107410totheexternalRAMs.Aseparateclockoutput,L2SYNC_OUTissentouthalfthedistancetotheSRAMsandthenreturnedasaninputtotheDLLonpinL2SYNC_INsothattherising-edgeoftheclockasseenattheexternalRAMscanbe
alignedtotheclockingoftheinternallatchesintheL2businterface.
Thecore-to-L2frequencydivisorfortheL2PLLisselectedthroughtheL2CLKbitsoftheL2CRregister.Generally,thedivisormustbechosenaccordingtothefrequencysupportedbytheexternalRAMs,thefrequencyofthePC7410coreandthephaseadjustmentrangethattheL2DLLsupports.Table17showsvariousexamplesofL2clockfrequenciesthatcanbeobtainedforagivensetofcorefrequencies.TheminimumL2frequencytargetis100MHz.
Note: ThecoreandL2frequenciesareforreferenceonly.Someexamplesmayrepresentcore
orL2frequencieswhicharenotuseful,notsupportedornottestedforbythePC7410;
see L2 Clock AC Specifications on page 21 for valid L2CLK frequencies. The
L2CR[L2SL]bitshouldbesetforL2CLKfrequencieslessthan110MHz.
SystemDesign
Information
PLLPowerSupplyFiltering
TheAVDDandL2AVDDpowersignalsareprovidedonthePC7410toprovidepowertotheclockgenerationphase-lockedloopandL2cachedelay-lockedloop,respectively.Toensurestabilityoftheinternalclock,thepowersuppliedtotheAVDDinputsignalshouldbefilteredofanynoiseinthe500kHzto10MHzresonantfrequencyrangeofthePLL.Acircuitsimilartotheoneshownin Figure27usingsurfacemountcapacitorswithminimumeffectiveseriesinductance(ESL)isrecommended.
ThecircuitshouldbeplacedascloseaspossibletotheAVDDpintominimizenoisecou-pledfromnearbycircuits.AnidenticalbutseparatecircuitshouldbeplacedascloseaspossibletotheL2AVDDpin.ItisoftenpossibletoroutedirectlyfromthecapacitorstotheAVDDpin,whichisontheperipheryofthe360-ballCBGAfootprintwithouttheinduc-tanceofvias.TheL2AVDDpinmaybemoredifficulttoroutebutisproportionatelylesscritical.
Table17.SampleCore-to-L2Frequencies
CoreFrequencyinMHz 1 1.5 2 2.5 3 3.5 4
350 350 233 175 140 117 100
366 366 244 183 147 122 105
400 400 266 200 160 133 114 100
433 - 288 216 173 144 123 108
450 - 300 225 180 150 128 112
466 311 233 186 155 133 116
500 333 250 200 166 143 125
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Figure27.PLLPowerSupplyFilterCircuit
PowerSupplyVoltageSequency
ThenotesinTable2containcautionsaboutthesequencingoftheexternalbusvoltagesandcorevoltageofthePC7410(whentheyaredifferent).Thesecautionsarenecessaryforthelongtermreliabilityofthepart.Iftheyareviolated,theelectrostaticdischarge(ESD)protectiondiodeswillbeforward-biasedandexcessivecurrentcanflowthroughthesediodes.Ifthesystempowersupplydesigndoesnotcontrolthevoltagesequenc-ing,oneorbothofthecircuitsofFigure28canbeaddedtomeettheserequirements.TheMUR420Schottkydiodesof Figure28controlthemaximumpotentialdifferencebetweentheexternalbusandcorepowersuppliesonpower-upandthe1N5820diodesregulatethemaximumpotentialdifferenceonpower-down.
Figure28.ExampleVoltageSequencingCircuits
DecouplingRecommendations
DuetothePC7410sdynamicpowermanagementfeature,largeaddressanddatabusesandhighoperatingfrequencies,thePC7410cangeneratetransientpowersurgesandhighfrequencynoiseinitspowersupply,especiallywhiledrivinglargecapacitiveloads.ThisnoisemustbepreventedfromreachingothercomponentsinthePC7410systemandthePC7410itselfrequiresaclean,tightlyregulatedsourceofpower.There-fore,itisrecommendedthatthesystemdesignerplaceatleastonedecouplingcapacitorateachVDD,OVDD,andL2OVDDpinofthePC7410.ItisalsorecommendedthatthesedecouplingcapacitorsreceivetheirpowerfromseparateV DD,(L2)OVDD,andGNDpowerplanesinthePCB,utilizingshorttracestominimizeinductance.
Thesecapacitorsshouldhaveavalueof0.01For0.1F.OnlyceramicSMT(surfacemounttechnology)capacitorsshouldbeusedtominimizeleadinductance,preferably0508or0603orientationswhereconnectionsaremadealongthelengthofthepart.ConsistentwiththerecommendationsofDr.HowardJohnsoninHighSpeedDigitalDesign:AHandbookofBlackMagic(PrenticeHall,1993)andcontrarytopreviousrec-ommendationsfordecouplingPowerPCmicroprocessors,multiplesmallcapacitorsofequalvaluearerecommendedoverusingmultiplevaluesofcapacitance.
VDD
10
2.2 F 2.2 F
GND
AVDD (or L2AVDD)
Low ESL surface mount capacitor
MUR420 MUR420
1N5820
1N5820
1.8V2.5V
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Inaddition,itisrecommendedthattherebeseveralbulkstoragecapacitorsdistributedaroundthePCB,feedingtheVDD,L2OVDD,andOVDDplanestoenablequickrechargingofthesmallerchipcapacitors.ThesebulkcapacitorsshouldhavealowESR(equivalentseriesresistance)ratingtoensurethequickresponsetimenecessary.Theyshouldalsobeconnectedtothepowerandgroundplanesthroughtwoviastominimizeinductance.Suggestedbulkcapacitorsare100-330F(AVXTPStantalumorSanyoOSCON).
ConnectionRecommendations
Toensurereliableoperation,itishighlyrecommendedtoconnectunusedinputstoanappropriatesignallevel.UnusedactivelowinputsshouldbetiedtoOV DD.UnusedactivehighinputsshouldbeconnectedtoGND.AllNC(no-connect)signalsmustremainunconnected.
PowerandgroundconnectionsmustbemadetoallexternalVDD,OVDD,L2OVDD,andGNDpinsofthePC7410.
SeeL2ClockACSpecificationsonpage21foradiscussionoftheL2SYNC_OUTandL2SYNC_INsignals.
OutputBufferDC
Impedance
ThePC741060xandL2I/Odriversarecharacterizedoverprocess,voltageandtem-
perature.TomeasureZ0,anexternalresistorisconnectedfromthechippadtoOVDDorGND.ThenthevalueofeachresistorisvarieduntilthepadvoltageisOV DD/2(seeFig-ure29).
Theoutputimpedanceistheaverageoftwocomponents,theresistancesofthepull-upandpull-downdevices.Whendataisheldlow,SW2isclosed(SW1isopen),andR NistrimmeduntilthevoltageatthepadequalsOV DD/2.RNthenbecomestheresistanceofthepull-downdevices.Whendataisheldhigh,SW1isclosed(SW2isopen),andR PistrimmeduntilthevoltageatthepadequalsOV DD/2.RPthenbecomestheresistanceofthepull-updevices.RPandRNaredesignedtobeclosetoeachotherinvalue.ThenZ0=(RP+RN)/2.
Figure29.DriverImpedanceMeasurement
OVDD
OGND
SW2
SW1
RN
RP
PadData
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Table18summarizesthesignalimpedanceresults.Theimpedanceincreaseswithjunc-tiontemperatureandisrelativelyunaffectedbybusvoltage.
Pull-upResistorRequirements
ThePC7410requireshigh-resistive(weak:10k)pull-upresistorsonseveralcontrolpinsofthebusinterfacetomaintainthecontrolsignalsinthenegatedstateaftertheyhavebeenactivelynegatedandreleasedbythePC7410orotherbusmasters.ThesepinsareTS,ARTRY,SHDOandSHD1.
Inaddition,thePC7410hasoneopen-drainstyleoutputthatrequiresapull-upresistor(weakorstronger:4.7 k10 k)ifitisusedbythesystem.ThispinisCKSTP_OUT.
Duringinactiveperiodsonthebus,theaddressandtransferattributesmaynotbe
drivenbyanymasterandmaythereforefloatinthehigh-impedancestateforrelativelylongperiodsoftime.SincethePC7410mustcontinuallymonitorthesesignalsforsnooping,thisfloatconditionmaycauseexcessivepowerdrawbytheinputreceiversonthePC7410orbyotherreceiversinthesystem.Itisrecommendedthatthesesignalsbepulledupthroughweak(10k)pull-upresistorsbythesystem,orthattheymaybeoth-erwisedrivenbythesystemduringinactiveperiodsofthebus.ThesnoopedaddressandtransferattributeinputsareA[0:31],AP[0:3],TT[0:4],andGBL.
InsystemswhereGBLisnotconnectedandanotherdevicemaybeassertingTSforasnoopabletransactionwhilenotdrivingGBLtotheprocessor,werecommendthatastrong(1k)pull-upresistorbeusedonGBL.
Thedatabusinputreceiversarenormallyturnedoffwhennoreadoperationisin
progressandthereforedonotrequirepull-upresistorsonthebus.Otherdatabusreceiversinthesystem,however,mayrequirepull-ups,orthatthosesignalsbeother-wisedrivenbythesystemduringinactiveperiodsbythesystem.ThedatabussignalsareD[0:63],DP[0:7]
Ifaddressordataparityisnotusedbythesystem,andtherespectiveparitycheckingisdisabledthroughHID0,theinputreceiversforthosepinsaredisabled,andthosepinsdonotrequirepull-upresistorsandshouldbeleftunconnectedbythesystem.Ifallpar-itygenerationisdisabledthroughHID0,thenallparitycheckingshouldalsobedisabledthroughHID0,andallparitypinsmaybeleftunconnectedbythesystem.
TheL2interfacedoesnotnormallyrequirepull-upresistors.
Table18.ImpedanceCharacteristicswithVDD=1.8V,OVDD=1.8Vor2.5V,Tj=-55Cto125C
Impedance Processorbus L2Bus Symbol Unit
RN 41.5-54.3 42.7-54.1 Z0 Ohms
RP 37.3-55.3 39.3-50 Z0 Ohms
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JTAGConfigurationSignals
Figure30.SuggestedTRSTConnection
Figure31.COPConnectorDiagram
Note: Pins10,12and14arenoconnects.Pin14isnotphysicallypresent.
COP Header
2KW 2KW
PC7410
HRESET
QACK
TRST
HRESET
QACK
From Target
Board Sources
1
2
3
4
5
6
7
8
9
10
11
12
1315
16 KEYNo pin
TMS
TCK
TDI
TDO
CKSTP
_OUT
HRESET
SRESET
RUN/STOP
CKSTP
_IN
VDD
_SENSE
TRST
QACK
Groun
d
Top View
Table19.COPPinDefinitions
Pins Signal Connection SpecialNotes
1 TDO TDO
2 QACK QACK Add2Kpull-downtoground.Mustbemergedwithon-boardQACK,ifany.
3 TDI TDI4 TRST TRST Add2Kpull-downtoground.Mustbemergedwithon-boardTRSTifany.
SeeFigure30.
5 RUN/STOP NoConnect Usedon604e;leaveno-connectforallotherprocessors.
6 VDD_SENSE VDD Add2Kpull-uptoOVDD(forshortcircuitlimitingprotectiononly).
7 TCK TCK
8 CKSTP_IN CKSTP_IN Optional.Add10Kpull-uptoOVDD.Usedonseveralemulatorproducts.Usefulfor
checkstoppingtheprocessorfromalogicanalyzerofotherexternaltrigger.
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BoundaryscantestingisenabledthroughtheJTAGinterfacesignals.(BSDLdescrip-t ions o f t he PC7410 are ava i lab le on the In te rne t a twww.mot.com/PowerPC/teksupport.)TheTRSTsignalisoptionalintheIEEE1149.1specificationbutisprovidedonallPowerPCimplementations.Whileitispossibleto
forcetheTAPcontrollertotheresetstateusingonlytheTCKandTMSsignals,morereliablepower-onresetperformancewillbeobtainediftheTRSTsignalisasserteddur-ingpower-onreset.SincetheJTAGinterfaceisalsousedforaccessingthecommonon-chipprocessor(COP)functionofPowerPCprocessors,simplytyingTRSTtoHRESETisnotpractical.
Thecommonon-chipprocessor(COP)functionofPowerPCprocessorsallowsaremotecomputersystem(typicallyaPCwithdedicatedhardwareanddebuggingsoftware)toaccessandcontroltheinternaloperationsoftheprocessor.TheCOPinterfacecon-nectsprimarilythroughtheJTAGportoftheprocessorwithsomeadditionalstatusmonitoringsignals.TheCOPportrequirestheabilitytoindependentlyassertHRESETorTRSTinordertofullycontroltheprocessor.Ifthetargetsystemhasindependentresetsources,suchasvoltagemonitors,watchdogtimers,powersupplyfailuresorpush-buttonswitches,thentheCOPresetsignalsmustbemergedintothesesignalswithlogic.
ThearrangementshowninFigure30allowstheCOPtoindependentlyassertHRESETorTRST,whileensuringthatthetargetcandriveHRESETaswell.Thepull-downresis-toronTRSTensuresthattheJTAGscanchainisinitializedduringpower-onifaJTAGinterfacecableisnotattached;ifitisattached,itisresponsiblefordrivingTRSTwhenneeded.
TheCOPheadershowninFigure30addsmanybenefitsbreakpoints,watchpoints,registerandmemoryexamination/modificationandotherstandarddebuggerfeaturesarepossiblethroughthisinterfaceandcanbeasinexpensiveasanunpopulatedfoot-printforaheadertobeaddedwhenneeded.
TheCOPinterfacehasastandardheaderforconnectiontothetargetsystem,basedonthe0.025square-post0.100centeredheaderassembly(oftencalledaBergheader).Theconnectortypicallyhaspin14removedasaconnectorkey,asshowninFigure31.
9 TMS TMS
10 N/A
11 SRESET SRESET Mergewithon-boardSRESET,ifany.12 N/A
13 HRESET HRESET Mergewithon-boardHRESET.
14 N/A Keylocation;pinshouldberemoved.
15 CKSTP_OUT CKSTP_OUT Add10Kpull-uptoOVDD.
16 Ground DigitalGround
Table19.COPPinDefinitions(Continued)
Pins Signal Connection SpecialNotes
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Definitions
DatasheetStatusDescription
LifeSupportApplications
Theseproductsarenotdesignedforuseinlifesupportappliances,devicesorsystemswheremalfunctionoftheseproductscanreasonablybeexpectedtoresultinpersonalinjury.AtmelcustomersusingorsellingtheseproductsforuseinsuchapplicationsdosoattheirownriskandagreetofullyindemnifyAtmelforanydamagesresultingfromsuchimproperuseorsale.
Table20.DatasheetStatusDatasheetStatus Validity
Objectivespecification Thisdatasheetcontainstargetandgoal
specificationsfordiscussionwithcustomerandapplicationvalidation.
Beforedesignphase
Targetspecification Thisdatasheetcontainstargetorgoal
specificationsforproductdevelopment.
Validduringthedesignphase
Preliminaryspecification
-site
Thisdatasheetcontainspreliminarydata.
Additionaldatamaybepublishedlater;could
includesimulationresults.
Validbeforecharacterizationphase
Preliminaryspecification-site Thisdatasheetalsocontainscharacterization
results.
Validbeforetheindustrializationphase
Productspecification Thisdatasheetcontainsfinalproduct
specification.
Validforproductionpurposes
LimitingValues
LimitingvaluesgivenareinaccordancewiththeAbsoluteMaximumRatingSystem(IEC134).Stressaboveoneormoreofthe
limitingvaluesmaycausepermanentdamagetothedevice.Thesearestressratingsonlyandoperationofthedeviceattheseorat
anyotherconditionsabovethosegivenintheCharacteristicssectionsofthespecificationisnotimplied.Exposuretolimitingvalues
forextendedperiodsmayaffectdevicereliability.
ApplicationInformation
Whereapplicationinformationisgiven,itisadvisoryanddoesnotformpartofthespecification.
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OrderingInformation
Note: 1. Foravailabilityofthedifferentversions,contactyourAtmelsalesoffice.
PC 7410 V GS U L x
Prefix
Type
Package (1)
G: CBGAGS: CI-CBGA
Screening Level(1)
U: Upscreening
Revision Level(1)
Rev. E
Application modifier (1)
L: 1.8V 100 mVN: 1.5V 50 mV
Temperature Range: Tj (1)
V: -40C, +110CM: -55C, +125C
Prototype
(X)
Max Internal Processor Speed(1)
400 MHz450 MHz500 MHz (TBC)
400
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At mel Co rp or at io n 20 02 .AtmelCorporationmakesnowarrantyfortheuseofitsproducts,otherthanthoseexpresslycontainedintheCompanysstandardwarrantywhichisdetailedinAtmelsTermsandConditionslocatedontheCompanyswebsite.TheCompanyassumesnoresponsibilityforanyerrorswhichmayappearinthisdocument,reservestherighttochangedevicesorspecificationsdetailedhereinatanytimewithoutnotice,anddoesnotmakeanycommitmenttoupdatetheinformationcontainedherein.NolicensestopatentsorotherintellectualpropertyofAtmelaregrantedbytheCompanyinconnectionwiththesaleofAtmelproducts,expresslyorbyimplication.Atmelsproductsarenotauthorizedforuseascriticalcomponentsinlifesupportdevicesorsystems.
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