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T13/D98109R4

Ultra ATA Implementation Guide-- Annex C --(Informative)

To: T13 Technical committeeFrom: Mark Evans

Quantum Corporation500 McCarthy BoulevardMilpitas, CA USA 95035Phone: 408-894-4019Fax: 408-952-3620Email: [email protected]

Date: 24 August 1999Subj: Ultra ATA implementation guide

Introduction: The following proposal is for a replacement for Annex C in the ATA/ATAPI-5 standard. This annex is intended to focus on providing details for implementation for Ultra ATA modes 0, 1, 2, 3, and 4.

GLOBAL MODIFICATIONS REQUIRED:

look at the stuff from the old Annex C and include where appropriate, particularly in C.1, C.1.1, C.2, C.2.1, etc. [1 pass done]

replace “should” with “may” [1 pass done] reference figures in the text [1 pass done] define “IC” and “ASIC” in glossary or change to things like “driver” and “receiver” [1 pass done] replace “TTL” and “CMOS” with “driver” and “receiver”, and modify the text accordingly [1 pass done] check that “I/O” connector is specified as such when that’s what is meant – also check on the word “pin”

[1 pass done] Source and receiver need to be identified in several figures check for where “drive” (“drives”, “driven”, et al.) should be replaced by “assert” and/or “negate” (et al.) check to make sure that “receiver” means the IC input and “recipient” means host or device [1 pass

done] search on “where”. there is probably a better way to say stuff where “where” is [1 pass done] search on “taken” and replace, where necessary, with “measured” or “defined” or “defined to be

measured from” change “receiver” to “recipient”, as necessary [1 pass done] check the number of modes in each timing “what is achievable” should be replaced by “The formula for the value at” search on “generated” and “can be determined” and replace with “when analyzing” change all of the equations [in clause C.5] to include showing the actual values search on “PCI”. This should be replaced by “33 / 30” where possible “the value is determined by…” should be checked carefully. There are instances where the formula

given DOES NOT determine the actual timing value [but rather the result of the calculation leading to the specified value]

search on “editor’s note:” for specific issues that need to be addressed

T13/D98109 Revision 4

The following should be added to clause 3 in the standard.

Definitions, abbreviations, and conventions

“Aggressor” Signal – A signal which is changing state and causing crosstalk on other signals.

Characteristic Impedance – The ratio of voltage to current for signals propagating at any point along a transmission line

Crosstalk – Voltage changes produced on one conductor in a bus as a result of capacitive and inductive coupling from signals on other conductors.

Driver – The active circuit inside a device or host which sources or sinks current in order to assert or negate a signal on the bus.

DST (Data Settling Time) – Amount of time within a cycle the receiver must wait before clocking data to ensure that crosstalk and ringing do not cause an incorrect value to be received.

IC (Integrated Circuit) – Refers to the entire device (die and package) which contains the ATA bus interface circuitry.

Impedance – For any two node device or subcircuit within an electrical circuit, the ratio of voltage across the two nodes to current through them. Depending on the nature of the device its impedance may be constant or may vary with frequency, voltage or current, or other factors.

I/O Cell – The combined driver and receiver circuitry within a device which is responsible for sending and/or receiving data on a particular conductor within the bus.

“Length” of an edge – For a change of voltage occurring over some duration of time at a single point in a distributed system, the physical distance within the system between the beginning of the change and the end of the change, at one instant in time as the change propagates through the system. Can be calculated as: edge length = (duration of edge/propagation delay of system) where propagation delay has units of time/length.

PCB – Printed Circuit Board

Propagation Delay – For a system containing continuously distributed capacitance and inductance, the amount of time required for an input signal at one part of the system to cause a disturbance to be seen at another part of the system. Propagation delay is determined by the velocity of light within the dielectric materials containing the electric fields in the system. For systems with uniform properties along their length, propagation delay is often specified as seconds/ft or seconds/meter.

Receiver – The IC of the recipient.

RLC – Resistance/Inductance/Capacitance – Refers to the major electrical characteristics which affect high-frequency signals traveling through a physical feature of a bus such as a connector or IC package.

Transmitter – The IC of the sender.

TTL (Transistor-Transistor Logic) – Logic family which ATA’s electrical specifications were originally based on. The most relevant specific feature is input threshold levels which are referenced to ground(vs being proportional to Vcc/Vdd) and are specified to fall within the range of 800mV to 2.0 V.

“Victim” Signal – A signal which is not changing state but may be interpreted by its receiver as having changed due to crosstalk which exceeds the threshold voltages.

Ultra ATA implementation guide


Table of Contents

C.1 Introduction...................................................................................................................................... 5C.2 The issues....................................................................................................................................... 5

C.2.1 Timing......................................................................................................................................... 5C.2.1.1 Skew....................................................................................................................................... 5C.2.1.2 Source-terminated bus............................................................................................................6C.2.1.3 Timing measurements for the 80-conductor cable assembly..................................................10C.2.1.4 Simulations for the 80-conductor cable assembly...................................................................11

C.2.2 Crosstalk................................................................................................................................... 11C.2.2.1 Capacitive coupling................................................................................................................13C.2.2.2 Inductive coupling.................................................................................................................. 14C.2.2.3 Mixed capacitive and inductive coupling.................................................................................16C.2.2.4 Crosstalk from distributed coupling........................................................................................18

C.2.3 Ground/Power Bounce...............................................................................................................23C.2.3.1 Measuring crosstalk in a system............................................................................................25C.2.3.2 System design considerations to minimize crosstalk..............................................................25

C.2.4 Ringing and data settling time (DST) for the 40-conductor cable assembly.................................26C.2.4.1 Controlling ringing on a 40-conductor cable assembly............................................................29C.2.4.2 STROBE lines on the 40-conductor cable..............................................................................31

C.3 System Guidelines for Ultra DMA...................................................................................................32C.3.1 System capacitance................................................................................................................... 32C.3.2 Pull up and pull down resistors...................................................................................................32C.3.3 Cables and connectors..............................................................................................................32C.3.4 PCB design............................................................................................................................... 33C.3.5 Transmitter and receiver I/O cells..............................................................................................33

C.4 Ultra DMA protocol........................................................................................................................ 34C.4.1 tSR, tRFS, and the number of additional transfers...........................................................................34C.4.2 Issues with tSR............................................................................................................................ 35C.4.3 Issues with tZIORDY relative to tENV.................................................................................................36C.4.4 Recipient pauses and implications for data handling and CRC calculation..................................36C.4.5 CRC calculation and comparison...............................................................................................37C.4.6 IDENTIFY DEVICE command....................................................................................................37C.4.7 STROBE minimums and maximums..........................................................................................38C.4.8 Typical STROBE cycle timing....................................................................................................38C.4.9 Holding data to meet setup and hold times.................................................................................39C.4.10 tACK timing................................................................................................................................. 39C.4.11 Host chances to delay a burst....................................................................................................39C.4.12 Maximums on all control signals from the device........................................................................40C.4.13 Bus turnaround.......................................................................................................................... 40

C.5 Ultra DMA Timing derivations.........................................................................................................41C.5.1 Fundamental timings, skews and delays....................................................................................41C.5.2 IC and PCB timings, delays, and skews.....................................................................................41C.5.3 System timing parameters.........................................................................................................43

C.5.3.1 t2CYCTYP (typical average two-cycle time).................................................................................43C.5.3.2 tCYC (cycle time)...................................................................................................................... 43C.5.3.3 t2CYC (two-cycle time)..............................................................................................................43C.5.3.4 tDS (data setup time)...............................................................................................................43C.5.3.5 tDH (data hold time)................................................................................................................. 44C.5.3.6 tDVS (data valid setup time).....................................................................................................45C.5.3.7 tDVH (data hold time)...............................................................................................................45C.5.3.8 tFS (first DSTROBE time)........................................................................................................47C.5.3.9 tLI (limited interlock time)........................................................................................................47C.5.3.10 tMLI (limited interlock time with minimum)............................................................................48C.5.3.11 tUI (unlimited interlock time)................................................................................................48C.5.3.12 tAZ (maximum driver release time)......................................................................................48C.5.3.13 tZAH (minimum delay time)..................................................................................................49C.5.3.14 tZAD (minimum driver assert/negate time)............................................................................49



C.5.3.15 tENV (envelope time)...........................................................................................................49C.5.3.16 tSR (STROBE to DMARDY– time).......................................................................................50C.5.3.17 tRFS (DMARDY– to final STROBE time)..............................................................................50C.5.3.18 tRP (DMARDY– to pause time)............................................................................................51C.5.3.19 tIORDYZ (maximum IORDY release time)...............................................................................52C.5.3.20 tZIORDY (minimum IORDY assert time).................................................................................52C.5.3.21 tACK (setup/hold before DMACK– time)...............................................................................52C.5.3.22 tSS (STROBE to DMARQ/STOP time)................................................................................52

Table of Figures

Figure C.1 – A transmission line with perfect source termination 6Figure C.2 – Waveforms on a source-terminated bus with rise time less than Tprop 7Figure C.3 – Waveforms on a source-terminated bus with rise time greater than Tprop 7Figure C.4 – Waveforms on a source-terminated bus with R_source less than cable Z0 8Figure C.5 – Waveforms on a source-terminated bus with R_source greater than cable Z0 8Figure C.6 – Typical step voltage seen in systems using an 80-conductor cable assembly 9Figure C.7 – Typical step voltage seen in systems using an 80-conductor cable assembly 10Figure C.8 – Positive crosstalk pulse during a falling edge 12Figure C.9 – Reverse crosstalk waveform from reflected edge 12Figure C.10 – Model of capacitive coupling 13Figure C.11 – Waveforms resulting from capacitive coupling 14Figure C.12 – Model of inductive coupling 15Figure C.13 – Waveforms resulting from inductive coupling 15Figure C.14 – Model of mixed capacitive and inductive coupling 16Figure C.15 – Waveforms resulting from mixed capacitive and inductive coupling 17Figure C.16 – Model of distributed coupling 18Figure C.17 – Waveforms resulting from distributed coupling at source and receiver 19Figure C.18 – Model of voltage divider for connector crosstalk formed by PCB and cable. 21Figure C.19 – Waveforms showing connector crosstalk dividing between PCB and cable 22Figure C.20 – Model of ground bounce in IC package 24Figure C.21 – Waveforms resulting from ground bounce 24Figure C.19 – Simple RLC model of 40-conductor cable assembly with all data lines switching 26Figure C.20 – Output of simple RLC model: waveforms at sender and recipient connectors 27Figure C.21 – DST measurement for a line held low while all others are asserting 28Figure C.22 – DST measurement for all lines switching 29Figure C.23 – Improved model of 40-conductor cable assembly ringing with termination at IC 29Figure C.24 – Improved model of 40-conductor cable assembly ringing with termination at connector 30Figure C.24 – Results of improved 40-conductor model with termination at IC versus connector 30Figure C.25 – Results of improved 40-conductor model with source rise time of 1, 5, and 10 ns 31Figure C.26 – STROBE and DMARDY– at sender and recipient 34Figure C.27 – DMARDY– to final STROBE tRFS synchronization 51



Annex C(informative)

Signal integrity

C.1 Introduction

The ATA bus (a.k.a. the IDE bus) is a disk drive interface originally designed for the ISA Bus of the IBM PC/AT. With the advent of faster devices, the definition of the bus has been expanded to include new operating modes. Each of the PIO modes, numbered zero through four, is faster than the one before (higher numbers translate to faster transfer rates). PIO modes 0, 1, and 2 correspond to transfer rates for the interface as was originally defined with maximum transfer rates of 3.3, 5.2, and 8.3 MB/s, respectively. PIO mode 3 defines a maximum transfer rate of 11.1 MB/s, and PIO mode 4 defines a maximum rate of 16.7 MB/s. Additionally, Multiword DMA and Ultra DMA modes have been defined. Multiword DMA mode 0, 1, and 2 have maximum transfer rates of 4.2, 13.3, and 16.7 MB/s, respectively. Ultra DMA modes 0, 1, 2, 3 and 4 have maximum transfer rates of 16.7, 25, 33.3, 44.4, and 66.6 MB/s, respectively.

Ultra DMA features such as increased frequencies, double-edge clocking, and non-interlocked signaling require improved signal integrity on the bus relative to that required by PIO and Multiword DMA modes. For Ultra DMA modes 0, 1 and 2 this is achieved by the use of partial series termination and controlled slew rates. For modes 3 and 4 an 80-conductor cable assembly is required. This cable assembly has ground lines interspersed between all signal lines on the bus in order to control impedance and reduce crosstalk, eliminating many of the signal integrity problems inherent to the 40-conductor cable assembly. However, many of the design considerations and measurement techniques required for the 80-conductor cable assembly are different from those used for the 40-conductor assembly. Hosts and devices intended to be used with 40- or 80-conductor cables should be designed to meet all requirements for operation with both types.

C.2 The issues

For operation in PIO modes 0 through 4, Multiword DMA modes 0 through 2, and Ultra DMA modes 0 through 2 with a 40-conductor cable assembly, concerns include (in order of importance): crosstalk between signals, ringing, and timing

For operation in Ultra DMA modes 3 and 4 with an 80-conductor cable assembly, major concerns are: timing, crosstalk between signals, and ground bounce

In the following these issues will be discussed along with suggestions for implementation. Because the fastest Ultra DMA modes present the greatest design challenges, the issues will be addressed in the following order: timing, crosstalk between signals, ground bounce, and ringing

C.2.1 Timing

Two of the features Ultra DMA introduced to the bus are double-edge clocking and non-interlocked (a.k.a. source-synchronous) signaling. Double-edge clocking allows a word of data to be transferred on each edge of STROBE (this is HSTROBE for an Ultra DMA data out transfer and DSTOBE for a data in transfer), resulting in doubling the data rate without increasing the fundamental frequency of signaling on the bus. Non-interlocked signaling means that DATA and STROBE are both generated by the sender during a data transfer. In addition to previous signal integrity issues such as double clocking on STROBE due to ringing and delay-limited interlock timings on the bus, non-interlocked signaling makes settling time and skew between different signals on the bus critical for proper Ultra DMA operation.

C.2.1.1 Skew

Skew is defined as the difference in total propagation delay between two signals as they transit the bus. Skew will be positive or negative depending on which signal is chosen as the reference. All skews in the Ultra DMA timing derivations are defined as STROBE delay minus data delay. A positive skew is a STROBE that is delayed more than the data.



Skew corresponds to the reduction in setup and hold times that occurs between the transmitter and the receiver. In order to insure that data is clocked correctly, the maximum allowable skew in each direction in a system should be less than the difference between the setup or hold time produced by the transmitter and required by the receiver. Skew between signals will increase as they transit the bus based on differences in the electrical characteristics of the paths followed by each signal. An understanding of the origins of skew and its importance to Ultra DMA requires an explanation of the nature of signal propagation on a ground-signal-ground (G-S-G) cable.

The 80-conductor cable assembly adds 40 ground lines to the cable interspersed between the 40 signals lines defined for the 40-conductor cable assembly. These added ground lines are connected inside each connector on the cable assembly to the seven ground pins defined for the 40-conductor cable assembly. These additional ground lines allow the return current for each signal line to follow a much lower impedance path to the outgoing current than was allowed by the grounding scheme in the 40-conductor cable assembly. This results in greatly reduced crosstalk on the data bus. The controlled impedance and reduced crosstalk of the 80-conductor cable assembly results in much improved behavior of electrical signals on the bus and reduces the data settling time to effectively zero regardless of switching conditions (the signal at a receiver is monotonic, such that the first crossing of the input threshold can be considered final). Reducing the time allowed for data settling from greater than 25 ns in Ultra DMA mode 2, to 0 ns with the 80-conductor cable assembly allows nominal cycle time to be reduced from 60 ns for mode 2, to 30 ns for mode 4.

C.2.1.2 Source-terminated bus

The bus operates as a “source-terminated” bus, meaning that the only low-impedance connection to ground is via the source impedance of the drivers in the transmitter.

R_source 100

CableZ0=100 TD=4 ns

V_source

R_rec1 M

Figure C.1 – A transmission line with perfect source termination

On a source-terminated transmission line, the initial voltage level produced at the source propagates through the system until it reaches the receiving end, that, by definition, is an open circuit – or at least has high impedance relative to the characteristic impedance of the transmission line. This open circuit produces a reflection of the original step with the same polarity and amplitude as the original step but travelling in the opposite direction. The reflected step adds to the first step to raise the voltage throughout the system to two times the original step voltage. In a perfectly terminated system (see Figure C.1), R_source matches the cable impedance resulting in an initial step voltage on the transmission line equal to fifty percent of V_source, and the entire system has reached a steady state at V_source once the reflection returns to the source.

The waveforms that are measured on the bus as a result of this behavior depend on the ratio of the signal rise time to the propagation delay of the system. If the rise time is shorter than the one-way propagation delay, the initial voltage step will be visible at the transmitter or at any point in the system except at the receiver, where the incoming voltage step is instantaneously doubled as it reflects back to the transmitter (see Figure C.2).



Figure C.2 – Waveforms on a source-terminated bus with rise time less than Tprop

If the rise time is longer than the propagation delay, the transmitter waveform changes, but the same behavior still occurs: the reflected step adds to the initial step at the transmitter while the receiver sees a delayed doubling of the initial step. Because the rising edges of the two steps overlap when measured at the transmitter, there is a temporary increase in slew rate instead of a step seen at the transmitter while the rising edge of the reflection adds to the edge still being generated by the transmitter (see Figure C.3).

Figure C.3 – Waveforms on a source-terminated bus with rise time greater than Tprop

In Figure C.4, the source impedance is perfectly matched to the cable impedance with the result that, after the first reflection returns to the source, there are no further reflections, and the system is at a steady state. In a system that is not perfectly terminated, there are two possibilities: If the source impedance is less than



the characteristic impedance of the transmission line, the initial step is greater than fifty percent of VoH, and the system is at a voltage higher than VoH when the first reflection returns to the receiver. In this case another reflection occurs at the source to reduce the system to a voltage below VoH but closer to VoH than the initial peak. Reflections continue but are further reduced in amplitude each time they reflect from the termination at the source.

Figure C.4 – Waveforms on a source-terminated bus with R_source less than cable Z0

If the source impedance is higher than the characteristic impedance, the initial step will be less than fifty percent of VoH, and multiple reflections back and forth on the bus will be required to bring the whole system up to a steady state at VoH (see C.5).

Figure C.5 – Waveforms on a source-terminated bus with R_source greater than cable Z0



Note that falling edges of the signals in Figure C.5exhibit the same transmission line behavior as rising edges. The only difference between the edges is that VoH and VoL are reversed. Also, in actual systems output impedance and slew rate of the drivers are often different between rising and falling edges, resulting in different step voltages and waveform shapes.

For typical implementations using 33 series termination, the effective driving impedance of a transmitter viewed from the cable connector ranges from 50 to 90 . The initial voltage step produced when an edge is driven onto the cable will be equal to the driver’s open-circuit VoH divided by the effective output impedance and the input impedance of the cable (typically 82 ), or a 50 to 60 printed circuit board trace in the case of hosts. This step voltage will typically fall in the range from 50 to 70 percent of VoH. For example, for a theoretical source with zero output impedance using 33 termination driving an 82 ohm cable the resulting step voltage cannot be greater than 100 ( 82 / (33 + 82 ) ) = 71.3 percent of VoH. Because the TTL level thresholds of a receiver are not centered with respect to the high and low voltages, the initial voltage step produced by a driver will often cross the receiver’s threshold on a rising edge but not on a falling edge. However, since the signal received at the end of the bus is a doubled version of the initial output at the transmitter, it will cross the switching thresholds for any reasonably low output impedance. Because of this the main voltage step only affects skew and delay for signals received at devices that are not at the end of the cable. The greater the distance a device is from the device end of the cable (i.e., closer to the host), the longer the duration of the step observed (see Figure C.6 and Figure C.7).

-20.00 ns 30.00 ns 80.00 ns #Avg 16 10.00 ns/div repetitive

Figure C.6 – Typical step voltage seen in systems using an 80-conductor cable assembly(measured at the device and host connectors during a READ)



-20 ns 30.00 ns 80.00 ns # Avg 16 10.0 ns/div repetitive

Figure C.7 – Typical step voltage seen in systems using an 80-conductor cable assembly(measured at the host and device connectors during a WRITE)

In addition to the step produced by the initial voltage driven onto the bus and the subsequent reflection, smaller steps are produced each time the propagating signal encounters a change in the bus impedance. The major impedance changes that occur in a system are 1) at the connections between the cable and the PCBs, 2) along the traces of the PCBs as the result of changing layers, and 3) at the connection between a motherboard and a backplane. In Figure C.7 the initial step voltage produced at the host connector is less than the usual range of 50 to 70 percent of VoH because it is based on the host transmitter driving the PCB trace impedance. A second step with a higher voltage follows after the reflection from the host connector has completed the round trip from the connector to the transmitter and back, adding to the reflection back from the device end of the cable. Steps such as this are produced by reflections at various points throughout the system and significantly change the shapes of edges and ringing.

The transmission line behavior of the 80-conductor cable assembly adds skew to the received signal in two ways: First, impedance differences along one line versus another will result in different amounts of delay and attenuation on each line due to reflections on the bus. This produces a time difference between the two signals’ threshold crossings at the receiver. Secondly, signals received at the device that is not at the end of the cable may cross the threshold during the initial voltage step or after the reflection from the end of the cable is received (depending on the supply voltage, series termination, output impedance, VoH, and PCB trace characteristics of the host).

Factors other than cable characteristics also contribute to skew. Differences in the capacitive loading between the STROBE and DATA lines on devices attached to the bus will delay propagating signals by differing amounts. Differences in slew rate or output impedance between drivers when driving the 82 cable load will result in skew being generated as the signal is sent at the transmitter. Differences between the input RC delays on STROBE and DATA lines will add skew at the recipient.

The fundamental requirement for minimizing skew in the entire system is to make the STROBE and DATA lines as uniform as possible throughout the system. Methods of achieving this are described in C.1.10.

C.2.1.3 Timing measurements for the 80-conductor cable assembly

The reflections that are present in a system make it difficult to measure skew and delays accurately. For the received signal at a device, the propagation delay from the device connector to the pin of the receiving IC is about 300 ps for typical PCBs and trace lengths. This introduces an error of plus or minus 300 ps in timing measurements made at the device connector since rising edges and falling edges will be measured before and after the step respectively. When comparing two signals, this can result in an error in measured skew of



plus or minus 600 ps due to the measurement position. This error is small enough relative to the total timing margin of an Ultra DMA system that it can usually be ignored.

Since the trace length on host PCBs can be significantly longer than those on devices, the propagation time for a signal from the host connector to the pin of the host’s IC can be as high as 2 ns. This can result in a plus or minus 2 ns accuracy in the measurement of a single signal and a plus or minus 4 ns accuracy for skew between two signals. These errors cannot be removed by adding or subtracting an allowance for PCB propagation delay depending on rising or falling edges because characteristics of the PCB and termination will affect the step levels and skew that actually occurs at the IC pin. As a result of this, accurate measurements of skew in signals received at the host are made either at pins of the host IC, or at points on the PCB traces as close to the IC pins as possible. Test pads, headers, or unconnected vias in PCB layouts may be designed allowing connection to DATA, STROBE, and ground for this purpose.

An alternate method of measuring skew at any point in a system is to break the continuity of the system at that point by disconnecting the signal line (in the case of DATA lines) or inserting a buffer with known input characteristics for a STROBE line since the system will not operate with a STROBE disconnected. A capacitance is then connected on the DATA line to match the load created by the buffer on STROBE. Breaking the continuity of the system results in a waveform at that point matching what would be seen at the receiving end of the bus into the same load as the one at the break if no further skew was introduced along the line.

It is important to note that all specifications in the standard are based on measuring signals at the interface connector.

C.2.1.4 Simulations for the 80-conductor cable assembly

The difficult nature of measuring skew in actual systems makes simulations a more important tool in determining the effect on skew of design decisions regarding I/O cells, PCB layout, cable lengths, and other aspects of system design. Because of the well-controlled impedance of the 80-conductor cable assembly, single line transmission line models can provide accurate predictions of the delay through the bus based on a given design choice for a given set of conditions on the bus. A large number of simulations should be run encompassing many different combinations of parameters in order to be certain of the system-wide consequences of a particular design choice. Simulations such as these were used to determine the timing specifications for Ultra DMA mode 4, and are the basis of the guidelines in the following text.

One aspect of skew that can be easily measured or simulated is output skew into a defined load. Output skew is measured at the connector of the sender into capacitive loads to ground of 15 pf and 40 pf. An alternate loading arrangement is to measure the signal produced at the end of an 18-inch 80-conductor cable assembly into typical device and host loads of 20 pf or 25 pf that are held uniform across STROBE and DATA lines. Skew is measured at the crossing of the 1.5 volt threshold. Skew should always be measured for all combinations of rising and falling edges on the signals involved.

Minimizing output skew is the best assurance of reliable signaling across the full range of cable loading and receiver termination conditions that will occur in systems.

C.2.2 Crosstalk

Although the ground-signal-ground configuration of the 80-conductor cable assembly greatly reduces coupling between wires on the cable, the host and device connectors generate a significant amount of crosstalk because they still use the original ground configuration with no ground lines separating the 16 pins of the data bus. In addition, crosstalk between traces on the PCB can reach high levels in systems with long traces or with tight spacing between traces. Cumulative crosstalk plus ground bounce measured at the connector of the recipient in typical systems using the 80-conductor cable ranges from 400 mV to 1 V peak, in short pulses with frequency content equivalent to the edge rates of the drivers being used. Although this level of total crosstalk may seem like a significant hazard to reliable signaling, crosstalk exceeding 800 mV normally occurs only during the interval when other signals are switching, and as a result it does not significantly affect the setup or hold times seen by the recipient (see figure C.8).



Figure C.8 – Positive crosstalk pulse during a falling edge(does not affect data setup or hold time)

A larger signal integrity hazard exists when crosstalk extends into the middle of the cycle when data should be stable at the recipient and could be clocked. This can result from a high level of reverse crosstalk seen at the recipient as the reflected signal propagates from the receiver back to the transmitter in the switching lines.

Figure C.9 – Reverse crosstalk waveform from reflected edge



(seen at the receiver in the middle of a cycle – marker X1)

Reducing a system’s creation of and susceptibility to forward and reverse crosstalk requires an understanding of how crosstalk is generated and propagates through the system. Crosstalk results from coupling between signals in the form of either a capacitance from one signal conductor to another or inductors in the path of each signal with overlapping magnetic fields. The capacitive and inductive coupling operate differently and are easiest to understand if treated as separate effects.

C.2.2.1 Capacitive coupling

Capacitive coupling in its simplest form consists of a capacitor connecting together two transmission lines somewhere along their length. When a change in voltage occurs on one line (called the aggressor line), a pulse on the non-switching signal (called the victim line) is produced with a peak amplitude proportional to the rate of change of voltage (dV/dt) on the aggressor line. The pulse on the victim line propagates both forward and backward from the point of coupling and has the same sign in both directions. Forward and backward are defined relative to the direction that the aggressor signal was propagating. Forward means that the propagation is in the same direction that the aggressor signal was propagating. Backward means that propagation is opposite the direction that the aggressor signal was propagating. Figure C.10 is a schematic of a model for capacitive coupling. Figure C.11 shows waveforms resulting from capacitive coupling at the transmitter and receiver of the aggressor and victim lines.

Figure C.10 – Model of capacitive coupling



Figure C.11 – Waveforms resulting from capacitive coupling(at transmitter and receiver of aggressor and victim lines)

C.2.2.2 Inductive coupling

Inductive coupling can be modeled as an inductor in series with each signal, with some coupling factor K representing the extent to which the inductors’ magnetic fields overlap. In effect these two inductors constitute a transformer, creating a stepped-down version of the aggressor signal on the victim line. The amplitude of the signal produced on the victim line is proportional to the rate of change in current (di/dt) on the aggressor line. Since the impedance of a transmission line is resistive, for points in the middle of a transmission line di/dt will be proportional to dV/dt. Because the crosstalk signal produced across the inductance in the victim line is in series with the transmission line, it has a different sign at each end of the inductor. Because the current in an inductor always opposes the magnetic field that produced it, the polarity of the crosstalk signal is reversed from the polarity of the di/dt on the aggressor line that produced it. As a result of these two facts, inductive crosstalk creates a pulse of forward crosstalk with polarity opposite to the edge on the aggressor, and a pulse of reverse crosstalk with the same polarity as the aggressor. Figure C.12 is a schematic of a model for inductive coupling. Figure C.13 shows waveforms resulting from inductive coupling at the transmitter and receiver of the aggressor and victim lines.



Figure C.12 – Model of inductive coupling

[editor’s note: what is the symbol before K1 in Figure 12 supposed to be? It is the coupling “component” –basically just a placeholder, but useful to anyone who wants to duplicate the circuit in Pspice.

Figure C.13 – Waveforms resulting from inductive coupling(at transmitter and receiver of aggressor and victim lines)



C.2.2.3 Mixed capacitive and inductive coupling

Most occurrences of electromagnetic coupling involve both capacitive and inductive coupling. In this case the forward and reverse crosstalk contributions of the capacitance and inductance add together. Because the forward inductive crosstalk and the forward capacitive crosstalk have opposite signs, they tend to cancel, while the reverse crosstalk from both effects have the same sign and add together. Depending on the ratio of inductive to capacitive coupling, the forward crosstalk may sum to zero when both effects are added together. Figure C.14 is a schematic of a model for mixed capacitive and inductive coupling. Figure C.15 shows waveforms resulting from mixed capacitive and inductive coupling at the transmitter and receiver of the aggressor and victim lines.

Figure C.14 – Model of mixed capacitive and inductive coupling



Figure C.15 – Waveforms resulting from mixed capacitive and inductive coupling(at transmitter and receiver of aggressor and victim lines)



C.2.2.4 Crosstalk from distributed coupling

When transmission lines are placed parallel with and in close proximity to each other, as is the case for PCB traces, wires in a ribbon cable, etc., the coupling that occurs is continuous along the length of the transmission lines. To find the crosstalk waveforms that result from this at the source and receiver, divide the transmission lines into segments and treat each segment as an instance of capacitive and inductive coupling as shown in Figure C.15. Each segment produces forward and reverse crosstalk as the aggressor edge goes by. Sum the contributions from each of these segments, delaying their arrival at the ends according to the segment’s position along the transmission line. Doing this shows that the forward crosstalk contributions all add together and arrive simultaneously with the aggressor edge, while the reverse crosstalk is spread out along the length of the transmission line and produces a long flat pulse travelling back toward the source. Figure C.16 shows a schematic model for a transmission line with three coupled conductors, connected as two signal wires and a ground return. The waveform at the source end of the victim line in figure C.17 shows that the reverse crosstalk pulse begins when the edge is driven onto the aggressor line and continues to be seen at the source until one system delay after the end of the edge is terminated at the receiver on the aggressor line. The waveform at the victim receiver shows that the forward crosstalk arrives simultaneously with the edge on the aggressor line, or even slightly before, due to the fact that the energy in the crosstalk pulse has been subtracted from the edge on the aggressor, reducing its risetime at the receiver.

Figure C.16 – Model of distributed coupling



Figure C.17 – Waveforms resulting from distributed coupling at source and receiver



In Figure C.16 the top two waveforms show the aggressor signal at the transmitting and receiving ends of the cable. The third waveform from the top is the crosstalk at the transmitter, and the bottom waveform is the crosstalk at the receiver. In this measurement the victim line was perfectly terminated at both ends, while the aggressor lines (the rest of the bus) were source-terminated by the transmitters. During the time that the initial edge is propagating from the transmitter to the receiver, the reverse crosstalk seen at the transmitter is a long flat pulse with the same polarity as the edge, while the forward crosstalk at the receiver is a short spike with polarity opposite to the edge on the aggressor lines. Then, the reflected edge on the aggressor lines reverses the situation and produces forward crosstalk at the transmitter end of the victim lines and reverse crosstalk at the receiver end.

In the simulation results in figuresC.11,C.13, and C.15 above the waveforms are simplified by the assumption that all transmission lines are perfectly terminated at both ends. In actual systems only the transmitter end of the bus has a low-impedance termination to ground, and this termination is rarely perfect. This has a number of consequences that should be taken into account to understand crosstalk in a system.

1) Crosstalk is produced by both the initial and reflected edges on the aggressor lines. Forward crosstalk produced by the initial edge as it propagates from the transmitter to the receiver arrives at the same time as the edge that produced it. The edge on the aggressor signals reflects from the high impedance at the receiver (or at the end of the cable) and returns back to the transmitter. Reverse crosstalk produced as this reflected edge propagates back to the transmitter is seen on the victim line at the receiver.

2) If reverse crosstalk from the initial edge is not perfectly terminated at the transmitter it will be reflected (with reduced amplitude) back towards the receiver. The quality of the transmitter termination depends on the instantaneous output impedance of drivers as they are switching, as well as the “on” resistance of the drivers in the high or low state once they have completed switching. Since the source impedance is made up of the driver output impedance in series with the termination resistors, the most accurate source termination can be achieved by using drivers with low output impedance combined with high value series resistors, creating a total output impedance near 75 ohms.

3) Crosstalk is seen with doubled amplitude at the high-impedance endpoint of the system (at the host receiver during READ operations and at the device receiver at the end of the cable during WRITE operations) due to the reflection. Since crosstalk occurs as a pulse rather than a step, the initial and reflected portions of the pulse only sum at the endpoint while the pulse is reflecting, and not at other points along the bus.

4) Series termination resistors at the receiving end of the bus serve to attenuate the amplitude of crosstalk seen at the pin of the receiving IC. Because the IC input impedance is predominantly capacitive, its impedance decreases at high frequencies. At the frequency where the impedance of the IC input equals the impedance of the series termination resistor, the crosstalk pulse amplitude seen at the IC input will be about half of the amplitude measured at the connector. The formula for determining this frequency is F = 1/(2**R*C) where F is the frequency, R is the value of the series termination resistor, and C is the input capacitance of the receiver. As a result of this, in systems where crosstalk levels are high enough to be a serious concern, measurements should be taken at the IC pin or on the IC side of the termination resistor. In design of systems, this filtering effect can be used to reduce a system’s susceptibility to crosstalk by increasing the value of series termination resistors and placing them close to the connector to maximize the amount of capacitance on the IC side of the resistor.

In systems using the 80-conductor cable the largest contributors to crosstalk are the connector at the sender, and the PCB traces in systems with long traces or a large amount of coupling between traces. The connector at the receiving end of the system generates less crosstalk than the one at the sending end because the net current flow through the aggressor lines is less at the receiving end. This is because the load on the IC side of the recipient’s connector is the PCB trace and a small capacitance inside the IC; only enough current flows through the connector to charge this total capacitance. At the sending end of the system, the instantaneous value of current through the connector is determined by the input impedance of the cable, and this amount of current flows for a length of time sufficient to charge the entire system including the cable and all attached devices up to the sender’s VoH .



NOTE explain why the device connector produces negligible crosstalk when it is receiving

Crosstalk in the connectors is almost entirely inductive. It is produced in both directions from the connector but not necessarily in equal amplitudes. The highest amplitude crosstalk is generated by many switching lines coupling into a small number of victim lines, which lowers the effective source impedance of the crosstalk, making it approximate a voltage source. This voltage source is in series with the transmission line impedance on each side of the connector on the victim line. As a result, the crosstalk voltage is divided between the two directions proportional to the impedance seen in each direction. Figure C.17 shows the schematic of a model which demonstrates this. The PCB and cable on the victim line have been replaced with resistors to simplify the resulting waveforms. Figure C.18 shows the current through the inductor on the aggressor line and the crosstalk voltage produced on the victim line into the resistors representing the PCB and cable impedances. The waveforms indicate that the crosstalk voltage divides in the expected ratio: the PCB receives (50/(82+50))*100=37.9% of the total voltage across the inductor, while the cable receives the remaining 62.1%. In an actual system, the crosstalk into the PCB would be terminated by the driver impedance, while the crosstalk measured at the receiver would be double the value of the pulse initially produced into the cable impedance.

Figure C.18 – Model of voltage divider for connector crosstalk formed by PCB and cable.



Figure C.19 – Waveforms showing connector crosstalk dividing between PCB and cable

Because of its polarity and directional characteristics, there is only one point in the cycle when connector crosstalk creates a serious hazard to signal integrity. After a rising edge has reflected off of the receiving end of the system it passes back through the connectors at each end of the cable. The reverse crosstalk this creates is positive and will propagate back to the receiver and be seen during the middle of the current cycle, creating the possibility of clocking bad data if the amplitude is high enough. At all other points during the cycle, connector crosstalk is either negative (forward crosstalk on a rising edge or reverse crosstalk during the reflection of a falling edge) or in the case of forward crosstalk on a falling edge, it occurs only during the time when all signals are switching and as a result does not significantly affect the setup and hold times at the receiver. For each edge on the bus four crosstalk pulses are created on non-switching victim lines due to the combined crosstalk in the PCB, connector, and cable:

1) Forward crosstalk from the initial edge has the same sign as the edge and is seen at the receiver as a pulse that arrives with the edge. The amplitude of the pulse is doubled at the receiver, however because it occurs during the interval when the data is changing it may decrease the signal’s setup or hold time but it presents a minor risk to data integrity overall.

2) Reverse crosstalk from the initial edge travels back towards the driver as a flat pulse with a width equal to the transition time of the driver. Based on the degree of mismatch between the driver’s output impedance and the cable impedance, this pulse may be reflected back towards



the receiver with reduced amplitude. Because it continues to arrive at the receiver well after the driver has completed switching, it creates a risk of incorrect data at the receiver in the middle of the cycle. However, it is unlikely to ever create a high enough amplitude at the receiver to cause a problem.

3) Forward crosstalk from the reflected edge arrives back at the driver simultaneously with the reflected edge on the aggressor lines. Depending on the impedance mismatch at the source it will be reflected back towards the receiver with reduced amplitude and arrives in the middle of the cycle, however it is not likely to create a high enough amplitude at the receiver to cause problems.

4) Reverse crosstalk from the reflected edge on the aggressor lines will be created travelling back toward the receiver and arrives there in the middle of the cycle. In host systems where the termination resistors are not placed next to the connector a larger portion of the crosstalk created in the connector will be reverse crosstalk on the cable side because of the divider formed by the 50-60 ohm pcb and the 82 ohm cable impedance. The pulse will be seen with doubled amplitude by the device at the end of the cable and presents a serious hazard to data integrity if it’s amplitude at the receiver exceeds 800mV.

In the worst case of reverse crosstalk from a reflected rising edge, the amplitude of crosstalk at the receiver will depend on the impedance on each side of the two connectors the signal passes through (propagating past a connector on the cable does not introduce a significant amount of crosstalk). If the host PCB trace impedance is low, a larger portion of the crosstalk created in the host connector will travel back towards the receiver.

C.2.3 Ground/Power Bounce

Ground bounce is a form of crosstalk that results from the resistance and inductance of the power and ground pins of IC packages. For single-ended drivers, the return current for all signals flows through the power and ground leads, with the result that any voltage drop across these pins is imposed on all signals equally. Voltage drops across these pins occur due to both resistance and inductance whenever there is a net current flow into or out of the signal pins of the IC, though inductance has the greatest effect. In terms of the voltage seen at the receiver, crosstalk due to ground bounce is indistinguishable from inductive crosstalk, with a sign opposite the polarity of the edge on the aggressor signal(s). See Figure C.20 for a model of ground bounce in IC package. See Figure C.21 for waveforms resulting from ground bounce at the transmittter and receiver of the aggressor and victim signals.

In order to measure ground bounce in a functioning system, it is necessary to remove all other sources of crosstalk(especially reverse crosstalk from points later in the system). This can be done by disconnecting the IC pin on which the measurement is being taken from the PCB and measuring the voltage at the pin while all other lines are switching. The ground bounce produced by the initial and the reflected edges on the switching lines should be measured. Measurements should be taken with the victim line in a high and in a low state. The ground inside the IC will “bounce” and produce crosstalk on a low victim line when many lines are switching from high to low and sinking current through the ground pins. The power inside the IC will “bounce” and produce crosstalk on a high victim line when many lines are switching from low to high, and drawing current through the power pins.



Figure C.20 – Model of ground bounce in IC package

Figure C.21 – Waveforms resulting from ground bounce

(at transmitter and receiver of aggressor and victim signals)



It is important to note in the simulation waveform that ground bounce occurs both when the initial edge is driven onto the bus and when the reflected edge returns to the transmitter and is terminated into the source impedance of the drivers. Ground bounce produced at the source IC by the reflected edge propagates back to the receiver as a positive pulse given a rising edge on the aggressor lines and is seen at the receiver after three total one-way system delays (3 5 ns in the example in Figure C.18). This ground bounce is the reason why as much transmitter impedance as possible in a system should be placed in termination resistors outside of the IC package, rather than inside the IC. When the reflected wave returns and is terminated at the transmitter, the total voltage of the edge is divided among the different components of the transmitter impedance. If half of the transmitter impedance is provided by the termination resistor and half is the output impedance of the transmitter, then the voltage step seen at the connector pin of the IC when the reflected wave returns will be only half of the total edge. Because the IC input is resistive (it is driving) the di/dt through the IC package will also be reduced by half, relative to what it would be if the entire source impedance were inside the IC package. This will result in half as much crosstalk due to ground bounce if half of the source impedance is outside of the IC package.

In order to measure ground bounce in a functioning system, it is necessary to remove all other sources of crosstalk, ideally by disconnecting the IC connector pin on which the measurement is being taken from the PCB and measuring on the pin. To measure the maximum ground bounce, a line in the middle of the data bus pins on the IC package is held low and measured while all other data lines are asserted at the same time. It is important to measure the ground bounce produced by the initial and the reflected edges.

C.2.3.1 Measuring crosstalk in a system

To measure the total crosstalk in a system: set up a data pattern in which one line in the middle of the data bus is held low while all other lines are asserted simultaneously. Measure the low line at the recipient connector or IC. This measurement includes ground bounce at the transmitter IC as well as the contributions to crosstalk of the PCBs, connectors, and cables. Determining the exact sources of the different features of the crosstalk measured by this technique can be difficult. The best method to isolate the crosstalk produced in a given portion of the system is to sever the line before and after the feature being tested and terminate the isolated segment to ground at the breaks with a resistor equivalent to the transmission line impedance that is normally seen at that point. Measuring the crosstalk voltage across the termination resistors will indicate the raw quantity of crosstalk produced by that portion of the system, independent of reflections due to impedance mismatches and attenuation due to capacitance along the bus. Adjusting for impedance mismatches and delays will allow the crosstalk from that portion to be identified in the total crosstalk of the system, and adjusting the impedance changes through the system may allow the impact of that crosstalk to be minimized.

C.2.3.2 System design considerations to minimize crosstalk

Because all crosstalk throughout the system is proportional to edge rate, the first factor in controlling crosstalk is controlling the output slew rate of the drivers. The second major factor is the impedance match of sources to the cable including the value and placement of termination resistors. This is important in order to prevent reverse crosstalk from reflecting off the source and being seen at the receiver, and to control the amount of reverse crosstalk generated by the reflected edge. Drivers, PCB layout, and resistors should be selected to provide a good source termination for crosstalk and the reflected signal edge. At each connector the impedance seen looking back toward the source should match the cable impedance in the forward direction. For devices, this means that the sum of driver output impedance and termination resistance should match the cable impedance (typically 80 to 85 ), minus five to ten percent to allow for attenuation due to the capacitive loading of other devices on the cable. Because the PCB traces on a device are short in comparison to the electrical length of edges on the bus, they have little effect on the device’s output impedance. For hosts, PCB traces are often long enough that for high-frequency crosstalk, the impedance at the host connector is determined by the PCB trace impedance and termination resistors (if they are located at the connector), rather than by the driver’s output impedance. Because of this, there are two options for hosts to ensure an ideal source termination:



1) Place the termination resistors near the transmitter and use a PCB trace impedance that matches the source impedance of the transmitter plus termination resistor, ideally slightly less than the cable impedance. In this case, trace impedance should be high, approximately 70 to 75 , and a large enough trace spacing should be maintained to keep crosstalk (especially reverse crosstalk) between PCB traces to a minimum.

2) Place the termination resistors near the connector and select PCB trace impedance and termination resistance to sum to the cable impedance or slightly less. In this case, the transmitter source impedance should match the PCB trace impedance rather than the cable impedance, since that is the load that it is immediately driving.

Option 2 is desirable for backward compatibility with older systems using the 40-conductor cable because placing the resistor near the connector helps to damp the ringing that occurs with that cable. In addition, 50 to 60 traces are easier to implement and produce less crosstalk than higher impedance traces.

In either case, the total output impedance should maintain a close match to the cable regardless of whether the drivers are at steady-state or switching, rising or falling, or experiencing over or undershoot conditions.

C.2.4 Ringing and data settling time (DST) for the 40-conductor cable assembly

High amplitude ringing may occur for some data patterns in systems using the 40-conductor cable assembly. The sixteen data lines (DD15:0) in a 40-conductor cable assembly are adjacent to each other and have only one ground on each side of the data lines. There are only seven ground lines present in the entire cable assembly. This lack of ground return paths has three negative effects on data signal integrity:

1) Crosstalk between data lines is very high due to inductive coupling.2) Conductors in the center of the set of data lines (e.g., DD11) exhibit very high inductance

because the distance from these signal lines to the current return path is large and the ground return path is shared with many other signal lines.

3) Conductors in the center of the set of data lines are shielded from ground by the other data lines around them. When these lines are switching in the same direction there is no potential difference and therefore no effective capacitance between lines.

This combination of factors results in the impedance of the conductors in the center of the set of data lines rising from 110 to 150 (measured when a single line is asserted or negated) to an almost purely inductive 300 to 600 when all lines are asserted or negated simultaneously in the same direction. Measured impedance varies with data pattern, edge rate, cable length, loading, and distance from chassis ground.

In a simplified model of the 40-conductor cable assembly with all data lines switching, a conductor in the center of the set of data lines can be described as a pure inductor, forming a series RLC resonant circuit with the capacitance of the IC and PCB traces, and the combined resistance of the driver source impedance and source series termination resistor (see Figure C.19). The voltage across C will ring sinusoidally in response to an input pulse at V_source, exponentially decaying over time towards a steady state value. The formula for determining the frequency of this ringing is F = 1 / (2 SQRT(LC)) where F is the frequency, R is the value of the series termination resistor, and C is the input capacitance of the receiver. The rate of decay is proportional to R/L. Figure C.20 shows the output of a simple RLC model with the waveforms as seen at the connectors of the sender and recipient.



R40

L0.8 H

C25 pfV_source

Figure C.19 – Simple RLC model of 40-conductor cable assembly with all data lines switching

10 v

5 v

0 v

-5 v0 ns 50 ns 100 ns 150 ns

Time

source end

receiving end

Figure C.20 – Output of simple RLC model: waveforms at sender and recipient connectors

Data settling time (DST) is defined as the portion of cycle time required for ringing to decrease in amplitude until a correct level is guaranteed to be detected based on the thresholds of 2.0 volts (V iH) and 800 mV (ViL). The worst-case situation for most systems occurs when all data lines are switching except for one line near the middle of the bus that is being held low (see Figure C.21).

In this situation crosstalk creates a pulse on the signal line being held low that rings with a frequency and damping determined by the effective RLC parameters of the system. The DST value is the duration of time between the nominal beginning of the cycle (i.e., when the switching lines cross the 1.5 volt threshold) and the time when the ringing on the line drops below ViL for the last time as measured at the receiver.



Figure C.21 – DST measurement for a line held low while all others are asserting(channel 1 is measuring DD3 at the receiver, channel 2 is measuring DD11 at the receiver)

The same situation can also occur with reversed signal polarity (i.e., one line staying high while others are switching). Another case arises when all lines are switching simultaneously and the voltage on conductors in the center of the set of data lines rings back across the switching threshold (see Figure C.22). This is normally only a problem in the high state as low side ringing is greatly reduced by the substrate diode clamp to ground that is inherent in CMOS logic.



-22.00 ns 28.00 ns 78.00 ns #Avg 10.0 ns/div repetitive y2 2.00000 v x2 31.800 ns y1 1.50000 v x1 5.000 ns delta y 500.000 mv delta x 26.800 ns 1/delta x 37.3134 MHz

X1

X2

Y1

Y2

source end

receiving end

Figure C.22 – DST measurement for all lines switching(channel 1 is measured at the connector of the sender,

channel 2 is measured at the connector of the recipient)

As the can be seen in Figure C.22, use of 3.3 volt signaling removes the high side voltage margin provided by the asymmetric threshold of the receiver. Consequently it is important to use slew rate controlled drivers to control ringing.

C.2.4.1 Controlling ringing on a 40-conductor cable assembly

An improved RLC model allows comparison between different termination schemes (see Figure C.23). This model includes separate capacitors to represent trace and IC capacitance at the receiver, as well as a clamping diode, representing the substrate diode in CMOS logic. Because this single-line simplified model does not include crosstalk between lines in the data bus, it cannot be used to predict DST for a particular design and combination of parameters. However, it can indicate the direction of changes in ringing frequency and damping in response to changes in system parameters.

R_source 7

Cable1 H

C_trace15 pf

V_source

R_series_src 33

R_series_rec 33

C_ICpin10 pf

D1D1N914

Figure C.23 – Improved model of 40-conductor cable assembly ringing with termination at IC



Figure C.24 – Improved model of 40-conductor cable assembly ringing with termination at connector

[editor’s note: we should have another figure showing a schematic of the capacitance being lumped when the resistor is not between the trace and the pin. Then this wording needs to be cleaned up.] Comparing the results given by theseis models for receiver termination resistors located at the IC versus the connector shows that greater damping is provided when termination is near the connector. In the schematic in Figure C.23 this corresponds to R_series_rec being connected on the left side of C_trace.

Figure C.24 – Results of improved 40-conductor model with termination at IC versus connector

These This simple models [editor’s note: i.e., those represented in figure 24 and the yet to be drawn figure] can be used in a similar way to determine the effects of changing slew rate, termination resistor value, output impedance, PCB trace length, or the length of the cable.



Figure C.25 – Results of improved 40-conductor model with source rise time of 1, 5, and 10 ns

As the results in Figure 25 show, increasing the rise time to above 5 ns results in a significant decrease in the amplitude of the ringing. Drivers with control over the shape of rising and falling edges can be used to reduce ringing even more.

Figure C.24 and Figure C.25 show that, although the diode clamps the voltage at the receiver at one diode drop below ground, a “ringback” pulse appears at around 100 ns. This pulse occurs because the combined series resistance of the termination resistor and diode is much lower than the impedance of the LC circuit that is ringing. In addition the diode only clamps the voltage across part of the capacitance involved in the ringing. A higher-resistance clamping diode would be more effective at dissipating energy from the resonant circuit but would be less effective at clamping the input voltage.

C.2.4.2 STROBE lines on the 40-conductor cable

Although the data bus on the 40-conductor cable has such a high level of crosstalk that transmission line effects are barely perceptible, the STROBE lines on the 40-conductor cable have a much more controlled impedance of approximately 115 because they are in a ground-signal-ground configuration. Although the STROBE lines are well shielded against crosstalk from each other and from the data bus, some devices using drivers with fast edge rates and no source termination resistors have experienced problems with overshoot and ringback on the STROBE lines. Ringing will occur when a large impedance mismatch exists between the driver output impedance and the 115 transmission line. If the ringback on a falling edge exceeds 800mV, STROBE may cross the threshold multiple times and cause extra words to be clocked at the receiver. After these problems were experienced almost all device and host manufacturers began using series termination resistors on the STROBE lines at both the transmitter and the receiver. hysteresis on strobe inputs, and deglitching schemes to spurious edges resulting from ringing.

With current I/O cell technology and the requirement for series termination resistors, ringing on the STROBE lines is seldom a problem for current systems. However, it is important to keep in mind that these are high speed edge triggered signals, and the possibility of double crossing of input thresholds due to noise, ringing, or transmission line reflections still exists. Because of this it is important that all hosts and devices implement some amount of hysteresis on STROBE inputs, possibly in addition to glitch filtering by digital logic after the inputs.



C.3 System Guidelines for Ultra DMA

This is a summary of recommendations for device, system, and chipset designers. These guidelines are not strict mandates, but are intended as tools for developing compatible, reliable, high-performance systems.

C.3.1 System capacitance

All hosts and devices should meet the specified capacitance value measured at the connector. This value is specified to be a maximum of 25 pf at the host and 20 pf at the device. With typical interface IC and PCB manufacturing technology, this limits host trace length to four to six inches. Capacitance is measured at 20 MHz as this is representative of typical ringing frequencies on a 40-conductor cable assembly.

PCB traces up to 12 inches long may be used if the following conditions are met:

1) The host chipset uses 3.3 volt signaling,2) The host chipset allows timing margin for the additional propagation delay in all delay-limited

interlocks, 3) Termination resistors are chosen to minimize input and output skew and are placed near the

connector,4) Total capacitance of traces, additional components, and host input pins is held to the

minimum possible, and5) An 80-conductor cable is installed for operation at Ultra DMA modes 2 and higher.

In this case capacitance at the connector will exceed the maximum value specified. As a result of this, systems may not operate reliably with a 40-conductor cable assembly in any Ultra DMA mode above mode 1 (22.2 megabytes per second). A host should not set mode 2 or above without insuring that an 80-conductor cable assembly is installed in the system.

C.3.2 Pull up and pull down resistors

Pull up and pull down resistors having a value below the specified minimum will increase skew. Use of a higher resistor value on IORDY (such as 2.0 k or 3.3 k will reduce skew and increase noise margin when IORDY is driven low.

Pull up and pull down resistors should be placed on the connector side of the series termination to minimize loss of DC margin due to pull up/pull down current through the series termination resistors.

C.3.3 Cables and connectors

Do not exceed the required 18 inch maximum cable length.

Ideal spacing for device connectors is six inches apart on 40- and 80-conductor cable assemblies from twelve to eighteen inches in length. For cable assemblies shorter than twelve inches, the connector on the cable for the device that is not at the end of the cable should be centered on the cable.

Exceeding a spacing of six inches between device connectors on an 80-conductor cable will cause increased skew when signaling to or from the device not at the end of the cable. As spacing between the devices decreases on a 40 conductor cable, the capacitance of the two devices (or the host and the device not at the end of the cable) act in parallel, resulting in decreased ringing frequency and increased DST.

In systems using a 40-conductor cable assembly, provide a continuous electrical connection from ground on the device chassis through the system chassis to the ground plane on the host PCB. The cable should be routed as close to the chassis as practical to minimize inductance and reduce data settling timeRouting the cable in close contact with the chassis will reduce data settling time, as long as it can be done without significantly increasing the cable length. [editor’s note: do we really want to say this? Or something else? This isn’t always the best routing.].



C.3.4 PCB design

Total output impedance of hosts and devices should be designed to be as close as possible to the cable impedance to minimize reflections and reverse crosstalk due to the impedance mismatch between the PCB and cable. The impedance of the 80-conductor cable is specified to fall within the range of 70 to 90 and is between 80 and 85 for typical cables with solid wire and PVC insulation.

The ratio of PCB trace spacing to height above ground plane should be kept high to control crosstalk between traces.

PCB trace characteristics should be controlled to minimize differences in propagation delay between STROBE and DATA lines. Factors that affect the delay are:

1) Trace length,2) Additional capacitance due to stubs, routing on inner layers, pads, and external components

such as pull up resistors and clamping diodes, and3) Additional inductance due to vias, series components such as termination resistors, and

routing across a break in the ground plane, over areas with no ground plane, or at a larger height above the ground plane.

Series termination resistors should be selected that make the total output impedance a close approximation to the cable impedance. Drivers and terminations should be designed together to provide a stable output impedance across switching conditions and process and temperature variations.

Series termination resistors should be placed as close as possible to the cable header or connector.

Series termination values should be chosen to equalize input RC delays for the STROBE and DATA lines. For typical host IC implementations the same type of I/O cell is used on all signals and therefore all termination resistors at both transmitters and receivers should have the same value.

Sufficient ground and power pins should be used on interface ICs to control ground bounce when many lines are switching at the same time.

C.3.5 Transmitter and receiver I/O cells

The 80-conductor cable assembly impedance is less than half that of the typical 40-conductor cable assembly impedance when multiple lines are switching at the same time. For some types of drivers this will result in more than double the current draw during switching and as a consequence the amplitude of ground bounce will also double.

Drivers should be designed to have a slew rate of 1.25 V/ns or less across the full range of loading conditions, process, and temperature.

I/O cells should be designed to produce output setup and hold times at the connector as specified in this standard across the full range of loading conditions, process, and temperature. Margin should be provided to allow for skew introduced between the IC and the connector.Device PCB traces and I/O cells should be designed to present similar loading between STROBE and DATA at the connector to minimize additional skew added to signaling between other devices on the bus.

All hosts and devices should use hysteresis on both data and STROBE inputs. Initial voltage steps on the bus are at undefined levels and may be near the thresholds, causing slow slew rates through the threshold that result in high sensitivity to noise if hysteresis is not used.

The following loading conditions should be used to test drivers as well as host and device output characteristics at the connector:

1) 0 pf to ground (open circuit, minimize test fixture capacitance)2) 15 pf to ground



3) 40 pf to ground4) 470 to ground, switching low to high5) 470 to Vcc, switching high to low

All tests (except open circuit) are conducted with the intended series termination resistance in place. Output skew and slew rates are measured between the series termination and the load. Rise and fall times measured between 10 and 90 percent of VoH should be 5 ns or longer into all loads.

C.4 Ultra DMA protocol

C.4.1 tSR, tRFS, and the number of additional transfers

[editor’s note: couldn’t the information in the following clause be included in the clauses on these timings? This information seems somewhat redundant.]If the recipient does not meet the tSR maximum value, then the Ultra DMA burst may be paused with zero, one, or two additional data transfers for modes 0, 1 and 2, and up to three additional transfers for modes 3 or 4. This does not imply that the sender is allowed to send up to two or three more STROBES after it detects the negation of DMARDY–. In most cases it would be a violation of tRFS to do so. The tRFS time is less than or equal to one transfer cycle time for modes 0, 1 and 2, and less than or equal to the time for two transfer cycles for modes 3 and 4. Sending two or three more STROBES once DMARDY– transitions at the sender’s end of the cable would always be a violation of t RFS

for modes 0, 1, and 3. In many cases sending two or three more STROBE edges would be a violation of the tRFS timing for modes 2, 3, and 4. Under all conditions, the sender stops generating STROBE edges within tRFS of the receiver negating DMARDY–.

[editor’s note: look at the following first sentence, and try to make it be more clear.]In most cases it would be a violation of the protocol for the sender to generate the maximum number of STROBE edges the recipient should be ready to receive after negating DMARDY–. In those same cases, it is still possible for the recipient that is attempting to pause to see two or three more STROBE edges after it negates DMARDY– without any violation of the protocol. This is due to the delay of the signals through cable.

In mode 2 when the STROBE time is 60 ns and signal delays add up to 6 ns, both STROBE from sender to recipient and DMARDY– from recipient to sender experience a cable delay of 6 ns. While the recipient negates DMARDY– after the instant that the sender toggles STROBE, it does not see the STROBE transition until after the DMARDY– negation. This would account for the first word received. By the time the sender sees the DMARDY– negation, there are only 49 ns until the next STROBE. This STROBE is within tRFS so the sender may send STROBE without violating the protocol. To the recipient, this would be the second transfer after it negates DMARDY–, but to the sender it would be the first and only allowable STROBE transition after seeing the DMARDY– negation.

STROBE @ sender60 ns

49 nsDMARDY- @ sender

6 ns

DMARDY- @ recipient

5 ns

STROBE @ recipient

6 ns

Figure C.26 – STROBE and DMARDY– at sender and recipient



It can be calculated that in the mode 2 corner cases where the cycle time is the minimum and the delays are maximized, any time that the recipient negates DMARDY– longer than tSR after it receives a STROBE edge, it may receive up to two more transfers. tSR is timing that defines the boundary between cases where it is possible for up to one word to be received after the negation of DMARDY- and the cases where it is possible for up to two words to be received. By the same type of analysis used to show that up to two words may be received in cases similar to the one shown above, it can also be proven that when t SR timing is met by the recipient, it can only receive up to one more word without the sender being in violation of the protocol.

It is important to note that these values are specified to be at the connector and not inside the IC. There will be some output delay of DMARDY– from inside the IC to the connector, and there will be input delay of STROBE from the connector to inside the IC. Even when tSR is met at the connector, two more words may be received inside the IC after the device system clock edge that generates the negation of DMARDY– without any part of the protocol or timing being violated. The first word received inside the IC would be an edge that transitions at the connector before the negation of DMARDY– gets there due to output delays, and the second edge would be the single STROBE (at the connector) that is allowed in the tSR case.

[editor’s note: look at a better way to word the following paragraph.]Additionally, a recipient can not expect a fixed number of words after negating DMARDY–. Every time a recipient begins a pause, it should be ready to accept zero more words, one more word, two more words, or three more words (for modes 3 and 4) at random. In addition, the recipient has to be capable of receiving STROBE edges until tRFS after it negates DMARDY–. The recipient should not use the receipt of two or three words after a pause has been initiated as an indication that the sender has paused. The recipient waits until tRP after the pause was initiated before taking any other action (e.g., terminating the burst). This is to allow the sender time to complete it’s process of transitioning to a paused state. This may take additional system clocks after the sender has sent it’s last STROBE transition.

It is impossible for an Ultra DMA recipient to stop a data transfer at an exact, predetermined boundary. Even by meeting tRP timing, the recipient can not avoid cases where the sender may toggle STROBE for one additional word. See XX on recipient pauses for additional implications of the tRFS timing.

C.4.2 Issues with tSR

[editor’s note: There could be a lead-in sentence here. This clause needs reworking. Why doesn’t this go down with the clause on this timing?]tSR defines a boundary between different pause cases. It could have been required that, for all recipient generated pauses, the recipient is able to receive up to two more words for modes 0, 1, and 2, and up to three more words for modes 3 and 4. However, a design could be produced in such a way as to always meet tSR through synchronizing the outgoing DMARDY– negation with the incoming STROBE signal from the sender. With this design a recipient would only be required to receive up to one more transfer. Even though this kind of design adds complexity and provides little advantage, t SR

was included for completeness.

A system where the DMARDY– is negated asynchronously with respect to the incoming STROBE is the preferred implementation. In this implementation, the negation of DMARDY– for pauses would be controlled by the state of the FIFO. Once a near-full condition occurs, DMARDY– could be negated. There is no advantage toward FIFO size in trying to meet tSR since synchronizing the outgoing DMARDY– signal with the incoming STROBE requires an additional STROBE to occur after a FIFO near-full condition is detected before the DMARDY– can be negated. If the asynchronous method is selected as recommended, then the recipient will always be ready for the maximum number of words allowed after it negates DMARDY– and will work under any of the described conditions.



C.4.3 Issues with tZIORDY relative to tENV

[editor’s note: this clause needs to be updated to reflect the new note for the timing table. Again, couldn’t the information in the following clause be included in the clauses on these timings? This information seems somewhat redundant.]

tZIORDY does [editor’s note: add something like, “…have a maximum value that is tENV plus tFS…” in this spot] not have a maximum value while both a minimum and maximum bound tENV. In the initiation of a data in burst, this means that STOP may be negated and HDMARDY– asserted (i.e., the host is ready for the first DSTROBE edge transferring data from the device) while DSTROBE is released (in the high-impedance state). For the initiation of a data out burst, STOP may be negated (the host is ready to transfer data when the device is ready) while HDMARDY– is released. In either case, there is no problem if IORDY:DDMARDY–:DSTROBE is released. If IORDY:DDMARDY–:DSTROBE is released by the device, it will be detected as electrically high at the host because the host is required to have a pull-up resistor on this signal line. PIO and DMA protocols rely on this pull-up to maintain an electrically high level on IORDY. These protocols only require this signal to be negated when a device is not ready.

For Ultra DMA, DDMARDY–:DSTROBE is only driven during a data burst. At the initiation of a data in burst, the device may wait until the first data transfer to drive DSTROBE. The device may wait t ZIORDY then assert DSTROBE. Then, for the first data transfer, the device negates DSTROBE. In both cases the host sees a negation for the first DSTROBE. The first STROBE of a burst is never a low-to-high transition. At the initiation of a data out burst, the device may wait until a ready signal is required before negating DDMARDY–. If the device does not us this implementation, it waits tZIORDY then negates DDMARDY– (i.e., drive it electrically high). Then, to signal that the device is ready to receive data, the device may negate DDMARDY–. Both implementations are equivalent since the negated state of this signal will appear the same to the host as the released state.

C.4.4 Recipient pauses and implications for data handling and CRC calculation

[editor’s note: we need some clarification of “internal clock” and the concept of “synchronization”. There is no STROBE once the signal is inside the device’s ASIC.]

The Ultra DMA protocol allows the recipient to pause and then terminate a burst at any time regardless of the state of STROBE or the data on the bus. Since a sender stops toggling STROBE in less than one transfer cycle time after DMARDY– negates at its input, it is impossible to avoid cases where data will be gated or latched to the bus but never strobed because the data is latched before DMARDY– is synchronized to the sender’s internal clock. For example, one possible Ultra DMA mode 2 design implementation would be with a 33 MHz system clock and two flip-flops to synchronize the DMARDY– signal. The first flip-flop would be on an active clock edge and the second on the normally unused clock edge. In this case t RFS is only long enough for the sender to synchronize the DMARDY– signal and then stop toggling STROBE. Any data placed on the bus but not yet strobed when DMARDY– is internally synchronized is not to be strobed.

There is no minimum cycle time for DMARDY–. The recipient does not have to wait for additional words or for tRP from the time it negates DMARDY– until it re-asserts DMARDY–. If, after negating DMARDY–, the device becomes ready, it may reassert DMARDY–. Based on the implementation of the sender, a negation and immediate re-assertion of DMARDY– may cause a subsequent STROBE timing to be delayed. It is recommended that some hysteresis be used in the FIFO trigger points for assertion and negation of DMARDY– to avoid oscillation in the transfer (DMARDY– being negated after every word or two).

The above information on recipient pauses has two major implications: the first is with output data handling, and the second with CRC calculation. If an output register is used when data is transferred from memory to the register in order for presentation on the bus, no assumptions are made that that data has been or will be transferred. If a pointer in memory is incremented or the data is cleared from memory when it is sent to the output register, then that data may be lost unless some recovery mechanism is present to decrement the pointer or restore the data if it is never strobed due to a burst termination after a pause. During a pause, other bus activity (like a status register read) might occur between when a burst is paused and it’s resumption. A design using an output register would have any data in that register overwritten during this



other activity. Other designs may involve similar considerations. It is most important to remember that data on the bus is not sent and is not be treated as sent until there is a valid STROBE edge.

[editor’s note: new clause – the following should be a new clause or the first paragraph of the next clause. The paragraph above this note may want to be combined with this clause, as well.]

Beside careful data handling to avoid the loss of a word, it is important what data is used for calculating the CRC. For each STROBE transition used for data transfer, both the host and device each calculate a new CRC value. Only words successfully transferred in the transfer phase of the burst are used to calculate CRC. This includes words legally transferred after a pause has been requested. Words put on the bus but never strobed are not to be used for CRC calculation. In addition, if STROBE is negated at the end of a pause and then the burst is terminated, the protocol requires STROBE to be re-asserted after DMARQ is negated or STOP is asserted, depending on the case (both conditions may be true when STROBE is re-asserted). No data is transferred on this STROBE edge and any data on the bus that was not strobed during the transfer phase of the burst is not used in the CRC calculation on this re-assertion of STROBE.

C.4.5 CRC calculation and comparison

As stated in the clause on recipient pauses (see XX) and implications for data handling and CRC calculation, CRC is calculated on successfully transferred data only. As explained above, there is no insurance that data placed on the bus will be strobed. CRC is only be calculated on words that are properly strobed.

The CRC generator is not to be clocked on the unsynchronized STROBE edge. [editor’s note: ---- is the following sentence necessary?]A synchronized version of STROBE is required to clock data from an input latch to a FIFO”. This same synchronized version of STROBE is used to strobe data to and clock the CRC generator. By directly clocking the CRC generator with the unsynchronized STROBE input, two problems could occur. Noise on the edge of STROBE that causes the input I/O cell to trigger more than once could cause the CRC generator to clock twice, but the synchronized versions of the STROBE would not have a glitch. In this case, the correct data could be strobed into the FIFO but the incorrect CRC value generated. Second, if there is an error in synchronization that causes the wrong data to be strobed into the FIFO, there is a possibility that the wrong data would be strobed to the FIFO while the correct CRC value is determined. The use of this incorrect structure makes the CRC value unreliable and eliminates its advantage.

While CRC generation is a bit-by-bit serial shifting process, data on the bus is transferred one word at a time making a serial implementation difficult. For Ultra DMA, short of having an internal clock with a period 16 times shorter than the minimum transfer cycle time tCYC, a clock with a longer period and a parallel equivalent to the serial process is to be used. This standard includes the equations that define the XOR manipulations to make on each bit and the structure required to perform this calculation using a clock generated directly from STROBE. Through the given equations, the correct CRC can be calculated by using a small number of XOR gates, a single 16-bit latch, and a word clock (one clock per STROBE edge). The equations define the value and order of each bit, and the order of each bit is be mapped directly to the same order lines of the bus. The CRC register is pre-set to 4ABAh. This requires pre-setting the latch (CRCOUT) to 4ABAh before the first word clock occurs. After that, CRCIN15 to the latch is tied through to CRCOUT15. When the burst is terminated CRCOUT15 is the final CRC bit 15 that is sent or received on DD15. This direct matching of bit order is true for all CRC bits. The proper use of the data sent on the bus bits DD0 through DD15 during the burst transfer is defined in the equations. The DD15 on the bus has the same value as bit DD15 in the equations to calculate CRC. This direct mapping is true for all bits strobed on the bus during a burst.

Once the burst is terminated and the host sends the CRC data to the device (the host always sends the CRC independent of whether the burst was a data in or data out transfer), the device compares this to the CRC it has calculated. While other CRC validation implementations may be possible, a CRC input register may be used on the device in combination with a digital comparitor to verify that the CRC value in the input register matches the value in it’s own CRC calculation register.



C.4.6 IDENTIFY DEVICE command

A device communicates its Ultra DMA capabilities and current settings to the host in the data returned by the device as a result of an IDENTIFY DEVICE command.

For the PIO and Multiword DMA protocols, only the host generates data STROBES so the minimum cycle times reported for those protocols in the IDENTIFY DEVICE data are used by the host for both data in and data out transfers to insure that the device’s capabilities are not exceeded. For the Ultra DMA protocol, both the host and device strobe data depending on the direction of that data. The host determines a mode setting based on both the device’s capabilities and its own. The sender may send data (toggle STROBE) at a minimum period of tCYC. A recipient receives data at the minimum tCYC for the currently active mode. If the device indicates that it is capable of an Ultra DMA mode, it receives at the minimum time for that mode, no additional cycle time information is required.

C.4.7 STROBE minimums and maximums

The Ultra DMA protocol does not define a maximum STROBE time. The sender may strobe as slowly as it chooses independent of the mode that has been set, though it has to meet the specified setup and hold times for the mode that has been set. Regardless of the frequency of the STROBE, the recipient has to be able to meet the setup and hold times of the received signal specified for the mode that has been set. The limit on the maximum STROBE time can be determined by the Ultra DMA device driver or BIOS time-out. This time out should be at least on the order of a few seconds. If for example a device begins to strobe once every ten seconds during a data in burst, this would not be in violation of the protocol. However, this could cause a driver to assume the device is hung. Whatever recovery mechanism the driver chooses to use will then be performed. The recovery will most likely be a reset to the device.

[editor’s note: the information in the following two paragraphs is already in, or should be combined into , the paragraph above.]

In addition to not being required to send at the minimum transfer cycle time, the sender is also not required to maintain a consistent cycle time throughout the burst. It would not be a violation of protocol for the cycle time to change on every cycle so long as all cycles are longer than or equal to the minimum cycle time for the mode that is set. A recipient should not use an upper timing bound or PLL to qualify the STROBE signal. The sender may consider the burst paused as soon as it meets the data hold time tDVH. For every word, after the sender has met the hold time, the sender may consider the burst to be paused. The other implication to this is that data to the recipient can stop on any word. After each word, the recipient waits (with exception of the case where it chooses to pause or stop) but never require an additional word before allowing the burst to be terminated.

While the sender can strobe data as slowly as it wishes, the recipient is always capable of receiving data at the minimum cycle time of the mode that has been set. The host controls the minimum cycle used by the device to send data for data in bursts by using the SET FEATURES command to set the transfer mode. The device may send at the fastest cycle time tCYC for the mode to which it has been set.

C.4.8 Typical STROBE cycle timing

The typical cycle times are 120, 80, 60, 45, and 30 ns for 16.67, 25.0, 33.3, 44.4, and 66.6 megabytes per second, respectively.

[editor’s note: this whole clause should read something like: “Neither minimum nor typical cycle times are required to be used by the sender. Other cycle times may be used by systems that do not have internal clocks that provide a frequency to generate signals at those cycle times. Then use the example of 25 MHz clock. This should reference the clauses about the relevant timings that follow.]

Using a common system clock rate of 66.7 MHz, the achievable typical cycle times are 120, 90, 60, 45, and 30 ns. A STROBE cycle time of 90 ns for mode 1 is not a violation of the specification as discussed above. A typical cycle time of 90 ns reflects 22.2 megabytes per second. The reason that Ultra DMA mode 1 cycle timing was specified for 80 ns typical instead of 90 ns was for better support of systems that use 25 MHz



clocks (40 ns period). A system running at 25 MHz may not be able to meet the minimum mode 2 timing (receive data at a minimum of 55 ns cycle time) but it should be able to meet the typical mode 1 timing. If the mode 1 timing was changed to 90 ns, a 25 MHz system would have to use an even slower cycle time of 120 ns (it’s next slower cycle time without using both edges) since 80 ns would be too short for the protocol.

While not a common clock rate, 50 MHz can meet all mode 0, 1, and 2 timings since it's clock period is 20 ns and might be used for mode 4 when the data is sent at 40 ns typical instead of the 30 ns typical.

C.4.9 Holding data to meet setup and hold times

[editor’s note: For this clause: just give one example of a way that works.]

The following are three examples of methods to meet the setup and hold times. The first example uses the same clock edge to change data and the STROBE but delay the data through some gates. The second example uses one edge of the clock to change the STROBE and then the next opposite edge to change data (half cycle). The third example uses one active edge of the clock to change STROBE and then the next to change data.

As an example: for Ultra DMA mode 4, if half of the two cycle typical time is 30 ns, and the corresponding clock period may be 15 ns. Using the values given in the timing derivations clause (see C.3), the sum of all skews from the output flip-flop clock to the input flip-flop (most of which are out of the control of the sender) are shown to be just under plus or minus 14 ns. The skew between STROBE and DATA is just as likely to be in either direction, and the required setup and hold times of two CMOS flip-flops should be within 200 ps of each other and both less than 1 ns. This results in the requirement that the minimum setup and hold times that the sender ASIC generates internally are both just greater than 14 ns. Using a single 66.7 MHz clock period between the STROBE and DATA is an ideal way of holding data. Since the setup and hold time margins are stringent for mode 4, it can be shown that either of the other two methods would fail due to gate delay variations and clock asymmetry. If the DATA transitions are not at the middle of a 30 ns mode 4 cycle, either the setup or hold time margin will be reduced.

C.4.10 tACK timing

The tACK value is defined for the setup and hold times before assertion and after negation of DMACK–. It is applied to all control signals generated by the host related to an Ultra DMA burst. These signals are STOP, HDMARDY–, HSTROBE and the address lines. The burst begins with the assertion of DMACK– and ends with the negation of DMACK–. For this burst period, all control signals start, remain, and end in specific states as defined by the protocol. Since there may be some signal skew between signals from the host to the device due to transmission and I/O circuitry affects, the host is required to set up all the control signals before asserting DMACK–. This insures that by the time all the signals reach the device, they will all be in the proper state at the instant that DMACK– is asserted. [editor’s note: couldn’t the following three sentences be deleted?] A critical signal is the host STROBE signal. If the STROBE does not meet the tACK

timing before the assertion of DMACK, there is a possibility that the device would see a spurious STROBE transition immediately after DMACK– is asserted. If at this point the device has asserted its DMARDY– signal, data would incorrectly be transferred and the burst would fail. Using tACK as the hold time for the signals after the negation of DMACK– insures that at the end of the burst, the control signals as seen by the device end in the states they are supposed in end in. This avoids any device state machine confusion.



C.4.11 Host chances to delay a burst

After a device has asserted DMARQ, the host has one opportunity to delay the start of the burst indefinitely for a data in burst and two opportunities for a data out burst. For both a data in and a data out burst, the first opportunity that the host has to delay the burst is by delaying the assertion of DMACK–. This delay has no specified maximum limit [editor’s note: but Curtis may hit us with multiple resets – ha!]. This is necessary for cases where overlap in PCI bus access may cause a delay in the time it takes for the host to become ready to receive data from a device after sending a data in command. For a data out burst, the host may delay the first STROBE signal. The difference in overhead between delaying and not delaying may seem small but can still be used to optimize for a faster overall system data transfer rate. The device as a sender does not delay its STROBE indefinitely since the device controls the signal that starts the transfer process (DMARQ).

Note that it is a violation of the protocol to terminate the burst unless at least one word has been transferred. If, after asserting DMACK–, the host sends or receives at least one word of data before terminating.

C.4.12 Maximums on all control signals from the device

All timing for signals from the device during a burst except for subsequent DSTROBEs after the first DSTROBE of a burst have maximum values. This is to bound the time it takes to perform burst initiation, pause, and termination so the host always knows in advance how long tasks performed by the device may take. Rather than waiting a few seconds for a command or burst time-out, the host can determine that a problem exists if activity is not detected within the specified maximums the host can set time-outs for functions performed by the device For instance, the longest the initiation of a data in burst may take from the host assertion of DMACK– to the first STROBE is tENV max plus tRS max. Also, the host may require a burst to terminate in a timely manner in order to service some other device on the bus or the system depending on the chip set design.

[editor’s note: what does the following have to do with this clause as it is titled? Isn’t this a “burst termination” paragraph?]

For both data in and data out bursts, the host may terminate the burst at any time. No matter what the device attempts to do to delay the termination of the burst, there is no way for it to indefinitely delay the burst if the host chooses to terminate it. For a device terminating a data in burst, once the device negates DMARQ, all the timings for which the device is responsible are limited with maximum times. The device may delay the negation of DMARQ after it has toggled DSTROBE for the last word of the burst or command. For the end of a command, it is likely that the host will assert STOP to terminate the command if the device delays its negation of DMARQ. Once STOP is asserted, the device can no longer delay the termination of the burst. It is required to negate DMARQ within tLI from the assertion of STOP. Similar timings apply for the termination of a data out burst, once the host asserts STOP, the device is required to respond to certain signals within tLI for the termination of the burst.

C.4.13 Bus turnaround

In Ultra DMA, there are some timings that are specified in relation to the driving of the data bus DD(15:0) to avoid device and host bus contention. This particularly applies to data in bursts when the device drives DD(15:0) until the end of a burst and then there is a turnaround so that the host can drive the CRC data on the bus.

At the initiation of a data in burst the host may be driving the data bus. DMARQ and DMACK– bound Ultra DMA bursts, and most of the bus turnaround timings are taken from these signals. At the assertion of DMACK– the host releases the bus within tAZ. The host may have already released the bus before the Ultra DMA burst started. Since there may be some system failure that causes the host to be in Multiword DMA mode and the device in Ultra DMA mode, there are two additional signals that should be in the proper state before the device drives data onto the bus. These signals are the negation of STOP and assertion of HDMARDY–. STOP is the same signal line as DIOW–, and HDMARDY– is the same signal line as DIOR–. Multiword DMA mode never asserts both DIOW– and DIOR– at the same time. The negation of STOP and assertion of HDMARDY– is equivalent to both DIOW– and DIOR– being asserted. Since the device requires



both signals to be in this state before driving the bus, it insures that the host is in Ultra DMA mode and not Multiword DMA and has released the data bus. Devices on the bus monitor STOP and HDMARDY– signals and, once both are in the proper state, wait tZAD before driving the data bus. The tZAD timing should be met from the last of the two signals to switch to the proper state. Once the device starts driving the data bus, it continues driving the data bus until the end of the burst.

At the end of a data in burst, there is another bus turnaround. Unlike the start of the burst, both host and device are known to be in Ultra DMA mode. Since the host drives data onto the bus before DMACK– is negated, the bus turnaround occurs before this time. Unlike Multiword DMA, for the Ultra DMA protocol, all data for a burst is insured to be sent by the time DMARQ is negated. After negating DMARQ, the device releases the bus within tAZ. This can be achieved by using the same system clock edge to do both functions. After detecting the negation of DMARQ, the host begins to drive the CRC onto the data bus no sooner than tZAH to insure that there will be no bus contention.

[editor’s note: should the following redundancy be deleted?]

Note that during a data in burst, the host should not attempt to drive the bus at any time after the t AZ timing discussed above at the initiation of the burst or before the tZAH timing discussed above at the end of the burst. In this time period, the device has full control of the data bus.

C.5 Ultra DMA Timing derivations

C.5.1 and C.5.2 describe. the assumptions by which the timing values in C.5.3 were derived.

C.5.1 Fundamental timings, skews and delays

Typical Cycle Times

Mode 0 = 120 ns (16.7 megabytes per second) = eight 66.7 MHz clock cyclesMode 1 = 80 ns (25 megabytes per second), or 90 ns with a 66.7 MHz clock (22.2 megabytes per

second) = six 66.7 MHz clock cyclesMode 2 = 60 ns (33.3 megabytes per second) = four 66.7 MHz clock cyclesMode 3 = 45 ns (44.4 megabytes per second) = three 66.7 MHz clock cyclesMode 4 = 30 ns (66.7 megabytes per second) = two 66.7 MHz clock cycles

Output Termination Resistor Delays (see C.1.2):

Rising transition delay = 0.34 ns minimum, 1.96 ns maximumFalling transition delay = 0.23 ns minimum, 2.61 ns maximum

Input Termination Resistor Delays

Data delay = –0.53 ns minimum, 0.76 ns maximumControl signal delay = –0.18 ns minimum, 0.12 ns maximum

Cable and System skews and delays

Output IC pin to input connector maximum negative skew = –3.37 ns (minimum STROBE delay minus maximum data delay)

Output IC pin to input connector maximum positive skew = 2.63 ns (maximum STROBE delay minus minimum data delay)

Output IC pin to input connector delay = 6.0 ns maximumOutput IC pin to input IC pin maximum negative skew = –3.52 ns (minimum STROBE delay minus

maximum data delay)Output IC pin to input IC pin maximum positive skew = 2.73 ns (maximum STROBE delay minus

minimum data delay)Output IC pin to Input IC pin delay = 6.2 ns maximum



C.5.2 IC and PCB timings, delays, and skews

While it is recommended that these timings be met, they are not requirements. [editor’s note: the following sentence needs to be cleaned up.] Meeting tighter timings in some areas will allow looser timings in others. A designer should take all the timings that are achieved for that design and re-derive the worst case timings for the protocol to determine if the timings for the protocol are met.

Possible clocks for bus timing and their characteristics

All frequencies are assumed to have 60/40% asymmetry

25 MHz (supports modes 0 and 1)Typical Period = 40 nsClock variation = 1 %

33 MHz clock (supports modes 0, 1, and 2)Typical Period = 30 nsClock variation = 1 %

[editor’s note: why is the following here?]33 / 30 MHz PCI clock (supports modes 0, 1, and 2)Typical Period = 30 / 33.3 nsClock variation = 1 %Minimum high or low time = 11.3 ns

50 MHz (supports modes 0, 1, 2, and 3)Typical Period = 20 nsClock variation = 3.5 %

66 MHz (supports modes 0, 1, 2, 3, and 4)Typical Period = 15 nsClock variation = 3.5 %

Note that if 33 MHz or a multiple of 33 MHz is used, the typical cycle time for mode 1 will be 90 ns instead of 80 as is achievable with 25 MHz or multiples thereof.

PCB Traces

Delay = 1.0 ns maximumSkew between signals due to traces = 0.1 ns maximum

IC inputs

Input delay from I/O pin to internal FF, includes input buffer and routing = 5.5 ns maximumInput skew from I/O pin to internal FF, (+/–) between STROBE and data = 4.3 ns maximum

IC outputs

[editor’s note: clear this up.] Output delay from internal system clock edge to I/O cell (including output buffer) = 18 ns maximum. If a 33 MHz or PCI 30 MHz clock is used, the output delay can be no more than 14 ns.

Output skew from internal system clock edge to I/O (+/–) between STROBE and data. The STROBE edge may be rising or falling and data edge may be rising or falling. This timing is met with any falling edge starting at I/O cell’s worst case high voltage level. VoH level or Vcc5 of system. This timing includes skew due to possible ground bounce during switching.

[editor’s note: the above needs to be cleaned up.]



With 25 or 33 MHz clock = 5.0 ns maximumWith 50 or 66 MHz clock = 5.5 ns maximum

Output rising vs. falling skew for a single buffer = 2.8 ns maximum

An additional 3 ns of delay are required for data than are required for STROBE for 33 MHz and and PCI30 MHz cases only. With these clocks, the data is held by a half cycle, and a minimum half cycle is not sufficient to meet the output hold time given the output skews listed above.

[editor’s note: the following needs to be cleaned up]The STROBE and data are skewed so that the typical data delay is longer than the typical STROBE delay. The only way to reduce this required skew and meet the hold time would be to reduce the total output skew listed above. The reduction in required data delay is equal to the reduction in total output skew.

IC flip-flops

Flip-flop setup time (internal) = 0.7 ns minimumFlip-flop hold time (internal) = 0.5 ns maximum

C.5.3 System timing parameters

All System timings for Ultra DMA (including tRP) are measured at the connector of the agent responsible for the timing. Internally the IC accounts for input and output delays and skews associated with all signals getting from the connector to the internal flip-flop of the IC and from the flip-flop of the IC to the connector.

While values are given for each possible clock frequency for some parameters, it is important to remember that each is only an example of what system timings will be when the above listed timing characteristics are met. An IC designer should re-derive all listed applicable timings based on the characteristics of the available system clock, IC and PCB that it are used to confirm that all system timing requirements are met.

C.5.3.1 t2CYCTYP (typical average two-cycle time)

This is the typical sustained average time of STROBE for the given transfer rate from rising edge to rising edge or falling edge to falling edge measured at the recipient’s connector. The minimum values for this timing are 240, 160, 120, 90, and 60 ns for modes 0, 1, 2, 3, and 4 respectively.

C.5.3.2 tCYC (cycle time)

This is the time allowed for STROBE from rising edge to falling edge or falling edge to rising edge measured at the recipient’s connector. This timing accounts for STROBE asymmetry and clock variation. The worst case for minimum tCYC is generated by using the maximum output buffer skew for signals switching in opposite directions. The formula for the minimum value is:

+ (Number of clock cycles to meet minimum typical cycle time with a minimum cycle time due to clock variation) (clock cycle time)

– Maximum skew time for switching in opposite directions on the same buffer

The minimum values for this timing are 112, 73, 54, 39, and 25 ns for modes 0, 1, 2, 3, and 4 respectively.

C.5.3.3 t2CYC (two-cycle time)

This is the time for STROBE for the given transfer rate from rising edge to rising edge or falling edge to falling edge measured at the recipient’s connector. Since this timing is measured from falling edge to falling edge or rising edge to rising edge of STROBE, asymmetry in rise and fall time has no affect on the timing. Clock variation is the only significant contributor to t2CYC variation. The formula for the minimum values is:

+ (2 x (Number of clock cycles to meet minimum typical cycle time with a minimum cycle time due to clock variation percent) for a 3.5 % variation in clock cycle) (clock cycle time)




C.5.3.4 tDS (data setup time)

This is the data setup time at the recipient. Since timings are measured at the connector and not at the ASIC, the effect of the termination resistors and traces should be considered when generating this number. Depending on the direction of the data signal and STROBE transitions, the skew between the two can change in both the positive and negative direction. A longer data signal delay will reduce the setup time, and a longer STROBE delay will increase the setup time.

In order to meet the required input skews given above [editor’s note: give specific reference to where above they are given], the number of buffers or amount of logic between the incoming signals and the input latch should be minimized. It may require the data input buffers to be routed directly to the input latch with no delay elements and the STROBE signal routed directly from it’s input buffer to the input latch clock with no delay elements.

The internal latch/flip-flop has a non-zero setup and hold time. tDS is sufficient to insure that the setup time of the flip-flop is met. The formula for the value for minimum setup required at the IC pin used in this annex is:

[editor’s note: is there an additional allowance for some other thing?]+ Maximum input skew+ Minimum flip-flop setup time

Setup at IC for all modes = 5.0 ns minimum.

What is achievable at the recipient’s connector without considering data settle time can be determined as follows:

+ time of Number of clock cycles to meet minimum typical cycle time with a minimum cycle time due to clock variation

– time of Number of clock cycles used to hold data with a minimum cycle time due to clock variation or with a minimum cycle symmetry if a half cycle is used

– Absolute value of maximum skew from sender IC to recipient connector between STROBE and DATA when DATA delay is longer.

– Maximum skew through sender trace (not included in IC to recipient connector skew value)

The timings specified add margin for settle time for all modes. The minimum values for this timing are 15, 10, 7, 7, and 5 ns for modes 0, 1, 2, 3, and 4 respectively.

C.5.3.5 tDH (data hold time)

This is the data hold time at the recipient. This time is sufficient to insure that the hold time of the internal flip-flop is met. The longest STROBE delay and shortest data delay is the worst case for hold time. The analysis is similar to the one for tDS above. The minimum hold required at the IC pin is:

+ Maximum input skew+ Minimum flip-flop hold time

Setup at IC for all modes = 4.8 ns minimum.

The formula for the value at the recipient’s connector without considering data settle time can be determined as follows:

+ Number of clock cycles used to hold data with a minimum cycle time due to clock variation or minimum half cycle time given worst asymmetry if a half cycle is used

– Absolute value of maximum skew from sender IC to recipient connector between STROBE and DATA when STROBE delay is longer.



– Maximum skew through sender trace (not included in IC to recipient connector skew value)

This assumes that one 50 or 66.7 MHz clock or half of a 33 MHz or slower clock has been used to hold data within the sender IC.

The minimum value for this timing is 5 ns for modes 0, 1, 2, 3, and 4 respectively.

C.5.3.6 tDVS (data valid setup time)

This is the data valid setup time measured at the sender’s connector. This timing is measured using a test load with no cable or receivers. This is the timing that, if met by the sender, will insure that the data setup time is met at the recipient. It is important that this timing be met using all capacitive loads from 15 to 40 pf to insure reliable operation for any system configuration that meets specification.

In the case of Ultra DMA modes 0, 1, and 2, the data settle time can be long due to [editor’s note: what kind of coupling? Is this really crosstalk?] coupling in the cable and on the PCB, and loading [editor’s note: what kind of loading?]. For modes above 2, there is little or no margin for ringing on the cable. For these modes, the 80-conductor cable assembly that reduces the coupling between signals and eliminates any ringing [editor’s note: Is this really zero? See above.] on the cable that crosses the threshold is required. Using the formulas given above [editor’s note: which formulas?] it can be demonstrated that the setup time required at the sender is met if both ICs meet the parameters listed [editor’s note: which parameters in which document? This annex?]. The identical parameters are therefore used here to calculate achievable setup time at the sender I/O cell [editor’s note: “These values generate values that will work?]:

+ Number of clock cycles to meet minimum typical cycle time at the minimum cycle time due to clock variation

– Number of clock cycles used to hold data at the minimum cycle time due to clock variation or at the minimum cycle symmetry if a half cycle is used

– Maximum skew through sender trace

The mode 4 value leaves no settle time in with a 66 MHz clock [editor’s note: does this mean that mode 4 won’t work with a 66 MHz clock??? This has to be clarified. Does this mean that this is true only with a 40-conductor cable?]. There should be about 5 ns worth of settle time available if mode 4 data is sent at a slower rate with a 50 MHz clock. In mode 3 there is about 14 ns of margin for data settle time. Given that all of these settle times are less than worst-case settle times with a 40-conductor cable assembly, an 80-conductor cable assembly is required for both modes 3 and 4.

The value specified for Ultra DMA mode 2 for tDVS is 34 ns. The only way this value may be achieved along with the required hold time is to reduce the output skew [editor’s note: is this really the only way? Isn’t the trace included]. If the total output skew is reduced by 2 ns, then the required data delay can also be reduced by 2 ns making the achievable tDVS 4 ns longer, that would meet the specification. For a 50 MHz clock the total output skew would have to be reduced by 4 ns, that will be difficult or impossible.


C.5.3.7 tDVH (data hold time)

This is the data valid hold time measured at the sender’s connector. This timing is measured using a test load with no cable or receivers. This is the timing that, if met by the sender, will insure that data hold time at the recipient is met. It is important that this timing be met using all capacitive loads from 15 to 40 pf to insure reliable operation for any system configuration that meets specification.

Two methods will be described to determine these values. One approach is to determine what value should be met in order to meet tDH. The minimum hold time required by the recipient has already been determined above (tDH) and the first approach will be based on this.

Hold time is reduced in the system with a STROBE delay that is longer than the data delay, this is represented by the maximum positive skew above. The hold time required at the output IC is therefore:



+ tDH

– Maximum positive IC to IC skew– Maximum trace skew

IC requirement = 7.63 ns

Given this requirement at the IC pin, the requirement at the connector pin can be determined. STROBE delay reduces the hold time and data delay increases it so the worst case would be as follows:

+ IC requirement just determined– Maximum trace skew– Maximum output falling delay through series termination+ Minimum output rising delay through series termination

tDVH all modes = 5.21 ns minimum

This value is rounded up to the nearest nanosecond to add a little margin so the tDVH specification for all modes is set to 6.0 ns.

After a connector timing requirement is determined, the IC pin requirement to meet this should be determined. A straightforward way to do this is to determine the extra margin added to t DVH by rounding up to the nearest nanosecond and add that same margin to the IC requirement already determined. The same result is found by taking the tDVH specification value and adding back the trace and termination resistor skew maximums as follows:

+ tDVH specification+ Maximum traces skew+ Maximum output falling delay through series termination – Minimum output rising delay through series termination

Actual IC requirement to meet tDVH = 8.42 ns

Either The achievable tDVH or hold at the IC pin can be determined and verified against the appropriate value listed above. The achievable tDVH can be determined as follows:

+ Minimum internal hold time. This will be a minimum half clock cycle time for a 25 or 33 MHz clock (clock at the minimum cycle time due to clock variation and the minimum asymmetry). For the PCI clock it will be the minimum PCI high or low time. For a 50 or 66 MHz clock it will be a minimum full clock cycle time (clock at the minimum cycle time due to clock variation).

– Maximum IC output skew– Maximum trace skew– Maximum output falling delay through series termination + Minimum output rising delay through series termination + Extra IC data delay over STROBE delay for 33 MHz and PCI clocks only

[editor’s note: the following paragraph is not clear.]If all timing characteristics given in the previous formula above are met, the hold time requirement at the IC in order to meet the tDVH specification will be met. As mentioned in the IC timing clause (see XX??). The required extra delay on the data over the STROBE can be reduced or eliminated by reducing the output skew for the IC. No other output delays or skews are under the control of the IC so this is the only way the required delay can be reduced. A full cycle time should not be used to hold data with a 33 MHz or PCI clock because this would be a maximum of over 30 ns internal hold time making it impossible to meet the required tDVS time. Simple gate delays can not be used in order to meet the hold time. Take, for example, an IC where the output buffer skews alone are reduced to only 2 ns. In order to meet tDVH, the internal hold time would have to be a minimum of 10.4 ns. Delays from transistor to transistor in a single IC can be well matched but over process, temperature, and voltage, transistor delay can vary by over 3X. Even if the



process were controlled well enough to insure a delay variation of 3X, the maximum internal hold would be over 30 ns and the tDVS time would not be met.

The minimum value for this timing is 6 ns for modes 0, 1, 2, 3, and 4.

C.5.3.8 tFS (first DSTROBE time)

This is the time for the device to first negate DSTROBE to clock the first word of data after the device has detected that the host has negated STOP and asserted HDMARDY- at the beginning of a data in burst. [editor’s note: which is measured where? There appears to be a prop delay missing someplace.]

This timing is used only for the beginning of a read command from the STOP negation and/or HDMARDY– assertion to first DSTROBE (all falling edges). The device detects that these two control signals from the host have changed. [editor’s note: the device has to determine the change of state of the last signal to change. From that point the device has to insure that the data valid set up time is legal and also that tFS is satisfied.] In general, synchronization is done with two flip-flops. After synchronization is achieved, data should be driven on to the bus and clock cycles counted off to meet the minimum setup time before the first STROBE is driven. In order for an IC based on a 25 MHz, 33 MHz, or PCI clock to meet t FS, data should be driven onto the bus no later than about 2.5 clock cycles after the control signal transitions. This could be done by synchronizing with both the active and inactive edge of the system clock or by using only active edges to synchronize but then driving data onto the bus on the next inactive edge of the clock after the signals are detected at the output of the second synchronization flip-flop. With a 50 MHz clock, the first word of data should be driven out no later than three cycles after the control transitions and with a 66 MHz clock, it may be four cycles. The maximum tFS timing is the sum of the following:

+ Maximum input STROBE falling edge delay through termination resistor+ Maximum PCB trace delay+ Maximum IC input delay to flip-flop+ Minimum flip-flop setup time + two, three, or four clock cycles at the maximum period due to frequency variation to synchronize

the control signals and start the data transfer cycle. For 25 MHz, 33 MHz, and PCI based systems, the data would be driven out ½ cycle after this [editor’s note: after what?], for other clock frequencies, data should be driven out no later than the three or four cycles allowed for here.

+ As many cycles as required to meet the tDVS minimum timing for the first word of data. Worst case for tFS is these at the maximum period due to frequency variation. For 25 MHz, 33 MHz, and PCI based systems, the number of cycles would be whatever is required to meet tCYC time. For 50 and 66 MHz clocks, it would be one fewer cycle.

+ Maximum output buffer delay+ Maximum falling edge output termination resistor (33 ) delay

The minimum value for this timing is 0 ns. The maximum values for this timing are 230, 200, 170, 130, and 120 ns for modes 0, 1, 2, 3, and 4 respectively.

C.5.3.9 tLI (limited interlock time)

The time is for limited interlock from sender to recipient or recipient to sender. This is the interlock time in this protocol that has a specified maximum.

The value of tLI needs to be large enough to give a recipient of the signal enough time to respond to an input signal from the sender of the signal. The derivation of tLI is similar to that of tFS since both involve the recipient of the signal responding to the control signal of the sender of the signal. As with t FS, the number of clock cycles that an IC may take to respond is dependent on the frequency of the clock being used. For a 25 MHz or PCI clock, the maximum time to respond is three cycles, for 33 MHz clock it is four, for a 50 MHz clock it is five, and for a 66 MHz clock it is seven cycles maximum for modes 0 through 2. Modes 3 and 4 require a faster response time. For a 50 MHz clock it is three and for a 66 MHz clock it is four clock cycles maximum. The achievable values of tLI derived as follows:



+ Maximum input delay through series terminations+ Maximum PCB trace delay.+ Maximum IC input delay to flip-flop.+ Maximum flip-flop setup time + three, four, five, or seven clock periods (depending on clock used and modes supported) at the

maximum period due to frequency variation to synchronize the signals to the internal clock and respond appropriately.

+ Maximum output buffer delay+ Maximum output delay through series termination (falling)

The minimum value for this timing is 0 ns. The maximum values for this timing are 150, 150, 150, 100, and 100 ns for modes 0, 1, 2, 3, and 4 respectively.

C.5.3.10 tMLI (limited interlock time with minimum)

The time is for the minimum limited interlock from sender to recipient.

This timing insures that some control signals are in their proper state before DMACK– is negated. It is important that STROBE and the control lines are in their proper states because all signals revert to their non-Ultra DMA definitions at the negation of DMACK–. If the signals are not in their proper state, the active device or another device may see a false read or write STROBE or data request. All control signals should be in their proper state and detectable at the device ASIC pins before DMACK– is negated so tMLI should overcome the following:

+ Maximum IC to IC delay+ Maximum IC input delay to flip-flop+ Minimum flip-flop setup time

The value determined for tMLI for all modes is slightly more than 12 ns.


C.5.3.11 tUI (unlimited interlock time)

This interlock timing is measured from an action of a device to a reaction by the host. In order to allow the host to indefinitely delay the start of a read or write transfer, this value has no maximum.


C.5.3.12 tAZ (maximum driver release time)

This is the maximum time that an output driver has to make the transition from being asserted or negated to being released. During data bus direction turn around, the driver of the bus is required to release the data on the same clock cycle as another action it is taking (at the latest) [editor’s note: specify which action by whom and when]. For the beginning of a read burst, the host should release the bus before or on the same clock cycle that it asserts DMACK–, for the end of a read burst, the device should release the bus before or on the same clock cycle that it negates DMARQ–. If the same clock is used, the maximum delay can be calculated using the following formula:

+ Maximum total IC output skew+ Maximum output (33 ) termination resistor delay

The value calculated by the formula above for tAZ for all modes is under 6 ns. The specified value for this timing allows for additional margin.

The maximum value for this timing is 10 ns for modes 0, 1, 2, 3, and 4.



C.5.3.13 tZAH (minimum delay time)

This is the minimum time that …

This timing is used only for the termination of a read when the actions taken by both the host and device to change the direction of the data bus are measured from DMARQ. In this case the device is allowed to continue driving the bus for a maximum of tAZ after the DMARQ negation. The device is driving both DMARQ and the data bus to start. The host should wait tZAH after the DMARQ negation to drive the data. Skew on the cable is the major factor to consider here and a longer data delay than DMARQ delay (aka maximum negative skew) is the worst case. To avoid bus contention, this value is calculated using the following formula:

+ Maximum tAZ

– Maximum negative I/O to I/O (overestimated by one set of termination resistors)

[editor’s note: what the heck does this mean? Is this one round trip propagation delay?]

The minimum value calculated by the formula above for tZAH is just under 14 ns. The specified value for this timing allows for additional margin.


C.5.3.14 tZAD (minimum driver assert/negate time)

This is the minimum time that an output driver has to make the transition from being negated to being asserted or negated. This timing is used only for the initiation of a read operation when the direction of the data bus is changed. Unlike the termination of a read operation where tZAH is used, the bus high impedance time (bus released) and bus driven time are measured from two different control signals. Since these control signals should meet tENV timing, that is a minimum of 20 ns, no additional delay is necessary based on the tZAH evaluation. The device should wait for the correct conditions to be present and then may immediately start driving the bus with no possibility of having bus contention. In practice, the device will require two flip-flop delays [editor’s note: for a total of tZAD time?] to synchronize the control signals before it begins driving the bus.


C.5.3.15 tENV (envelope time)

This time is from which the host asserts DMACK– until it negates STOP and asserts HDMARDY– at the beginning of a data in burst, and the time from which the host asserts DMACK– until it negates STOP at the beginning of a data out burst. Electrically these are all falling edge signals. Since tENV only applies to outputs from the host, the timings are synchronous with the host clock. Based on an argument similar to the one for tMLI, the minimum for tENV is set to 20 ns. This insures that all control signals at all the devices are in their proper (non-Ultra DMA mode) states before DMACK– is asserted and are sensed as changing only after DMACK– has been asserted. The 20 ns accounts for cable and gate skew between DMACK– and the control signals on device inputs. Since tENV involves synchronous events only and an increase in tENV reduces the performance of the specification, a maximum is applied.

Enough clock cycles should be used between the assertion of DMACK– and the other control signals to insure tENV minimum is met. For a 25 MHz, 33 MHz or PCI clock this is a single cycle, for 50 or 66 MHz clocks this should be two cycles. The minimum tENV value is calculated using the following formula:

+ one or two system clock cycles (depending on frequency used) at the minimum period due to frequency variation to delay control signals inside the IC

– Maximum total IC output skew– PCB trace skew– Maximum output falling delay through series termination+ Minimum output falling delay through series termination



Using the number of clock cycles specified above for each possible frequency, the minimum is met. The tENV

maximum should also be met. For a 25 MHz and PCI clock a single cycle should still be used. For a 33 or 50 MHz clock a maximum of two cycles may be used, and with a 66 MHz a maximum of three clock cycles may be used. The maximum tENV can be determined using the following formula:

+ one, two, three, or four clock cycles (depending on frequency used) at the maximum period due to frequency variation to delay control signals inside the IC

+ Maximum total IC output skew+ PCB trace skew+ Maximum output falling delay through series termination Minimum output falling delay through series termination

Using the number of clock cycles specified above, the maximum is met. Note that all the minimum and maximum number of clock cycles to be used are based on the timing characteristics given in this annex and fewer or more clock cycles may be used with some frequencies given reduced output skew. If the timing characteristics here are just met, then the internal IC delay should use the following number of clock cycles to be within tENV minimum and maximum values.

1) with 25 MHz, delay is one cycle2) with PCI (30 or 33 MHz), delay is one cycle 3) with 33 MHz, delay is one or two cycles4) with 50 MHz, delay is two cycles5) with 66 MHz, delay is two or three cycles

The minimum value for this timing is 20 ns for modes 0, 1, 2, 3, and 4 respectively. The maximum values for this timing are 70, 70, 70, 55, and 55 ns for modes 0, 1, 2, 3, and 4 respectively.

C.5.3.16 tSR (STROBE to DMARDY– time)

If DMARDY– is negated before this maximum time after a STROBE edge, then the recipient will not receive more than one additional STROBE (i.e., one more word of valid data). This timing is applicable only to modes 0, 1, and 2 because the transfer rate of modes 3 and 4 is too high to insure that only one additional STROBE will be sent after DMARDY– is negated.

The maximum values for this timing are 50, 30, and 20 ns for modes 0, 1, and 2 respectively. This timing is not applicable for modes 3 and 4.

C.5.3.17 tRFS (DMARDY– to final STROBE time)

This is the maximum time after DMARDY– is negated after which the sender will not transmit any more STROBE edges (i.e., no additional valid data words). This timing gives the sender time to detect the negation of DMARDY– and respond by not sending any more STROBES. The tRFS time may affect the number of words transferred.

Since tRFS involves a response to a request for a pause, the sender should stop sending data as soon as practical. An example of an input synchronization method is to use two flip-flops where the first is clocked on the active edge of the clock and the second on the normally unused (inactive) edge of the clock. The action to stop the STROBE signal would be taken on the next active clock edge (i.e., if there had been a STROBE scheduled for that edge it would not be sent). In this example a half cycle of the clock gives adequate time to avoid metastability while synchronizing the signal. The following timing diagram shows possible cases:



FF1

tRFS range

Clock

STROBE

DMARDY-

Next STROBE would havebeen here

FF2

Figure C.27 – DMARDY– to final STROBE tRFS synchronization

[editor’s note: the following paragraphs need to be made consistent with the figure above. The dotted lines are gone, and Pete shifted the FF2 is ½ clock time too far to the right.]The diagram above shows the range of possible STROBE to DMARDY– transition relationships and the possible synchronization flip-flop responses. When a 66 MHz or higher clock frequency is used, two clock periods may be used to synchronized the data as long as no STROBE edge is sent on the subsequent clock edges until the transfer is resumed.

The case where the tRFS time may be the longest is where the DMARDY– transition occurs before a clock cycle, but, due to skews and missed setup time, the transition is not clocked into the first flip-flop until the next clock (the dotted line transition on FF1 and later on FF2). When this happens one clock cycle before a STROBE transition is generated (as shown by the left tRFS range marker near the middle of the DMARDY– transition range in the diagram above), the next STROBE transition will occur (as shown in dotted lines). For all other cases, the tRFS time will be shorter. The maximum tRFS is calculated using the following formula:

+ Maximum input falling delay through series termination+ Maximum trace delay+ Maximum total IC input delay to flip-flop+ Minimum setup time for flip-flop + one or two clock cycles at the maximum system clock period due to frequency variation for

synchronization+ Maximum total IC output delay from clock to output pin+ Maximum trace delay on STROBE+ Maximum output delay through series resistor (falling)

A system using a 25 MHz clock can not meet the tRFS minimum time of 60 ns. Only a system using a 50 MHz clock can meet that minimum for mode 2. All systems and devices with clock frequencies other than 50 MHz can not meet this time for the worst case condition. The values for this parameter are 75, 70, and 60 ns for modes 0, 1, and 2 respectively.

The maximum values for this timing are 75, 70, 60, 60, and 60 ns for modes 0, 1, 2, 3, and 4 respectively.

C.5.3.18 tRP (DMARDY– to pause time)

This is the minimum time after DMARDY– is negated after which the recipient will not receive any more STROBE edges (i.e., no additional valid data words). STROBE edges may arrive at the sender until after this time period. Since this time parameter applies to the recipient only (as the recipient waits for STROBES), the parameter is measured at the recipient connector. Because of this, the output delay of DMARDY– from inside the IC to the connector and the input delay of a STROBE edge from the connector to the associated internal IC flip-flop should be considered.

There are two ways to determine the tRP minimum. One method is to consider how long it will take from the negation of DMARDY– at the recipient for the sender to see the negation and become paused. This would



involve synchronizing DMARDY– as it is done for tRFS, and then taking one more system clock cycle to change the state of the state machine to a paused state. Using this method, the minimum time is calculated using the following formula:

+ Maximum IC to IC delay (overestimates the delay by one termination resistor)+ Maximum total IC input delay to flip-flop+ Minimum setup time for flip-flop + two or three clock cycles (depending on clock used) at the maximum period due to clock

frequency variation

A second method to calculate this value is to consider how long it might be for the last STROBE to be detected after negating DMARDY–, and make sure tRP is long enough so that the internal assertion of STOP occurs after the last STROBE has latched the last word of data. This method is applied in the following formula:

+ Maximum IC to IC delay (this overestimates the delay by one termination resistor)+ Maximum tRFS for mode+ Maximum IC to IC delay (this overestimates the delay by one termination resistor)+ Maximum total IC input delay to flip-flop+ Minimum flip-flop setup time

Using both of the above, it can be shown that tRP is met given the tRFS requirement and is sufficient to receive the last STROBE for all modes with all clock frequencies. All of the numbers measured at the connector, and the time to wait internal to the IC should be longer than the value of tRP. For higher frequency clocks, the internal delay may need to be more than one clock cycle longer than the value of tRP in order to account for total output and input delays.


C.5.3.19 tIORDYZ (maximum IORDY release time)

This is the maximum time allowed for the device to release IORDY at the end of a burst.

The maximum value for this timing is 20 ns for modes 0, 1, 2, 3, and 4 respectively.

C.5.3.20 tZIORDY (minimum IORDY assert time)

This is the minimum time allowed for the device to release IORDY at the beginning of a burst.


C.5.3.21 tACK (setup/hold before DMACK– time)

This is the minimum setup and hold time before assertion or negation of DMACK by the host.


C.5.3.22 tSS (STROBE to DMARQ/STOP time)

This is the minimum time after a STROBE edge before a device negates DMARQ or a host asserts STOP.



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