power electronics notes betz

ELEC3250 Notes - Power Electronics1

R.E. BetzSchool of Electrical Engineering and Computer Science

University of Newcastle, Australia.email: [email protected]

c©2012

April, 2012

1First created: July 20, 2005Revised on 2012-04-30 00:27:06 +1000 (Mon, 30 Apr 2012) by R.E. BetzSVN Version: 513

[email protected]

Preface

The notes in this document are for a course in the School of Electrical Engi-neering and Computer Science at the University of Newcastle, Australia. Thiscourse covers a number of topics that can be broadly grouped under the title of“power electronics”.

The first section of the course will look at switch mode power supplies intheir various forms. The main structures for switch mode power supplies will beconsidered. Again practical issues will be emphasised. Design of the magneticsfor switching supplies will be considered, as well as some control issues. Thecontrol issues are only briefly considered due to the lack of background of somestudents doing the course.

The second part of the course considers high powered converter and invertertopologies. There will be an emphasis on the grid connection of converter tech-nologies. An introduction to matrix converters is presented. Issues such ascommutation, modulation strategies, and devices are covered.

There are several appendices covering some useful topics which may be usefulin the context of the remainder of these notes.

It should be noted that these notes are constantly being added to, altered,correctly, clarifications added – in other words they are a work in progress. Thelatest version can be downloaded from anonymous ftp at:ftp://vcs2.newcastle.edu.au/Elec3250_Power_Electronics/elec3250_notes.pdf.

Robert E. Betz – Newcastle, Australia, April, 2012.

ftp://vcs2.newcastle.edu.au/Elec3250_Power_Electronics/elec3250_notes.pdf

ftp://vcs2.newcastle.edu.au/Elec3250_Power_Electronics/elec3250_notes.pdf

Revision History

April-May 2012 (REB) Made corrections and added new material on SpaceVectors.

April-May 2011 (REB) Added new chapter on grid interfacing and renew-ables.

March 11 2011 (REB) Did some minor conversions of the file to allow opera-tion in Subversion. Have also fixed up some minor typos that were foundlast year.

July 30 2010 (REB) Made a few wording error corrections in the first chapter.Minor typos really.

July 29 2010 (REB) Typo corrections from last year were made. Added asmall section on the linear interpretation of switching poles as a DC-DCtransformer.

July 23 2009 (REB) Have added a number of sections. A whole section onmatrix converters added. A new introductory chapter on Switching Basicsadded, several Appendices added – space vectors, Syncrel inductances,imaginary power.

July 25, 2008 (REB) Started adding a section on matrix converters. Stillincomplete.

July 24, 2008 (REB) Have converted the original Latex notes to Lyx. Com-plete compilation achieved.

August 1, 2005 (REB) The initial distribution version for the students. Someadditions have been made for snubbing circuits, but at this stage theseadditions are incomplete. There have also been some changes made to theAppendix on second order circuits.

July 20, 2005 (REB) The initial version of these notes was constructed fromthe notes that were developed for Elec3230. The main difference with thecurrent set of notes is that they no longer include the section on digitalswitching and printed circuit boards. This initial version basically was theElec3230 notes with the digital switching cut out. As the notes developnew sections will be added with respect to high power power electronics.

Contents

List of Figures xv

List of Tables xxiii

Nomenclature xxv

I Switched Mode Power Supplies 1

1 Switching Basics 1-11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11.2 Why Use Switching? . . . . . . . . . . . . . . . . . . . . . . . . . 1-21.3 Taxonomy of Power Electronic Systems . . . . . . . . . . . . . . 1-4

1.3.1 Naturally Commutated Systems . . . . . . . . . . . . . . 1-41.3.2 Forced Commutated Systems . . . . . . . . . . . . . . . . 1-6

1.3.2.1 Linearising the Non-linear System . . . . . . . . 1-81.3.2.2 Basics of PWM and Frequency Spectra . . . . . 1-10

1.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18

2 Fundamental Topologies 2-12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12.2 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12.3 Taxonomy of Switch Mode Converters . . . . . . . . . . . . . . . 2-2

2.3.1 Step-down or Buck Converters . . . . . . . . . . . . . . . 2-22.3.2 Step-up or Boost Converters . . . . . . . . . . . . . . . . 2-42.3.3 Buck–Boost Converters . . . . . . . . . . . . . . . . . . . 2-52.3.4 Cúk Converters . . . . . . . . . . . . . . . . . . . . . . . . 2-72.3.5 Full Bridge Converters . . . . . . . . . . . . . . . . . . . . 2-9

2.4 Basic Analysis of Switch Mode Converters . . . . . . . . . . . . . 2-112.4.1 Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 2-112.4.2 Basic PWM Generator . . . . . . . . . . . . . . . . . . . . 2-112.4.3 Simplified Analysis of the Buck Converter . . . . . . . . . 2-14

2.4.3.1 Continuous Conduction Mode . . . . . . . . . . 2-142.4.3.2 Boundary between Continuous and Discontinu-

ous Conduction . . . . . . . . . . . . . . . . . . 2-162.4.3.2.1 Discontinuous Current with Constant

Vd. . . . . . . . . . . . . . . . . . . . . 2-18

viii CONTENTS

2.4.3.2.2 Discontinuous Current with ConstantVo. . . . . . . . . . . . . . . . . . . . . 2-19

2.4.3.3 Output Ripple . . . . . . . . . . . . . . . . . . . 2-232.4.3.4 Simulation . . . . . . . . . . . . . . . . . . . . . 2-25

2.4.4 Simplified Analysis of the Boost Converter . . . . . . . . 2-282.4.4.1 Continuous Conduction Mode . . . . . . . . . . 2-282.4.4.2 Boundary between Continuous and Discontinu-

ous Conduction . . . . . . . . . . . . . . . . . . 2-282.4.4.2.1 Discontinuous Current with Constant Vd.2-31

2.4.4.3 Simulation . . . . . . . . . . . . . . . . . . . . . 2-332.4.5 A Brief Look at the Buck-Boost Converter . . . . . . . . 2-362.4.6 A Brief Analysis of the Cúk Converter . . . . . . . . . . . 2-362.4.7 Full Bridge dc-dc Converter . . . . . . . . . . . . . . . . . 2-38

2.4.7.1 Bipolar Switching . . . . . . . . . . . . . . . . . 2-392.4.7.2 Unipolar Switching . . . . . . . . . . . . . . . . 2-42

2.4.8 Comparison of Basic Converter Topologies . . . . . . . . . 2-442.4.8.1 Switch Utilisation . . . . . . . . . . . . . . . . . 2-44

2.4.8.1.1 Buck Converter . . . . . . . . . . . . . 2-452.4.8.1.2 Boost Converter . . . . . . . . . . . . . 2-452.4.8.1.3 Buck-Boost Converter . . . . . . . . . . 2-462.4.8.1.4 Full Bridge Converter . . . . . . . . . . 2-47

2.4.9 Synchronous Rectifiers . . . . . . . . . . . . . . . . . . . . 2-492.4.10 Switching Losses and Snubber Circuits . . . . . . . . . . . 2-50

2.4.10.1 Diode Snubbers . . . . . . . . . . . . . . . . . . 2-512.4.10.2 Snubbers for Thyristors . . . . . . . . . . . . . . 2-582.4.10.3 Snubbers and Transistors . . . . . . . . . . . . . 2-58

2.4.11 Resonant and Soft-Switching Converters . . . . . . . . . . 2-652.4.11.1 Why One Should Not Use Resonant Converters 2-672.4.11.2 Why One Should Use Quasi-Resonant Converters 2-67

2.4.12 Example: ZVS Converter Design and Analysis . . . . . . 2-68

3 Switch Mode Power Supplies 3-13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13.2 Isolated Converter Topologies . . . . . . . . . . . . . . . . . . . . 3-1

3.2.1 The Forward Converter . . . . . . . . . . . . . . . . . . . 3-13.2.1.1 Other Forward Converter Topologies . . . . . . . 3-7

3.2.1.1.1 Two Switch Converter . . . . . . . . . . 3-73.2.1.1.2 Push-Pull Converter . . . . . . . . . . . 3-7

3.2.2 The Flyback Converter . . . . . . . . . . . . . . . . . . . 3-123.2.3 Utilisation of Magnetics . . . . . . . . . . . . . . . . . . . 3-18

3.3 Introduction to Control Techniques for Switching Power Supplies 3-223.3.1 Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-253.3.2 Protection Issues . . . . . . . . . . . . . . . . . . . . . . . 3-27

3.3.2.1 Soft Start . . . . . . . . . . . . . . . . . . . . . . 3-273.3.2.2 Voltage Protection . . . . . . . . . . . . . . . . . 3-283.3.2.3 Current Limiting . . . . . . . . . . . . . . . . . . 3-28

3.3.3 Control Architecture of a Switch Mode Power Supply Sys-tem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-303.3.3.1 Voltage Mode Control . . . . . . . . . . . . . . . 3-303.3.3.2 Voltage Feed-forward PWM Control . . . . . . . 3-33

CONTENTS ix

3.3.3.3 Current Mode Control . . . . . . . . . . . . . . . 3-333.3.3.3.1 Slope Compensation . . . . . . . . . . . 3-37

4 Introduction to Practical Design of Switch Mode Power Sup-plies 4-14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14.2 Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2.1 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24.2.1.1 Values . . . . . . . . . . . . . . . . . . . . . . . . 4-24.2.1.2 Resistor Types . . . . . . . . . . . . . . . . . . . 4-24.2.1.3 Tolerance . . . . . . . . . . . . . . . . . . . . . . 4-34.2.1.4 Selecting Values . . . . . . . . . . . . . . . . . . 4-34.2.1.5 Maximum Voltage . . . . . . . . . . . . . . . . . 4-34.2.1.6 Temperature Coefficient . . . . . . . . . . . . . . 4-44.2.1.7 Power Rating . . . . . . . . . . . . . . . . . . . . 4-44.2.1.8 Shunts . . . . . . . . . . . . . . . . . . . . . . . 4-54.2.1.9 PCB Track Resistors . . . . . . . . . . . . . . . 4-6

4.2.2 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64.2.2.1 Types of Capacitors . . . . . . . . . . . . . . . . 4-74.2.2.2 Standard Values . . . . . . . . . . . . . . . . . . 4-74.2.2.3 Tolerance . . . . . . . . . . . . . . . . . . . . . . 4-84.2.2.4 ESR and Power Dissipation . . . . . . . . . . . . 4-84.2.2.5 Aging . . . . . . . . . . . . . . . . . . . . . . . . 4-84.2.2.6 dv/dt Rating . . . . . . . . . . . . . . . . . . . . 4-94.2.2.7 Series Connection of Capacitors . . . . . . . . . 4-9

4.2.3 Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94.2.3.1 Schottky Diodes . . . . . . . . . . . . . . . . . . 4-94.2.3.2 PN diodes . . . . . . . . . . . . . . . . . . . . . 4-10

4.2.4 The BJT . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-124.2.5 The MOSFET . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.2.5.1 Bi-directional Conduction . . . . . . . . . . . . . 4-134.2.5.2 Power Losses . . . . . . . . . . . . . . . . . . . . 4-134.2.5.3 MOSFET Gate Resistors . . . . . . . . . . . . . 4-144.2.5.4 Maximum Gate Voltage . . . . . . . . . . . . . . 4-14

4.2.6 Operational Amplifiers . . . . . . . . . . . . . . . . . . . . 4-144.2.6.1 Offsets . . . . . . . . . . . . . . . . . . . . . . . 4-15

4.2.6.1.1 Input Offset Voltage . . . . . . . . . . . 4-154.2.6.1.2 Input Offset Current . . . . . . . . . . . 4-164.2.6.1.3 Input Bias Current . . . . . . . . . . . 4-16

4.2.6.2 Limits on Resistor Values . . . . . . . . . . . . . 4-174.2.6.3 Gain-Bandwidth Product . . . . . . . . . . . . . 4-194.2.6.4 Phase Shift . . . . . . . . . . . . . . . . . . . . . 4-204.2.6.5 Slew Rate Limits . . . . . . . . . . . . . . . . . . 4-20

4.2.7 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . 4-204.2.7.1 Hysteresis . . . . . . . . . . . . . . . . . . . . . . 4-214.2.7.2 Comparator Interfacing . . . . . . . . . . . . . . 4-22

4.3 Introduction to Magnetics Design . . . . . . . . . . . . . . . . . . 4-224.3.1 Review of the Fundamentals . . . . . . . . . . . . . . . . 4-23

4.3.1.1 Ampere’s Law . . . . . . . . . . . . . . . . . . . 4-234.3.1.2 Faraday’s Law . . . . . . . . . . . . . . . . . . . 4-24

x CONTENTS

4.3.1.3 Inductance . . . . . . . . . . . . . . . . . . . . . 4-244.3.1.4 A Note on Units . . . . . . . . . . . . . . . . . . 4-264.3.1.5 The Three R’s . . . . . . . . . . . . . . . . . . . 4-26

4.3.1.5.1 Reactance . . . . . . . . . . . . . . . . 4-264.3.1.5.2 Remanence . . . . . . . . . . . . . . . . 4-264.3.1.5.3 Reluctance . . . . . . . . . . . . . . . . 4-27

4.3.2 The Ideal Transformer . . . . . . . . . . . . . . . . . . . . 4-274.3.3 Real Transformers . . . . . . . . . . . . . . . . . . . . . . 4-29

4.3.3.1 Core Materials . . . . . . . . . . . . . . . . . . . 4-304.3.3.2 Saturation . . . . . . . . . . . . . . . . . . . . . 4-324.3.3.3 Other Core Limitations . . . . . . . . . . . . . . 4-32

4.3.3.3.1 Curie Temperature . . . . . . . . . . . 4-324.3.3.3.2 Core Losses . . . . . . . . . . . . . . . . 4-32

4.3.4 Optimal Design Issues . . . . . . . . . . . . . . . . . . . . 4-334.3.5 Design of an Inductor . . . . . . . . . . . . . . . . . . . . 4-35

4.3.5.1 Key Magnetic Parameters . . . . . . . . . . . . . 4-384.3.5.1.1 Initial Permeability . . . . . . . . . . . 4-384.3.5.1.2 Effective Permeability . . . . . . . . . . 4-384.3.5.1.3 Amplitude Permeability . . . . . . . . . 4-384.3.5.1.4 Incremental Permeability . . . . . . . . 4-384.3.5.1.5 Effective Core Dimensions . . . . . . . 4-394.3.5.1.6 Inductance Factor . . . . . . . . . . . . 4-39

4.3.5.2 Details of Inductor Design . . . . . . . . . . . . 4-404.3.5.3 Issues in Forward Converter Transformer Design 4-46

4.3.5.3.1 Turns Ratio = 1:1 . . . . . . . . . . . . 4-474.3.5.3.2 Turns Ratio = 2:1 . . . . . . . . . . . . 4-474.3.5.3.3 Turns Ratio = 3:1 . . . . . . . . . . . . 4-474.3.5.3.4 Turns Ratio = 4:1 . . . . . . . . . . . . 4-47

4.3.6 Design of Manufacturable Magnetics . . . . . . . . . . . . 4-484.3.6.1 Wire Gauge . . . . . . . . . . . . . . . . . . . . 4-484.3.6.2 Wire Gauge Ratio . . . . . . . . . . . . . . . . . 4-484.3.6.3 Toroidal Core Winding Limits . . . . . . . . . . 4-484.3.6.4 Tape versus Wire Insulation . . . . . . . . . . . 4-494.3.6.5 Layering of Windings . . . . . . . . . . . . . . . 4-494.3.6.6 Number of Windings . . . . . . . . . . . . . . . 4-504.3.6.7 Potting . . . . . . . . . . . . . . . . . . . . . . . 4-504.3.6.8 Safety Requirements . . . . . . . . . . . . . . . . 4-50

II Line Commutated Converters and High Power In-verters 4-53

5 Introduction to High Power Converter Technology 5-15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1.1 Applications of Power Converter Technology . . . . . . . 5-15.2 Review of Power Semiconductor Devices . . . . . . . . . . . . . . 5-3

5.2.1 Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35.2.1.1 Series Diodes . . . . . . . . . . . . . . . . . . . . 5-8

5.2.2 Thyristors . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-85.2.2.1 Turn-on Transient . . . . . . . . . . . . . . . . . 5-11

CONTENTS xi

5.2.2.2 Turn-off Transient . . . . . . . . . . . . . . . . . 5-135.2.3 Gate Turn-off Thyristors . . . . . . . . . . . . . . . . . . . 5-13

5.2.3.1 Snubbers and GTO Thyristors . . . . . . . . . . 5-155.2.3.2 GTO Turn-on . . . . . . . . . . . . . . . . . . . 5-175.2.3.3 GTO Turn-off . . . . . . . . . . . . . . . . . . . 5-17

5.2.4 Insulated Gate Bipolar Transistors (IGBTs) . . . . . . . . 5-215.2.4.1 IGBT Operation . . . . . . . . . . . . . . . . . . 5-225.2.4.2 IGBT Turn-on . . . . . . . . . . . . . . . . . . . 5-245.2.4.3 IGBT Turn-off . . . . . . . . . . . . . . . . . . . 5-25

5.2.5 Other Devices and Developments . . . . . . . . . . . . . . 5-265.2.5.1 Power Junction Field Effect Transistors . . . . . 5-265.2.5.2 Field Controlled Thyristor . . . . . . . . . . . . 5-265.2.5.3 MOS-Controlled Thyristors . . . . . . . . . . . . 5-265.2.5.4 New Semiconductor Materials . . . . . . . . . . 5-27

6 Line Frequency Uncontrolled Rectifiers 6-16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16.2 Some Mathematical Preliminaries . . . . . . . . . . . . . . . . . . 6-1

6.2.1 Fourier Analysis of Repetitive Waveforms . . . . . . . . . 6-26.2.1.1 Measures of Waveform Distortion . . . . . . . . 6-36.2.1.2 Power and Power Factor . . . . . . . . . . . . . 6-5

6.3 The Half Wave Rectifier Circuit . . . . . . . . . . . . . . . . . . . 6-116.3.1 Pure Resistive Load . . . . . . . . . . . . . . . . . . . . . 6-116.3.2 Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . 6-116.3.3 Inductive Load with Back EMF . . . . . . . . . . . . . . . 6-13

6.4 The Concept of Current Commutation . . . . . . . . . . . . . . . 6-156.5 Practical Uncontrolled Single Phase Rectifiers . . . . . . . . . . . 6-19

6.5.1 Unity Power Factor Single Phase Rectifier . . . . . . . . . 6-256.5.2 Effect of Current Harmonics on Line Voltages . . . . . . . 6-306.5.3 Voltage Doubler Single Phase Rectifiers . . . . . . . . . . 6-316.5.4 The Effect of Single Phase Rectifiers on Three Phase, Four

Wire Systems . . . . . . . . . . . . . . . . . . . . . . . . . 6-326.6 Three Phase, Full Bridge Rectifiers . . . . . . . . . . . . . . . . . 6-34

7 Introduction to Other Power Electronic Devices and Applica-tions 7-17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17.2 Inverters and Applications . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2.1 Pulse Width Modulation . . . . . . . . . . . . . . . . . . . 7-47.2.1.1 Space Vectors and PWM . . . . . . . . . . . . . 7-8

7.2.2 Dead-time Issues . . . . . . . . . . . . . . . . . . . . . . . 7-147.2.3 Some Inverter Applications . . . . . . . . . . . . . . . . . 7-15

7.2.3.1 Variable Speed Drives . . . . . . . . . . . . . . . 7-157.2.3.2 Grid Connected Applications . . . . . . . . . . . 7-17

7.3 Multilevel Converters and Applications . . . . . . . . . . . . . . 7-207.4 Basic Introduction to Matrix Converters . . . . . . . . . . . . . 7-20

7.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 7-207.4.2 Switching Rules . . . . . . . . . . . . . . . . . . . . . . . . 7-217.4.3 Switching – Some More Detail . . . . . . . . . . . . . . . 7-22

7.4.3.1 Alesina/Venturini Modulation Algorithm . . . . 7-22

xii CONTENTS

7.4.3.2 Space Vector Modulation Techniques . . . . . . 7-287.4.4 Implementation Issues . . . . . . . . . . . . . . . . . . . . 7-37

7.4.4.1 Bidirectional Switches . . . . . . . . . . . . . . . 7-377.4.4.2 Current Commutation . . . . . . . . . . . . . . . 7-407.4.4.3 Input Filters . . . . . . . . . . . . . . . . . . . . 7-447.4.4.4 Over-voltage Protection . . . . . . . . . . . . . . 7-44

7.4.5 Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46

8 Grid Connected Converters and Renewable Energy Systems 8-18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1.1 Wind Power . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28.1.2 Photovoltaics . . . . . . . . . . . . . . . . . . . . . . . . . 8-28.1.3 Outline and Scope of this Chapter . . . . . . . . . . . . . 8-2

8.2 Photovoltaic Inverters . . . . . . . . . . . . . . . . . . . . . . . . 8-38.2.1 Review of Power Electronic Configurations for Grid Con-

nected Converters . . . . . . . . . . . . . . . . . . . . . . 8-38.2.1.1 How do photovoltaic devices work? . . . . . . . 8-58.2.1.2 Equivalent Circuit of a Solar Cell . . . . . . . . 8-88.2.1.3 Traditional PV Inverter Topologies . . . . . . . 8-14

8.2.2 New PV Inverter Topologies . . . . . . . . . . . . . . . . . 8-268.2.2.1 H5 Inverter (SMA) . . . . . . . . . . . . . . . . 8-268.2.2.2 HEIRC Inverter (Sunways) . . . . . . . . . . . . 8-328.2.2.3 Full Bridge with DC Bypass (Ingeteam) . . . . . 8-338.2.2.4 Neutral Point Clamped (NPC) Half-Bridge In-

verter . . . . . . . . . . . . . . . . . . . . . . . . 8-358.2.2.5 Some Other Topologies and Issues . . . . . . . . 8-37

8.2.3 Grid Requirements for PV Systems . . . . . . . . . . . . . 8-418.2.3.1 Discussion of the International Standards . . . . 8-428.2.3.2 Anti-islanding Standards . . . . . . . . . . . . . 8-498.2.3.3 Australian Standards . . . . . . . . . . . . . . . 8-51

8.2.4 Grid Synchronization and Related Control for PV Systems 8-538.2.4.1 Brief review of PLLs . . . . . . . . . . . . . . . . 8-548.2.4.2 Brief Review of Synchronisation Techniques for

Power Systems . . . . . . . . . . . . . . . . . . . 8-608.2.5 Islanding Detection Techniques . . . . . . . . . . . . . . . 8-73

8.3 Wind Turbine Converter Systems . . . . . . . . . . . . . . . . . . 8-738.3.1 Grid Requirements for Wind Turbine Systems . . . . . . . 8-738.3.2 Grid Synchronization for Three Phase Systems . . . . . . 8-738.3.3 Brief Overview of Wind Turbine Converter Control . . . . 8-76

III Appendices 8-77

A Review of Second Order Circuits A-1A.1 Series RLC Circuits . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.1.1 Quality Factor . . . . . . . . . . . . . . . . . . . . . . . . A-4A.1.2 Time Domain Response . . . . . . . . . . . . . . . . . . . A-5

A.1.2.1 Forced Response of Series RLC Circuit with Ini-tial Inductor Current . . . . . . . . . . . . . . . A-7

A.2 Parallel RLC Circuits . . . . . . . . . . . . . . . . . . . . . . . . A-8

CONTENTS xiii

A.2.1 Quality Factor . . . . . . . . . . . . . . . . . . . . . . . . A-10

B Introduction to Space Vectors B-1B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1B.2 The Sinusoidal Assumption . . . . . . . . . . . . . . . . . . . . . B-1

B.2.1 Winding Interaction with Spatial Flux Density DistributionB-2B.2.2 Winding Interaction with Temporal Flux Density VariationB-6

B.3 dq Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8B.3.1 Stationary Frame Transformations . . . . . . . . . . . . . B-9

B.3.1.1 MMF transformations . . . . . . . . . . . . . . . B-9B.3.1.2 Current Transformations . . . . . . . . . . . . . B-11B.3.1.3 Voltage Transformations . . . . . . . . . . . . . B-12B.3.1.4 Impedance Transformations . . . . . . . . . . . . B-13B.3.1.5 Flux Linkage Transformations . . . . . . . . . . B-14

B.3.2 Rotating Frame Transformations . . . . . . . . . . . . . . B-14B.3.3 Example – SYNCREL Linear dq Model . . . . . . . . . . B-17

B.4 Space Vector Model . . . . . . . . . . . . . . . . . . . . . . . . . B-21B.4.1 Current Space Vectors . . . . . . . . . . . . . . . . . . . . B-22

B.4.1.1 Stationary Frame Current Vectors . . . . . . . . B-22B.4.1.2 Rotating Frame Current Vectors . . . . . . . . . B-24

B.4.2 Flux Linkage Space Vector . . . . . . . . . . . . . . . . . B-25B.4.3 Voltage Space Vector . . . . . . . . . . . . . . . . . . . . . B-27B.4.4 Example – SYNCREL Space Vector Model . . . . . . . . B-27B.4.5 Space Vector Power Expression . . . . . . . . . . . . . . . B-28B.4.6 Space Vector Expression for SYNCREL Torque . . . . . . B-29B.4.7 Relationship Between Space Vectors and dq Models . . . B-32

C Calculation of Inductances for a Synchronous Reluctance Ma-chine C-1C.1 Calculation of Inductances . . . . . . . . . . . . . . . . . . . . . . C-1

C.1.1 Self Inductances . . . . . . . . . . . . . . . . . . . . . . . C-3C.1.2 Mutual Inductances . . . . . . . . . . . . . . . . . . . . . C-11C.1.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . C-14

D Introduction to Instantaneous Imaginary Power D-1D.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1

D.1.1 Single Phase Reactive Power . . . . . . . . . . . . . . . . D-1D.1.2 Three Phase Instantaneous Imaginary Power . . . . . . . D-3

E Introductory Exercise using Saber Simulator E-1E.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1E.2 Circuit Schematic Capture . . . . . . . . . . . . . . . . . . . . . . E-2E.3 Executing the Transient Analysis . . . . . . . . . . . . . . . . . . E-6E.4 Plotting and Processing Results . . . . . . . . . . . . . . . . . . . E-7

E.4.1 Manipulating Results . . . . . . . . . . . . . . . . . . . . E-9E.4.2 Fourier Analysis . . . . . . . . . . . . . . . . . . . . . . . E-11

E.5 A Practice Exercise . . . . . . . . . . . . . . . . . . . . . . . . . . E-13

xiv CONTENTS

F PV Related Information F-1F.1 SunnyBoy Transformerless PV Inverter . . . . . . . . . . . . . . . F-2F.2 Tianwei PV Array Datasheet . . . . . . . . . . . . . . . . . . . . F-4F.3 Australian Standards for PV Inverter Connections . . . . . . . . F-6

F.3.1 AS4777.2-2005: Grid connection of energy systems viainverters Part 2: Inverter Requirements . . . . . . . . . . F-6

F.3.2 AS4777.3-2005 Grid connection of energy systems via in-verters Part 3: Grid protection requirements . . . . . . . F-17

G Python Listing for Two Phase PLL G-1

Bibliography G-21

List of Figures

1.1 Conceptual diagram of a traditional linear DC linear power supply. 1-31.2 Simple half wave rectifier circuit with LR load. . . . . . . . . . . 1-41.3 Plots for a half wave rectifier with an LR load – L = 200mH and

R = 50Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51.4 Forced commutated switching pole. . . . . . . . . . . . . . . . . . 1-71.5 Output of the switching pole. . . . . . . . . . . . . . . . . . . . . 1-71.6 Example buck converter with waveforms. . . . . . . . . . . . . . 1-91.7 Conceptual diagram of a H-bridge. . . . . . . . . . . . . . . . . . 1-101.8 Conceptual diagram showing how to generate double edge natu-

rally sampled PWM. . . . . . . . . . . . . . . . . . . . . . . . . 1-121.9 Close-up of naturally sampled PWM process. . . . . . . . . . . . 1-131.10 Equivalence between a switching pole and a variable turns ratio

DC-DC transformer. . . . . . . . . . . . . . . . . . . . . . . . . . 1-141.11 Saberr circuit used to simulate double edged naturally sampled

PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-151.12 Saberr simulation output for double edged naturally sampled

PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-161.13 Component waveforms for double edged naturally sampled PWM. 1-171.14 Spectrum when the triangular modulation waveforms are 180

out of phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

2.1 Block diagram of the structure of a typical DC-DC converter. . . 2-22.2 A basic buck or step-down converter. . . . . . . . . . . . . . . . . 2-42.3 A basic boost or step-up converter. . . . . . . . . . . . . . . . . . 2-52.4 Two switch buck–boost converter. . . . . . . . . . . . . . . . . . . 2-62.5 Single switch Buck–boost converter circuit. . . . . . . . . . . . . 2-72.6 The Cúk converter. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82.7 Cúk converter with the switch open. . . . . . . . . . . . . . . . . 2-82.8 Cúk converter with the switch closed. . . . . . . . . . . . . . . . 2-92.9 Full bridge converter. . . . . . . . . . . . . . . . . . . . . . . . . . 2-102.10 Definition of the terms related to duty cycle. . . . . . . . . . . . 2-122.11 Waveforms in a sawtooth based PWM modulator. . . . . . . . . 2-132.12 Simple PWM generator circuit. . . . . . . . . . . . . . . . . . . . 2-142.13 Currents and circuit configurations for a buck converter. . . . . . 2-152.14 Current waveform at the point of discontinuous current in the

inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-172.15 Current waveform for a buck converter with discontinuous current.2-18

xvi LIST OF FIGURES

2.16 Voltage ratio of the buck converter for continuous and discontin-uous operation modes and constant Vd. NB. ILBmax

= TsVd8L . . . 2-20

2.17 Characteristics of the buck converter with constant Vo. NB.ILBmax = TsVo

2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-222.18 Output voltage ripple for a buck converter. . . . . . . . . . . . . 2-242.19 Circuit used in simulation of the buck converter. . . . . . . . . . 2-262.20 Waveforms for a buck converter with D = 0.5, RL = 100, and

continuous inductor current. . . . . . . . . . . . . . . . . . . . . . 2-272.21 Initial startup waveforms for a buck converter with D = 0.5,

RL = 40kΩ, and discontinuous inductor current. . . . . . . . . . 2-272.22 Currents and circuit configurations for a boost converter. . . . . 2-292.23 Voltage ratio of a boost converter versus duty cycle. . . . . . . . 2-292.24 Current waveform on the edge of continuous current. . . . . . . . 2-302.25 Plot of the normalised continuous current boundary for the boost

converter (Vo constant). . . . . . . . . . . . . . . . . . . . . . . . 2-312.26 Current waveforms for the boost converter with discontinuous

current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-322.27 Duty cycle versus normalised output current for the boost con-

verter with constant Vo. . . . . . . . . . . . . . . . . . . . . . . . 2-342.28 Boost converter simulated using Saberr. . . . . . . . . . . . . . . 2-352.29 Simulated waveforms for a boost converter with D = 0.5 and

continuous current. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-352.30 Output of a boost converter in continuous current mode with

several different duty cycles. . . . . . . . . . . . . . . . . . . . . . 2-362.31 Steady state currents and voltages in a Cúk converter. . . . . . . 2-372.32 Waveforms for a full bridge converter with a bipolar switching

strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-412.33 Waveforms for a full bridge converter with a unipolar switching

strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-432.34 The input current into a buck-boost converter with a large input

inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-472.35 Plot of switch utilisation for the common converter types. . . . . 2-482.36 (a) Conventional non-synchronous rectifier based boost converter.

(b) Synchronous rectifier based boost converter. . . . . . . . . . . 2-502.37 (a) Step-down converter circuit with a RC snubber; (b) The diode

reverse recovery current [2]. . . . . . . . . . . . . . . . . . . . . . 2-522.38 Equivalent circuit of the snubber used to protect diodes. (a) Full

equivalent circuit; (b) simplified circuit with Rs = 0. . . . . . . . 2-542.39 Waveforms for the simplified (Rs = 0) snubber circuit. . . . . . . 2-552.40 Plot of the normalised capacitor voltage versus Cbase/Cs. . . . . 2-562.41 Turn-off snubber circuit for a transistor step-down converter. . . 2-592.42 Stray inductances that are important in a transistor switching

circuit during turn-on [2]. . . . . . . . . . . . . . . . . . . . . . . 2-602.43 Current and voltage trajectories during turn-on and turn-off for

a step-down transistor converter. . . . . . . . . . . . . . . . . . . 2-612.44 Equivalent circuit for the turn-off RCD snubber and approximate

waveforms for different values of capacitance [2]. . . . . . . . . . 2-622.45 Switching trajectories for different turn-off capacitor values. . . . 2-632.46 Typical turn-on snubber for a transistor step-down converter. . . 2-632.47 Over-voltage snubber for a transistor step-down converter. . . . . 2-64

LIST OF FIGURES xvii

2.48 Undeland snubber for a step-down converter circuit. . . . . . . . 2-652.49 A zero current switching (ZCS) resonant buck converter. . . . . . 2-662.50 A zero voltage switching (ZVS) resonant buck converter. . . . . . 2-672.51 A quasi-resonant forward converter. . . . . . . . . . . . . . . . . 2-682.52 Zero Voltage Switching quasi resonant buck converter for example.2-692.53 Waveforms in the ZVS circuit (scanned from [2]) . . . . . . . . . 2-702.54 Voltage across the freewheeling diode in the ZVS circuit. . . . . . 2-722.55 Final design of the resonant buck ZVS circuit. . . . . . . . . . . . 2-772.56 ZVS circuit without output filter but with an ideal current source

load at 6 Amps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-782.57 ZVS circuit with output filter and ideal current source load at 6

Amps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-792.58 Saber circuit used for the 6 Amp full simulation. . . . . . . . . . 2-802.59 ZVS circuit with output filter and resistive load at 6 Amps. . . . 2-802.60 ZVS circuit with filter circuit and resistive load, output current

20 Amp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81

3.1 Basic circuit of the forward converter. . . . . . . . . . . . . . . . 3-23.2 A practical forward converter. . . . . . . . . . . . . . . . . . . . . 3-33.3 Equivalent circuit for a practical forward converter. . . . . . . . . 3-33.4 Current waveforms for a practical forward converter. . . . . . . . 3-53.5 Circuit diagram of a two switch forward converter. . . . . . . . . 3-73.6 Push-pull forward converter. . . . . . . . . . . . . . . . . . . . . . 3-83.7 Currents flowing in the push-pull forward converter with SW1

closed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93.8 Currents flowing in the push-pull forward converter with SW1

and SW2 open. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103.9 Flux imbalance in the push-pull circuit. . . . . . . . . . . . . . . 3-123.10 Connection between the Buck-Boost and Flyback converter. . . . 3-133.11 Flyback converter with the switch closed. . . . . . . . . . . . . . 3-143.12 Flyback converter with the switch open. . . . . . . . . . . . . . . 3-153.13 The voltage, current and flux in the ideal Flyback Converter. . . 3-163.14 Typical BH loop for a magnetic material. . . . . . . . . . . . . . 3-183.15 Core excitation waveforms. (a) forward converter. (b) full bridge

converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-193.16 Block diagram of a typical switch mode power supply. . . . . . . 3-233.17 Feedback circuit using a small forward converter. . . . . . . . . . 3-243.18 Example of a simple bootstrap power circuit for a PWM genera-

tor chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-263.19 Bootstrap circuitry modified for increased hysteresis range. . . . 3-273.20 Block diagram of the Unitroder high speed PWM generator. . . 3-283.21 Operation of a constant current limit. . . . . . . . . . . . . . . . 3-293.22 Operation of a fold-back current limit. . . . . . . . . . . . . . . . 3-303.23 Conceptual diagram of a control system for a switch mode power

supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-313.24 Linearised model of a switch mode power supply. . . . . . . . . . 3-323.25 Block diagram of a nested loop control system for a switch mode

power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-323.26 Waveforms for tolerance band current control. . . . . . . . . . . . 3-343.27 Waveforms for constant “off” time control. . . . . . . . . . . . . . 3-35

xviii LIST OF FIGURES

3.28 Waveforms for constant frequency with turn-on at clock time con-trol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36

3.29 Open loop instability of current mode control. (a) stability withduty cycle < 0.5; (b) instability with duty cycle > 0.5; (c) stabil-ity with duty cycle > 0.5 and slope compensation. . . . . . . . . 3-38

3.30 Geometrical relationship of the current waveform slopes whenthere is a current perturbation. . . . . . . . . . . . . . . . . . . . 3-39

3.31 Inductor current response of current mode converter. . . . . . . . 3-403.32 Optimal slope compensation to eliminate RLC type oscillations. . 3-40

4.1 Equivalent circuit model of a current shunt . . . . . . . . . . . . 4-54.2 Method of voltage sharing for series capacitors. . . . . . . . . . . 4-104.3 Reverse recovery in a converter secondary circuit. . . . . . . . . . 4-104.4 Reverse recovery in a boost converter circuit. . . . . . . . . . . . 4-114.5 Operational amplifier circuit for discussion of offsets. . . . . . . . 4-154.6 Conventional inverting Op Amp circuit with a gain of 1000. . . . 4-174.7 Inverting Op Amp circuit with alternative feedback network. . . 4-184.8 Gain-bandwidth product of an Op Amp. . . . . . . . . . . . . . . 4-194.9 Comparator with hysteresis. . . . . . . . . . . . . . . . . . . . . . 4-214.10 Interfacing a comparator to an NPN transistor. . . . . . . . . . . 4-224.11 A loop of wire enclosing an area of time varying flux density. . . 4-244.12 A BH loop for a magnetic material. . . . . . . . . . . . . . . . . 4-264.13 Circuit symbol for a transformer. . . . . . . . . . . . . . . . . . . 4-284.14 Simplified model of a real transformer. . . . . . . . . . . . . . . . 4-304.15 Ferrite choice (from [9]). . . . . . . . . . . . . . . . . . . . . . . . 4-364.16 Initial permeability with respect to frequency for 2P iron powder

Ferroxcube material (from [8]). . . . . . . . . . . . . . . . . . . . 4-364.17 Incremental permeability as a function of magnetic field strength

for 2P iron powder Ferroxcube material (from [8]). . . . . . . . . 4-374.18 Core type selection table (from [8]). . . . . . . . . . . . . . . . . 4-404.19 Core data for toroidal cores using powdered iron (from [8]). . . . 4-424.20 Typical BH characteristic for 2P magnetic material (from [8]). . 4-444.21 Losses in 2P material with respect to flux density and frequency

(from [8]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-444.22 Winding interleaving for high-dielectric isolation and good pri-

mary to secondary coupling. . . . . . . . . . . . . . . . . . . . . . 4-504.23 A transformer design to satisfy safety requirements. . . . . . . . 4-51

5.1 The current-voltage characteristic of a diode. . . . . . . . . . . . 5-45.2 Conceptual structure of a conventional diode. . . . . . . . . . . . 5-55.3 Conceptual structure of a power diode. . . . . . . . . . . . . . . . 5-55.4 Typical reverse recovery characteristic for a diode. . . . . . . . . 5-75.5 Series connection of diodes to support higher voltage. . . . . . . 5-85.6 Conceptual diagram of a thyristor. . . . . . . . . . . . . . . . . . 5-95.7 Transistor model of the thyristor. . . . . . . . . . . . . . . . . . . 5-105.8 Typical characteristic of a thyristor. . . . . . . . . . . . . . . . . 5-115.9 Typical turn-on waveforms for a thyristor. . . . . . . . . . . . . . 5-125.10 Typical thyristor turn-off waveforms. . . . . . . . . . . . . . . . . 5-145.11 An example of a dc chopper circuit using a GTO thyristor . . . . 5-165.12 Turn on waveforms for a GTO thyristor. . . . . . . . . . . . . . . 5-18

LIST OF FIGURES xix

5.13 Turn-off waveforms for a GTO thyristor. . . . . . . . . . . . . . . 5-195.14 GTO thyristor circuit with additional “crowbar” SCR . . . . . . 5-215.15 A schematic diagram of the basic structure of the IGBT. . . . . . 5-225.16 The IGBT voltage and current transfer characteristics and circuit

symbol: (a) output characteristic; (b) transfer characteristic; (c)and (d) n-channel IGBT circuit symbols. . . . . . . . . . . . . . . 5-23

5.17 Current flows in the IGBT. . . . . . . . . . . . . . . . . . . . . . 5-285.18 Equivalent circuits for the IGBT: (a) approximate equivalent cir-

cuit for normal operating conditions; (b) more complete equiva-lent circuit showing the parasitic thyristor. . . . . . . . . . . . . . 5-29

5.19 Typical turn-on waveforms for an IGBT. . . . . . . . . . . . . . . 5-305.20 Turn-off waveforms for an IGBT. . . . . . . . . . . . . . . . . . . 5-315.21 Schematic and circuit symbol for the P-MCT. . . . . . . . . . . . 5-31

6.1 Line current waveform distortion. . . . . . . . . . . . . . . . . . . 6-36.2 Phasor relationship for complex power. . . . . . . . . . . . . . . . 6-66.3 Diagram of the normalised single phase power components with a

30 phase angle – the power is normalised by dividing by VrmsIrms. 6-76.4 Half wave rectifier with a resistive load. . . . . . . . . . . . . . . 6-116.5 Half wave rectifier with an LR load. . . . . . . . . . . . . . . . . 6-126.6 Plots for a half wave rectifier with an LR load – L = 200mH and

R = 50Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-136.7 Half wave rectifier circuit with an inductor and back emf. . . . . 6-146.8 Plots for a half wave rectifier with an inductor and back emf as

a load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-146.9 Test circuit used for current commutation discussion. . . . . . . . 6-156.10 Circuit configurations during current commutation of the circuit

in Figure 6.9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-166.11 Plots of the currents in the test circuit of Figure 6.9 – vs =

50 sinωt, Ls = 5mH, Id = 1 Amp. . . . . . . . . . . . . . . . . . . 6-186.12 A practical single phase rectifier. . . . . . . . . . . . . . . . . . . 6-196.13 Equivalent circuit of the single phase rectifier when the diodes

are conducting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-206.14 Waveforms for the practical single phase rectifier circuit of Fig-

ure 6.12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-216.15 Input current and output voltage harmonics in a single phase

rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-226.16 Real and imaginary components of the harmonic phasors for the

harmonics single phase rectifier harmonics plotted in Figure 6.14. 6-236.17 Single phase rectifier with input and dc link filters. . . . . . . . . 6-266.18 Circuit for the a single phase rectifier with current wave shaping

boost converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-276.19 Waveforms for a single phase rectifier with active current wave-

shaping – (a) the input current and voltage; (b) the boost con-verter input voltage and inductor current. . . . . . . . . . . . . . 6-28

6.20 Block diagram of the control system for a single phase rectifierwith active current wave-shaping. . . . . . . . . . . . . . . . . . . 6-30

6.21 Single phase rectifier showing the point of common coupling. . . 6-316.22 Single phase rectifier voltage doubler. . . . . . . . . . . . . . . . . 6-32

xx LIST OF FIGURES

6.23 Single phase rectifiers loads in a three phase, four wire distribu-tion system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33

6.24 Basic three phase, six pulse, full wave rectifier circuit. . . . . . . 6-356.25 Waveforms of a three phase rectifier with a constant current

source load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36

7.1 Definition of rectifier and inverter modes of operation [2]. . . . . 7-27.2 Generic power processing block [2]. . . . . . . . . . . . . . . . . . 7-27.3 Block diagram of a generic AC drive system. . . . . . . . . . . . 7-37.4 Specific implementation of an inverter. . . . . . . . . . . . . . . . 7-47.5 Single leg of inverter and the PWM waveforms. . . . . . . . . . . 7-57.6 Switch positions and the resultant voltage space vectors. . . . . . 7-97.7 Switching waveforms for double edge pulse width modulation. . . 7-97.8 Switching time determination. . . . . . . . . . . . . . . . . . . . . 7-117.9 Voltage limit hexagon. . . . . . . . . . . . . . . . . . . . . . . . . 7-137.10 Inverter showing the initial and final current flow after a leg is

fired. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-157.11 Example of dead-time induced switching error in an inverter. . . 7-167.12 Generic non-battery based photo-voltaic supply system. . . . . . 7-187.13 Some grid connected FACTS units offered by Siemens. . . . . . . 7-197.14 Conceptual diagram of a matrix converter. . . . . . . . . . . . . . 7-207.15 Reconfigured conceptual diagram of the matrix converter. . . . . 7-217.16 General form of switching pattern [16]. . . . . . . . . . . . . . . . 7-247.17 (a) Direction of the output line-to-neutral voltage vectors for the

active switch configurations. (b) Directions of the input line cur-rent vectors generated by the active switch configurations. . . . . 7-31

7.18 Derivation of the voltage components for a desired voltage spacevector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33

7.19 Double sided switching sequences for a matrix converter over onecontrol cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38

7.20 Diode bridge bidirectional switch cell. . . . . . . . . . . . . . . . 7-387.21 Common emitter and common collector back-to-back bidirec-

tional switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-397.22 Short and open circuit situations that can occur during commu-

tation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-417.23 Two phase switching matrix example. . . . . . . . . . . . . . . . 7-427.24 Four step commutation process between bidirectional switch cells

in Figure 7.23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-437.25 Matrix converter input filters and damping resistors. . . . . . . . 7-457.26 Matrix converter with over-voltage diode clamp protection. . . . 7-45

8.1 Block diagram of a generic PV system [21] . . . . . . . . . . . . . 8-68.2 Band gap diagram of a solar cell (pn junction). . . . . . . . . . . 8-78.3 Optical generation of carriers in a pn junction. . . . . . . . . . . 8-98.4 Equivalent circuit of an ideal solar cell. . . . . . . . . . . . . . . . 8-118.5 Equivalent circuit of a non-ideal solar cell. . . . . . . . . . . . . . 8-118.6 Circuit symbols for a solar cell and a series array of solar cells. . 8-128.7 Maximum power diagram for a solar cell. . . . . . . . . . . . . . 8-138.8 Relative merits of different inverter topologies for PV systems [24].8-158.9 Single-phase multi-string converter [25]. . . . . . . . . . . . . . . 8-17

LIST OF FIGURES xxi

8.10 Detailed view of a single single phase output module [25]. . . . . 8-188.11 Multi-string converter with a three phase output stage [25]. . . . 8-198.12 A transformerless bridge converter interface for a PV system. . 8-208.13 Equivalent circuit for the H-bridge PV converter with S1 and S4

turned on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-218.14 Equivalent circuit for the H-bridge PV converter with S2 and S3

turned on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-218.15 Equivalent circuit for the H-bridge PV converter with S1 and S3

turned on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-248.16 Hybrid Switching H-bridge converter. . . . . . . . . . . . . . . . 8-268.17 Hybrid Switching H-bridge converter equivalent circuit for the

two positions of the low frequency switches. . . . . . . . . . . . . 8-278.18 H5 H-bridge converter. . . . . . . . . . . . . . . . . . . . . . . . . 8-288.19 H5 H-bridge equivalent circuit for Vg > 0. . . . . . . . . . . . . . 8-298.20 H5 H-bridge equivalent circuit for Vg < 0. . . . . . . . . . . . . . 8-318.21 The HERIC PV inverter topology (Sunways) . . . . . . . . . . . 8-338.22 The full bridge DC bypass PV inverter (Ingeteam). . . . . . . . . 8-348.23 Basic NPC single phase leg. . . . . . . . . . . . . . . . . . . . . . 8-378.24 NPC with Vg > 0 and i > 0. . . . . . . . . . . . . . . . . . . . . . 8-388.25 NPC with Vg < 0 and i < 0. . . . . . . . . . . . . . . . . . . . . . 8-398.26 Basic structure of a single phase PV interface with a high fre-

quency isolated boost converter. . . . . . . . . . . . . . . . . . . 8-408.27 Basic structure of a single phase PV interface with a low fre-

quency transformer and non-isolated boost converter. . . . . . . . 8-418.28 Test set up for testing the compliance of a distributed resource

with the IEEE 1547 standard in anti-islanding. . . . . . . . . . . 8-508.29 VDE 0126-1-1 anti-islanding standard test circuit. . . . . . . . . 8-518.30 Lightning impulse test waveform. . . . . . . . . . . . . . . . . . . 8-538.31 Classic PLL block diagram. . . . . . . . . . . . . . . . . . . . . . 8-548.32 Block diagram of a PLL control system when in lock. . . . . . . . 8-568.33 Root locus and Bode plot for a 1st order classic PLL. . . . . . . 8-588.34 Root locus and Bode plot for the 2nd order PLL. . . . . . . . . . 8-598.35 Open loop Bode plots for a 2nd order PLL with zero added. . . . 8-608.36 Closed loop magnitude response of a 2nd order PLL with zero

added. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-618.37 Basic in-quadrature PLL. . . . . . . . . . . . . . . . . . . . . . . 8-628.38 Xcos simulation model of the basic in-quadrature PLL. . . . . . . 8-648.39 Xcos simulation result – input waveform and feedback sine wave-

form. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-658.40 Xcos simulation result – the error between the input waveform

and the sine feedback waveform. . . . . . . . . . . . . . . . . . . 8-658.41 Xcos simulation result – the output of the PI controller which

indicates the difference between the input frequency and the loopcentre frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-66

8.42 In-quadrature PLL implemented with a Park transformation. . . 8-678.43 The three phase quadrature PLL using a Park Transformation. . 8-688.44 Space vector representation of the convergence process of a Park

Transformation based quadrature PLL. . . . . . . . . . . . . . . . 8-698.45 Space vector representation when the Park Transformation quadra-

ture based PLL is locked. . . . . . . . . . . . . . . . . . . . . . . 8-70

xxii LIST OF FIGURES

8.46 Two phase PLL implemented in Python showing the estimatedwaveform versus the actual waveform. . . . . . . . . . . . . . . . 8-71

8.47 Two phase PLL implemented in Python showing the estimatefrequency error from the centre frequency of the PLL. . . . . . . 8-72

8.48 Two phase PLL implemented in Python showing the estimatedwaveform versus the actual waveform when there is a 30% 5thinput harmonic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-73

8.49 Two phase PLL implemented in Python showing the estimatefrequency error from the centre frequency of the PLL when thereis a 30% 5th input harmonic. . . . . . . . . . . . . . . . . . . . . 8-74

8.50 Two phase PLL implemented in Python showing the estimatefrequency error from the centre frequency of the PLL when thereis a 30% 5th input harmonic and filter. . . . . . . . . . . . . . . . 8-75

A.1 Series RLC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . A-2A.2 Series RLC circuit pole positions. . . . . . . . . . . . . . . . . . . A-3A.3 Time response of a series RLC circuit with Q = 6.3. . . . . . . . A-7A.4 Parallel RLC circuit. . . . . . . . . . . . . . . . . . . . . . . . . . A-9

B.1 MMF calculation integration path. . . . . . . . . . . . . . . . . . B-3B.2 Dimensions of a single coil. . . . . . . . . . . . . . . . . . . . . . B-6B.3 Three phase to two phase transformation. . . . . . . . . . . . . . B-9B.4 Two phase stationary to two phase rotating transformations. . . B-16B.5 Conceptual diagram of a three phase SYNCREL. . . . . . . . . . B-18B.6 Ideal dq equations. . . . . . . . . . . . . . . . . . . . . . . . . . . B-20B.7 Resolving the current space vector onto the abc axes. . . . . . . . B-23B.8 Relationship between the dq-axes and current space vectors. . . . B-24B.9 Space vector rotating frame transformations. . . . . . . . . . . . B-25

C.1 Two pole three phase Syncrel – conceptual diagram . . . . . . . . C-2C.2 Developed diagram of a Syncrel. . . . . . . . . . . . . . . . . . . C-5C.3 d axis developed diagram for Syncrel . . . . . . . . . . . . . . . . C-6C.4 ‘a’ phase inductance plot. . . . . . . . . . . . . . . . . . . . . . . C-11

D.1 Phasor relationship for complex power. . . . . . . . . . . . . . . . D-2D.2 Space vector diagram. . . . . . . . . . . . . . . . . . . . . . . . . D-6

E.1 Simple single phase, half wave rectifier, with an LR load. . . . . . E-2E.2 Initial screen upon invoking SaberSketch. . . . . . . . . . . . . . E-3E.3 An example of a parts gallery screen. . . . . . . . . . . . . . . . . E-4E.4 The wire attributes window. . . . . . . . . . . . . . . . . . . . . . E-7E.5 An example of SaberSketch with the Saber guide toolbar activated.E-8E.6 An example dc/transient simulation set-up window. . . . . . . . E-9E.7 The input-output table of the dc/transient analysis window. . . . E-10E.8 The initial SaberScope window. . . . . . . . . . . . . . . . . . . . E-11E.9 A signal plotted in SaberScope. . . . . . . . . . . . . . . . . . . . E-12E.10 An example of a waveform calculation in SaberScope. . . . . . . E-13E.11 Fourier analysis dialogues in Saber. . . . . . . . . . . . . . . . . . E-14

List of Tables

1.1 Switch configurations and output voltages for a generic H-bridge. 1-11

4.1 Resistor application selection guide . . . . . . . . . . . . . . . . . 4-34.2 Capacitor application guide . . . . . . . . . . . . . . . . . . . . . 4-74.3 Core materials and their uses. . . . . . . . . . . . . . . . . . . . . 4-314.4 Inductor specifications. . . . . . . . . . . . . . . . . . . . . . . . . 4-35

6.1 Fourier coefficient formulae with symmetry. . . . . . . . . . . . . 6-36.2 Current harmonic amplitudes. . . . . . . . . . . . . . . . . . . . . 6-25

7.1 Switching combinations and associated phase and line-to-line volt-ages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

7.2 Switching combinations and associated phase and phase-to-neutralvoltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

7.3 PWM firing times for various sectors . . . . . . . . . . . . . . . . . 7-127.4 Voltage limit γ’s . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-147.5 Switching values used in SVM. . . . . . . . . . . . . . . . . . . . 7-307.6 Selection of switching configurations for combinations of output

voltage and input current vectors. . . . . . . . . . . . . . . . . . 7-32

8.1 EN50160 European standards for public distribution grid voltageharmonics limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-45

8.2 Comparison of US and European Standards on disconnectiontimes for PV inverters under abnormal voltage variations. . . . . 8-45

8.3 Comparison of European and US standard for disconnection withrespect to frequency deviations. . . . . . . . . . . . . . . . . . . . 8-46

8.4 European and US reconnection conditions for PV inverter sys-tems after a trip [21]. . . . . . . . . . . . . . . . . . . . . . . . . . 8-47

8.5 European and US DC current injection limitations . . . . . . . . 8-478.6 IEC and IEEE standards for injected current harmonics . . . . . 8-488.7 IEC61000-3-2 current harmonic limits. . . . . . . . . . . . . . . . 8-488.8 Australian Standard voltage and frequency limits. . . . . . . . . 8-52

B.1 Summary of Stationary Frame Transformations . . . . . . . . . . B-14B.2 Summary of Rotating Frame Transformations . . . . . . . . . . . B-17

E.1 Number magnitude specifiers in Saber . . . . . . . . . . . . . . . E-6

xxiv LIST OF TABLES

Nomenclature

D Duty cycle = tonT .

gop Optical generation rate (EHP/cm3/sec)

I0 Diode reverse saturation current.

isw Current through a semiconductor switch.

itr Current through a pass transistor in a linear power supply.

k Boltzmann’s constant (1.38× 10−23J/K).

Ln Mean diffusion length of electrons in p materials.

Lp Mean diffusion distance of holes in n materials.

q Charge of an electron (1.6× 10−19C).

T Switching period.

ton On-time of a switch. On means that the switch is closed.

TK Temperature in Kelvin.

Vd DC input voltage to a linear or switching power supply.

vsw Voltage across a semiconductor switch.

vtr Voltage across a pass transistor in a linear power supply.

BJTs Bipolar Junction Transistors

EHP Electron-hole-pairs.

GTO Gate Turn Off Thyristor.

IBGT Insulated Gate Bipolar Junction Transistor.

MOSFET Metal Oxide Semiconductor Fiedl Effect Transistor.

PWM Pulse Width Modulation.

SCR Silicon Controlled Rectifier or Thyristor.

SMPS Switch Mode Power Supplies.

xxvi Nomenclature

Part I

Switched Mode PowerSupplies

Chapter 1

Switching Basics

1.1 Introduction

Power electronics is an enabling technology for a carbon constrained world.Power electronic systems allow the very efficient conversion of electrical energyto forms which can be more easily utilised. For example, photovoltaic collectorsnaturally generate DC output voltages, the level of the voltage being dependenton the number of series cells. In order to utilise photovoltaics in the powersystem as it currently exists, the DC voltage needs to be converted to AC voltageof the correct magnitude. Without the use of power electronics this conversionis very difficult to achieve at reasonable cost. Power electronics is essential topower all electric and hybrid electric vehicles, allow efficient air-conditioning,drive new technology lighting systems, allow interfacing of wind turbines to thegrid and so on.

Another major use of power electronics is in variable speed drives. AC elec-trical machines are normally constant speed systems, with the shaft rotationalspeed being related to the AC supply frequency and the number of pole pairs inthe machine. In order to change the speed of an AC machine one needs a variablefrequency, variable voltage supply. Prior to the advent of power electronics, thiswas achieved by the use of electrical machine based frequency converters. Thiswas a very expensive solution, which meant the variable speed AC systems werealmost never used. If one wanted a variable speed electrical machine one usedthe DC machine, where the shaft speed can be controlled by the magnitude ofthe DC armature voltage. Power electronics, coupled with microprocessors hasallowed the development of completely static (i.e. no rotating parts) power elec-tronic variable frequency, variable voltage supplies for AC electrical machines(know as inverters). Inverters can be built using current technology up to theseveral megawatts. The variable speed AC machine drive market is now worthtens of billions of dollars per year on a global basis.

Power electronics is also embedded in many consumers products as well –most home electronic systems, for example, are powered by a switch mode powersupply (computers, LCD and plasma TVs, video recorders etc). The reason forthe switch mode power supply’s ubiquitous use is related to their light weight,efficiency, and multi-voltage capabilities.

The remainder of this chapter will examine the basic switch building blocks

1-2 Switching Basics

for power electronic systems. These will be examined in a very generic wayinitially, and then some specific implementations will be considered throughoutthe remainder of the course.

1.2 Why Use Switching?

One question that needs to be answered before looking at how switching isimplemented is:

“Why bother using switching in electronic circuits?”

Clearly the answer depends on what one is trying to achieve. One can useswitching to implement a classic switch function – i.e. connect one part of acircuit to another part. One can use a mechanical or a semiconductor basedswitch for this. Usually once a switch of this type is closed or opened it tends toremain this way for a long period of time. Whilst this is a valid use of switching,it is not the focus of the switching discussed in this course.

The switching that will be discussed here is relatively high frequency switch-ing that occurs continuously whilst the circuit is operating. This means thatthe electronic circuit’s operation is in a constant transient state.

Switching is used in power electronic systems because the power conversionis very efficient. This is due to the fact that if a device is switched then ideallythe voltage across the device is zero. Therefore the power dissipated in theswitching element is:

p = vswisw = 0× isw = 0 (1.1)

where vswis the voltage across the switch, and isw is the current through theswitch. Obviously the power dissipated in the switch is zero regardless of isw.Similarly one can have voltage across a device, and due to external circuitconditions the current through the device can be zero, and again the powerdissipated in the switch will be zero.Power dissipated in

the switch is zero.Remark 1.1 The previous paragraph is simply a statement as to why switchesare in general used in electrical systems. The trick to using switching electronicelements in power electronic systems is that by using high frequency switching(which can only be obtained electronically), together with specific external circuitconditions, one can obtain a linearly controllable output from the system withoutdissipating any power.

Remark 1.2 Switches used in real systems do have resistance and offset volt-ages across them. Therefore the switches do dissipate power when they switchis closed, but the power dissipated is often very low compared to the amount ofenergy being controlled by the switching circuit.

Remark 1.3 Another advantage of power conversion using switching is that thesize and weight of the power conversion device is far less than power conversiontechniques that do not use switching. This is largely due to the fact that inductorsand capacitors are frequency dependent devices, and the switching frequency inpower electronics systems are high which means that these components can bemade smaller.

1.2 Why Use Switching? 1-3

vref

vout

ControlVd CoutRL

vtr = (Vd ¡ vout)

itr

Figure 1.1: Conceptual diagram of a traditional linear DC linear power supply.

The benefits of switching can clearly be seen if one considers the traditionallinear DC power supply. These power supplies take a DC input voltage andtraditional linear

DC power supply convert it to a lower DC voltage. This are implemented by using a circuit of thegeneral configuration shown in Figure (1.1). As can be seen from this figure,there is a substantial voltage across the pass transistor, and therefore the powerdissipated in the transistor is:

ptr = vtritr = (Vd − vout)itr (1.2)

where vtr is the voltage across the pass transistor, itr is the current throughthe pass transistor, and Vd is the DC input voltage to the power supply. Thepass transistor is essentially behaving as an electronically controlled resistor, itsvalue being dynamically changed by the control circuit to maintain the outputvoltage at the desired output voltage.

Remark 1.4 As can be seen from (1.2) if Vd − vout is a large value and thereis a reasonable current flow, itr through the device, the power dissipated can bevery large. Therefore the efficiency of these power supplies is usually very low.The pass transistor requires a large heat sink under these conditions, making thesupply bulky.

Remark 1.5 The key point to note in Figure 1.1 is that the NPN transistoris operating in its linear region of operation. This is similar to Class A ampli-fiers that one may be familiar with from linear electronics. As with the ClassA amplifier, operation in the linear region means that a lot of power is beingdissipated in the transistor.


+ -vL

vdiode

vout

+

-

+

-

vs

+ - iL

L

R

Figure 1.2: Simple half wave rectifier circuit with LR load.

1.3 Taxonomy of Power Electronic SystemsPower electronic systems fall into two broad categories, depending on how theswitches in the system are switch off:

• naturally commutated systems;

• and forced commutated systems.

We shall briefly consider these, in a very generic sense, below. Both theseswitching strategies will be further developed later in the course.

1.3.1 Naturally Commutated Systems

Naturally commutated power electronic devices are very common – a diode rec-tifier consists of naturally commutated devices called diodes (which the readersshould be very familiar with). Natural commutation means that the powerdevice is turned off by a “natural” process derived from the external circuit con-ditions. For example consider a simple half wave rectifier circuit with an LRload as shown in Figure 1.2. In this circuit the diode will switch (or turn) onwhen the voltage vd across the diode becomes positive, and it will naturally turnoff when the current attempts to reverse through the diode – this is the point ofnatural commutation or transition from the conduction mode of the diode to theturned off state. Note that this point of turn-off is determined by the externalcircuit conditions (i.e. the input voltage waveform and the specific values of theload resistor and inductor). Figure 1.3 on page 1-5 shows the waveforms forthis particular circuit, and one can see that when the current through the loadattempts to reverse the diode turns off and the diode voltage becomes that ofthe supply waveform.

Remark 1.6 One can see that with this circuit the turn-on time of the diode isdetermined by the properties of a diode – i.e. turns on immediately it becomes

1.3 Taxonomy of Power Electronic Systems 1-5

(V)

-60.0

-40.0

-20.0

0.0

20.0

40.0

60.0

t(s)0.0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

(A)

-0.2

0.0

0.2

0.4

0.6

0.8

t1 t

2t3

iL

vs v

out vL

vdiode

Due to simulation numerics

Area A

Area B

Figure 1.3: Plots for a half wave rectifier with an LR load – L = 200mH andR = 50Ω.

forward biased. The turn-off time is determined by the load and supply propertiesonly, and the fact that a diode cannot conduct current in the reverse direction.We shall see that the turn-on time of some naturally commutated circuits canbe controlled.

A variant of the basic diode rectifier circuit can be obtained by replacing thediode with a thyristor or Silicon Controlled Rectifier (SCR). These devices aresimilar to a diode in that it turns off, or commutates, when the current attemptsto reverse through the device. However it is different from the diode because itdoes not turn on immediately it becomes forward biased, but must have a firingpulse put into it via a third “gate” terminal, assuming that it is already forwardbiased.

There are a variety of systems that fall under the category of naturally com-mutated – single and three phase rectifiers, and thyristor rectifiers or converters.

Remark 1.7 One of the main problem application areas with naturally com-mutated devices is DC. Because these devices require a reverse of current andvoltage across them to turn off, DC systems are a problem. It is possible toturn off naturally commutated devices in DC systems, but it requires complexauxiliary circuitry.

Summary 1.1 Naturally commutated switching devices are characterised by theproperty that they turn off or commutate from the conducting mode to the non-conducting mode due to external circuit conditions. There is not an explicit


input under the designers control that results in the device turning off. The turnon time may or may not be a controlled time.

1.3.2 Forced Commutated SystemsPower electronic systems are categorised as forced commutated if the turn onand turn off times are determined by an externally generated firing pulse, thetiming of which is completely controlled by the system designer. From a hard-ware perspective, the devices used for such systems are bipolar junction transis-tors (BJTs), MOSFETs, Insulated Gate Bipolar Junction Transistors (IBGTs),Gate Turn-off thyristors (GTOs) etc.

Remark 1.8 Forced commutated systems are more flexible than naturally com-mutated systems because they can more easily handle DC input voltages. Nat-urally commutated systems have problems with DC inputs because without spe-cial provision the circuit conditions cannot reverse the current flow through theswitching device to facilitate a natural commutation.

Switch mode power supplies (SMPS), which are the subject of this section ofthe course, almost exclusively use forced commutation. An alternative name toindicate this that is often used in the SMPS literature is “hard switched”. Thisrefers to the fact that the device can be switched off regardless of the currentand voltage conditions across the switching element.

Remark 1.9 It should be noted that not all SMPS are forced commutated.There is a strategy for switching, what would normally be forced commutatedswitching devices, called soft switching, or resonant mode switching. This switch-ing strategy has many aspects similar to natural commutation, where extra cir-cuitry is used to force conditions that allow zero voltage or zero current throughthe switching device at the time of switching. However, even under this condi-tion, the device switching gate has to be activated to turn off the device – it doesnot do it naturally.

The fundamental element of a forced commutated system is the switching pole,which is shown conceptually in Figure 1.4 on page 1-7. As can be seen fromthis figure, the switch is modeled as a single pole double throw switch. Theconnection of the switch is controlled by the S/W ctrl input to the switch. Theoutput voltage is either v or 0 volts depending on the switch connection.

By its very nature, the switching pole is a non-linear element – the outputcan only take one of two different values. Assuming that the control circuit isswitching the output from v to 0 at a particular frequency then the output ofthe circuit appears as shown in Figure 1.5 on page 1-7. The non-linearity of theoutput of the circuit is clearly evident.

From a control perspective non-linear behaviour is undesirable. In mostelectronic circuits it is desired that the output of the circuit is related to the inputof the circuit in a linear fashion – e.g. in amplifier or attenuator applications.Therefore the output of Figure 1.5 needs to be modified in some way so thatthe switching system behaves linearly.


vout

v

S/W ctrl

Figure 1.4: Forced commutated switching pole.

t

vout

Vd

T

ton

Figure 1.5: Output of the switching pole.


Remark 1.10 The upshot of the linearisation of the converter system is that itallows the use of conventional and familiar linear control theory on the convertersystems.

Remark 1.11 Another consequence of the quest for linearisation of switchingsystems is that the control rates and switching frequencies have to be high. Thisallows the overall control for these systems to be organised as a nested hierarchyof control loops, with the inner most loops having the highest bandwidth. Theinner control loops, as far as the slower outer control loops are concerned, appearto be algebraic in nature. This approach allows a “decoupled” control designapproach to be used, and greatly simplifies the design.

Remark 1.12 There is a move in the control of power electronic systems toembrace the non-linearity of the system by the use of non-linear control strategiessuch as Model Predictive Control (MPC). It should be noted that the applicationof such control methodologies to power electronic systems has only been madepossible because of the availability of low cost powerful microprocessor systems.

1.3.2.1 Linearising the Non-linear System

To linearise the basic switching pole one needs firstly to define what the in-put/output relationship is. An examination of Figure 1.5 shows that the switch-ing waveform average value over the period T is controlled by the time that thevoltage is at Vd and at 0 volts. A way of capturing this is to define the dutycycle of the waveform:

D =ton

T(1.3)

where 0 ≤ D ≤ 1 and ton is the on-time of the switch which means that theswitch is closed so that the output is connected to the input voltage.

The average voltage output of the waveform is:

vave =1

T

∫ ton

0

Vd dt (1.4)

=1

T

∫ DT

0

Vd dt (1.5)

= DVd (1.6)

As can be seen from (1.6) the relationship between the average output voltageand the input voltage is linear with respect to the duty cycle – i.e. vave ∝ Vd

when the constant of proportionality is D the duty cycle.1 One could alsoconsider that the relationship is vave ∝ D, where the constant of proportionalityis the input voltage magnitude, andD is regarded at the input to a linear system.

However, if the waveform of Figure 1.5 is fed into a resistive load the currentwould look like the output voltage waveform. What is usually required in realworld applications is a DC current through the load that is related to the averageoutput voltage vave.

Most readers will see that what is required is a filter on the output of the...what is required isa filter on the out-put of the switchingpole.

switching pole. The filter will only respond to the low frequency components in1The switching pole, in an average sense, behaves like an electronically controlled attenu-

ator.


vout

Vd

S/W ctrl

Cout RL

L

iL

vL

iL

IL

t

t

vout

Filter

Figure 1.6: Example buck converter with waveforms.

the output waveform of Figure 1.5, the lowest frequency being DC. Thereforeif the filter has a lower enough role off frequency the AC components in thewaveform will be attenuated, and the DC component will be predominant.

Figure 1.6 shows the previous switching pole with the output filter added.The waveforms for the inductor current and the output voltage are also shown.As can be seen, the inductor current waveform and the output voltage waveformsare smoothed compared to the square wave voltage and current waveforms atthe switch. This particular circuit is a basic switched mode power supply circuitknown as a buck converter. We shall examine this circuit in much more detailin Chapter 2 on page 2-1.

Remark 1.13 The amount of ripple on the current and voltage waveforms de-pends on the values of the filtering components in Figure 1.6. For example, ifthe inductor is made larger then the peak-to-peak ripple on iL can be decreased,and similarly if Cout is made larger then the ripple on the output voltage can bemade smaller. The other parameter that affects the magnitude of both ripples isthe frequency of switching (i.e. fs = 1/T ). The higher the frequency, then forgiven values of L and Cout , the smaller the ripple on iL and vout respectively.

Remark 1.14 The observations and remarks in Remark 1.13 above are an-other way of saying that the frequency characteristics of the output filter are thedetermining factor for minimising the ripple on the output for a given switchingfrequency.

Remark 1.15 If it is desired to have vout as a variable quantity – i.e. the outputcan move to different reference outputs vref , then the dynamics associated withthe output filter are very important. If the ripple is to be kept low, then theswitching frequency should be very high, this allowing the filtering componentsto be kept small to achieve a low output ripple. The small filter components willallow rapid transient output voltage changes with set-point changes.


vout

Vd

S=W1 S=W2

Load

S=W1 ctrl S=W2 ctrl

vsw1 vsw2

Figure 1.7: Conceptual diagram of a H-bridge.

1.3.2.2 Basics of PWM and Frequency Spectra

From the previous section one can deduce that the linearisation of the non-linear switching waveforms from the switching pole is related to the relationshipbetween the frequency characteristics of the switching pole output waveformsand the frequency characteristics of the output filter. Given this relationship,we shall introduce some basic theory on the frequency characteristics of Pulse...frequency charac-

teristics of PulseWidth Modulation

Width Modulation (PWM), which is the main technique used to generate theoutput waveforms for most forced commutated power electronic systems.

In order to introduce PWM we shall consider a basic building block for manypower electronic systems – the H-bridge. A basic schematic of this building blockcan be seen in Figure 1.7. One can see that the name of the topology is derivedfrom the shape of the circuit when drawn.

The outputs of this circuit can be easily tabulated by considering that a‘1’ is when the switch is connected to the top terminal in Figure 1.7, and a‘0’ is when a switch is connected to the bottom terminal. The possible switchconfigurations and the vout voltages are shown in Table 1.1. As can be seen thisparticular circuit is capable of producing three different output voltages.

The simplest way of switching the H-bridge is to use the ‘10’ and ‘01’ switch-ing strategies to produce a ±Vd output voltage waveform. The average voltageis then determined by the length of time that waveforms spend on each of thevoltages. For example, if the time spent at Vd is equal to the time spent at −Vd

then the average output voltage is obviously 0 volts.


S/W1 S/W2 vout

0 0 00 1 −Vd

1 0 Vd

1 1 0

Table 1.1: Switch configurations and output voltages for a generic H-bridge.

Remark 1.16 The H-bridge circuit is a very versatile power electronic circuit.With the addition of one more parallel switching pole it becomes an invertermodule capable of three phase output waveforms. As presented in Figure 1.7on page 1-10 it is capable of positive and negative output voltages by simplychanging the effective duty cycle of the output waveforms.

As noted later in the course in Section 2.4.7 on page 2-38 one can developmore sophisticated switching strategies to produce less ripple in the output(when the output is filtered) without an increase in the switching frequency ofthe devices. I will not preempt this material here, but instead present a moregeneral consideration of PWM switching strategies, their harmonic implications,and implementation approaches.

We shall consider a form of PWM called double edge naturally sampledPWM[1]2. A conceptual diagram of how this PWM is implemented is shown ...double edge nat-

urally sampledPWM

in Figure 1.8. Consider the top part of the diagram. As can be seen thebasic idea is that the sinusoidal reference waveform is compared to a triangularmodulating waveform of the same amplitude using a comparator. The outputof the comparator is a digital waveform. If one takes the average of this digitalwaveform it is 1/2 and the peak-to-peak value is 1 (since it is digital). Thereforethe waveform has a DC component in it of 1/2. The widths of the pulses inthis waveform vary, and over each interval corresponding to one period of thetriangular carrier the average output is a scaled value of the reference waveformwith the 1/2 DC offset added to it. A similar argument can be made for thewaveform at the bottom part of the diagram. The difference here is that thereference waveform is an inverted version of the reference for the top half of thecircuit, therefore the this comparator is trying to PWM the output to producea voltage that is the opposite of the top half of the circuit. These two offsetwaveforms are then subtracted, which removes the DC component from theoutput, and doubles the average output voltage compared to the DC offsetwaveforms. This also means that the output waveform is now bipolar.

Let us consider a little theory associated with this. Consider Figure 1.9which shows a close up of the modulation process. This is a simplified situationin that the reference waveform Vref is considered to be a DC level. Neverthelessone can see the basic idea by analysing this situation.

2Note that there are a variety of forms of PWM, and this is but one. It does happen tohave some nice properties with respect to the spectrum though.


+

-

+

-

t

t

t

t

+

-

vref

vref

PWM output

§

Figure 1.8: Conceptual diagram showing how to generate double edge naturallysampled PWM.

Carrying out some simple geometry on these waveforms we can write:

Vref = Vtri −(

4Vtri

T

)(ton − t0) (1.7)

∴ ton =T

4

(1− Vref

Vtri

)+ t0 (1.8)

Similarly one can also write:

Vref = −Vtri +

(4Vtri

T

)(toff − t1) (1.9)

t1 = t0 +T

2(1.10)

∴ toff =T

4

(Vref

Vtri+ 3

)+ t0 (1.11)

It is simple to see that:

δt = toff − ton =T

2

(1 +

Vref

Vtri

)(1.12)

and therefore the average voltage over one cycle of the triangular modulatingwaveform is:

vave =1

T[δt · Vd] (1.13)

=Vd

2

(1 +

Vref

Vtri

)(1.14)


Vref

Vd

Vtri

t

t

T

ton to®

m =4Vtri

T

t1t0

m = ¡4Vtri

T

¡Vtri

Figure 1.9: Close-up of naturally sampled PWM process.


vout

Vd

S/W ctrl

Cout RL

L

iL

vL

vout

Vd

Cout RL

L

iL

vL

vsw vsw

1 D

1

2Vtri

+

+§

Vref

1

2

Figure 1.10: Equivalence between a switching pole and a variable turns ratioDC-DC transformer.

If we let Vtri = 1 and normalise to Vd then we can write the average voltageas:

vave

Vd=

1

2+

1

2Vref (1.15)

Remark 1.17 One can see from (1.15) that there is a DC offset in the outputwaveform that is unrelated to Vref .

Remark 1.18 Equation (1.14) can be broken into two components; the DCoffset Vdc = Vd

2 ; and the component related to the reference signal Vd2Vtri

Vref =

kpoleVref , where kpole = Vd2Vtri

can be considered to be the gain of the switchingpole. Now equate (1.6) and (1.14):

DVd =Vd2

+Vd

2VtriVref (1.16)

∴ D =1

2+

1

2VtriVref (1.17)

Figure 1.10 shows the equivalence between the switching pole and a variable turnsratio transformer. The switching pole, in an average sense behaves as a DC-DC transformer with an infinite turns ratio. When analysing the performanceof the system from a control perspective, the ripple in the currents and voltagescan be ignored because of the averaging effect of the filter, and the switching polecan be consider to be a linear transformation with a ratio of D.

If a similar analysis is carried out for the negative reference waveform and the180 phase shifted triangular waveform then one one will get a similar expres-sion:

vave

Vd=

1

2− 1

2Vref (1.18)

and therefore if these two expressions are subtracted then the difference wave-form will eliminate the DC component, and the average difference waveform willbe Vref .

A simulation of the PWM scheme of Figure 1.8 was set up in the Saberr.This simulation also allows the Fourier components of the waveform to be easily


combined_output

ZeroPhaseDelay

frequency:10000

offset:−1

amplitude:2

delay:0

c_sin

amplitude:0.9

frequency:50

d2var

conv_d2var

diff

d2var

conv_d2var

rel_oper_gte

out

in1

in2

rel_oper_gte

out

in1

in2

k:−1

c_saw3

frequency:10000

offset:−1

amplitude:2

delay:0

Figure 1.11: Saberr circuit used to simulate double edged naturally sampledPWM.

obtained. The Saberr circuit appears in Figure 1.11. As can be seen this circuitessentially mirrors the conceptual diagram of Figure 1.8.

Figure 1.12 shows the output of the modulator along with its spectrum.In this simulation the triangular waveform has a frequency of 10kHz, and thereference waveform is a 50Hz sine wave with an amplitude of 0.9. Several ob-servations can be made from this figure:

• Fundamental component of the output is at 50Hz and its amplitude is 0.9.

• The first appreciable harmonics in the PWM output waveform are side-bands of the 10kHz triangular wave frequency.

• There are no harmonics at the switching frequency of 10kHz.

Let us examine the PWM generated in a little more detail. The absence ofthe harmonics at the triangular wave frequency (which is the effective switchingfrequency if a H-bridge converter is being driven) is a direct consequence ofthe 0 phase shift in the triangular wave for the bottom modulation stream inFigure 1.8 on page 1-12. This results in a 0 phase difference between the 10kHzharmonic produced in either leg in the H-bridge. Therefore when the harmoniccomponents are implicitly subtracted by the H-bridge one is subtracting twowaveforms that are in phase, and the net result is zero.

Figure 1.13 shows the component waveforms for the simulation that pro-duced the results of Figure 1.12. One can see that the “ZeroPhaseLegSwWave-form” and “DelayedPhaseLegSwWaveform” have a DC offset – this is evidentfrom the time domain waveforms and the spectrum where the DC componentcan be seen in the spectrum of both signals as 0.5.

The other interesting observation is that the spectrum of the “ZeroPhase-LegSwWaveform” and “DelayedPhaseLegSwWaveform” both have the 10kHz


Graph0

(−)

−1.0

−0.5

0.0

0.5

1.0

t(s)

20.0m 21.0m 22.0m 23.0m 24.0m 25.0m 26.0m 27.0m 28.0m 29.0m 30.0m 31.0m 32.0m 33.0m 34.0m 35.0m 36.0m 37.0m 38.0m 39.0m 40.0m

Ma

g(−

)

0.0

0.2

0.4

0.6

0.8

1.0

f(Hz)

0.0 1.0k 2.0k 3.0k 4.0k 5.0k 6.0k 7.0k 8.0k 9.0k 10.0k 11.0k 12.0k 13.0k 14.0k 15.0k

(−) : t(s)

combined_output

Reference

Mag(−) : f(Hz)

combined_output

Figure 1.12: Saberr simulation output for double edged naturally sampledPWM.

switching harmonic, but in the “combined_output” waveform this componentis missing. As mentioned previously this is due to the 180 phase shift in thetriangular modulating waveforms and the leg reference waveforms.

Given the above cancellation, it is informative to consider the case wherethe triangular modulation waveforms are 180 out of phase, as compared to inphase. Figure 1.14 shows the spectrum in this case, and as expected the 10kHzswitching frequency in each of the leg switching waveforms is no longer cancelledand appears in the combined output waveform. The real and imaginary com-ponents of the Fourier components were taken. As can be seen the real 10kHzcomponents in the leg switching waveforms are opposite in magnitude indicatingthat when they are subtracted they will add together to give a resultant in theoutput waveform. The imaginary component is only present in the fundamentalas it is a sine wave and hence at 90 to the assumed cosine waveforms for theFourier series in Saberr.

Remark 1.19 The main point to note from the above harmonic analysis isthat when triangular PWM is used the phase angle between the triangular car-rier waveforms can have important implications on the harmonic content of theoutput waveforms.

The PWM sampling strategy presented above is called naturally sampled be-cause the switching occurs at the “natural” cross-over points of the triangular


Graph0

Ma

g(−

)

0.0

0.2

0.4

0.6

0.8

1.0

f(Hz)

−2.0k 0.0 2.0k 4.0k 6.0k 8.0k 10.0k 12.0k

Mag

(−)

0.0

0.2

0.4

0.6

t(s)

19.5m 20.0m 20.5m 21.0m 21.5m 22.0m 22.5m 23.0m 23.5m 24.0m 24.5m

(−)

−0.5

0.0

0.5

1.0

(−)

−0.5

0.0

0.5

1.0

Ma

g(−

)

0.0

0.2

0.4

0.6

(−)

−1.0

−0.5

0.0

0.5

1.0

Mag(−) : f(Hz)

combined_output

Mag(−) : f(Hz)

DelayedPhaseLegSwWaveform

Mag(−) : f(Hz)

ZeroPhaseLegSwWaveform

(−) : t(s)

DelayedPhaseLegSwWaveform

(−) : t(s)

ZeroPhaseLegSwWaveform

(−) : t(s)

Reference

Figure 1.13: Component waveforms for double edged naturally sampled PWM.

Graph0

f(Hz)

0.0 1.0k 2.0k 3.0k 4.0k 5.0k 6.0k 7.0k 8.0k 9.0k 10.0k 11.0k 12.0k 13.0k 14.0k 15.0k

Mag(−

)

0.0

0.2

0.4

0.6

0.8

1.0

(−)

−0.2

0.0

0.2

0.4

0.6

(−)

−0.2

0.0

0.2

0.4

0.6

Mag(−

)

0.0

0.1

0.2

0.3

0.4

0.5

(−)

−0.6

−0.4

−0.2

0.0

0.2

(−)

−0.4

−0.2

0.0

0.2

0.4

0.6

Mag(−

)

0.0

0.2

0.4

0.6

Mag(−) : f(Hz)

combined_output

(−) : f(Hz)

Imag_Leg2

(−) : f(Hz)

Real_Leg2

Mag(−) : f(Hz)

Leg2

(−) : f(Hz)

Imag_Leg1

(−) : f(Hz)

Real_Leg1

Mag(−) : f(Hz)

Leg1

Figure 1.14: Spectrum when the triangular modulation waveforms are 180 outof phase.


waveform and the reference waveform. This form of modulation is particularlysuitable to analogue implementation, and indeed many early analogue modu-lators used this strategy or variants of it. However, this particular techniqueis difficult to implement digitally because the times for switching at the cross-over points can only be calculate by solving a transcendental equation, which istime consuming in a microprocessor system. To make the strategy amenable todigital implementation, a regular sampled double edge PWM strategy can beregular sampled

double edge PWM employed. This is achieved by sampling the reference waveform at the peak ofthe triangular waveform and then holding this sample constant until the nextpeak of the triangular waveform. It is this constant sampled value that it com-pared to the triangular wave to determine the switching time. The use of thisconstant sample means that the cross point of the triangular waveform is easyto compute digitally. Sampling at the peak of the triangular waveform preventsmultiple switching due to the reference step changing at in inappropriate time.

1.4 SummaryThis chapter has outlined the following:

1. Why use switching? – it allows very efficient control of electrical energy.

2. The basic taxonomy of power electronic converter systems into naturallycommutated systems and forced commutated systems. The fundamentaldifferences in the operational principles of these two different approachesare presented, and the semiconductor devices that are associated withthem are briefly discussed.

3. The fundamental operational element of forced commutated systems, theswitching pole, was introduced.

4. Discussion of the use of filtering on the output of forced commutatedpower electronic systems to hide the inherent non-linearity of the systemis introduced.

5. Finally some of the basic concepts of PWM and its frequency spectra arepresented.

Chapter 2

Fundamental Topologies

2.1 Introduction

This course part will not attempt to cover every issue related to the design andoperation of switch mode power supplies – there is more than enough work inthis area to fill a whole course by itself. Instead, the material shall seek to em-phasise the main types of switch mode converter structures, their fundamentaloperational principles, the various areas where the different structures are useful,and finally aspects of the design and control of the switch mode converters.

Before looking at the different structures for switch mode converters, weshould firstly define what we mean by switch mode converters.

Definition 2.1 Switch Mode Converters (SMCs) are converters which accepta DC input and generate a DC output. Switched mode converters are usuallyonly operating at powers up to 10’s of kilowatts.

The switched mode converter usually finds application as a power supply reg-ulator in such items as computers, television sets, stereo systems etc., in factalmost all modern electronic consumer devices use some form of switch modeconverter. One of the other areas of application of switch mode converters areaerospace systems, where weight is a very important consideration.

The switch mode inverter, on the other hand accepts a DC input and gener-ates an AC output. These are treated in their own section of this course, sincethese devices tend to find application in the high power industrial systems area,and are most often used for the control of electrical machines (although theyare not exclusively used for this).

2.2 References

References to switch mode power supplies are often contained in texts on elec-tronics and power electronics. There are some specialised book written on thedesign of switching power supplies. Tutorial references that readers may finduseful are [2, 3, 4, 5].

One can find a lot of material in the IEEE Transactions on Industrial Elec-tronics, and the IEEE Transactions on Power Electronics. This information

2-2 Fundamental Topologies

tends to be of a more detailed nature on specific design issues with converters,or new converter topologies.

2.3 Taxonomy of Switch Mode ConvertersThere are literally hundreds of different circuit configurations for switch modeconverters. However, one can classify most of the them into two basic categories:

• Step-down or buck converters.buck converters

• Step-up or boost converters.boost converters

Many of the other topologies that are in the literature are combinations of thesetwo basic topologies.

The basic layout of a SMC system is shown in Figure 2.1 below. The inputto the converter is usually the mains. Since this is AC the first step is to convertthis to DC via a rectifier. Notice that one can also feed DC, from a battery,directly in at the output point of the rectifier. The unregulated DC is usuallyfiltered with a capacitor, before feeding the DC-DC converter electronics. Theoutput of this stage then feeds the load.

Uncontrolleddiode rectifier

Battery

ACline voltage

DC(unregulated)

DC(unregulated)

DC(regulated)

LoadDC-DC

converterFilter

capacitor

Desired outputvoltage

(1 or 3phase)

Figure 2.1: Block diagram of the structure of a typical DC-DC converter.

In the following diagrams the switches are assumed to be unidirectional. Thedirection of current flow is indicated by the arrow on the switch.

2.3.1 Step-down or Buck ConvertersThe step-down or buck converter is distinguished by the fact that the outputvoltage is always less than the input voltage. This means, that regardless of theoutput voltage is al-

ways less than inputvoltage

switching strategy, it is impossible to get the output at a higher voltage thanthe input. The distinguishing circuit feature of the buck converter is that onecannot get any current to flow in the circuit when the power device is turnedon, if the output voltage is greater than or equal to the input voltage.

Figure 2.2 shows a basic circuit for a buck converter. Before analysing thecircuit, let us look at it heuristically to determine its basic operation. When

2.3 Taxonomy of Switch Mode Converters 2-3

the switch SW closes, current will flow to the resistive load via the inductorL. The capacitor C will charge up during this process. Note that there is atransient involved in the inductor current building up and the voltage beingestablished on the capacitor. When the switch is opened the current throughthe inductor cannot stop instantly (if it does then the voltage across the inductorwill become very large and the circuit will most probably be destroyed). Thediode in the circuit will become forward biased, allowing the current in theinductor to continue flowing in the same direction (towards the load). Duringthis phase of operation the energy that was stored in the field of the inductorduring the switch on time is being transferred to the load. If the switch remainsopen for a long time the inductor current gradually decreases to zero, and atthe same time the current drawn from the capacitor increases. If the switch isclosed before the inductor current decreases to zero, then the current begins toincrease again.

Remark 2.1 Note that the maximum current that can flow through the inductorif the switch is left closed is Vd/RL.

Remark 2.2 If the inductor current goes to zero then the converter is said tobe operating in discontinuous mode. If it does not go to zero, then the converteris operating in continuous current mode. Generally speaking, it is desirableto operate the converter in one mode or the other, without a change of mode.Changes in mode can result in difficulties in controlling the output voltage of theconverter. A change of mode can occur depending on load changes.

Remark 2.3 If the filter were not present in Figure 2.2 then the output voltagewould exactly mirror the input voltage – i.e. if the switch is opened an closedthen the output would be a square wave voltage. The filter has to be designed sothat the cutoff frequency is significantly below the switching frequency. If this isthe case then the filter will reject most of the AC components present at the vod,so that the output voltage will essentially be a DC value equal to the averagevalue of the voltage vod.

Remark 2.4 One of the distinguishing features of this type of circuit is thatwhen the switch is closed the input is connected to the output, but when the buck converter dis-

tinguishing featuresswitch is open the input is disconnected from the output.Another distinguishing feature of the buck converter is that the inductor is

not placed across the input voltage when the switch is closed. The inductor has avoltage imposed across it that is usually somewhat lower than the input voltage.This means that the inductor does not store all the energy being supplied by theinput.

Remark 2.5 If multiple output voltages are required then the buck converter asdepicted here is not the topology to use. Other converters, such as the forwardconverter, that are related to the buck converter can be used.

Remark 2.6 Since the switch is at the input to the converter, then the in-put current is discontinuous. Therefore the input filter to this circuit is morecomplicated compared to other converter types.


Load

Low pass filter

Vd

Vo

iL

+ -v

LR

L

vod C

L

SWid

io

Energy storage

inductor

Figure 2.2: A basic buck or step-down converter.

Practical issue 2.1 Driving the gate of a buck converter can be a problem. Ifwe assume that the switching element is a n-channel MOSFET (as it would befor many designs), then the gate voltage often has to be 5V, and in some cases10V above the supply voltage. This complicates the gate drive, since one has tofabricate the higher voltage using a transformer based gate drive circuit.

2.3.2 Step-up or Boost Converters

As the name implies, the boost or step-up converter has an output voltage thatis always greater than the input voltage. The boost converter also has the addedoutput voltage that

is always greaterthan the input volt-age

advantage that the output can isolated from the input (using transformer iso-lation).

Figure 2.3 shows a conceptual diagram of a non-isolated boost converter.The basic operation mechanism is that when the switch is closed the load isisolated from the input by the diode, and current builds up in the inductor. Thiscurrent build is effectively storing energy in the field of the inductor. When theswitch is opened, the current in the inductor wishes to continue to flow in thesame direction and with the same magnitude. Therefore the diode will turn onand the current will immediately flow into the filter capacitor and any connectedload.

Remark 2.7 If the voltage on the capacitor is larger than the supply voltage,the inductor will produce what ever voltage is required so that Vd + vL = Vo.This is required in order for the current to continue to flow in the inductor.One can see that because the polarity of vL shown in Figure 2.3 always has toreverse for this situation, then the output voltage must always be greater thanthe input voltage (except under initial start-up conditions).

Remark 2.8 The main feature of the boost converter is that current can flowthrough the switch regardless of the relationship between the input and outputvoltages. This usually occurs because the input to the circuit is disconnectedfrom the output when the switch is closed. It is this feature that one must lookboost converter dis-

tinguishing features for when one is trying to ascertain what category a particular topology falls into.


SW

L

+ -

Vd

+

-

Vo

io

vL

C

Energy storage

iL

Figure 2.3: A basic boost or step-up converter.

When the switch is opened, the input is connected to the output because the diodeswitches on.

Another distinguishing feature is that when the switch is closed the inputvoltage is placed across the inductor (so that it stores all the energy being suppliedby the input), and when the switch is opened the inductor is placed in series withthe load. and this stored energy is transferred to the load.

Remark 2.9 In a boost converter the inductor fulfills an energy storage func-tion, whereas in the buck converter the inductor forms a filtering function.Therefore, one can view the boost converter as not having a filter capacitor.This distinction is not very clear for the non-isolated converter, but when welook at isolated converters in the next chapter we shall see that there is a cleardistinction.

Remark 2.10 There is a maximum power that is practical to build for convert-ers that rely on the energy storage principle. This is especially true for low inputvoltages. As we shall see in the next chapter a related converter is the flybackconverter, which operates using the same principle, and hence suffers from thesame power limitations. In order to cater for high power output with an energystorage converter, one needs to have a very small energy storage inductor (sinceE = 1

2Li2, and therefore the current contributes most significantly to the stored

energy). It turns out that for powers much above 50W when the input voltageis low, the inductance becomes very small and is comparable with the parasiticsof the circuit. Therefore, the circuit becomes very difficult to manufacture.

2.3.3 Buck–Boost Converters

The buck–boost converter seeks to combine the properties of the previous twoconverters. This converter type allows the output to be less than or greater thanthe input voltage. Furthermore, this type of converter also allows a negativepolarity output to be generated.

The most obvious way of generating a buck–boost converter is to cascadethe buck and the boost converter. In practice, however, this is not usually done,since one can obtain the same performance from the system using a single switch


arrangement. In this case one must really consider the circuit configuration tobe a new one, and not a combination of the previous two.1

In order to understand the operation of this circuit let us firstly look at a twoswitch implementation. Figure 2.4 shows the conceptual circuit for this. In thiscircuit both switches are either closed at the same time, or they are open at thesame time. If both the switches are closed, then the circuit takes on the classicboost converter configuration. If the output voltage is higher than the inputvoltage, current can still flow through the inductor. When both the switchesare opened, then the inductor is positioned in the circuit as in the classic buckconverter, and the current built up during the switch closed stage circulates viathe diodes through the output capacitor.

Remark 2.11 The key to the circuit of Figure 2.4 is that the switches effectivelychange the circuit configuration, from a boost circuit during the energy storagephase, to a buck circuit when energy is transferred to the load.

RLC

SW1

SW2

iL

+ -vL

Vo

io

Vd

L

Figure 2.4: Two switch buck–boost converter.

Figure 2.5 shows a simplified circuit for a buck-boost converter circuit usingonly one switch. The crucial change in this circuit is the swap of the inductorand the switch and the reversal of the diode as compared to the boost converterof Figure 2.3. The swapping of the inductor and the switch and reversing thediode means that the full input voltage is applied across the inductor when theswitch is closed (as in the boost converter). This means that the inductor isessentially a energy storage element, as in the boost converter. However, whenthe switch is opened the input is no longer connected to the supply (as is thesituation in the buck converter), and therefore the constraint that the outputmust be larger than the input is removed. The resultant voltage across thecapacitor is simply related to the amount of energy stored in the inductor, andthe current required by the load resistor. If one wishes to increase the outputvoltage then the switch is closed for a longer period of time, and it the voltageis to be decreased then the switch is closed for a shorter period of time.

Remark 2.12 One can see from the above explanation that the operation of thiscircuit has characteristics of both the buck and the boost converter. Reiterating,the energy storage in the inductor is from the boost converter (when the switch

1One must consider the buck-boost converter to be a configuration in its own right, sinceit is very difficult to see the separate buck or boost converters in the single switch circuits.


Vd

iL

io

RL

VoCL

+

-

vL

SWid

Figure 2.5: Single switch Buck–boost converter circuit.

is closed), and the disconnection of the input from the output when the switchis open is the same as the buck converter.

One can therefore identify a buck–boost topology by looking for the fact thatthe inductor is placed across the supply and disconnected from the load during theenergy storage phase when the switch is closed, and the inductor is disconnectedfrom the supply and placed in the output circuit when the switch is opened.

Remark 2.13 One should note that the voltages one can obtain from the buck–boost converter are related to the relationship between the load, the capacitor,and the inductor

.

Remark 2.14 The limitations on the performance of the buck-boost converterare very similar to those of the buck and the boost. In addition the presence oftwo diodes in the circulating current path can lead to inefficiency (even whenSchottky diodes are used).

2.3.4 Cúk ConvertersThis converters peculiar name arises from its inventor (pronounced Ch-ooo-k).It was arrived at by essentially forming a dual of the buck–boost converter.Similarly to the buck–boost converter it is capable of producing voltages thatare larger and smaller than the input voltage, and the output voltage is negativerelative to the same reference as the input voltage. One fundamental differenceis that the primary storage element is a capacitor, as opposed to the inductorin the buck–boost converter.

Figure 2.6 shows a basic Cúk converter. This circuit is slightly more difficultto understand. Therefore we shall consider two situations: one when the switchis closed, and the other when the switch is open.

Consider Figure 2.7, which shows the situation when the switch is open. Forthe sake of the discussion it shall be assumed that the current in the inductors


SW

L1

Vd

L2

RL

C

C1

iL

1

iL

2vC

1

vL

1

+ - +-v

L2

+ -

Vo

io

Figure 2.6: The Cúk converter.

is continuous. In this case the capacitor is charged by the current iL1flowing

from the input. The current iL2flowing on the load side of the circuit continues

to deliver energy to the load. Note that both iL1and iL2

would be decreasingunder this circuit condition.

Remark 2.15 The input current, iL1 , would be decreasing because the capacitorvoltage is greater than the input voltage. This can be deduced from the fact that:

vc1 = Vd + Vo (2.1)

Remark 2.16 Equation (2.1) results from the fact that the average voltageacross the inductors in the circuit must be zero under steady state conditions –the total volt-seconds change across an inductor must be zero over a completeswitching cycle under steady state conditions.

L1

L2

C RL

vL

1+ - v

L2

+-

iL

1iL

2

Vo

Diode is short circuit

+ -

vC

1

io

Vd

Figure 2.7: Cúk converter with the switch open.

Let us consider the situation when the switch is closed. The circuit under thiscondition is shown in Figure 2.8. Clearly the diode is reverse biased under thiscondition, and the input inductor, L1 is storing energy with the input voltage


L1

L2

RL

vL

1+ - v

L2

+-

iL

1 iL2

Vo

Switch is closed circuit

+ -

vC

1

io

Vd

C2

C1

Figure 2.8: Cúk converter with the switch closed.

appearing across it. The current, iL2 is also flowing through the switch. Thiscurrent to will be increasing with the capacitor voltage driving it. Therefore,the energy that has been stored in the capacitor is being transferred to the load.

Remark 2.17 The important point to note about the operation of the Cúk con-verter is that the capacitor C1 is the element that is actually transferring theenergy to the output (and not the inductor as in the other converters that wehave looked at). The inductors in the circuit are essentially performing a filter-ing function on the input currents.

Remark 2.18 Examination of Figures 2.7 and 2.8 indicate that the switch sim-ply transfers the capacitor from the input where it receives energy from the sup-ply, to across the load where it supplies energy to the load.

Remark 2.19 The capacitor in the Cúk converter has to be able to handle highripple currents.

2.3.5 Full Bridge Converters

This is the most complex of the converters, in terms of the number of semicon-ductor components, that we shall look at. It is also the most versatile, in that itcan find application in everything from SMCs to dc-to-ac drives. We shall onlybe considering the former of these two applications.

Figure 2.9 shows a conceptual diagram of the full bridge converter circuit.Notice that it has a total of eight semiconductors, with four of them beingunidirectional switches.

The application of a full bridge circuit depends on the control applied tothe bridge. One of the most important properties of the full bridge is that itoperates in all four quadrants of the iovo plane. This means that the convertercan produce positive and negative output voltage and positive and negativecurrent. The previous converters could only operate in one quadrant (positiveor negative voltage, and only positive current). This fact also means that the full


DC machine load

La

Ra

ea

+

-

SWA+

SWA-

SWB+

SWB-

DA+

DA-

DB+

DB-

i0

Leg A Leg B

vAN

vBN

v v vAN BN0

= -

N

Vd

Figure 2.9: Full bridge converter.

bridge converter can accept a dc input and produce an ac output (this mode ofoperation is known as inversion, and will not be discussed further at this stage).

One can see from Figure 2.9 that the switches have diodes in parallel withthem. This acknowledges the fact that the switches shown in the diagram areconsidered to be constructed of a technology that only conducts current in onedirection. It also means that if a switch is closed and the current is in thereverse direction then the current will flow through the diode and not throughthe switch.

There are two main switching strategies that can be adopted using the fullbridge inverter:

• Bipolar switching.

• Unipolar switching.

Bipolar switching is the name given to the switching strategy when the A+and B− are switched together, and the B+ and A− are switched together.Therefore the voltage applied to the load is ±Vd. There are no other voltagesthat can be applied. One can deduce that it the switching is such that 50% ofthe time the A+, B− is in force, and the remainder of the time the B+, A−state in in force, then the average voltage across the load is zero. By varyingthe switching around this the voltage can be varied from zero to Vd (when onlyA+, B− are in force) to −Vd (when only B+, A− are in force).

Remark 2.20 The full bridge converter can only produce output voltages thatare in the range of −Vd ≤ vo ≤ Vd.

Unipolar switching, on the other hand, exploits another degree of freedom avail-able in the full bridge to gain a lower current ripple in the output. One can

2.4 Basic Analysis of Switch Mode Converters 2-11

also switch two devices in different legs but on the same rail. For example, onecould switch the A+, B+ devices. This effectively places zero volts on the load,and allows the current to freewheel through one of the switches and the diodeparalleling the other device. The mode of operation clearly changes the rate ofchange the current as compared to the bipolar switching mode.

2.4 Basic Analysis of Switch Mode Converters

In this section we shall do some basic analysis of the converters mentioned inthe previous section. Before carrying out this analysis we shall firstly define theconcept of duty cycle, also known as mark-space ratio. We shall also introducethe concept behind the development of the switching waveforms. This work hasalready been presented in a general way in Section 1.3.2.2 on page 1-10, so someof what is below is a refresher of this presentation with an emphasis on thisparticular application of PWM.

2.4.1 Duty Cycle

Consider Figure 2.10, which shows a switching waveform. The duty cycle of thiswaveform is defined as:

D =tonTs

(2.2)

Considering the waveform in Figure 2.10 we can work out the average voltageproduced:

vave =1

Ts

∫ Ts

0

vodt

=1

Ts

∫ ton

0

Vddt+

∫ Ts

ton

0dt

=tonTsVd

= DVd (2.3)

From (2.3) one can see that the average voltage is directly proportional to theduty cycle of the switching.

2.4.2 Basic PWM Generator

In the previous section we defined the concept of a duty cycle. The next questionthat arises is: “how does one generate the switched output in a manner thata desired average output voltage is produced?”. The simplest technique, thatactually arose from the days of complete analogue PWM generators is to usea sawtooth or triangular waveform. This concept is shown schematically inFigure 2.11.

One can see from Figure 2.11 that the slope of the sawtooth is:

m =vstTs


ton

toff

Ts

Vd

v0

Vd

SW

t

v0

V0

R

0

ON OFF

Figure 2.10: Definition of the terms related to duty cycle.


Therefore one can say that:

ton =Vcontrolm

(2.4)

=Vcontrolvst

Ts (2.5)

One can see from (2.5) that:

D =Vcontrolvst

(2.6)

and hence:vave = DVd =

Vcontrolvst

Vd (2.7)

orvave ∝ Vcontrol

where the constant of proportionally is Vd/vst.

tontoff

Ts

ON OFF

Vcontrol

vst

Sawtooth waveform

Vd

Figure 2.11: Waveforms in a sawtooth based PWM modulator.

Remark 2.21 Note that if Vd = vst then the constant of proportionality is one.Therefore the average output voltage is the same as the control voltage. In mostPWM generators this is not the situation.

The circuitry required to perform the PWM generation using the waveformsof Figure 2.11 is very simple. Figure 2.12 shows a conceptual diagram of therequired circuit.

Remark 2.22 The PWM generator circuit shown in Figure 2.12 is usuallyimplemented using analogue circuitry. This can be done at a very low cost. Itcan also be implemented in a digital system.


Amplifier

Comparator

+

-

+

-

Vdesired

V0

vcontrol

Switchcontrol

Sawtoothwaveform

Figure 2.12: Simple PWM generator circuit.

2.4.3 Simplified Analysis of the Buck Converter

In this section we shall carry out a simplified analysis of the characteristics ofthe buck converter. The assumptions used are detailed later. However, oneobservation that can be made about the circuit is that the inductor/capacitorcombination in Figure 2.2 effectively form a low pass filter. This filter filters outthe harmonics in the switching waveform, which is of the form of Figure 2.10.For the filtering action to be effective, the -3db roll-off of the LC circuit has to besubstantially lower than the switching frequency of the inverter (i.e. fs = 1/Ts).This means that the effect of the switching on the output current is largelyeliminated, and the switching current is essentially dc. This fact forms the basisof one of the assumptions made later.

As mentioned Section 2.3.1 the buck converter can operate in continuousconduction mode or discontinuous mode. This term refers to the current in theinductor. In continuous mode, the current in the inductor never goes to zero,whereas in discontinuous mode the current will go to zero at some point in theswitching time Ts. Let us now consider each of these modes separately.

2.4.3.1 Continuous Conduction Mode

We shall assume that the circuit is in steady state for the development of theexpressions. If the circuit is in steady state then we immediately know that thesum of the volt-seconds applied across the inductor when the switch is closedplus the volt-seconds when the switch is open must equal zero.2 The waveformsand circuit configurations for the buck converter are shown in Figure 2.13.

Note 2.1 The following analysis assumes that the capacitor voltage essentiallyremains constant over a complete PWM cycle. This in turn implies that thevalue of the capacitor is large enough that it can absorb the charge supplied fromthe inductor current without significant voltage rise.

2This is true because λ =∫vdt, and the flux in the inductor must not increase over a

complete period for the circuit to be in steady state.


Remark 2.23 A consequence of the previous note is that over a complete cycleof the PWM the average current supplied by the inductor must be equal to theaverage current supplied to the load. If this were not the case then the capacitorvoltage would continually rise or fall over time as the circuit operated, therebyviolating the steady state assumption.

Notation 2.1 The capitalised currents and voltages in Figure 2.13 and the fol-lowing analysis refer to the average values of the currents, and not the instan-taneous values.

B

vL

t

t

V Vd o

-

-V0

iL

0

0

IL

iL

vL

vL

iL

ton t

off

+ - + -V

oV

oC C

L L

io

io

Vd

Vd

Ts

Io

A

Figure 2.13: Currents and circuit configurations for a buck converter.

Remark 2.24 As stated above the average inductor voltage over the completePWM interval has to be zero for steady state operation. Therefore, by inspectionof the inductor voltage plot in Figure 2.13 we can say that the volt-secondsapplied must be zero.3 Therefore:

(Vd − Vo)ton = Vo(Ts − ton) (2.8)

This expression can be rearranged to give: linear voltage gain

VoVd

=tonTs

= D (duty cycle) (2.9)

3Note the dc output voltage assumption appears in Figure 2.13 as the constant voltagesover each of the switching intervals.


Remark 2.25 Keeping in mind the assumptions in the above analysis, this(2.9) means that the output voltage varies linearly with the duty cycle, given afixed input voltage.

Remark 2.26 One could also obtain the relationship of (2.9) by averaging thevo voltage shown in Figure 2.10, realising that this voltage waveform is the formof the input waveform. The output is then obtained since the average inputvoltage has to be the same as the average output voltage for steady state toexist in the circuit (else the current through the inductor would be increasing ordecreasing over a number of cycles.)

By using conservation of energy one can also calculate the ratio of the inputand output currents. Assuming that the circuit is essentially lossless, then wecan say:

Pd = Po (2.10)

This can be clearly expanded as:

VdId = VoIo (2.11)

orIoId

=VdVo

=1

D(2.12)

Remark 2.27 As can be seen from (2.12) the buck converter acts the same asan electronic transformer when in continuous current mode.

Remark 2.28 Even though the current iL is fairly smooth, the input currentid is jumping from some peak value to zero every time the switch is opened.Depending on the source for the converter, the input may have to be filtered tosmooth out these current fluctuations.

2.4.3.2 Boundary between Continuous and Discontinuous Conduc-tion

In this section we shall establish the condition for the converter to move fromcontinuous to discontinuous conduction.

Discontinuous conduction occurs when the current iL goes to zero at orbefore the end of the control period. Consider the current waveform shownin Figure 2.14. One can formally work out that the average value of such awaveform is 1

2 iLpeak , which is also obvious using geometric arguments based onthe fact that the waveform is made up of triangles. Therefore one can derivethe following expression for the minimum average current that must be flowingin the circuit to sustain continuous conduction:

ILB =1

2iLpeak =

1

2L[(Vd − Vo)ton] =

DTs2L

(Vd − Vo) = IoB (2.13)

where ILB , is the minimum average inductor current, and IoB , the minimumoutput current value (remember the two are the same given the steady stateassumption).

Equation (2.13) can be further manipulated using the expression (2.9) toeliminate V0, and assuming that Vd is constant, giving:current required

for continuousinductor current


ILB = IoB =TsVd2L

(D −D2) (2.14)

On can differentiate (2.14) to find the duty cycle for the maximum ILB for givenVd, Ts, D, and L:

dILBdD

=TsVd2L

(1− 2D) (2.15)

Clearly from (2.15), the maximum value occurs at D = 12 Therefore using (2.14)

that value is:

ILBmax=TsVd8L

(2.16)

tont

off

iL

peak

iL

v V VL d o

= -( )

-Vo

0

Current is zero here

Ts

I ILB oB

=

t

Figure 2.14: Current waveform at the point of discontinuous current in theinductor.

Remark 2.29 Equation (2.14) defines the value of the average current requiredin the inductor to just allow continuous conduction. Therefore, the maximumvalue for this average current, which is the value defined in (2.16) occurs whenthe duty cycle is 1/2. This means that the onset of discontinuous current oper-ation occurs first if the duty cycle is around this value (which implies that theoutput voltage is 1

2Vd).

Remark 2.30 The previous remark implies that one can design the converterso that the minimum load current is larger than ILBmax

in order to ensure contin-uous conduction (assuming that continuous conduction is the desired operationmode). Note that one of the main design parameters is the inductance valueitself. Another point to note is that the input voltage is a parameter in (2.16),so if this voltage varies over a range then this must be taken into considera-tion. Finally, the load of the system will define the load current required, andvia the other considerations mentioned above it will define the parameters of theconverter.


Remark 2.31 There are two main cases to investigate in relation to discon-tinuous current – the constant Vd case and the constant Vo case. Let us nowconsider each of these.

2.4.3.2.1 Discontinuous Current with Constant Vd. In many applica-tions the input voltage remains constant, and only the output voltage is varied.We are interested in what the voltage gain of the inverter is under the conditionof discontinuous current. Note that we found that with continuous current thevoltage gain of the converter was D, and hence it operated linearly. However,as we shall see if the converter operates in discontinuous mode then the volt-age gain of the converter becomes non-linear. The following discussion is withreference to Figure 2.15.

D1T

s

iL

peak

iL

v V VL d o

= -( )

-Vo

0

Ts

I IL o

=

t

DTs

D2T

s

Current iszero here

Figure 2.15: Current waveform for a buck converter with discontinuous current.

In order to calculate the voltage conversion ratio, we firstly start by usingvoltage conversionratio the volt-seconds condition – i.e. the total volt-seconds over a control interval

must be zero for steady state operation:

(Vd − Vo)DTs + (−Vo∆1Ts) = 0 (2.17)

which leads to the following relationship for the voltage ratio:

VoVd

=D

D + ∆1(2.18)

The next relationship to establish is the value of the average current in theinductor under this condition depicted in Figure 2.15. We shall use a techniquesimilar to that used for (2.13). We must firstly get an expression for the peakinductor current. It can be seen from Figure 2.15 that iLpeak can be written as:

iLpeak =Vo∆1Ts

L


We are now in a position to calculate the average inductor current over a period.This is most easily carried out by calculating the area under the iL current inFigure 2.15 for a complete control cycle and dividing by Ts. Therefore we canwrite:

Io =12 iLpeak(DTs + ∆1Ts)

Ts(2.19)

=1

2iLpeak(D + ∆1) (2.20)

=1

2

Vo∆1TsL

(D + ∆1) (2.21)

Substituting for Vo using (2.18) one can manipulate (2.21) to give: average inductorcurrent discontinu-ous modeIo =

1

2

TsVdL

D∆1 (2.22)

Clearly this can also be expressed in terms of the minimum load current thatresults in discontinuous conduction using (2.16) to give:

Io = 4ILBmaxD∆1 (2.23)

We can now find an expression for ∆1 in (2.18) by rearranging (2.23) to give:

∆1 =Io

4ILBmaxD

(2.24)

Substituting (2.24) into (2.18) and rearranging we get the final expression forthe voltage ratio:

VoVd

=D2

D2 + 14

(Io

ILBmax

) (2.25)

Remark 2.32 The most notable feature of (2.25) is that the voltage ratio isnow non-linear. In other words there is a non-linear gain through the converter. voltage ratio is now

non-linearClearly this complicates the design of the control. Furthermore, the onset of non-linearity with the onset of discontinuous current would make the control evenmore difficult if the converter moved from continuous current to discontinuouscurrent operation.

Figure 2.16 is a plot of (2.25) in the discontinuous region, and (2.9) in thecontinuous region.

Remark 2.33 As noted in the previous remark, the voltage ratio to duty cyclerelationship for discontinuous operation can be seen, from Figure 2.16, to bevery non-linear .

2.4.3.2.2 Discontinuous Current with Constant Vo. In many applica-tions the output voltage should be kept constant whilst the input voltage varies.An example of this type of application is a traditional switch mode power supply(SMPS), where the power supply should keep a constant voltage output despite constant voltage

outputvariations of the mains supply voltage.


0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

0.2

0.4

0.6

0.8

1 Boundary for onset of

discontinuous current

D =10.

D = 0 9.

D = 0 8.

D = 0 7.

D = 0 6.

D = 0 5.

D = 0 4.

D = 0 3.

D = 0 2.

D = 01.

D = 0 0.

I

I

o

LBmax

V

V

o

d CONTINUOUS

CURRENT

REGION

DISCONTINUOUS

CURRENT

REGION

Figure 2.16: Voltage ratio of the buck converter for continuous and discontin-uous operation modes and constant Vd. NB. ILBmax

= TsVd8L


If one uses (2.14) and the linear voltage ratio (2.9), one can calculate thevalue of the current at the edge of continuous current conduction in the inductor.Substituting for Vd in (2.14) one gets:

ILB =TsVo2L

(1−D) (2.26)

which clearly has a maximum at D = 0, giving:

ILBmax =TsVo2L

(2.27)

Remark 2.34 Note that (2.27) is the expression for ILBmaxin terms of Vo

whereas the expression (2.14) is in terms of Vd. In (2.27) the assumption isthat Vo is constant (held there by the control of D), and Vd is totally variable.

Remark 2.35 Operation at D = 0 for a constant finite Vo is a mathematicalartifact, since this would imply that Vd =∞ (given that D = Vo/Vd in continu-ous current mode).

Using (2.26) and (2.27) we can write:

ILB = (1−D)ILBmax(2.28)

Using (2.18), (2.21), and (2.27) one can write the following expression (notethat both (2.18) and (2.21) are valid regardless of the constraint on Vd or Vo).Now from (2.18) we have:

Vo =DVd

D + ∆1(2.29)

Substituting into (2.21) one can write:

Io =TsVd2L

D∆1 (2.30)

Using (2.27) we can write:

Ts2L

=ILBmax

Vo(2.31)

Substituting this into (2.30) we get:

Io =ILBmax

VdD∆1

Vo(2.32)

which can be manipulated to give:

∆1 =Io

ILBmax

VoDVd

(2.33)

which can be substituted back into (2.18) and manipulated to give:

D =VoVd

(Io

ILBmax

1− VoVd

) 12

(2.34)


0 0.2 0.4 0.6 0.8 1 1.20

0.2

0.4

0.6

0.8

1

V

V

d

o

= 125.

V

V

d

o

= 15.

V

V

d

o

= 2 0.

V

V

d

o

= 3 0.

V

V

d

o

= 4 0.

V

V

d

o

= 5 0.

DISCONTINUOUS

CURRENT

REGION

CONTINUOUS

CURRENT

REGIOND

I

I

o

LBmax

Figure 2.17: Characteristics of the buck converter with constant Vo. NB.ILBmax

= TsVo2L .


Remark 2.36 As can be seen from (2.34) the relationship between D and Vo/Vdis again highly non-linear. As in the constant Vd case, the control for constantVo would be much simpler if operation is maintained in the continuous currentmode.

Remark 2.37 The ILBmaxin Figure 2.17 is different from that in Figure 2.16.

Figure 2.17 shows the inter-relationship between the duty cycle, load currentand inverse voltage ratio for the buck converter. The non-linearity in the dis-continuous current region of operation is very evident from the figure.

Remark 2.38 Figures 2.16 and 2.17 are actually equivalent. For example, atD = 0.5 in Figure 2.16 Vo

Vd= 0.5 and Io

ILBmax(D=0.5)

= 1. The corresponding

point in Figure 2.17 is VdVo

= 2 (i.e. VoVd

= 0.5), D = 0.5 and IoILBmax(D=0)

= 0.5.

The latter can be seen from (2.27) and (2.16) as follows. From (2.16):

ILBmax(D=0.5)=TsVd8L

=TsVoD8L

(using Vd =VoD

) (2.35)

=TsVo4L

(for D = 0.5) (2.36)

=1

2ILBmax(D=0)

(2.37)

Correspondence can be found for all the other points.

2.4.3.3 Output Ripple

In the analysis thus-far we have assumed that the capacitor is large enoughthat the voltage at the output does not change substantially. This was anapproximation that made the analysis simpler, but in reality is not true. Inmany applications that ripple at the output is important – for example, inpower supply applications many circuits cannot tolerate significant ripple.

In order to get a feel for the voltage ripple we shall assume that the current voltage rippleis continuous. A further simplification is that the impedance of the capacitor isvery much lower than the load resistance, and therefore we can assume that theac component of the current ripple all flows into the capacitor, and the averagecurrent over a switching interval flows into the resistor. The following analysisis with reference to Figure 2.18.

Remark 2.39 One can immediately see from Figure 2.18 that we are assumingthat the ripple is small enough to be insignificant compared to the voltage acrossthe inductor – hence the inductor voltages are drawn as piecewise constant.

Remark 2.40 One could also carry out a complete circuit analysis for the buckconverter and get very precise voltage ripple waveforms. The equations for thisare straight forward, but just a little messy.


vL

V vd o-

-vo

Ts

0

DIL

2

Ts

2

t

t

iL

I IL o

=

vo

t

0

0

DQ

DVoVo

Figure 2.18: Output voltage ripple for a buck converter.


The output voltage ripple expression can be developed using a capacitor chargeapproach:

∆Vo =∆Q

C=

1

C

(1

2

∆IL2

Ts2

)(2.38)

The next step is to get an expression for ∆IL. From the definition of the voltageacross an inductor we can say the following:

∆IL =vL∆t

L(2.39)

Considering the off time, we can carry out the following calculations. If ∆t =toff, and we can write toff = Ts − ton, and ton = DTs (from (2.2)) then we get∆t = toff = (1−D)Ts. Using this expression, and the fact that vL = Vo we canwrite:

∆IL =VoL

(1−D)Ts (2.40)

Substituting this expression into (2.38) we can write the following expressionfor the voltage ripple:

∆Vo =Ts8C

VoL

(1−D)Ts (2.41)

∴∆VoVo

=1

8

T 2s (1−D)

LC(2.42)

This expression can be further manipulated into a form that highlights thefiltering requirements of the LC combination. Realising that:

fc =1

2π√LC

(2.43)

then (2.42) can be written as:

∆VoVo

=π2

2(1−D)

(fcfs

)2

(2.44)

where fs = 1/Ts.

Remark 2.41 Equation (2.44) emphasises that fact that making the filter poleof the LC filter circuit much smaller than the frequency of the PWM results ina lower output voltage ripple.

Remark 2.42 Note that (2.44) indicates that the ripple is independent of theaverage inductor current (in continuous conduction mode). Therefore, keepingin mind the assumptions made in the analysis, the load on the inverter doesnot influence the amount of ripple. The most relevant of these assumptions inrelation to this issue is that the capacitor impedance is much lower than that ofthe load.

2.4.3.4 Simulation

One can set up a computer simulation of the buck converter circuit. The partic-ular simulator used for this exercise is the Saberr by Analogy. The circuit setup in the simulator is shown in Figure 2.19. The switching device is modeled


by a switch which has a very high off resistance, and a very low on resistance.The diodes in the circuit are essentially ideal, in that they have a zero turn onvoltage.

v_oswitch_output_voltage

v_dc 10

BITSTREAM

prbit_l4

pwld

100e-6

50e-3

40000

sw1_l4

pwld sw1_

l4

100

BITSTREAM

prbit_l4

Figure 2.19: Circuit used in simulation of the buck converter.

If the load is set at 100Ω, the switching duty cycle to 0.5, and the switchingfrequency to 100kHz, then the plot of Figure 2.20 results. Note that this lowvalue of load resistance ensures that the current is continuous in the inductor.The plots shows the initial startup transient (that was missing from the steadystate analysis that we have carried out above). Once the transient has diedaway then the output voltage settles to the 5 Volt level that is predicted fromthe theory. The inductor current settles to the load current, which is Io =5/100 = 0.05 Amp. Notice that the capacitor current is essentially zero. Ifone magnifies the graph it can be seen that the capacitor is absorbing the accurrents resulting from the high frequency switching.

Remark 2.43 One can also simulate the performance of the buck converter ifthere is discontinuous current flow in the inductor. However, the simulationtime required for the system to go into steady state is very long due to a problemwith the initial transient. This phenomena can be seen in Figure 2.21 whichshows the currents for a 50% duty cycle and a load resistance of 40kΩ. Noticethat we get an initial LC transient which leaves the capacitor with a charge ofapproximately 9 Volts (i.e. about twice the applied average voltage of 5 Volt).Once this voltage has appeared on the capacitor it can only dissipate via the loadresistor. Therefore the time for the voltage to decay to the steady state value isof the order of 4 to 5 seconds.

Remark 2.44 The slow transient that is evident in Figure 2.21 would not occurin a practical discontinuous mode buck converter. It occurs in the example casebecause the converter control is open loop. In a practical converter the duty cycleis varied depending on the error between the output voltage and the desired outputvoltage, so as to force the output voltage to the desired.


(V)

0.0

2.0

4.0

6.0

8.0

10.0

t(s)

0.0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225

(A)

-0.2

0.0

0.2

0.4

(A)

-0.2

0.0

0.2

(V) : t(s)

v_o

(A) : t(s)

Inductor cur

(A) : t(s)

Capacitor cur

Figure 2.20: Waveforms for a buck converter with D = 0.5, RL = 100, andcontinuous inductor current.

(V)

0.0

2.0

4.0

6.0

8.0

10.0

(A)

-0.2

0.0

0.2

(A)

-0.2

0.0

0.2

t(s)

0.0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225

(0.11243, 167.57u)

(0.11243, 70.099u)

(0.11243, 8.8035)

(V) : t(s)

v_o

(A) : t(s)

Inductor cur

(A) : t(s)

Capacitor cur

Figure 2.21: Initial startup waveforms for a buck converter with D = 0.5,RL = 40kΩ, and discontinuous inductor current.


2.4.4 Simplified Analysis of the Boost Converter

In a manner similar to the analysis of the buck converter we shall also analysethe basic properties of the boost converter. The converter analyzed is thatshown in Figure 2.3. As with the buck converter there are two cases to consider– the continuous inductor current case, and the discontinuous inductor currentcase.

2.4.4.1 Continuous Conduction Mode

The following discussion is in relation to Figure 2.22. Using the same approachas with the buck converter, we can say that in steady state that the time integralof the voltage across the inductor over a complete switching period is zero.Therefore, by inspection of Figure 2.22 we can write:

Vdton + (Vd − Vo)toff = 0 (2.45)

Rearranging this gives the voltage ratio of the converter:boost convertervoltage ratio

VoVd

=Tstoff

=1

1−D(2.46)

Assuming a lossless circuit we can say that Pd = Po, and hence:

VdId = VoIo (2.47)

which can be rearranged to give the current ratio of the converter:boost current ratio

IoId

= (1−D) (2.48)

Remark 2.45 Equation (2.46) indicates that the voltage ratio goes to infinityif D = 1. This arises from the fact that the steady state assumption means via(2.45) that the output voltage becomes increasingly large as D → 1.

Remark 2.46 Equation (2.46) indicates that the voltage ratio is not linear fora boost converter. A plot of the voltage ratio is shown in Figure 2.23. Note thevery large increase in the voltage ratio as D → 1. In reality this increase does notoccur. The analysis that lead to (2.46) involved ideal components. However, ifone includes resistance in the inductors and capacitors, and accounts for the verypoor switch utilisation under large duty cycles, then as D → 1, then Vo/Vd → 0,and not ∞.

2.4.4.2 Boundary between Continuous and Discontinuous Conduc-tion

The following discussion is with reference to Figure 2.24. This figure shows thecurrent waveform at the edge of continuous conduction. Following an analysistechnique similar to that for the buck converter, we can write that the averagevalue of the inductor current at this boundary is:inductor current

continuous currentboundary


B

vL

t

t

Vd

iL

0

0

IL

iL

vL

vL

iL

ton t

off

+ - + -V

oV

oC C

L L

io

io

Vd

Vd

Ts

A

V Vd o

-

Figure 2.22: Currents and circuit configurations for a boost converter.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

10

20

30

40

50

60

70

80

90

100

D (Duty Cycle)

V

V

o

d

Figure 2.23: Voltage ratio of a boost converter versus duty cycle.


ILB =1

2iLpeak (2.49)

=1

2

VdLton (2.50)

=TsVo2L

D(1−D) (2.51)

Equation (2.51) can be further manipulated by realising that the inductor cur-rent and the input current in this converter are the same (i.e. id = iL). Thereforeusing (2.48) we can say that Io = (1−D)IL, and hence:output current

continuous currentboundary IoB =

TsVo2L

D(1−D)2 (2.52)

tont

off

iL

peak

iL

v VL d

=

V Vd o

-

0

Current is zero here

Ts

ILB

t

Figure 2.24: Current waveform on the edge of continuous current.

If we consider that the output voltage of the boost converter is kept constant,then one can differentiate (2.51) and equate to zero to get the value of D = 0.5for the maximum value of inductor current at the edge of continuous conduction.This value of current is:maximum inductor

continuous currentboundary

ILBmax=TsVo8L

(2.53)

Similarly, one can differentiate (2.52) and equate to zero to get the maximumvalue of IoB at D = 1/3. The value of IoB is:maximum output

continuous currentboundary IoBmax

=2

27

TsVoL

= 0.074TsVoL

(2.54)

Both ILB and IoB can be expresses as follows in terms of their maximum values:

ILB = 4D(1−D)ILBmax (2.55)

IoB =27

4D(1−D)2IoBmax

(2.56)


If we normalise (2.51) and (2.52) using (2.53) we can get the plot shown inFigure 2.25.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1

3

D

ILB

IoB

I IoB LBmax max

= 0 59.

ILBmax

I

ILBmax

Figure 2.25: Plot of the normalised continuous current boundary for the boostconverter (Vo constant).

Remark 2.47 Figure 2.25 can be interpreted in the following way. If the cur-rent in the inductor is less than ILB then the converter will begin to operatewith discontinuous inductor current. This translates to the output current be-ing less than IoB, since the inductor current is not the output current for thistype of converter. Notice that the largest value of the continuous output currentboundary occurs at D = 0.33, which does not correspond to the point where thelargest value of the continuous inductor current boundary occurs. This is due tothe fact that the inductor current does not linearly relate to the output current.

Remark 2.48 Figure indicates that for continuous current flow in the inductor,either keep the inductor current above ILB, or the output current above IoB. Ifthe output is above IoB, then IL is above ILB, and vice-versa.

2.4.4.2.1 Discontinuous Current with Constant Vd. We shall assumethat Vd and D remain constant as the output load varies. Under normal operat-ing conditions there would be a controller that would vary D so as to maintain


Vo constant despite load variations. However, the above assumptions allow aneasier understanding of the discontinuous current condition.

The following discussion is with reference to Figure 2.26 which shows thecurrent under the discontinuous current condition.

D1T

s

iL

peak

iL

v VL d

=

V Vd o

-

0

Ts

IL

t

DTs

D2T

s

Current iszero here

Figure 2.26: Current waveforms for the boost converter with discontinuouscurrent.

The integral of the voltage over one control interval must be equal to zero forthe circuit to be in steady state. Therefore we can write the following equation:discontinuous volt-

age ratioVdDTs + (Vd − Vo)∆1Ts = 0 (2.57)

∴VoVd

=∆1 +D

∆1(2.58)

Again using the fact that the converter is assumed to be lossless, then we cansay Pd = Po, and hence the current ratio under discontinuous operation is:discontinuous cur-

rent ratioIoId

=∆1

∆1 +D(2.59)

If we consider Figure 2.26, and using the fact that the current waveform canbe broken down into a number of triangles, we can calculate the average inputcurrent. The peak current is:

iLpeak =VdDTsL

(2.60)

and hence the average input current can be deduced to be:discontinuous aver-age input current

Id =VdDTs

2L(D + ∆1) (2.61)


Using (2.59) one can write the average output current expression as:discontinuous aver-age output current

Io =

(TsVd2L

)D∆1 (2.62)

We can use (2.58), (2.62) and (2.54) to get an expression for the duty cycle interms of the voltage ratio and the output current. From (2.54) we can write:

TsL

=27

2VoIoBmax (2.63)

and from (2.58) one can write:

∆1 =D

VoVd− 1

(2.64)

Substituting both of these into (2.62) and manipulating one can get the expres-sion: discontinuous duty

cycleD =

√4

27

VoVd

(VoVd− 1

)Io

IoBmax

(2.65)

Using (2.65) we can develop a plot of D versus Io/IoBmax for various Vo/Vd.The normal operating mode would be that Vo is constant, and Vd is varying.The development of this plot is slightly complicated due to the fact that theIo/IoBmax

for discontinuous current is a function of the duty cycle. Using (2.56)and (2.65) it is possible to get the following expression for the limit on the dutycycle for discontinuous conduction, for a given value of Vd/Vo:

Dlim =

[2− 1

1x (1− 1

x )

]±√[

2− 11x (1− 1

x )

]2− 4

2(2.66)

where x = VdVo

. The negative of the two solutions gives a value of D in the validrange of 0 → 1. This sets the limit on the D values, and therefore a limit onthe Io/IoBmax range via (2.56). The characteristics of the boost converter witha constant Vo are shown in Figure 2.27.

Remark 2.49 One can see from Figure 2.27 that the duty cycle has a highlynon-linear relationship to the output current in the discontinuous region of oper-ation. Once outside this region the duty cycle is constant for a particular voltageratio output.

2.4.4.3 Simulation

To complete this section on the boost converter we shall construct a simulationof the circuit shown in Figure 2.28. The circuit simulated has the switch outputswitch closed, therefore the load resistance is approximately 100Ω.

The voltage output of the circuit, inductor current, load current, and en-ergy stored in the output capacitor and with a 50% duty cycle is shown inFigure 2.29. Notice that the output voltage is 2Vd, as one would predict from(2.46). After the initial startup transient the energy in the capacitor settles


0 0.2 0.4 0.6 0.8 1 1.20

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

DISCONTINUOUS

CURRENT REGION

CONTINUOUS

CURRENT REGION

I

I

o

oBmax

D

V

V

d

o

= 01.

V

V

d

o

= 0 25.

V

V

d

o

= 0 5.

V

V

d

o

= 0 75.

V

V

d

o

= 0 9.

Figure 2.27: Duty cycle versus normalised output current for the boost con-verter with constant Vo.


to a dc value, indicating that the circuit is now in steady state. The inductorcurrent is essentially constant, which means that the current being pulled fromthe supply is very close to constant.

The effect of applying several different duty cycles when there is continuousconduction is shown in Figure 2.30. Again the simulation output conformsalmost exactly to the predicted values of the output using (2.46).

v_o

v_dc 10

BITSTREAM

prbit_l4

100e-6 40000

sw1_

l4

100

BITSTREAM

prbit_l4

50e-3

sw1_

l4

pwld

Figure 2.28: Boost converter simulated using Saberr.

(V)

0.0

20.0

40.0

t(s)

0.0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22

(A)

0.0

0.2

0.4

0.6

0.8

(A)

0.0

0.2

0.4

(J)

0.0

0.02

0.04

(V) : t(s)

v_o

(A) : t(s)

(A) : t(s)

(J) : t(s)

Inductor cur

Cap energy

I_o

Figure 2.29: Simulated waveforms for a boost converter with D = 0.5 andcontinuous current.


(V)

0.0

10.0

20.0

30.0

40.0

50.0

60.0

t(s)

0.0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225

(V) : t(s)

v_o;D=0.5

v_o;D=0.8

v_o;D=0.2

Figure 2.30: Output of a boost converter in continuous current mode withseveral different duty cycles.

2.4.5 A Brief Look at the Buck-Boost ConverterWe shall not carry out a complete analysis of the buck-boost converter. We canconsider the buck-boost converter can be considered to be a cascade of a buckconverter and a boost converter. Therefore, assuming that both converters areoperated with the same duty cycle, that the current conduction is continuous,then the output voltage ratio is simply the cascade of the two expressions alreadyderived for the buck and boost converters:buck-boost voltage

ratio VoVd

=D

1−D(2.67)

As with the previous converters, if we use the lossless converter assumption wecan get the current ratio for the buck-boost converter as:buck-boost current

ratioIoID

=1−DD

(2.68)

Equation (2.67) can easily be shown to hold for the single switch version of theconverter as in Figure 2.5. The situation with discontinuous current is morecomplex, and cannot be considered to be a cascade of the individual convertersunder this condition.

2.4.6 A Brief Analysis of the Cúk ConverterThe following analysis is with reference to Figures 2.6, 2.31, 2.7 and 2.8. Itis assumed in the following analysis that the voltage on the capacitor VC1

isconstant. This implies that the capacitor is fairly large.


vL1

vL2

iL1

iL2

t

t

t

t

0

0

0

0

OFF

ON

ON

OFF

Vd

V V Vd C o

- = -

1

V VC o

1

-

-Vo

IL1

IL2

( )1- D Ts

DTs

( )= ton ( )= toff

Figure 2.31: Steady state currents and voltages in a Cúk converter.


Under the constant VC1and steady state operation assumptions, the integral

of the voltages across the inductors must be zero. Therefore we can write:

VdDTs + (Vd − VC1)(1−D)Ts = 0 (2.69)

∴ VC1 =1

1−DVd (for L1) (2.70)

and

(VC1− Vo)DTs + (−Vo)(1−D)Ts = 0 (2.71)

∴ VC1 =1

DVo (for L2) (2.72)

Using (2.70) and (2.72) we can write:Cúk voltage ratio

VoVd

=D

1−D(2.73)

As with the previous converter analysis, if we assume that the converter islossless, then we can develop the current ratio:Cúk current ratio

IoId

=1−DD

(2.74)

Remark 2.50 Equations (2.73) and (2.74) are the same as those for the buck-boost converter.

One can calculate the current and voltage ratios using an alternate techniquebased on the charge transferred by the capacitor. This technique is illuminatingin that it emphasises the fact that it is the capacitor that is storing the energythat is being transferred from the source to the load. It shall be assumed thatthe inductors, L1 and L2, are large enough that the ripple in the currents canbe ignored – i.e. iL1 = IL1 and iL2 − IL2 . If the circuit is in steady state thenthe total charge delivered to the capacitor over a complete control interval iszero. This can be expressed mathematically as follows:

IL1(1−D)Ts − IL2DTs = 0 (2.75)

∴IL2

IL1

=IoId

=1−DD

(2.76)

Using the lossless argument once again (Po = Pd), then one gets:

VoVd

=D

1−D(2.77)

2.4.7 Full Bridge dc-dc Converter

We shall now consider the calculation of the output voltage ratio and currentsfor the full bridge dc-dc converter. As was previously noted, this converter iscapable of producing both ac and dc outputs, but in this analysis we shall onlyconsider dc output. The following discussion is with respect to Figure 2.9.


Assuming that the switches are switched in such a way that the current iscontinuous in the load, then the output voltage is only a function of the switchstates. Let us consider Leg A in Figure 2.9. If switch SWA+ is closed and ifio is positive then the current will flow through SWA+. If io is negative thenthe current will flow through DA+. In either case, the Leg A load connection isconnected to the positive rail of the dc supply. Therefore:

vAN = Vd (for SWA+ on and SWA− off) (2.78)

Remark 2.51 The assumption stated above essentially means that one of theswitches in a leg is switched on at a particular instant of time. As we shall seelater, if both switches are open in a leg, then the output voltage is no longer afunction of the switch states, but depends on the direction of the load currentfrom the leg.

The alternative switching position for Leg A is SWA+ off and SWA− on. Inthis case a positive current flows through DA− and a negative current throughSWA−. Hence in both cases the Leg A load connection is connected to the nega-tive of the supply, which is also the reference point for the voltage measurements.Therefore:

vAN = 0 (for SWA− on and SWA+ off) (2.79)

Remark 2.52 Expressions (2.78) and (2.79) indicate that the output voltageis dependent only on the status of the switches, and not on the direction of thecurrent.

Given Remark 2.52 then the output voltage of Leg A averaged over a completeswitching cycle Ts, depends only on the input voltage Vd and the duty ratio ofSWA+. Therefore the average Leg A voltage is:

VAN =Vdton + 0 · toff

Ts= Vd · duty cycle of SWA+ (2.80)

Similar arguments apply to Leg B. Therefore VBN is:

VBN = Vd · duty cycle of SWB+ (2.81)

independent of io.Given VAN and VBN , then we can calculate the output voltage for the con-

verter as follows:Vo = VAN − VBN (2.82)

Equation (2.82) is a general expression for the output voltage.It was mentioned in Section 2.3.5 that there are two main strategies for

arranging the switching in full bridge converters. We shall now investigatethese strategies in detail.

2.4.7.1 Bipolar Switching

This is a switching strategy where the top switch in one leg is closed and thebottom switch in the other leg is closed. Therefore the switches are grouped asdiagonal pairs in Figure 2.9.


In a manner similar to that shown in Section 2.4.2, the PWM for bipolarswitching is implemented conceptually by comparing a reference voltage with atriangular waveform. We can work out the output voltage of the converter withthis type of switching with the aid of Figure 2.32.

In the bipolar converter the basic algorithm is that when the control voltageis greater than vtri then SWA+ and SWB− are turned on. If the control voltageis less than vtri then SWA− and SWB+ are turned on. The logic behind thisswitching algorithm, is that the triangular switching waveform can be consideredto be a scaled version of the integral of the leg waveform with respect to thevoltage reference point. Therefore, for a particular leg voltage one has to simplyfind the scaling factor for the control voltage or the triangular wave.

From Figure 2.32A we can see that:

vtri = Vtri1(Ts4

) t (2.83)

At the switching time t1 one can see that vtri = vcontrol. Substituting this intothe above expression we can write:

t1 =vcontrol

Vtri

Ts4

(2.84)

Again referring to Figure 2.32A we can see that the total on time for Leg A ofthe inverter is:

ton = 2t1 +1

2Ts (2.85)

We can now use (2.2) to give the duty cycle for the SWA+ and SWB− switchpair:Leg A duty cycle

D1 =tonTs

=1

2

(1 +

vcontrol

Vtri

)(2.86)

The duty cycle for the SWB+ − SWA− leg (i.e. leg B) is therefore:Leg B duty cycle

D2 = (1−D1) (2.87)

Using (2.82) we can write:

Vo = D1Vd −D2Vd = (2D1 − 1)Vd (2.88)

which becomes, substituting (2.86) :full bridge bipolaroutput voltage

Vo =Vd

Vtrivcontrol = kvcontrol (2.89)

Remark 2.53 Equation 2.89 indicates that the output voltage is linear withrespect to the control voltage. This makes the control of the converter fairlysimple.

Remark 2.54 From Figure 2.32 it can be seen that the voltage across the loadis bipolar in nature, hence the name of this switching strategy. It should also benoted that the fact that the voltage is going from positive to negative will resultin higher ripple in the output current, as compared to any strategy that keepsthe voltage unipolar.


vtri

vAN

vBN

v v vo AN BN

= -

Io+ ve

Io

- ve

t

t

t

t

Vd

Vd

Vd

-Vd

Vo

t

t

vcontrol

t1

t1

Ts

Ts/ 2

100110 01 10

10 10 1001 01

10 01 10 01 10

Io

-Io

$Vtri

SW

SW

A

B

+

-

D

D

A

B

-

+

SW

SW

A

B

-

+

D

D

A

B

+

-

SW

SW

A

B

+

-

io

io

SW

SW

A

B

+

-

D

D

A

B

+

-

SW

SW

A

B

-

+

SW

SW

A

B

+

-

D

D

A

B

-

+

A

B

C

D

E

F

Figure 2.32: Waveforms for a full bridge converter with a bipolar switchingstrategy.


Remark 2.55 From (2.88) it can be seen that as the duty cycle D1 is variedfrom 0 to 1 the output voltage varies from −Vd to Vd. This variation is indepen-dent of the direction of the current, although different switching components areresponsible for the conduction of the current depending on the current direction.This can be seen from Figure 2.32E and F, where the various conduction devicesare shown.

2.4.7.2 Unipolar Switching

An alternative switching strategy to the bipolar strategy is the unipolar strat-egy. This switching strategy takes into account another degree of freedom ascompared to the bipolar strategy. The basic idea of this switching strategy isto keep the voltage across the load unipolar if the desired voltage is unipolar.This is achieved by the voltage switching from Vd to 0.

Examination of Figure 2.9 indicates that there are two basic strategies forobtaining unipolar operation. For example, assuming that the current directionis positive, then one can have switch SWB− switched on, and then open andclose SWA+ depending on the average voltage that one desires. This wouldresult in the voltage across the load going from Vd with SWA+ closed, and 0with SWA+ open (and hence SWA− closed). The other strategy is to switch legB. For example, assuming the same current direction, one could open SWB−(and hence close SWB+), the current then circulating through via SWA+ andDB+.

Both of the above switching strategies are employed in the switching algo-rithm drawn in Figure 2.33. One could use a switching scheme similar to that ofthe bipolar case, where one has a unipolar control voltage. In this case only oneof the two switching patterns could be easily incorporated. This would result ina larger output voltage for unipolar switching as compared to bipolar switching.Both of the switching strategies could be used however, if one has the bipolarcontrol voltage shown in Figure 2.33. The switching times are determined asfollows:

SWA+ closed if: vcontrol > vtri (2.90)

and

SWB+ closed if: − vcontrol > vtri (2.91)i.e. vtri < −vcontrol (2.92)

This switching strategy allows both the positive and negative parts of the trian-gular waveform to be utilised. The net result of switching using this strategy isshown in Figure 2.33C. As compared to the bipolar strategy, or a unipolar strat-egy where only one of the switching options are used, the switching frequencyhas effectively been doubled without actually changing the switching frequencyof the switches themselves.

Remark 2.56 The effective doubling of the switching frequency means that theripple in the current using the unipolar strategy is less than the ripple using thebipolar strategy.

Examination of the waveforms in Figure 2.32B and C and Figure 2.33B andC indicate that the duty cycles are the same for the unipolar case and the bipolar


vtri

vAN

vBN

v v vo AN BN

= -

Io+ ve

Io

- ve

t

t

t

t

Vd

Vd

Vd

-Vd

Vo

t

t

vcontrol

t1

t1

Ts

1000

10 10

10

Io

-Io

$Vtri

io

io

SW

SW

A

B

+

-

A

B

C

D

E

F

-vcontrol

t1

t1

t1

1110 0000 10 11

11 10 00 10 11

10 00 10 11 10 00 10 11

D

SW

A

B

-

-

21

t 21

t

SW

D

A

B

-

-

D

D

A

B

+

-

SW

SW

A

B

+

-

D

D

A

B

+

-

D

SW

A

B

-

-

SW

SW

A

B

+

-

SW

D

A

B

-

-

D

D

A

B

+

-

Figure 2.33: Waveforms for a full bridge converter with a unipolar switchingstrategy.


case (the VAN and VBN waveforms are the same in both cases). Rewriting thesefor convenience:full bridge duty cy-

cleD1 =

1

2

(vcontrol

Vtri+ 1

)(2.93)

andD2 = 1−D1 (2.94)

Clearly then in this case the output voltage is exactly the same as that of thebipolar case – i.e.:full bridge unipolar

output voltageVo = (2D1 − 1)Vd =

Vd

Vtrivcontrol (2.95)

Remark 2.57 Because of the effectively higher switching frequency of the unipo-lar strategy, it is the preferred method of switching for these types of converters.

2.4.8 Comparison of Basic Converter Topologies

In this section we shall attempt to compare the basic converter topologies in-troduced in this chapter. This comparison is somewhat limited, as there area great many topologies that fall into these general categories of those intro-duced, that in particular applications have advantages over others. Neverthelessthis somewhat theoretical comparison is beneficial in that it highlights some ofthe fundamental structural differences between the converters, and in additionintroduces some of the metrics used for carrying out comparisons.

One of the first points to notice about most of the converter structures thatwe have looked at is that they produce unipolar output voltages. There is oneexception to this – the full bridge converter. In addition to the unipolar opera-tion, all except the full bridge converter can only handle current in one direction;into the load. Therefore the buck, boost, buck-boost and Cúk converters aresaid to operate in one quadrant of the iovo operation plane. The full bridgeconverter on the other hand can operate on all four quadrants of the iovo plane.

2.4.8.1 Switch Utilisation

One of the important metrics of power electronic devices is the switch utilisation.This refers to how well a particular converter topology uses the voltage andcurrent ratings of the semiconductor switches used. If a switch is poorly utilisedthen a larger semiconductor switch must be used for a given power output forthe converter. This corresponds to more expensive switches.

In order to calculate the switch utilisation for the previous converters wefirstly need a few assumptions:

1. The average current is at its rated value of Io. The ripple in the currentcan be ignored.

2. The output voltage is ripple free and is at a constant rated value of Vo.

3. The input voltage is allowed to vary and the duty cycle is varied by acontrol algorithm to keep the output voltage at its fixed rated value.


Given these assumptions the peak switch voltage VT and current IT are calcu-lated. The switch peak power rating is then calculated as PT = VT IT . Theswitch utilisation is then calculated as:switch utilisation

definitionUs =

PoPT

(2.96)

where Po = VoIo.

Remark 2.58 The low ripple assumption used in the following analysis implic-itly allows one to remove the particular value of inductance used in the circuitfrom the switch utilisation expressions – i.e. the expressions are circuit valueindependent. It also serves to simplify the analysis whilst still capturing theessential character of the expressions.

Let us now consider the switch utilisation of the generic converter types thatwe have considered in this chapter.

2.4.8.1.1 Buck Converter The peak voltage across the switch is:

VT = Vd (2.97)

This can be written in terms of the output voltage using (2.9) allowing the peakswitch voltage to be written as:

VT =VoD

(2.98)

Examination of Figure 2.2 reveals that the peak current through the switch mustbe the same as the average load current, since when the switch is closed the twocurrents have to be the same (via the no inductor current ripple assumption).Therefore:

IT = Io (2.99)

Using these two expressions for VT and IT we can write the expression for theswitch rating power:

PT = VT IT =VoIoD

(2.100)

Therefore: buck converterswitch utilisationUs =

PoPT

=VoIo(VoIoD

) = D (2.101)

2.4.8.1.2 Boost Converter A similar analysis for the boost converter canalso be carried out. Again the basic equations for the voltage ratio, (2.46), andthe current ratio, (2.48) can be used.

The key to getting the switch utilisation in this case is to realise that theaverage input current id and the inductor current iL are the same. Since we areassuming that the inductor is large enough that there can be little ripple in theinductor current, then the switch current must also equal the inductor current.The same assumption also means that we can replace the instantaneous currentswith their average values (since they will be the same). Therefore id = Id andiL = IL. We can therefore write:

IT = Id (2.102)


Using (2.48) we can relate the Id and Io, therefore we have:

IT = Id =Io

1−D(2.103)

From Figure 2.3 one can see that the peak voltage across the transistor is theoutput voltage – i.e.:

VT = Vo (2.104)allowing the switch peak power to be written as:

PT = VT IT =VoIo

1−D(2.105)

and the switch utilisation as:boost converterswitch utilisation

Us =PoPT

=VoIo(VoIo1−D

) = 1−D (2.106)

2.4.8.1.3 Buck-Boost Converter The determination of the switch utilisa-tion for the buck-boost converter is a little more complicated than the previouscases. This complication occurs due to the fact that the average current ID isnot the peak current value flowing through the switch device (as was the casein most of the above). This occurs due to the fact that the switch disconnectsthe input from the output.

The waveform for the input current (which is also the switch current in thiscase) is shown in Figure 2.34. Note that the constant value of the current from0 to DTs is due to the large inductance assumption. It can be seen that thataverage input current is:

ID =iDDTsTs

= iDD (2.107)

and therefore the peak current through the switch is:

iD =IDD

(2.108)

Using (2.68) and (2.108) we can write:

IT = iD =

(1

1−D

)Io (2.109)

The maximum voltage across the switch (from Figure 2.5) can be seen to be:

VT = Vd + Vo (2.110)

and using (2.67) we can write:

VT =1−DD

Vo + Vo =VoD

(2.111)

Using (2.109) and (2.111) we can now write the peak switch power:

PT = VT IT =1

D(1−D)VoIo (2.112)

and hence the switch utilisation factor is:buck-boost switchutilisation

Us =PoPT

= D(1−D) = D −D2 (2.113)

The Cúk converter has the same switch utilisation as the buck-boost converter.


iD

ID

DTs

( )1- D Ts

Inputcurrent

t

Figure 2.34: The input current into a buck-boost converter with a large inputinductance.

2.4.8.1.4 Full Bridge Converter When we consider the switch utilisationfor the full bridge converter we shall look at SWA+ and then divide the resultby four, because there are four switches in this converter. In other words werequire fours times the amount of semiconductor material in this converter, andhence we consider then the peak power is divide across these four devices.

Remark 2.59 The division of the single switch utilisation is a technique forsaying that the converter is using more silicon than other converters. However,it should be noted that each individual switch has to satisfy the peak power priorto being divided by four.

From Figure 2.9 it is obvious that the peak voltage across a switch is:

VT = Vd (2.114)

Similarly it is clear that the peak current is the load current:

IT = Io (2.115)

Therefore the peak switch power is:

PT = VT IT = VdIo (2.116)

We need to get the output power. Since we have expressed the peak switchpower in terms of Vd we need to get the output power in terms of this as well.This can be achieved by using (2.89) in conjunction with (2.86) which allows usto write:

vcontrol = Vtri(2D1 − 1) (2.117)


and hence:Vo = Vd(2D1 − 1) (2.118)

and therefore the output power is:

Po = VoIo = Vd(2D1 − 1)Io (2.119)

Therefore the switch utilisation for SWA+ is:

USWA+=PoPT

= (2D1 − 1) (2.120)

In order to get the final value we divide then single switch value by four:full bridge switchutilisation

Us = 0.5D1 − 0.25 (2.121)

The best way to get an overall comparison of the switch utilisation for thevarious converters is to plot the switch utilisation versus duty cycle for them.This plot is shown in Figure 2.35.

Remark 2.60 One can see from Figure 2.35 that the buck-boost converter, theCúk and the full bridge converter do not have good switch utilisation as comparedto the buck or the boost converter. Therefore, where possible it is better to usethese converters, since a lower cost switch can be used for a given application.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Boost Buck

Buck-boost

and CukFull bridge

P

P

o

T

D

Figure 2.35: Plot of switch utilisation for the common converter types.


Remark 2.61 If both higher and lower voltages than the supply are requiredthen one has to use either the buck-boost or the Cúk converters. A significantadvantage of the Cúk converter is that the front end of the converter looks likethat of the conventional boost converter. Therefore it shares the property of thisinverter that the input current is reasonable constant, and hence the filtering ofthe input is significantly simplified as compared to the buck-boost converter wherethe input (and output) currents are highly discontinuous. Similarly the outputcurrent of this converter can also be kept almost constant. A disadvantage of theCúk converter is that the capacitor has to have a high ripple current capacity.

Remark 2.62 The full bridge converter should only be used if four quadrantoperation is required.

2.4.9 Synchronous Rectifiers

In a switching power supply is being used in very low voltage applications thedrop of voltage across the rectifier diodes can be significant. This voltage dropobviously results in less efficiency from the converter. In some of the moredemanding applications efficiency takes precedence over other considerations.

One halfway solution to the efficiency problem is to use of Schottky diodesfor the rectifier. These devices have an “on” voltage of approximately 0.2 volt,as compared to the 0.6–0.7 volt of the conventional diode. However, in the verydemanding applications this drop is still too much.

The solution employed is the use of the so-called synchronous rectifier. Thisuses a MOSFET instead of the diode. The reader should be aware that a MOS-FET has a conventional diode intrinsically built into its structure. This is notthe diode that is being used in the synchronous rectifier. The synchronous rec-tifier uses the fact that a MOSFET is a symmetric structure, and consequentlyconducts current from the Drain to the Source and vice-versa. This means thatwhen the internal diode is reverse biased the MOSFET is not turned on (therebyoperating as a reverse biased diode). But when the diode is forward biased theMOSFET is turned “on”. This effectively shorts out the internal diode since the“on” voltage of a MOSFET is significantly lower than the “on” voltage of theinternal diode. This is due to the fact that the MOSFET essentially functionsas a resistance when turned “on” hard, and the “on” state resistance of manymodern MOSFETs is very very low – of the order of 10−3mΩ. This principle isshown in Figure 2.36 which shows a conventional boost converter circuit withand without a diode rectifier.

One feature in Figure 2.36 is the parallel Schottky diode with the MOSFET.This diode is required to carry the current when the bottom MOSFET turns“off”, and the rectifier MOSFET is “off”. This gap is required so that shootthrough from the load cannot occur (and from the supply for the buck con-verter). The body diode of the MOSFET should not be allowed to carry thiscurrent because of the very high reverse recovery time.

Remark 2.63 One other advantage of using synchronous rectifiers is that onecan make sure that there is continuous conduction under all load conditions.This occurs because the current can flow in either direction through the inductorwith a series MOSFET as opposed to a diode.


+V +V

(a) (b)

Synchronousrectifier

Figure 2.36: (a) Conventional non-synchronous rectifier based boost converter.(b) Synchronous rectifier based boost converter.

2.4.10 Switching Losses and Snubber CircuitsIt has been shown that the losses in power electronic switches due to the switch-ing process itself and be between two and four times the static losses when theswitch is conducting [4] depending on the switching frequency. Clearly theselosses will increase in proportion to frequency. The switching losses are switch-ing device and topology dependent.

Switching losses occur primarily because as a device switches on or off theremay be both substantial voltage and current across the device. Consequentlythere is a spike of power dissipation during this interval.

Specifically the purpose of snubber circuits are [2]:

1. Limit voltages applied across semiconductor devices during turn-off and/orturn-on transients.

2. Limit the rate of rise of current through devices (di/dt) during turn-on.

3. Limit the rate of rise of voltage across devices during turn-off or re-appliedforward blocking voltages.

4. Shape the switching trajectory so that the device remains in the safeoperating area (SOA)4 under all switching circumstances.

Topologies, which use transistor switching devices, and have a transformer pri-transistor switches4The SOA is the area in the VI plane for devices operation where the manufacturer will

guarantee that the device will not be damaged. The device must remain within this areaunder static and dynamic conditions.


mary in series with the switching device tend to have their switching losses con-centrated in the turn-off switching cycle (as compared to the turn-on switchingcycle). This is because the leakage inductance of the transformer limits the rateof rise of current upon switching device turn-on, and therefore there is littlecurrent flowing the device whilst the voltage is at a substantial level across thedevice.

Remark 2.64 Any topology where there is an inductor in series with the powerdevice will have a lower turn-on loss because of the slow rise of current at turn-on.

Remark 2.65 The non-isolated buck converter, at first sight, would appear tofall into the low turn-on loss category of converters. However, in the case ofthis converter there is a free wheeling diode at the junction point of the inductorand the switching device which completely changes the situation. In fact thestored charge in the free wheeling diode exacerbates the situation by providinga short circuit to ground upon switching device turn-on. This results in a veryhigh current spike with a very rapid rise time. Therefore in this case there aresignificant turn-on losses. During turn-off the transistor is protected by the sametypes of snubber circuits as other topologies.

If the switching device is a MOSFET the switching losses tend to be concen- MOSFET switchestrated at turn-on. This is due to the devices own self capacitance Co, which isin parallel with the device. At turn-on one gets a large spike of current due tothis capacitance being charged, often to the level of twice the supply voltage.The turn-off losses of the MOSFET tend not be be very high because of thevery rapid turn-off of this type of device.

Remark 2.66 Snubbers are often required with MOSFETs, not because of theturn-off losses as with transistors, but because of inductive spikes across thedrain-source due to parasitic inductance. The fact that MOSFETs can turn-offvery quickly exacerbates this inductive spike issue.

Not only do active switching elements need snubbers, but so do naturally com-mutated elements such as diodes and thyristors. As a starting point to thisanalysis we shall consider diode snubbing.

2.4.10.1 Diode Snubbers

This section is still in development and is far from complete at the moment.Currently it only introduces the various applications of snubbers but doesnot include comprehensive analysis.

The simplest situation to analyse is the diode in a buck converter situation[2]. Consider the diagram in Figure 2.37. A snubber circuit is required acrossthe diode because of the large voltage that can occur across it as a result of thereverse recovery current and the parasitic inductance.

In Figure 2.37 the Lσ is the leakage inductance in the diode recovery path.The highly inductive load is being modeled as an ideal current source, Io. Whenthe switch T is opened the current flowing in the load is allowed to flow up


Ls

Lis

sR

sCdV

oI

fDi fD Dv

+

-

T

oI

0 t

rrI

fD ddi V

dt Ls

= -

fDi

(a)

(b)

SWt

0t

st

Figure 2.37: (a) Step-down converter circuit with a RC snubber; (b) The diodereverse recovery current [2].


through the diode Df , therefore preventing the large voltage spike that wouldotherwise result from the highly inductive load. This is shown in Figure 2.37(a),where IDf = Io. When the switch T is closed again at time tSW then the currentiDf remains initially at Io and starts to decrease. It remains at this level becauseof the inevitable parasitic inductance of the circuit associated with the diode.The voltage Vd is applied across the leakage inductance, hence the linear decreaseof the current.

At time t0 the current through the diode (and the Lσ inductor) becomeszero. After this time the current flowing through the diode begins to flow in thereverse direction of normal forward bias current flow. This will continue untilthe stored charge in the diode is exhausted, and at time ts the diode “snaps off”.At ts the current through Lσ is Irr and if nothing is done, the voltage producedby di/dt through Lσ in order to keep Irr flowing would be enormous. Hence therequirement of a snubber circuit RsCs.

In order to analyse the snubber circuit consider the equivalent circuit ofFigure 2.38. This shows the full equivalent circuit for the snubber section of thecircuit, as well as a simplified circuit when the resistor is zero. We shall use thelater initially to carry out the analysis, even though this circuit is not used inpractice. Nevertheless the basic principles of operation are shown by using thiscircuit. Not that the following analysis is based on this presented in [2].

The circuit in Figure 2.38(b) is a simple LC circuit, and therefore can besolved using the standard differential equation. It can be shown that the solutionto this circuit is:

iL(t) = IL0 cosω0(t− t0) +Vd − VCs0

Z0sinω0(t− t0) (2.122)

vCs(t) = Vd − (Vd − VCs0) cosω0(t− t0) + Z0IL0 sinω0(t− t0)(2.123)

where:

ω0 = 2πf0 =1√LσCS

Z0 =

√LσCs

Ω

In this particular case, we shall assume that the t = 0 time is at the pointwhere the diode snaps off. Therefore the initial conditions for the inductorcurrent and the capacitor voltage are iL0 = Irr and vCs = 0. Figure 2.39 showsthe waveforms that are generated for the simplified circuit of Figure 2.38(b).Note that the capacitor voltage is the negative of the diode voltage.

Let us define a base capacitance value:

Cbase = Lσ

[IrrVd

]2

(2.124)

(this is derived from the expression 12LσI

2rr = 1

2Csv2Cs

, and saying that thecapacitor voltage is the input voltage).

Substituting Lσ = Cbase

[VdIrr

]2into (2.123) and manipulating we can write:

vCs = Vd

[1− cosω0t+

√Cbase

Cssinω0t

](2.125)


Ls

sR

sC

Diode

Snap-offdV

rrI

sCv

Ci

K

A

sCdV

Lis

sCv

0sR =

(a)

(b)

Ls

Figure 2.38: Equivalent circuit of the snubber used to protect diodes. (a) Fullequivalent circuit; (b) simplified circuit with Rs = 0.


vCsmax

L¾diL

dt= Vd

Irr

Vd

t

vCs

Figure 2.39: Waveforms for the simplified (Rs = 0) snubber circuit.

Taking the derivative of this expression we and equating the result to zero(the find the extremum) we can write:

sinω0t = −√Cbase

Cscosω0t (2.126)

or

tanω0t = −√Cbase

Cs(2.127)

where ω0t is the “optimal” value for θ. Note that due to the properties of thetan function, we can also write:

tan(ω0t± π) = −√Cbase

Cs(2.128)

We shall make us of the following trigonometric identities:

sinx =tanx√

1 + tan2 x(2.129)

cosx =1√

1 + tan2 x(2.130)

where x denotes the optimal value for the phase in the expressions (note that xcan equal ω0t or ω0t± π). Due to the ambiguity of the x value, then the abovetwo expressions can be positive or negative depending on whether x = ω0t or


0.0 0.5 1.0 1.5 2.0 2.5 3.0C_base/C_s

2.0

2.2

2.4

2.6

2.8

3.0

Norm

alis

ed v

_Cs

Figure 2.40: Plot of the normalised capacitor voltage versus Cbase/Cs.

x = ω0t± π. Using these expressions we can write from(2.125):

vCsmax= Vd

[1± 1√

1 + tan2 x±√Cbase

Cs

tanx√1 + tan2 x

](2.131)

= Vd

1− 1√1 + Cbase

Cs

+

√Cbase

Cs

−√

Cbase

Cs√1 + Cbase

Cs

(2.132)

= Vd

1±1 + Cbase

Cs√1 + Cbase

Cs

(2.133)

= Vd

[1±

√1 +

Cbase

Cs

](2.134)

The negative solution does not make sense – the maximum voltage would beless than the input voltage. Therefore chose the positive solution, which gives:

vCsmax= Vd

[1 +

√1 +

Cbase

Cs

](2.135)

Remark 2.67 One can see from (2.135) that if Cs < Cbase that vCsmaxin-

creases, and for small values very large values of voltage would occur. Themaximum capacitor voltage is impressed across the diode, and therefore has tobe kept under control.

Figure 2.40 shows a plot of this normalised capacitor voltage versus theCbase/Cs value. As can be seen, if Cbase/Cs > 1 then the capacitor voltages


become quite large. However, one can also see that the Cs has to be fairly largeto reduce the voltage to any significant margin.

The above analysis was only approximate in that we neglected the Rs resis-tance in the circuit to get an approximate feel for the effect of the capacitance.However, in reality there is a resistor there, and it is required in order to pre-vent large currents from flowing into the switching transistor when the switchis turned back on. The differential equation for the circuit under this conditionis:

LσCsd2vDfdt2

+RsCsdvCfdt

+ vDf = −Vd (2.136)

where vDf is the diode voltage after t = 0 which is the instant that the diodesnaps off. The initial conditions at this point are the initial inductor currentof Irr and the initial capacitor voltage is zero (as was the case for the previ-ous analysis). These conditions then lead to the boundary condition for thedifferential equation of vDf (0+) = −IrrRs and:

dvDf (0+)

dt= −Irr

Cs− RsVd

Lσ− IrrR

22

Lσ(2.137)

Using standard solution techniques one can show that the solution is:

vDf (t) = −Vd −√LσCs

Irrcosφ

e−αt cos(ωαt− φ− γ) (2.138)

where:

ωα =

√1− α2

ω20

α =Rs2ωα

φ = tan−1

(Vd − IrrRs

2

ωαLσIrr

)γ = tan−1

(ωαα

)As in the previous case the maximum value can be found by taking the

derivative, and then setting to zero and solving for the time. If this is done thenthe time at which the maximum voltage occurs can be found to be:

tm =φ+ γ − π

2

ωα(2.139)

If this is substituted into (2.138) then the normalised maximum reverse voltageacross the diode is:

Vmax

Vd= 1 +

√

1 +Cbase

Cs+

RsRbase

− 0.75

(RsRbase

)2 e−αtm (2.140)

where Rbase = VdIrr

and Cbase is as defined previously.


2.4.10.2 Snubbers for Thyristors

RC snubbers, similar to those used for diodes, are also required for thyristorcircuits. For example, when thyristors are being used in the controlled rectifierapplications, when only thyristor is turned off by another being turned on, thenthere is a reverse recovery current that flows through the thyristor that is beingturned off. This current will snap-off very rapidly when the reverse recoveryis complete. The inductance of the circuit that this reverse recovery current isflowing through will result in a large voltage occurring across that device thatis commutating off (i.e. undergoing the reverse recovery). If nothing is doneabout this the device may suffer failure due to over-voltage.

Details of design to be presented later. In the meantime information can befound in [2].

2.4.10.3 Snubbers and Transistors

This section is incomplete – the analysis has not been completed. Refer to[2] for more details.

Snubbers are required for transistor switches in order to improve their switch-ing trajectory. Transistors (regardless of whether they are BJTs, MOSFETs etc)experience stresses during turn-on and turn-off. These stresses are due to ei-ther higher than normal current through the device while there is substantialcurrent across of the device (this usually occurs at turn-on due to diode reverserecovery), or higher than normal voltage across the device while there is sub-stantial current flowing in the device (this usually occurs are turn-off due tostray inductances). Both of these situations can be managed by judicious useof snubber.

A typical turn-off snubber circuit for a transistor switch in a step-downturn-off snubberconverter is shown in Figure 2.41. It is fairly obvious how this circuit works– when the transistor turns off the voltage across the capacitor cannot changeinstantly. Therefore as the current through the transistor falls it is transferredto the capacitor via the snubber diode. Whilst the voltage across the capacitoris less than the supply voltage the freewheeling diode around the current sourceremains off. Therefore this circuit keeps the voltage across the transistor nearzero as the current through the device falls. Therefore the power dissipation inthe transistor during the switching transient is low.

Note 2.2 Note that most snubbers are essentially transferring energy from thesilicon switching device to a passive component (e.g. a resistor). Therefore theymay not improve the efficiency of a circuit, but the power dissipation may beeasier to handle in a passive device as opposed to a transistor where criticalfunction temperatures are of vital importance with respect to lifetime.

Remark 2.68 Note that the turn-off snubber also helps prevent over-voltageson the transistor due to stray inductances. When diode Df turns on an equiv-alent LC circuit is formed with the leakage inductances in the circuit and thesnubber capacitor. Normally a high voltage could be induced in the leakage in-ductance as the current changes when the freewheeling diode turns on, but with


the snubber capacitor there an LC circuit is formed that limits the voltage riseacross the device.

SCi

SD

SR

0IfDI

dV

Figure 2.41: Turn-off snubber circuit for a transistor step-down converter.

When the transistor switches back on, the diode DS in Figure 2.41 willbe reverse bias. Hence the capacitor CS will discharge through the resistor RS .Providing the capacitor is largely discharged before the transistor is next turnedoff the circuit will function as described above.

Remark 2.69 The discharge current through Rs resistor is added to the turn-on current through the transistor. The turn-on current through the transistorcan be quite large under some circumstances due to the stored charge in thefreewheeling diode. This is the main reason for a turn-on snubber discussedlater.

Let us look in more detail at the reasons for the turn-on and turn-off snubbers.Figure 2.42 shows the various stray inductances in a transistor circuit that caninfluence the switching of the circuit. The L1 to L5 inductors are effectivelyin the switching path during turn-on and turn-off, and the affect the switchingtrajectories of the device (i.e. the v versus i relationship during the switchingof the transistor).

Figure 2.43 shows a conceptual diagram of the turn-on and turn-off switch-ing trajectories under the influence of the stray inductances. At t0 the transistoris on, and at t+0 the turn-off of the device begins. As the process proceeds thecurrent through the device begins to fall and the voltage across the device beginsto rise. The trajectory moves towards the point on the graph that is denoted


Vd

L1

L2

L3

L5

L4

Io

Figure 2.42: Stray inductances that are important in a transistor switchingcircuit during turn-on [2].

with t1. As the switching trajectory moves towards this point there is clearlypower being dissipated in the device as there is simultaneously substantial cur-rent and voltage through and across the device. The over-voltage at t1 is dueto the inductances in the circuit – i.e. Lσ = L1 + L2 + · · ·+ L5 and the diC

dt ofthe switch current as the device turns off.

Note 2.3 The over-voltage at t1 would result in considerable extra power dissi-pation in the switching device, since there can often still be considerable currentflowing in the device at the time of this over-voltage.

The device finally turns off at point t3 when it supports the full supplyvoltage and has zero current flowing through it. When the device turns backon, it follows the trajectory from t3 to t4 and up to t5 and finally t6.. The bumpabove the rated current at t5 is due to the reverse recovery of the freewheelingdiode that has been taking the load current whilst the transistor has been turnedoff. As with the turn-off situation clearly one has considerable voltage across thedevice simultaneously with a more than rated current through the device at thispoint, which indicates that there will be considerable power dissipation due tothis. In addition to this, the reverse recovery current could, in some cases, causedamage to the device over time. This is especially true if the switching deviceis a minority carrier based switch such as a bipolar junction transistor (BJT).These devices suffer from secondary break down due to a negative temperaturecoefficient resulting in hot spots in the device under circumstances similar tothose just describe.

Remark 2.70 During the turn-on phase the current being handled by the tran-sistor is Io+ irr where irr is the reverse recovery current of the diode. When thediode snaps off, it is only the irr component of this current that is undergoing arapid rate of change, and consequently only the energy stored in 1

2Lσi2rr has to

be handled by any snubbering circuitry.


vCE

iC

t0

t1

t3t4

t5

t6

Idealised switching

loci

Turn-on

Turn-off

0

Io

t0 t1 t3

Vd

t4 t5

Io

t6

L¾diC

dt

L¾ = L1 + L2 + ¢ ¢ ¢

L¾iC

dt

vCE

iC

Figure 2.43: Current and voltage trajectories during turn-on and turn-off for astep-down transistor converter.


Io

CSiC

Vd

Vd

iCS

tfi

Vd

tfi

Vd

Io

iC

iDf

iC

iDf iDf

iC

tfi

CS small CS = CS1 CS big

iCS= Io ¡ iC

Model of transistor switch during turn-o®

vCS

Figure 2.44: Equivalent circuit for the turn-off RCD snubber and approximatewaveforms for different values of capacitance [2].

If one now considers the operation of the turn-off snubber with different values ofcapacitor Cs we get the plots in Figure 2.44. One can see that if the capacitor issmall then the voltage across it does not stay low during the turn-off, and therecan still be substantial current and voltage across the switch. The CS = CS1ischaracterised by the fact that the capacitor charge time is exactly the fall timeof the current. For the large value of capacitor the charge time is far longer thanthe fall time of the current. Consequently for the whole of the turn-off periodthe voltage across the switch has a very low value.

Remark 2.71 Clearly, from a switch power dissipation perspective, the largevalue of CS is superior. However, the down side of this approach is that the en-ergy stored in CS has to be dissipated in the RS resistor on the next turn-on ofthe switch. Therefore it is best, for efficiency reasons to choose a sensible com-promise based on a balance between switch losses and RS losses. An optimumvalue can be found to minimise the total losses in the circuit [2].

Figure 2.45 shows the switching trajectories for the different values of capac-itor shown in Figure 2.44. This simply confirms the comments in Remark 2.71.

A typical turn-on snubber is shown in Figure 2.46. As mentioned in a pre-turn-on snubbervious remark, the function of turn-on snubbers is to alleviate the large currentsthat can flow at turn-on due to reverse recovery currents from diodes that areconducting at the time of turn-on.

As can be seen from Figure 2.46 the turn-on snubber works by using theinductance of the series inductance LS to limit the rate of rise of current duringthe turn-on phase. Therefore, since the diode Df will be a short circuit due to


iC

vCE

CS = 0

CS small

CS = CS1

CS large

SOA

Io

Vd

Figure 2.45: Switching trajectories for different turn-off capacitor values.

0IfD

SL

SLD

SLR

dV

Figure 2.46: Typical turn-on snubber for a transistor step-down converter.


reverse recovery during for a period of time during the turn-on the LS inductorwill be supporting approximately Vd volts across it, and hence the voltage acrossthe transistor will almost be zero.

The price paid for the turn-on snubber is that the energy stored in the LSinductor must be dissipated. In order to do this additional components RLS andDLS are included to provide a path for the current to flow when the transistoris turned off. When the current flows through this path there will be a slightover-voltage impressed across the transistor. The resistor RLS is chosen so thatthe current in the inductor will be dissipated in a reasonable time after turn-off– i.e. before the next turn-on. In addition it also has to be chosen so that thevoltage rise on the transistor is not too great during turn-off as the inductorcurrent flows through it.

The final type of snubber we shall consider is the over-voltage snubber. Thisover-voltage snub-ber type of snubber is specifically designed to prevent over-voltage on the transistor

due to the stray inductances in the circuit. It does not prevent voltages fromappearing across the device during turn-off, and does not add any current atthe turn-on of the device. The over-voltage snubber and the turn-off snubbershould not be used at the same time. The basic structure for the over-voltagesnubber is shown in Figure 2.47.

ovD

fD

Ls

dV

0I

ovC

ovR

Figure 2.47: Over-voltage snubber for a transistor step-down converter.

In this circuit the voltage across the capacitor is at Vd when the switch isclosed (diode Dov is reverse biased). When the transistor is switched off thendiode Df turns on and the stray inductance Lσ causes diode Dov to turn onforming a resonant circuit with Cov. This allows the energy to flow into Covpushing its voltage above Vd. The amount the voltage goes above Vd dependson the relative values of Lσ and Cov. The over-voltage across the capacitor thendissipates through the resistor back to the supply during the transistor off time.


IoDf

RS LS

TCS

Cov

Cd

Vd

Figure 2.48: Undeland snubber for a step-down converter circuit.

Remark 2.72 As noted previously turn-off snubbers can perform the functionof over-voltage protection. The question then arises why bother with the over-voltage snubber? The main reason is that there is more freedom to address theover-voltage problem without running into difficulties with the discharge timeand subsequent resistance dissipation of the turn-off snubber. Also, in someother circuit configurations that employ turn-on snubbers, the over-voltage ca-pacitor serves to capture the energy from the di

dt limiting turn-on inductor.

A snubber that attempts to combine aspects of all the previous snubbers, butwith reduced component count is the Undeland Snubber. This combines char-acteristics of the turn-on, turn-off and over-voltage snubbers. Figure 2.48 showsan Undeland snubber for a step-down converter circuit.

2.4.11 Resonant and Soft-Switching Converters

This section of the notes will be undergoing a major revision during coursepresentation in 2005. The material below is still correct as far as it goes,but it is only a very brief and not particularly erudite presentation of someaspects of resonant converters.

These notes will not look at resonant converters in any detail. These typesof converters are not in the mainstream of converter technology at this time,and in fact some people in the switch mode power supply area think that they


are a fad [5]. Nevertheless one should know what they are and what are theirlimitations. By the way I think that over time resonant converter technologieswill certainly have increased application in specialist areas. Currently they arebeing used in areas where weight and losses are of particular importance (e.g.aerospace).

A resonant converter is a converter that intentionally has a resonant LCtank circuit as a fundamental part of its operation. This tank circuit is excitedby the switching of the converter, so that the resonance is maintained duringoperation. There are a variety of different topologies to achieve this operation.

The reason for having this resonance is that if the switching of the mainpower devices occurs at the time when the voltage across, or the current throughthe device is zero. This means that the power dissipated in the device ideallyis zero. Consequently it is possible to increase the switching frequency of theconverter, without incurring excessive losses in the switching devices.

In order to have some idea of the configurations of a resonant convertersconsider Figures 2.49 and 2.50. Figure 2.49 shows a resonant buck converterthat is designed to switch when the current through the switch reaches zero.Figure 2.50 is a resonant buck converter which switches when the voltage iszero across the switch. We shall not look at the details of the operation of these(for details look in [2, 4]), but one can see that both circuits have the extra LCcomponents represented by Cr and Lr. These are the components that representthe resonant circuit that is used to assist the switching of the power devices.

+

-

Lr

Cr D Cf

RL

SW

Vd

Lf

Io

Figure 2.49: A zero current switching (ZCS) resonant buck converter.

Remark 2.73 We shall see that the concepts used in resonant converters areactually very old. These ideas were originally used in forced commutated siliconcontrolled rectifier (SCR) circuits from as far back as the 1960s.

Before considering the pros and cons of resonant converters we need to distin-guish between them and the so-called soft switching converters (a name oftenused in the literature to mean a resonant converter). Soft switched convertersare also known as quasi-resonant converters. A resonant converter is one inwhich the power waveforms (current and voltage) are sinusoidal, and switchingoccurs when the voltage and/or current go through zero. Therefore the switch-ing losses (ideally) should be zero. The quasi-resonant converter on the otherhand is intermediate between the resonant converter and the conventional PWMconverter. The circuit of these converters is so arranged that it creates a tankcircuit for a portion of the switching period so that the switch transitions arenearly lossless.


+

-

Lr

Cr

D Cf

RL

SW

Vd

Lf

Io

Dr

Figure 2.50: A zero voltage switching (ZVS) resonant buck converter.

2.4.11.1 Why One Should Not Use Resonant Converters

Resonant converters have several problems in practice. The first major one isthat the switching frequency is a function of the load. This causes problems in switching frequency

is a function of theload

the design of the EMI filters.A more serious problem is that it is common to use the parasitic capacitances

parasitic capaci-tances

as one of the elements in the resonant tank circuit. This makes is virtuallyimpossible to build units that behave the same on the production line. Theobvious solution to the problem is to parallel the parasitics with a capacitorthat swamps its effects. However, this has the effect of lowering the oscillationfrequency of the tank circuit, which is the whole objective of having the resonantconverter in the first place.

In addition to the above problems, resonant converters still have problemswith large line voltage changes, short-circuited or unloaded outputs, and com-ponent tolerances in general. They also operate mainly at higher peak transistorcurrents for the same output power compared to conventional PWM inverters,and in some configurations at larger voltage stresses.

2.4.11.2 Why One Should Use Quasi-Resonant Converters

Before discussing the benefits of using these converters it may be beneficial toreview the operation of a quasi-resonant converter. Consider Figure 2.51, whichis a conceptual diagram of a quasi-resonant forward converter. Notice that themain difference between this converter and that of Figure 3.1 is the addition ofthe capacitor across the switch.

The presence of the capacitor across the switch forms an LC circuit togetherwith the magnetising inductance of the transformer. When the switch is opened,the voltage across the capacitor is zero. The current through the magnetisinginductance will continue flowing into the capacitor, and a resonant ring begins.This ring will continue until the voltage on the capacitor falls back to the sup-ply voltage. At this point the voltage on the magnetising inductance will bepositive at the dot end of the primary. This will cause the diode rectifier in thesecondary to turn on, and the remainder of the energy stored in the magnetising


Vd

VoC

L

vL

+ -

iL

D1

D2

N2

N1 R

L

SW

Switch voltage

CSW

Vd

t

Figure 2.51: A quasi-resonant forward converter.

inductance is transferred to the load. One can see that the quasi resonant con-verter essentially forms a zero voltage switching (ZVS) device, since the voltagezero voltage switch-

ing across the capacitor cannot change instantaneously when the switch is opened.One must be sure to choose the LC components so that the LC ring is

complete before the start of the next control interval. However, this is not toolimiting, and there is usually a reasonable range of components that can bechosen.

Another possible problem is the presence of a charged capacitor across theswitching device when it is turned on. However, a few calculations for practicalsituations show that the energy dissipated in a MOSFET switch due to this isvery small.

The major advantage of the quasi-resonant converter is the fact that it essen-tially works the same as the standard hard switched PWM converters, and theswitching rate is determined by the PWM controller chip. Therefore the designof the filtering and EMI circuits is greatly simplified compared to frequency wildconverters such as many of the pure resonant designs.

2.4.12 Example: ZVS Converter Design and Analysis

This example comes from a previous assignment in this course.Figure 2.52 is a diagram of a Zero Voltage Switching (ZVS) quasi resonant

buck converter.The key equations for LC series circuits are as follows [2]. The equation for

the current through the inductor is:

iL(t) = IL0cosω0(t− t0) +

Vd − Vc0Z0

sinω0(t− t0) (2.141)

and the equation for the voltage across the switch capacitor is:

vCr (t) = Vd − (Vd − VC0) cosω0(t− t0) + IL0

Z0 sinω0(t− t0) (2.142)


+

-inV

swi

rL

rC

oC LoadR

oL

rCv

ovbulkC

swD

fD

rLi

Li o oi I»

Figure 2.52: Zero Voltage Switching quasi resonant buck converter for example.

where:

ω0 =1√LrCr

(2.143)

Z0 =

√LrCr

(2.144)

iL(t0) = IL0(the initial inductor current) (2.145)

vCr (t0) = VC0(the initial capacitor voltage) (2.146)

t ≥ t0 (2.147)

a. Explain how the circuit of Figure 2.52 works. Use the above equationsabove appropriately to augment your explanation. Provide sketches ofthe current through the Lr inductor, and the voltage across the capacitorvCr as the circuit moves through its very states of operation.

b. Carry out a design of the circuit assuming 24V input, a 5 Volt output,30→100 Watt output power range, 100mV output ripple, and continuousoutput current conduction. Make the resonant frequency 100kHz.

c. Simulate the design to show that it works as designed.

Solution

Answer to Part (a)

The fundamental assumption made in the following discussion is that the outputcan be modeled over one switching period as a constant current sink. Usuallythis assumption, for most realistic values of the output filter inductor, is rea-sonable. The following discussion is taken almost directly from Mohan[2]. Thisbook gives a very clear explanation of the operation and behaviour of this circuit.

The following explanation is with respect to Figure 2.53 from Mohan[2].This diagram has been scanned from the text book, and therefore the quality isa little compromised.

There are five main areas of operation is this figure. Each of these areasshall be discussed in turn.


Figure 2.53: Waveforms in the ZVS circuit (scanned from [2]).

Interval t0 → t1 The assumed starting point of the switching cycle is that theswitch is opened at t0 (it has been closed up until this time), and thatvCr = 0 and the current through the Lr inductor is the load current Io.The fact that vCr = 0 when the switch is opened means that this is azero voltage switch operation. Since this current is constant then therewill be no voltage across the inductor. Consequently the freewheelingdiode will have a voltage across it of Vd Volts and hence will be off. Thisin turn implies that all the current will be flowing through the capacitor.Therefore as time progresses from t0 the capacitor will be linearly chargingin the polarity shown in Figure 2.53. The equivalent circuit at this timeis shown in the Figure. Therefore the expression for the voltage on thecapacitor is:

vc =

∫ t

t0

IoCr

dt t ≤ t1 (2.148)

Interval t1 → t2 The next interval can be divided into several sub-intervals.


We shall discuss these in detail with the appropriate supporting equations.

At time t1 the voltage across Cr becomes equal to Vd Volts, and thereforethe voltage across the diode is 0 Volts. As t becomes greater that t1 thenthe voltage across the diode will attempt to go forward bias, and hence thefree wheel diode will turn on and the load current will begin to transferto it. The Lr current will also continue to flow in the CrLr part of thecircuit. Since the right hand side of Lr is now connected to ground, theCrLr circuit now becomes a resonant circuit, where the initial conditionin the circuit for the inductor current is Io.

The inductor current for t1 ≤ t ≤ t2 is can be found by using the appro-priate initial conditions in (2.141). In this case at t1 we have IL0

= I0 andVc0 = Vd hence (2.141) can be written as:

iL(t) = I0 cosω0(t− t1) t1 ≤ t ≤ t2 (2.149)

Similarly, for the capacitor voltage. We already know that the initial con-dition on the Cr capacitor at the beginning of the t1 time is Vd. Thereforewe can write the expression for the voltage on the capacitor from (2.142)as:

vc(t) = Vd + IL0Z0 sinω0(t− t1) t1 ≤ t ≤ t2 (2.150)

As can be seen from (2.150), the capacitor voltage is essentially that ofa resonant circuit with a Vd voltage offset. Therefore the peak capacitorvoltage is Vd + Z0IL0 , and this occurs when the inductor current is zero.This is also the time when all of the load current is flowing through thefreewheeling diode.

At t = t′1 the resonant current in the circuit will attempt to reverse indirection. There is no current in the inductor, and therefore no energyto keep the current flowing in the same direction. The voltage on thecapacitor is in such a polarity to begin to make the current flow in thenegative direction through the inductor. Consequently, as per (2.150) thevoltage across the capacitor begins to decrease.

The resonant pulse continues to t′′1 , at which point the voltage on thecapacitor has reached the initial value at the start of the resonant cycle,and therefore in an offset sense is starting to reverse the voltage acrossit. This continues until time t2 when the voltage across the capacitorattempts to go negative. This is prevented by the diode Dr across theswitch, which turns on.

The situation at t2 is that freewheeling diode is still on, diode Dr hasjust turned on, the Lr inductor has a negative current flowing through it,and the freewheeling diode has both the load current and the negative Lrcurrent flowing through it.

Interval t2 → t3 During this interval the current through the Lr inductor,which is initially negative at t2, will start to increase linearly. One cansee from the equivalent circuit in Figure 2.53 that the rate of change ofcurrent through the Lr inductor is:

diLdt

=VdLr

(2.151)


dV

0t 1t 2t 3t 4t

ioviov

0V

1s

s

Tf

=

Figure 2.54: Voltage across the freewheeling diode in the ZVS circuit.

This linear increase in the Lr current will continue whilst ever the switchdiode and the freewheeling diode are on.Immediately after t2 (between t2 and t′2) the switch should be closed, andthis will allow the current to flow through the switch when it attempts toreverse direction through the Lr inductor. If this is not done, then therewill be a different resonant cycle through the CrLr components. Thisis undesirable, as one can end up with a non-zero voltage across the Crcapacitor, and there would be a non-zero voltage switch on of the switchin the next complete cycle.

Interval t3 → t4 The switch is closed , therefore vCr is clamped at zero. Thefreewheeling diode is on and the Lr current at Io and freewheeling diodeis off. At this point the whole sequence can now repeat if the switch isopened.

Remark 2.74 The average output voltage for this circuit is controlled by con-trolling the period t3 → t4. The period t0 → t3 is determined by the load currentand the resonant circuit parameters, and is therefore not under the control ofthe circuit controller. Therefore if one wishes to have a lower average outputvoltage then t3 to t4 has to be made very short. Figure 2.54 shows the voltagewaveform across the freewheeling diode. If the circuit is in steady state then theaverage voltage on the diode side of the Lf filter inductor has to be equal to theaverage output voltage. n

Remark 2.75 It should be noted that the circuit has to be designed so thatZ0I0 > Vd. If it isn’t the resonant ring will not have sufficient amplitude tocause the voltage across the switch to become zero at time t2. Therefore therewould be a non-zero voltage switching if this occurs. This means that it isimportant to understand the minimum output current in order to make surethat zero voltage switching occurs under all load conditions. n

Answer to Part (b)

The first part of the design is to work out the resonant circuit components.There are two factors that must be taken into account when designing thesecomponents:


• The resonant frequency required – in this case 100kHz.

• The minimum current that will be pulled through the converter. Thisvalue will determine the Z0I0min

value. This must be larger than all valuesof Vd in order to ensure ZVS under all circumstances.

These two constraints can be used to determine the two circuit parameters.The specifications say that the minimum power the circuit has to supply is

Po = 30 Watts at a voltage of 5 Volts. Therefore Iomin = 6Amps. We only haveto cope with a constant input voltage of 24 Volts.

The key equations are:

fr =1

2π√LrCr

(2.152)

∴ LrCr =1

4π2f2r

(2.153)

In relation to the minimum power requirement we have:

Z0Iomin≥ Vd (2.154)

Now Z0 =

√LrCr

(2.155)

∴ Lr ≥ Cr(

VdIomin

)2

(2.156)

Now Iomin=

Pomin

Vo= 30

5 = 6Amps. Therefore(

VdIomin

)2

= 16. We shall choosethis value to be 20, so that it is well above the minimum value. Using (2.156)we can write Lr = 20Cr. Using this expression in (2.153) we can after a littlemanipulation write:

Cr =

√1

80π2f2r

=

√1

80π2(100e3)2= 0.3559µF (2.157)

Therefore using Lr = 20Cr we have that Lr = 7.112µH. As a check these valuesgive:

Z0Iomin= 26.83 (2.158)

which is clearly greater than the 24 Volt supply.In order to have continuous conduction the output filter inductor must be

able to supply the energy for the whole of the period whilst the switch is open.As noted previously, the time that the switch is open in this circuit is not acontrollable quantity, but is dependent on the circuit parameters and the outputcurrent.

The precise answer to this question could be quite complex due to the factthat the output current varies the time that the switch is open in the circuit. Inorder to make the design robust to variations in design parameters and variationsin circuit operational conditions that occur in real life, I will take a conservativeapproach to the design of the filter inductor.

This conservative approach manifests itself in the calculation of the timethat the switch is open. When the switch is open, ignoring the ramp slope


shown in Figure 2.54 and assuming the output voltage is constant, we can writethe following expression under steady state conditions for the voltage across thefilter inductor:

−Votopen + (Vd − Vo)tclosed = 0 (2.159)

where topen is the effective time that the switch is open, and tclosed is theeffective time that the switch is closed. The word effective relates to the factthat the actual time that the switch is open and closed is not related to the truetime that these switches are open and closed for this converter. This is due tothe fact that the voltage appearing across the output filter inductor does notcorrespond to the actual points where the switch is switched.

Clearly equation (2.159) implies that for the system to be in steady state:

tclosed =

(Vo

Vd − Vo

)topen (2.160)

Remark 2.76 Note that this expression contains an implicit assumption be-cause the slope on the diode voltage waveform when the switch is first opened isbeing ignored. The expression in its full form becomes a function of the resonantcapacitor and the load current since these determine the time for the slope. n

In addition we require that the average current over the total switching cycle isis equal to the Iomin = 6Amp current. Since the current waveform in the filterinductor (Lo) is a triangular waveform, this implies that the average over halfthe period also equals the same value.

The next question to resolve is the value of the topen time. This is where theworst case analysis comes in. One could calculate from the resonant waveformand the current value what the precise time is for the capacitor voltage to goto zero at t2. The time from t2 → t3 could then be calculated. This togetherwith the linear charge time of t0 → t1 gives the total effective open time forthe switch. A more conservative approach is to assume the maximum possibleeffective open time for the resonant frequency chosen. For the resonant part ofthe cycle this is the time to the negative peak of the resonant capacitor voltageplus the linear charge time of the capacitor and the linear current increase timefrom t2 → t3. If the circuit is continuous for this time it will be continuousunder all contingencies for ZVS for this circuit design.

We shall now calculate topen. The linear charge time t0 → t1 is given by:

δt0→1 =CrIomin

Vd =0.3559e−6 × 24

6= 1.4236e−6secs (2.161)

Three quarters of the resonant period is 7.5µsecs – this is the time to whenthe resonant capacitor voltage has reached its maximum negative value in theworst case. As mentioned above we are assuming that this is the time when thetotal voltage across the capacitor is zero. The final time to calculate is the timeit takes the current in the Lr to again reach Iomin

from zero. This time is:

δt2→3 =LrIomin

Vd(2.162)

=7.112e−6 × 6

24= 1.778e−6secs (2.163)


Therefore the total effective time that the switch is open is, adding to the timescalculated above, equal to topen = 10.7016µsecs. The actual physical maximumswitch open time is:

tphy open = 1.4236e−6 + 7.5e−6 = 8.9236µsecs (2.164)

where tphy open is the actual true physical time that the switch is open. Noteagain that this is NOT the effective open time.

These times give the time axis in calculation of the average current underthe inductor ripple current. Assuming that this current is on the verge of dis-continuity, then it is a triangle that starts at zero, goes to a maximum valueand then back to zero at the end of the switching interval.

Remark 2.77 This is an interesting situation. In the analysis for the converterwe make the assumption that the current through the output filter inductor ismore or less continuous and constant at the average current value. Indeed wesometimes model it as a current source. However in the situation of being theverge of discontinuity and the Lr inductor current reaching zero at the negativemaximum voltage of the Cr capacitor, both the current in Lo and Lr are zero.Therefore the effective inductor for the current build-up is Lr + Lo. A situ-ation completely violates the assumptions we made to establish theoperation of the circuit. The waveforms applied to the output side ofthe circuit do not appear as shown in Figure 2.54. n

Keeping in mind the limitations of the analysis from the previous remark, westill need to make some sort of an estimate for the Lo filter inductor value.During the topen time we shall assume that the current is freewheeling throughthe diode. If the output side of the circuit is on the verge of discontinuity, thenthis current will approximately reach zero during this period. If the iLo currentis assumed to be triangular in shape then the average current is iave = 1

2 ipeak.Therefore, since iave = Iomin

= 6A then ipeak = 2Iomin= 12A. So this is the

value of current that has to decrease to zero during topen when the voltageapplied to the inductor is −Vo.

ipeak =

(VoLo

)topen (2.165)

and the average current for a triangular waveform such as this is 12 ipeak. Since

the average current has to be Iomin= 6Amps the ipeak = 2Iomin

and usingthe fact that tclosed =

(Vo

Vd−Vo

)topen from equation (2.160) and realising that

VoVd

= 524 = 0.2083 allows us to write5:

Lo =

(Vo

2Iomin

)topen (2.166)

=

(Vo

2Iomin

)=

5

2× 6× 8.92e−6 = 3.71µH (2.167)

The final section to the design is capacitor design for the output. The speci-fication says that the ripple has to be less than 100mV. The equation developed

5See remark below with respect to the meaning of the following value of inductance.


in the notes for working out ripple can be used for this situation. This equationuses the concept of duty cycle. As can be seen from Figure 2.54 the effectivewaveform across the output is similar to that of a conventional hard-switchedconverter. Therefore the same relationships hold with respect to duty cycle.One of the main results we found previously when considering hard-switchedconverters is that the output voltage is a function only of the duty cycle insteady state, regardless of the load current. A similar property applies in thiscase.

Notwithstanding the approximations with respect to the wave-shapes in-volved, the switching period is Ts = topen+tclosed = topen(1+ 5

24−5 ) = 13.518µsecs.The switch closed time is tclosed = 5

24−5 topen = 2.8162µsecs. Therefore theswitching frequency is fs = 73975Hz under steady state conditions for all loadcurrents.

Using the traditional definition of the duty cycle we can write:

Deff =tclosed

topen + tclosed=

2.8162

2.8162 + 10.7016= 0.2083 (2.168)

Remark 2.78 We have to use the effect duty cycle, because the switch is ac-tually closed after 8.9µsecs, but voltage is not applied at the output until theiL = Io – i.e. the resonant inductor (Lr) current has reached the load outputcurrent. Consequently duty cycle cannot be defined by the true on and off timesof the switch as in other converters. n

The expression for the ripple form the notes is:

Co =1−Deff

8f2sLo

(∆voVo

) =1− 0.2083

8× 739752 × 3.71e−6 × 0.15

= 244µF (2.169)

Remark 2.79 The values for the filter inductor and capacitor are very muchthe worst case values. In fact the inductor has been chosen so that the ripplecurrent is the maximum possible value before the current becomes discontinuous.As can be seen from the value it is smaller than the value of the inductance inthe resonant circuit. One of the key approximations made in the above analysiswas that the current through the Lo inductor could be considered constant overa switching cycle. Clearly if the ripple current is of the order of the averagecurrent itself then the Lo inductor cannot be considered to be a virtual currentsink. If this assumption is not correct then all of the previous calculations willbe thrown out by a significant amount. Therefore a value of Lo should bechosen that is much larger than the minimum value chosen, and alsomuch larger than the resonant inductor value as well so that it seesthis inductor as a current sink.We shall choose a value for the filter inductor of Lo = 300µH. This value issomewhat arbitrary but is two orders of magnitude above that previous calcu-lated, and, more importantly is significantly larger than the resonant inductor.It is not a ridiculously large value that would make it difficult or expensive tomanufacture. n

If we use the value of Lo = 300µH then we can recalculate the value of the filterinductor. Substituting this value of Lo into (2.169) we get:

Co = 3µF (2.170)


+

-inV

swi

7.112 HrL m=

0.3559 FrC m=

3 FoC m=

LoadR

300 HoL m=

rCv

ovbulkC

swD

fD

rLi

Li o oi I»

Figure 2.55: Final design of the resonant buck ZVS circuit.

This completes the design calculations for the power supply under minimumcurrent conditions. The completed design is show in Figure 2.55 with the circuitparameters shown.

If the circuit is operating at maximum power the operational frequency ofthe converter will change. This is due to the fact that in the t2 → t3 time will belonger. You may recall from (2.151) that the rate of increase of the iL currentis only related to the input voltage and the value of Lr. Since the negativecurrent starting point when the switch is re-closed is a large value, then clearlythis time will be much larger. This means that the effective topen time of theswitch will be much longer, and consequently the tclosed time will need to belonger to compensate for this increase in time.

Remark 2.80 The point made in the previous paragraph is a negative for theZVS resonant converter. It appears to be much more susceptible to load effectswith respect to the switching frequency as compared to the ZCS form of theconverter. n

The worst case rise time of the current is:

δt2→3 =LrVdδiL =

7.112e−6

24× 40 = 11.85µsecs (2.171)

Therefore the total worst case time for there to be no voltage applied to theoutput inductor is:

topen = 10.7016e−6 + 11.85e−6 = 22.5516µsecs (2.172)

Remark 2.81 This value is likely to be quite inaccurate because it was derivedusing worst case assumptions – we used you may recall the three quarters pointin the resonant cycle for the worst case resonant time. In the high current casethis will be more in error because of the large amplitude of the resonant pulse.n

The effective duty cycle has to be such as to produce the correct average outputvoltage. As in the previous analysis we have:

tclosed =5

24− 5topen = 5.93µsecs (2.173)


ZVS Resonant Buck − Ideal current sink load at 6 Amp

t(s)

1.66m 1.67m 1.68m 1.69m 1.7m 1.71m

(V

)

−10.0

0.0

10.0

20.0

30.0

40.0

(V

)

−10.0

0.0

10.0

20.0

30.0

40.0

50.0

60.0

(A

)

−7.5

−5.0

−2.5

0.0

2.5

5.0

7.5

locmax: (0.0016679, 50.81)

Ave: 5.0797

period: 12.8u

M

Switch sig

(V) : t(s)

Diode voltage

(V) : t(s)

Cr cap voltage

(A) : t(s)

Lr inductor current

Figure 2.56: ZVS circuit without output filter but with an ideal current sourceload at 6 Amps.

Therefore the effective duty cycle becomes in this case:

Deff =tclosed

topen + tclosed=

5.93

22.5516 + 5.93= 0.2083 (2.174)

as was found previously. The new switching frequency is:

fs =1

topen + tclosed=

1

22.5516e−6 + 5.93e−6= 35110 Hz (2.175)

Remark 2.82 One can see that the frequency of operation has dropped signifi-cantly. This will therefore affect the output filter components dramatically if thesame ripple is to be obtained. n

Answer to Part (c)

In this section we consider the simulation results. The first set of results inFigure 2.56 are for the light load case where the load is modeled as an idealcurrent sink of 6 Amps. As can be seen the frequency of operation and thewaveform amplitude are as predicted in the design.

If we include the load filter in the circuit, but still with an ideal current sinkas the load, then we can the results shown in Figure 2.57. As can be seen theresults are largely the same as those in Figure 2.56.


VS resonant buck − I_o = 6Amp, LoCo filter, Current Source Load.

(V

)

4.9

4.925

4.95

4.975

5.0

5.025

5.05

5.075

5.1

t(s)

8.035m 8.04m 8.045m 8.05m 8.055m 8.06m 8.065m

(V

)

−10.0

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

(A

)

−7.5

−5.0

−2.5

0.0

2.5

5.0

7.5

period: 12.8u

X_Max: (0.008055, 50.79)

PK2PK: 0.0838

M

n_15

(V) : t(s)

Vo

(V) : t(s)

Cr voltage

(A) : t(s)

Lr inductor curret

Figure 2.57: ZVS circuit with output filter and ideal current source load at 6Amps.

Finally if we include a resistor in circuit. The Saber model appears in Fig-ure 2.58, and the results of the simulation with a 6 Amp output current appearin Figure 2.59. As can be seen the results are very similar to the ideal cases.The ripple current is within specification.

If we increase the output current to the full load value of 20 Amps thenwe have to make a change in the frequency and the timing in the circuit. Theresult of the simulation of this circuit appears in Figure 2.60. As can be seenthe frequency of operation at 45872Hz is different from that calculated, mainlydue to the different time for the resonant pulse. This was noted as a point ofinaccuracy above. The rise time of the inductor current is virtually exactly ascalculated. The waveforms have again the correct form as discussed earlier.

Remark 2.83 In order to get a more accurate design one would need to pre-cisely calculate the resonant pulse width for the Cr capacitor voltage. n

Remark 2.84 One very interesting observation from the results in Figure 2.60is that the output ripple has not increased as we had predicted. The reason forthis is subtle. When we calculated the ripple we were assuming a normal buckconverter operating in continuous current mode. However, in the ZVS resonantconverter case during the period of t2 → t3 the Lr inductor current is buildingup, and therefore not all the current being supplied to the the load is having to besupplied from the Lo inductor. Therefore it does not use as much stored energy,and hence it is able to keep more continuous current flow. Therefore the ripplespecification is satisfied without having to change the output filter capacitor. n


gnd

sw1_l4

7.112u

ref:l1

v_dc

24

pwld

pw

ld

ref:

pw

ld2

BIT

STREAM

prbit_l4

bits:[(tx=0,bit=_1),(tx=1n,bit=_1),(tx=1.1n,bit=_0),(tx=8.5u,bit=_0),(tx=8.5001u,bit=_1)]

period:12.8u

pwld

0.3

55

9u

ref:

c3

300u

ref:l2

3u

ref:c2

0.8333

Figure 2.58: Saber circuit used for the 6 Amp full simulation.

ZVS resonant waveforms, with output filter and resistor − 6 Amp output

t(s)

4.305m 4.31m 4.315m 4.32m 4.325m 4.33m 4.335m 4.34m 4.345m 4.35m

(A

)

−7.5

−5.0

−2.5

0.0

2.5

5.0

7.5

(V

)

−10.0

0.0

10.0

20.0

30.0

40.0

50.0

60.0

(V

)

4.925

4.95

4.975

5.0

5.025

5.05

period: 12.8u

Maximum: 50.82

PK2PK: 0.06894

M

n_15

(A) : t(s)

Lr current

(V) : t(s)

Cr voltage

(V) : t(s)

V_o

Figure 2.59: ZVS circuit with output filter and resistive load at 6 Amps.


ZVS resonant buck − Io=20Amp, Output filter and R load

t(s)

6.33m 6.34m 6.35m 6.36m 6.37m 6.38m

(A

)

−20.0

0.0

20.0

40.0

(V

)

0.0

50.0

100.0

150.0

(V

)

4.92

4.94

4.96

4.98

5.0

5.02

(V

)

−20.0

0.0

20.0

40.0

(A

)

19.7

19.8

19.9

20.0

20.1

M

n_15

(A) : t(s)

Lr current

(V) : t(s)

Cr voltage

(V) : t(s)

Vo ripple

(V) : t(s)

Diode voltage

(A) : t(s)

Lo current

period: 21.8u

PK2PK: 0.062998

Delta X: 11.85u

X_Max: (0.0063686, 112.83)

Delta X: 5.9446u

Delta X: 17.276u

Delta X: 4.224u

Figure 2.60: ZVS circuit with filter circuit and resistive load, output current20 Amp.

Chapter 3

Switch Mode Power Supplies

3.1 Introduction

In the previous chapter we looked at some fundamental topologies for switchmode converters. In this chapter we shall build on this basic information byconsidering some topologies that are used for commonly available switch modepower supplies (SMPSs). Towards the end of the chapter we shall consider someaspects of the control of these power supplies.

3.2 Isolated Converter Topologies

The converters presented in the previous chapter were all non-isolated convert-ers. However, in practice isolated converters are very common. This is due tothe fact that these converters do offer electrical isolation, but more importantlythat allow the simple production of a number of voltages that are all electricallyisolated. simple production

of a number ofvoltages

In this section the isolated converters will be related back to the basic topolo-gies of the previous chapter. We do not look at all possible isolated topologies,since there are far too many to do this. Instead we concentrate on the ba-sic types, from which all the others have common features. The fundamentalprinciples of operation are emphasised.

3.2.1 The Forward Converter

Figure 3.1 shows the basic idealised circuit for the forward converter. Theforward converter is derived from the buck converter shown in Figure 2.2. Theconnection between the two converters is not obvious at a first glance. Onemay recall that the main distinguishing feature of the buck converter is thatwhen the switch is closed the input is connected to the output. In the caseof the forward converter this is not literally true due to the isolation of thetransformer. However, when the switch is closed the secondary side of thetransformer is reflected to the primary, so in effect this connection exists.

When the switch in the buck converter is opened then the input is discon-nected from the output. In the forward converter this occurs due to the factthat the voltage across the transformer reverses (because of the trapped flux in

3-2 Switch Mode Power Supplies

the transformer), and the diode D1 is reversed biased and disconnects the loadfrom the transformer secondary.

Remark 3.1 The above-mentioned trapped flux in the magnetising inductanceof the transformer is a new problem that does not exist in the conventionalbuck converter. If one were to operate the forward converter as described in theparagraph above then the switch would be destroyed by the very high voltagescreated as the flux in the magnetising flux attempts to maintain the currentthrough the open switch.

Vd

VoC

L

vL

+ -

iL

D1

D2

N2

N1 R

L

SW

Figure 3.1: Basic circuit of the forward converter.

Figure 3.2 shows a practical forward converter circuit. In this circuit wepractical forwardconverter introduce a third winding to transfer the energy trapped in the magnetising

inductance back to the supply. This winding plays no part when the switchis turned on, but when the switch is turned off and the voltage across themagnetising inductance reverses then, due to the turn direction of the thirdwinding, diode D3 turns on and current flows back into the supply. This limitsthe rate at which the flux collapses in the magnetising inductance, and thereforethe voltage induced by this collapse is controlled.

The operation of the circuit can be better understood by referring to theequivalent circuit in Figure 3.3. This circuit is based on using the concept ofthe ideal transformer that does not require any mmf to operate.1

Ignoring the leakage inductances, the flux is stored in the Lm inductance.When the switch is closed current builds up in this inductance, and at the sametime current, i1 flows into the transformer. The voltage v1 appears across themagnetising inductance, and this is reflected via the transformer voltage ratio to

1The transformer has a magnetic structure with infinite permeability and consequently thecoupling between the windings is one. This also implies that the primary winding has infiniteinductance.

3.2 Isolated Converter Topologies 3-3

VoC

L

vL

+ -

iL

D1

D2

N2 R

L

D3

N1

N3

SW

Vd

Figure 3.2: A practical forward converter.

D1

D2

D3

Ll1

Ll2

LiL

CR

L Vo

Vd

SW

Lm N

1N

2

N3 + -v

L

i1

i2

i3

vsw

im v

1

Ideal transformer

Figure 3.3: Equivalent circuit for a practical forward converter.


winding 2 (the secondary). Similarly the current i1 is reflected as i2 in winding2 via the transformer current ratio. This current then feeds the load via theoutput LC filter.

When the switch is opened then the current im flowing in the magnetisinginductance cannot stop instantaneously. As can be seen from the equivalentcircuit the current can flow in a loop via the ideal transformer. The dot rela-tionship between the primary and ternary winding means that the voltage Vdappears across the ternary winding. This voltage is reflected to the primarywinding voltage as v1 = −Vd. This implies that vsw = 2Vd. Therefore, thepresence of the third winding keeps the voltage across the switch to a reason-able and controllable value, and essentially returns the energy trapped in themagnetic field of the magnetising inductance to the supply.

The above discussion omitted the influence of the leakage inductance. Un-fortunately the presence of leakage disrupts the ideal operation. If we againinfluence of leakage

inductance consider Figure 3.3, we can see that the leakage inductance carries im + i1, andtherefore it would store the energy 1

2Ll1(im + i1)2. As with the magnetisingcurrent this stored energy will attempt to maintain the current in the samedirection. Therefore when the switch is opened a large voltage can be producedacross this inductance, which would also result in a high vsw voltage. Even forfairly small values, the voltage produced could result in the destruction of theswitch.

Remark 3.2 In order to minimise the leakage inductance the primary andternary winding are often bifilar wound – i.e. they are both wound on the samearm of the transformer. The secondary may not be wound like this as largevoltage isolation between the primary and secondary is often very important.

Remark 3.3 In order to catch any voltage spikes associated with the leakagesone may need some “snubbers” across the switch.

Remark 3.4 The wire used for the ternary winding can be much smaller gaugethan the secondary winding as it only has to carry the magnetising current ofthe transformer.

Now let us consider the operation of this forward converter in a little more detail.Assuming for the moment that we are dealing with the ideal forward converteras depicted in Figure 3.1, and assuming that the transformer is ideal. If theswitch is turned on, then there will be current flowing through the transformerprimary, and hence the secondary. Since the voltage ratio of a transformer is:

v2

v1=N2

N1(3.1)

then we can deduce that:

vL =N2

N1Vd − Vo for 0 < t < ton (3.2)

which is a positive value, causing iL to increase in value.When the switch is turned off then the diode D1 is reverse biased, effec-

tively disconnecting the transformer from the remainder of the secondary side


circuit. The trapped energy in the filter inductor causes the diode D2 to turnon, allowing current to circulate. In this case the inductor voltage is:

vL = −Vo for ton < t < Ts (3.3)

which is negative, resulting in a decreasing current in the filter inductor.If one integrates the inductor voltage over one complete period and equate

to zero one gets: forward convertervoltage ratioVo

Vd=N2

N1D (3.4)

Remark 3.5 One can see from (3.4) that the voltage ratio is the same, inprinciple, as that for the buck converter. However, whilst a buck convertercan only produce voltages less than the input voltage, the forward converter canproduce voltages that are greater than the input voltage with an appropriate turnsratio for the transformer.

As we have previously noted, in a practical forward converter one must accountfor the energy trapped in the magnetising inductance. Let us now consider howthis requirement alters the operational range of the converter output voltages.The following discussion is with reference to Figures 3.3 and 3.4.

Vd

v1

-

N

NV

d

1

3

t

t

t

iL

ton

toff

Ts

isw

i1

im

i im1

=

tm

Figure 3.4: Current waveforms for a practical forward converter.


When the switch is closed then:

v1 = Vd for 0 < t < ton (3.5)

and the current through the magnetising inductance, im, increases at a linearrate (as can be seen in Figure 3.4). When the switch is opened at time ton, theimton must instantaneously keep flowing. This is achieved via the primary coilof the ideal transformer.

Note 3.1 The capacity for the magnetising current to flow through the primaryof the ideal transformer is due to a property of transformers. The circuitryconnected to the secondary winding of the transformer is reflected (via a turnsratio relationship) to the primary. Therefore, the current is actually flowing inthe secondary circuit, but reflects in such a way as to create the illusion that itis flowing in the primary. From this point of view Figure 3.3 is a little deceptive.

When the switch is opened, as previously mentioned, the voltage induced inwinding 2 is such that the diode D1 is reversed biased, thereby disconnectingthe secondary circuit. At the same time, diode D3 turns on due to the voltageinduced in winding 3. Therefore this winding effectively becomes the secondaryunder this condition. Under this condition the currents flowing in the circuitsare: i1 = −im, i2 = 0 and i3 becomes (from the normal current ratio for anideal transformer):

i3 =N1

N3im (3.6)

During the time tm, when the i3 current flows, the voltage across the transformerprimary is:

v1 = −N1

N3Vd for ton < t < ton + tm (3.7)

since Vd is the voltage across winding 3.When the transformer demagnetises, then im = 0 and v1 = 0. The time

can be obtained by realising that the time integral of the voltage across themagnetising inductance must be zero over a complete time period (for steadystate operation). Considering Figure 3.4 one can see that:

VdDTs −N1

N3Vdtm = 0 (3.8)

∴tmTs

=N3

N1D (3.9)

If the transformer has to be totally demagnetised before the start of the nextcontrol interval, then the maximum value of tm/Ts = 1 − D. Therefore themaximum duty cycle, using (3.9) is:Forward converter

maximum duty cy-cle (1−Dmax) =

N3

N1Dmax (3.10)

∴ Dmax =1

1 + N3

N1

(3.11)

Remark 3.6 Equation (3.11) indicates that the maximum duty cycle is 0.5 ifN1 = N3 (a common choice in many designs).


3.2.1.1 Other Forward Converter Topologies

We shall not go into detail into the other forward converter topologies, but shallsimply show the basic design and highlight a few pertinent properties. Only asubset of the available of forward converter topologies will be presented.

3.2.1.1.1 Two Switch Converter This topology is shown in Figure 3.5.In this converter each of the switches are turned on and off simultaneously.Consequently each switch only has to stand a maximum voltage of Vd. Oneof the other nice features of the circuit is that the magnetising and leakagecurrents can flow via the diodes to the supply, thereby eliminating the ternarywinding on the transformer, and negating the requirement for snubbing acrossthe switches. A Dmax = 0.5 limitation applies to this converter.

Vd V

oN

2N

1

SW2

SW1

Figure 3.5: Circuit diagram of a two switch forward converter.

3.2.1.1.2 Push-Pull Converter This topology is shown in Figure 3.6. Thesalient feature of this topology is the centre tap transformer used. One of themain limitations of the previous forward converters was that the duty cycle waslimited to a maximum value of 0.5. This limitation occurred due to the needto demagnetise the transformer prior to the start of the next switching cycle.The push-pull form of the forward converter effectively allows one to get a fullduty cycle range, at the cost of a more elaborate transformer and two switchingdevices.

We shall spend a little more time investigating this circuit because a fewimportant concepts can be gleaned from this that are of use in Power Electronicsand circuits in general.

One can see from Figure 3.6 that only one half of the transformer is activeat any one time, since only one of the switches is turned on at any one time.For example, if SW1 is closed then current will flow from the supply via the


SW1

SW2

N1

N1

N2

N2V

d

Vo

D1

D2

L

RLC

Figure 3.6: Push-pull forward converter.

top half of the primary through SW1. This will result in a voltage developingacross the top half of the secondary winding consistent with the dot conventionof the windings. The resultant current flows via diode D1 to the load.

If SW2 is closed (then SW1 is open) a similar pattern occurs. In this case thecurrent flows from the source via the bottom half of the primary through SW2.The dot convention with this half of the primary in relation to the secondarymeans that diode D2 is forward biased (and D1 is reverse biased). Thereforeagain current flows to the load. The diode arrangement on the secondary is aconventional full wave rectifier circuit.

As with the previous cases one ends up with magnetic energy trapped in themagnetising inductance of the primary. In this particular case the other halfof the primary winding that is not conducting current when the correspondingswitch is closed corresponds to the ternary winding shown in Figure 3.2. Thetwo halves of the primary essentially form an autotransformer. If we operatethe circuit so that there is a period of operation when both of the switches areoff, then a question that immediately arises is “what happens to the trappedmagnetic energy in the core of the transformer?”. This turns out to not bean easy answer in the sense that the solution takes a deal of insight into howtransformers work.

We shall consider the operation of the circuit if both switches are in theoff state using two approaches – the first is the conventional equivalent circuitapproach, and the second is based on realising that the total mmf in the circuitcannot change instantaneously.

Consider the situation where switch SW1 has been closed and then it hasbeen opened. Switch SW2 is left open. When SW1 was closed then the top halfof the secondary transformer would be positive, and consequently the diode D1

is forward biased. We shall assume that the filter inductor L is large enoughthat the current iL is constant. Hence the current iL flows through D1.

When SW1 is opened then there is flux in the core of the transformer. Thisflux must be maintained by a current. This current is often called the magnetis-ing current, and it is assumed to flow through a “fictitious” circuit element called


the magnetising inductance. This element is usually placed in the primary sideof a transformer.

From Figure 3.7 one can see that the current flowing through SW1 is com-posed of two components – the load current (with the appropriate turns ratio)and the magnetising current. Normally the magnetising current is small com-pared to the load component. We are assuming that the transformer is ideal –i.e. it does not require any mmf to magnetise it. The magnetising current isflowing through the magnetising inductance to produce the flux that is presentin any “real” transformer.

When SW1 is opened then we have the situation shown in Figure 3.8. Onthe primary side of the transformer there are two main effects to consider.The current shown in Figure 3.7 flowing through the leakage inductance of theprimary (Ll) wishes to continue flowing. Therefore a voltage is developed acrossthe leakage in an effort to achieve this. This voltage appears in conjunction withthe supply voltage across SW1 – this is voltage vLl+Vd in Figure 3.8. A snubberis often required across the transistors to cope with this voltage spike.

N1

N1

N2

N2

Vo

D1

D2

L

RLC

Vd

im

Lm

Ll

SW1

N

Ni iL m

2

1

+iL

Ideal transformer

N

NiL

2

1

Diode is open

circuit.

N

NV

d

2

1

Vd

N

NV

d

2

1

Figure 3.7: Currents flowing in the push-pull forward converter with SW1 closed.

The second salient point on the primary side of the circuit is that the currentflowing through the magnetising inductance cannot be changed instantaneously.Therefore a voltage would normally develop across the magnetising inductancein an effort to maintain this current. This voltage has a polarity with thepositive on non-dotted terminal of the top half of the transformer. However,this is coupled by the ideal transformer to the secondary. This would producea positive voltage on the non-dotted terminals of the secondary. Consequentlythe diode D2 would become forward biased. Diode D1 also remains forwardbiased as well, meaning that the (constant) iL current splits between D1 andD2. This then provides a path for the magnetising current to flow. If this circuitwas a normal push-pull inverter circuit then the diode across SW2 would turn


N1

N1

N2

N2

Vo

D1

D2

L

RLC

Vd

im

Lm

Ll

SW1

iL

Ideal transformer

im

vL

l

+

v VL d

l

+

+

Both diodes

short circuit

iL

i N

Ni

L

m2

1

2

+

i N

Ni

L

m2

1

2

-

Figure 3.8: Currents flowing in the push-pull forward converter with SW1 andSW2 open.

on and clamp the voltage across the top half of the winding to Vd. However,the presence of the full wave rectifier circuit on the secondary side of the circuitchanges this “normal” scenario.

One point that is not obvious in Figure 3.8 is why does the current iL splitbetween the two secondary windings? When D2 becomes forward biased whydoesn’t D1 become reverse biased? The answer to these questions is that theconstant load inductor current prevents this from happening. If D1 attemptsto turn off, then the load current would immediately be diverted into the lowerhalf of the secondary. This would mean that a voltage would be induced inthis part of the winding (since a rate of change of flux in the core would result)such that diode D2 would turn off, and D1 would turn on. Therefore the stablesituation is that shown in Figure 3.8. Note that due to the dots on the secondary,the iL/2 current in each half of the windings would produce fluxes that canceleach other. Therefore the only component of flux producing current is themagnetising component reflected into the secondary which circulates around theloop comprising the two diodes and the transformer secondaries. Another wayof reasoning this is to realise that when SW1 is opened the reflected iL currentmust become zero. Consequently the effective iL current through the secondaryof the transformer must also be zero (else we cannot have zero reflected iL onthe primary side). Given that iL is held constant by the filter inductor, theonly way that this can be achieved is if there is net zero flux produced by thesecondary winding due to iL. This is achieved by D1 and D2 both being on,since this results in flux cancellation in the secondary winding.

There is an alternative way of reasoning the splitting of the inductor currentbetween the two secondary windings. This technique is simple, and can beapplied to very complex coupled winding situations. For the moment considerthe transformer to be ideal – i.e. the magnetising inductance is infinite. WithSW1 closed all the current flowing in the primary is reflected into the secondary.In terms of mmf, an ideal transformer does not require any mmf to set up the


flux in the core. Therefore we have:

N1i1 +N2iL = 0 (3.12)

i.e. no net mmf in the transformer.When SW1 opens the net mmf in the core cannot change since the trans-

former is ideal – i.e. it has to remain zero. The current in the load inductor isconstant, therefore this current must split between the two secondary windingsso that the flux produced by one is cancelled by that produced by the other,thereby keeping mmf in the core zero – i.e. when the switch is opened i1 = 0,therefore the second term in the mmf expression must also be zero. This oc-curs if the other term is 1

2N2iL+(− 12N2iL), which implies the above-mentioned

splitting of the currents.The overall result ofD1 andD2 being on simultaneously is that the secondary

windings are short circuited. This value is mirrored to the primary, and itsvoltage will be zero (if D1 and D2 are ideal).

It can be shown that the voltage ratio [2] for this converter is: push-pull voltageratio

VoVd

= 2N2

N1D (3.13)

where 0 < D < 0.5. Therefore, even though the range of the duty cycle islimited to 0.5, the output voltage can achieve values as if the duty cycle has arange from 0 to 1.

Remark 3.7 One potential problem with the push-pull converter is that theswitches are subject to maximum voltages of 2Vd. For low voltage applicationsthis is of little consequence, but for mains line applications with 240VAC thismeans that the devices will be subject to minimum voltages of 700V. Therefore,1000V MOSFETs are required to ensure that there is sufficient over voltagecapacity.

Remark 3.8 One of the potential problems with the push-pull circuit is thatsmall differences in the timing of the duty cycles of the two switches can lead tooffsets in the flux of the transformer. These timing differences can occur becauseof differences between the turn-on times of the transistors, or differences in thespeeds of the firing circuits. Consider Figure 3.9 which shows a typical BH curvefor a ferro-magnetic material. As the ideal push-pull circuit operates it normallymoves from B1 to B2 via the hysteresis loop shown. If the “on” transistor isdriving the flux density to B2, and its on-time is a little less than the othertransistor, then the flux density may not quite get to B2, but instead only getsto B2a. Therefore, when the other device turns on it will drive the flux densityto a value a little higher than B1, B1a. This process will continue, and themaximum flux density B1a will creep up higher on the BH characteristic. If theprocess continues then the core will saturate at the higher flux densities and themagnetising inductance of the core will become very small and excessive currentswill flow through the transistor that is on when this occurs. This often resultsin transistor failure. Current mode control is often used to fix this problem.MOSFET transistors also help, as they have a positive temperature coefficient,and as they heat up more of the voltage is dropped across the device, therebyrobbing volt seconds from the magnetising inductance. The resistance of theprimary also helps via a similar mechanism.


H

B

B1

B2

Normal

operation

loop

Loop with

flux imbalance

B B1 2

=

Ba2

Ba1

Figure 3.9: Flux imbalance in the push-pull circuit.

Practical issue 3.1 One very nice feature of the push-pull converter is thatboth of the transistors are referenced to the same ground rail. This simplifiesthe drive circuits for transistors as compared to other topologies where one hastransistors floating at different voltage levels.

3.2.2 The Flyback Converter

The Flyback converter is an isolated converter that is derived from the buck-boost converter described in Section 2.3.3 of the previous chapter. Figure 3.10diagrammatically shows this connection. Recall from Section 2.3.3 that theimportant properties of the buck-boost were that when the switch is closed itperforms similarly to a boost converter, with the input disconnected from theoutput and the current flowing through an inductor storing energy. When theswitch is opened then the energy stored in the inductor is then transferred to thesecondary winding, and in the process of doing this the energy storage inductoreffectively becomes the filter inductor in the load section of the circuit. Thisinductor connects the input to the output when the switch is open.

If we compare the buck-boost shown in Figure 3.10 with the Flyback con-verter, then we can see that the magnetising inductance of the transformercarries out the same function as the storage inductor in the traditional circuit.During the phase when the switch is closed current flows through the magnetis-ing inductance. During the time the output circuit is disconnected from theinput because the diode is reversed biased. When the switch is opened, thecurrent through the magnetising inductance wishes to keep flowing in the samedirection. It therefore produces a positive voltage on the non-dot end of theprimary, resulting in a corresponding positive voltage on the non-dot end of thesecondary. Consequently the diode in the secondary becomes forward biased,


and the magnetising current in the primary is reflected (via the turns ratio)in the secondary. This current flows into the output capacitor. In effect themagnetising inductance in the primary has been reflected into the secondary,and it performs the same function as the filter inductor in the classical buckconverter circuit.

Vd

SW

Vd

N1

N2

Buck-Boost Converter Flyback Converter

Vo

Vo

Figure 3.10: Connection between the Buck-Boost and Flyback converter.

Now let us consider the operation of the Flyback converter in more detail.Again we shall assume steady state operation, and the output voltage is consid-ered constant. We shall look in some detail at the variation of the flux in thecore, since it is the flux that stores the energy that is transferred to the load.

One can calculate the flux in an inductor by using Faraday’s Law:

vL =Ndφ

dt(3.14)

∴ φ(t) =1

N

∫ t

0

vL(τ)dτ + φ(0) (3.15)

In the case when the switch is closed, as shown in Figure 3.11, there is a constantvoltage of Vd applied across the magnetising inductance, Lm. The secondary sideof the circuit may as well not be there, since the diode in the secondary effectivelydisconnects the load from the primary. The load current Io is supported bythe capacitor. It is therefore important that the capacitor be large enough tosupport the current and voltage appropriately during the switch “on” period.Equation (3.15) can therefore be written as:

φ(t) = φ(0) +VdN1

t for 0 < t < ton (3.16)

and clearly the peak flux in the magnetising inductance at the end of the “on”period is: flyback peak flux

φ = φ(0) +VdN1

ton (3.17)

At the end of the time ton the switch is opened. Because the current flowingin the magnetising inductance cannot change instantaneously, or alternatively


Diode reverse biased

SW

Lm

im

v1

Vd

Vo

iD

= 0

N1

N2

N

Nv

N

NV

d

2

1

1

2

1

=

Io

C RL

Figure 3.11: Flyback converter with the switch closed.

the total mmf in the transformer cannot change instantaneously, then a voltageis induced on the secondary (the polarity determined by the dot convention), insuch a manner as to turn on the diode in the secondary. The circuit configurationthen changes to that shown in Figure 3.12.

As can be seen from the figure a voltage of Vo is produced across the sec-ondary so that the diode turns on. The voltage N1

N2Vo is produced across the

primary, with a polarity that will cause the magnetising current to decrease.Another way to look at this is to realise that the secondary circuit is reflectedto the primary by the transformer, and therefore the magnetising current canflow in this reflected circuit.

During the “off” stage of operation, the flux in the transformer core willdecrease from the peak value calculated in (3.17). Therefore the time evolutionof the flux during this time is again given by applying Faraday’s Law:

φ(t) = φ−N1

N2Vo

N1(t− ton) (3.18)

∴ φ(t) = φ− VoN2

(t− ton) for ton < t < Ts (3.19)

From (3.19) one can deduce, using (3.19) and (3.17), that the flux at the end ofthe control interval:flyback flux at Ts


Diode forward biased

SW open

Lm

im

Vd

Vo

iD

N1

N2 V

o

vN

NV

o1

1

2

=

Io

C RL

Figure 3.12: Flyback converter with the switch open.

φ(Ts) = φ− VoN2

(Ts − ton) (3.20)

= φ(0) +VdN1

ton −VoN2

(Ts − ton) (3.21)

We are again assuming that the system is in steady state, therefore the flux atthe beginning and end of a control interval must be the same. This means that:

φ(Ts) = φ(0) (3.22)

which, using (3.21) allows us the write:

φ(0) +VdN1

ton −VoN2

(Ts − ton) = φ(0) (3.23)

∴VdN1

ton =VoN2

(Ts − ton) (3.24)

Rearranging this, and using (2.2) we can write: flyback voltage ratio

VoVd

=N2

N1

(D

1−D

)(3.25)

Remark 3.9 The voltage ratio in (3.25) is identical to the voltage ratio calcu-lated for the buck-boost converter, as shown in (2.67).

The currents flowing in the circuit under the switch “on” and “off” conditionsare shown in Figure 3.13


t

t

t

v1

Vd

-

N

NV

o

1

2

tont

off

0

Io

f

f( )0

iD

N

Nim

1

2

Ts

Figure 3.13: The voltage, current and flux in the ideal Flyback Converter.


Let us calculate the currents flowing in the Flyback converter. This analysisbasically follows the same procedure as the calculation of the magnetising flux.Assume that the current at the beginning of a control interval has an initialvalue of im(0). Therefore during the ton period the magnetising and switchcurrent is:

im(t) = im(0) +VdLm

t for 0 < t < ton (3.26)

As with the flux, the peak magnetising current at the end of the “on” period is: peak magnetisingand switch current

im = im(0) +VdLm

ton (3.27)

Remark 3.10 Note that im is also the peak current flowing through the switch.

During the “off” period the switch current is obviously zero. During this timethe voltage across the magnetising inductance is of a polarity so that the currentdecreases. The current during this period is:

im(t) = im −N1

N2Vo

Lm(t− ton) (3.28)

The current in the diode during this period is simply a scaled version of theinductor current (by the transformer turns ratio). i.e.: flyback diode cur-

rent

iD(t) =N1

N2im(t) =

N1

N2

[im −

N1

N2Vo

Lm(t− ton)

](3.29)

Using the equations that we have derived it is now possible to get the peakmagnetising current in terms of the load current and voltage and the dutycycle. This is an important equation for this type of converter, since the peakmagnetising current needs to be known so that saturation of the core can beavoided, and the switches can be sized. The first step is to work out the averageexpression for the diode current, which is also equal to the average load current(in steady state).

Taking the average of (3.29) and rearranging we can get the expression forthe peak current in terms of the average load current and the output voltage: peak switch current

im =N2

N1

Io(1−D)

+1

2

Vo

(N1

N2

)Lm

(1−D)Ts (3.30)

The peak voltage across the switch can be seen to be the supply voltage plusthe voltage produced by the transformer:

vsw = Vd +N1

N2Vo (3.31)

which can be written, using (3.25), as:

vsw =Vd

(1−D)(3.32)


3.2.3 Utilisation of Magnetics

One important factor in the performance of converters is the utilisation of themagnetic material. Converters such as the boost and flyback converter arestoring energy in the magnetic field and then transferring this stored energy tothe load when the switching device is turned off. A converter such as the forwardconverter is transferring energy via direct transformer action – the stored energyis a nuisance in that it has to be transferred somewhere when the power deviceis turned off. Despite this two different modes of operation, both these convertertypes are only magnetising the core in one direction. The full bridge converter,on the other hand, is really a variant of the forward converter, but it is differentin that the core is magnetised on both directions during normal operation.This bidirectional magnetisation has implications on the utilisation of the corematerial.

One of the main motivations for the use of SMPSs is their low weight andvolume. Therefore it is essential that the magnetic material is well utilised toachieve these objectives.

Consider Figure 3.14 which shows a typical BH curve for a magnetic material.The flux density Bm is the maximum flux density that can be achieved whenthe material is saturated. The flux density Br1 is the remnant flux density whenthe core is not being subject to an mmf.

H

B

Bm

Br1

Original magneticmaterial (no air gap)

Magnetic materialwith air gap

Br2

Figure 3.14: Typical BH loop for a magnetic material.

Figure 3.15 shows the excitation waveforms for a forward converter witha feedback winding such that N1 = N3 (Figure 3.15(a)), and a full bridgeconverter (Figure 3.15(b)) with the same primary turns. The voltage v1 is thevoltage across the primary winding. We shall assume that both converters areoperating with D = 0.5. ∆Bmax is the excursion of the flux density from theaverage value of the flux density.

Note 3.2 It should be noted that the use of a full bridge converter in this modeis entirely artificial. Under a duty cycle of 0.5 the average output voltage of thisconverter is zero. The output could be used to drive a transformer connected


to a rectifier to get a different output voltage. If a modulation strategy usingzero voltage application is used then control of the DC output voltage could beobtained.

The reason for the artificial D = 0.5 restriction is that this will force the fluxin the core (under appropriate start up conditions) to be bidirectional.

Remark 3.11 A better converter to use for this example is the push-pull con-verter. This converter can perform all the functions of the full bridge if a DCoutput is required, only involves two switches, and can be made to operate withsymmetric bidirectional flux in the core of the transformer (with modified firingof the switches using a combination of current control and zero voltage applica-tion).

t

t t

t

1v

1v

DB DB

( )maxDB( )maxDB

Tf

s

s

( )=1

Tf

s

s

( )=1

ton tontoff

toff

Vd

Vd

0

0 0

0

(a) (b)

-Vd

-Vd

Figure 3.15: Core excitation waveforms. (a) forward converter. (b) full bridgeconverter.

Let us consider the expression for the maximum deviation of the flux densityaway from the average value. We know from Faraday’s Law, (3.14), and therelationship φ = BAc, where Ac , the area of the core, that flux density canbe written as:

B =1

N1Ac

∫ ton

0

v1dτ +B(0) (3.33)


We are interested in the total change in B from whatever initial condition thereis. We shall call this ∆B. This allows us to ignore the initial condition B(0)in the following evaluation.2 Assuming that D = 0.5 (which implies that ton =Ts/2), and v = Vd then we can write:

∆B =1

N1Ac

∫ Ts2

0

Vddτ (3.34)

=VdTs

2N1Ac=

Vd2N1Acfs

(3.35)

This value corresponds to the peak value of the flux in Figure 3.15(a). Toevaluate the average value we calculate the area under the ∆B curve and divideby the time (since in Figure 3.15(a) the ∆B waveform is triangular). Thereforeusing (3.35) the expression for ∆Bave is:

∆Bave =

(Vd

2N1Acfs

)Ts2

Ts(3.36)

=Vd

4N1Acfsfor D = 0.5 (3.37)

We can now find ∆Bmax, the maximum deviation of the flux from the averageflux, by subtracting (3.37) from (3.35) to give:

∆Bmax =Vd

4N1Acfsfor D = 0.5 (3.38)

which is valid for both converters.Maximum flux ex-cursion. A little earlier we mentioned that we had ignored the initial value of the flux

density, but in the footnote we noted that this would be important. Referringto Figure 3.14, one can see that when there is no excitation of the core thatthe remnant flux density is Br. Therefore this point on the BH characteristicis the starting point for any unidirectional flux excursion – i.e it is the initialcondition B(0) in (3.33). Therefore, using the definitions in Figure 3.14 theforward converter flux excursion ∆Bmax becomes:

∆Bmax =1

2(Bm −Br) (3.39)

i.e. the flux excursion is limited by the remnant flux density in the core. Becausethe flux is starting off with the Br offset, then the flux cannot undergo largeflux excursions.

In the case of the full bridge converter, the flux undergoes symmetric fluxdensity excursions about the zero flux density point in Figure 3.14.3 Therefore∆Bmax is limited only by the saturation flux of the core – i.e.:

∆Bmax = Bm (3.40)

2Note the the initial condition is very important when it comes to evaluating the magneticutilisation, as we shall see.

3This is achieved because of the switch drive circuits are designed to produce these fluxexcursions. Note that it is not intrinsic in the design of these converters that this wouldhappen.


What are the implications of these differences in the maximum flux density thatcan be achieved with these converters? These can be gleaned by considering(3.38) in the light of the above comments. Rearranging (3.38) we get:

Ac =Vd

4N1(∆B)maxfs(3.41)

We can see from this expression that if ∆Bmax is large then Ac can be smaller.Therefore, given the same applied voltages, duty cycle and switching frequency,and for the same number of turns on the primary, the full bridge converter willhave a significantly smaller core for the magnetics as compared to the forwardconverter.

Remark 3.12 Equation (3.41) assumes that fs is the same and N1 is the sameunder the condition of smaller core cross-sectional area. However, as can be seenfrom (4.23) in the following chapter, reproduced here for convenience:

L =µN2

1Aclc

(3.42)

where lc is the magnetic path length of the core, the inductance of the core ismuch less. This should also be obvious from the definition of inductance:

L =λ

i=N1BAc

i(3.43)

If Ac is smaller, then for the same current i the B will be the same (via AmperesLaw), and therefore λ will be smaller.

Therefore implicit in (3.41) is the fact that the current is allowed to increasewhen we have the smaller core area, since the same voltage is applied by theconverter across the winding for the same time, but the inductance is less.

Remark 3.13 As can be gleaned from Remark 3.12 there is a trade-off forthe reduced size magnetics under the condition specified – for the same poweroutput we have a larger magnetising current, therefore higher losses, and largerswitching devices.

Remark 3.14 The fact that one does not have to demagnetise the core in thepush-pull converter means, without considering the maximum flux density issue,one can produce more power from the same magnetic core. The effective maxi-mum duty cycle is 1, whereas for the forward converter it is 0.5 (depending onthe relative turns ratio of the ternary winding).

Remark 3.15 In general a bidirectional flux density change type of converteruses the magnetic material more effectively than a unidirectional flux densityconverter.

Remark 3.16 One can see from (3.39) that the maximum excursion of the fluxin the forward converter is limited by the remnant flux in the core. Thereforeone way to utilise the magnetics better in these types of converters is to reducethe remanence. This can be achieved by putting an air gap in the core. Thisto a large degree linearises the core operation, and also dramatically lowers theremnant flux density. This effect is shown diagrammatically by the dashed BHcharacteristic in Figure 3.14.


Under the condition of identical duty cycle, identical turns in the primary wind-ing and identical core area (i.e. the magnetising inductance of both cores is thesame), then flux in the cores is:

Forward converter:

Bmax = Bave + ∆Bmax +Br (3.44)

Bave =(2∆Bmax)Ts

2Ts(3.45)

∴ Bmax = 2∆Bmax +Br (3.46)

For the push-pull converter, assuming appropriate control (i.e. current con-trol), then:

Bave = 0 (3.47)∴ Bmax = 0 + ∆Bmax = ∆Bmax (3.48)

Therefore the push-pull converter has less than half the peak flux density in thecore. This would means that the core losses in this converter would be lowerthan those of the forward converter (see below on core losses).

The other issue that can limit the utilisation of magnetic cores in switchingpower supplies are core losses. The general expression for the core loss per unitvolume or weight is of the form:

Core Loss density = kfas [(∆B)max]b (3.49)

where the k, a, and b are determined from the particular material.One can see from this expression that the core losses are a complex func-

tion of frequency of switching and the maximum flux density excursion. If, forexample, the switching frequency is increased, then the maximum flux densitybecomes less, with everything else the same. Therefore, depending on the spe-cific values of a and b, the overall losses will be smaller. Also the total corevolume will be smaller, since the maximum flux density is less. On the otherhand, the switching losses in the active devices will increase with increased fre-quency. One can see that the optimisation of the core losses must be carriedout for each specific device.

3.3 Introduction to Control Techniques for Switch-ing Power Supplies

Now that we have looked in detail at several idealised converter topologies suit-able for switching power supplies, we shall now look at overall topological andcontrol issues. Due to the varying background of the students doing this subjectwe shall not delve deeply into the control issues, but instead, an overview of theconcepts involved will be presented. There are many references on issues relatedto the control of switching supplies, both in books and in several of the IEEETransactions, namely Power Electronics, Industrial Electronics, and IndustryApplications. Some of the books on these issues are [2, 5, 4].

Before looking at the control issues, we shall consider some broader topolog-ical and practical issues of switching supplies. Consider Figure 3.16 which is ablock diagram of a typical switching power supply (from [2]).

3.3 Introduction to Control Techniques for Switching Power Supplies 3-23

Error

Amplifier

PWM

Controller

Base and gate

drive circuitry

Rectifier

and

filterSwitches

Rectifier

and

filter

EMI

filter

Rectifier

and

filter

DC

DC

Mains

Supply

Vo

Vo -ref

Isolation

barrier

HF

Signal

Transformer

HF

Power

Transformer

Small

Mains

Transformer

DC-DC power convertion

Feedback circuitry

AC

Figure 3.16: Block diagram of a typical switch mode power supply.

As can be seen from Figure 3.16 we have looked at the detail of the dc-dcconversion section of the power supply in the first part of this chapter. The lowerhalf of the diagram is related to sensing of the feedback signals and the controlcircuitry. The important point to note here is that the feedback signals haveto be isolated from the input if we are to have an isolated power supply. Thiscomplicates the design of the supply considerably. The circuit of Figure 3.16is a conceptual diagram of one way of designing the isolated feedback. In thisconfiguration the control circuitry and PWM generation is on the output sideof the isolation. The other alternative is to have this circuity on the supply sideof the isolation, and only the output voltage is feedback in an isolated fashion. feedback isolation

The relative merits of the control circuitry on the supply side and the outputside are not clear cut. Having the control circuitry on the output side (as inFigure 3.16) has the advantage that one is transmitting pulsed signals (basicallyfiring pulses) across the isolation. This would also allow one to use an opto-coupler instead of a signal transformer. On the negative side the base drivecircuitry is a little more complicated.

If the PWM and control circuitry is on the supply side then the base drivecircuitry is usually a little simpler compared to the output side circuitry. On thenegative side, getting the output voltage and/or current in an isolated fashioncan be difficult. One technique is to use a voltage-to-frequency converter onthe output side, and a frequency-to-voltage converter on the supply side. Somepower supplies attempt to use opto-couplers in a linear mode of operation.However, opto-couplers are an inherently non-linear device, and this is difficultto do. To complicate the issue even further they are subject to temperature


variations.

One rather nice and simple technique of getting isolated feedback variableswith the control on the supply side is the circuit shown in Figure 3.17 which wasproposed in [5]. This circuit uses a small forward converter to transfer the ana-logue voltage value of the output voltage across the isolation barrier. The BJTis connected to the output of the main power converter, and is turned off and onby the pulsating voltage here. This then operates a low power forward converterthat transfers the main converter output voltage via the transformer to mainconverter primary reference. The small transformer would have a turns ratio sothat the output voltage is higher than the main converter output voltage. Bydoing this any voltage drop across the rectifying Schottky diode is insignificant.One crucial aspect of the performance of this circuit is that the duty cycle of themain converter (which is used to control the small feedback forward converter)does not affect the output voltage. This is achieved because the output circuitis a peak detector, and the precise duty cycle does not affect the peak detected.The peak is related to the output voltage of the main converter. The forwardfeedback converter output voltage is then resistive divided to give a voltage thatis appropriate for the error amplifier. It is claimed that this circuit is capableof giving an accuracy of 2% and has a bandwidth that is controlled by the RCtime constant of the capacitor/resistive divider network at the output of thefeedback circuit.

S

P

SR1

R2

Feedback circuitry

Vo

P

vfeedback

P S

Forward

converter

Main converter

output

Isolation

barrier

Figure 3.17: Feedback circuit using a small forward converter.


3.3.1 Start-Up

Another interesting practical aspect of a SMPS is how to start it up. Thedilemma takes the form of a chicken or egg argument – one needs power to startthe switching, and one needs switching to get power. The solution to this prob-lem could take the form of that shown in Figure 3.16, where we have a separatepower transformer for the control logic. Power is therefore immediately availablefor the PWM and feedback circuitry when the main power is applied. However,in many situations this would be considered to be an expensive solution.

Another much lower cost solution is to use a control logic power winding, aresistor and a capacitor [5]. This is suitable for converters where the control logicis referenced to the primary. A circuit for this is shown in Figure 3.18. Initiallythe transformer section of the circuit is inoperative. When power is applied tothe power supply the unregulated DC supply comes on-line. Consequently theelectrolytic capacitor in Figure 3.18 will charge up. The zener diode is to limitthe voltage to a value safe for the PWM generator IC. The PWM generator nowhas enough voltage to operate.

Unfortunately many PWM generator ICs only have a small hysteresis bandof operation around the nominal voltage of operation. For example, the UC3825PWM generator IC by Unitroder Semiconductor Products (now owned byTexas Instrumentsr) operates with voltages from 9 Volts to a maximum of30 Volts. There is a 400mV hysteresis around the 9 Volt minimum voltage.Therefore, once the circuit starts operating (at 9 Volts) then it will continue tooperate until the voltage falls to (9 - 0.4) Volts. This implies that the capacitorvoltage in Figure 3.18 cannot fall by the 0.4 Volt hysteresis value during thetime that the main power circuit starts to supply power to the PWM genera-tor. If the voltage does fall by this amount then the PWM generator will stopworking, and the resistive charging process will cause the cycle to repeat. Thecircuit will therefore operate in a type of limit cycle.

In order to make the onset of limit cycle behaviour less likely during start-up of the power supply, one needs to create a larger hysteresis in the operatingsupply of the PWM IC. The PWM IC is designed limited to a certain hystere-sis, so the increased range must be obtained by circuitry external to the chip.Figure 3.19 shows one way of achieving this [5]. improved power

start-up circuitThis circuit effectively allows the capacitor to charge up to a higher voltagebefore the PWM IC is allowed to operate. The capacitor charges up as describedfor Figure 3.18. When the voltage on the capacitor reaches a value equal tothe value of the breakdown voltage of zener Z2 plus the threshold voltage ofthe MOSFET, then the MOSFET will turn on. This then allows the PNPtransistor to turn on and voltage is applied to the PWM IC, which begins tooperate. The resistor RG feeds back voltage to the gate of the MOSFET so thatit will remain on, even if the voltage across zener Z2 drops below its thresholdvoltage. The feedback will remain active while the voltage on the gate of theMOSFET remains above the threshold voltage.

As a specific example of the operation of this circuit, consider zener Z2 to be12 Volt and the gate threshold of the MOSFET to be 2 Volt. Therefore whenthe voltage on the capacitor reaches approximately 14 Volt, zener both Z2 andthe MOSFET will be on. Consequently the PNP will turn on, and the 14 Volton the capacitor will appear on the Vcc pin of the PWM IC. The capacitor


+

Vcc

PWMGeneratorChip

UnregulatedDC supply

Power windingwhen running

Initialchargingresistor

Figure 3.18: Example of a simple bootstrap power circuit for a PWM generatorchip.


+

Vcc

PWMGeneratorChip

UnregulatedDC supply

Power windingwhen running

Initialchargingresistor

RG

1R

BZ2

Z1

Hysteresis circuit

RG

2

Figure 3.19: Bootstrap circuitry modified for increased hysteresis range.

will then begin to discharge. The PWM IC will continue to operate until thecapacitor voltage falls below its minimum operating voltage, which in the caseof a UC3825 is 9 Volt. Therefore, the circuit has created a voltage hysteresisfor 14− 9 = 5 Volt.

Remark 3.17 The increased hysteresis created by the circuit shown on Fig-ure 3.19 means that the capacitor can be a smaller size and still be able to keepthe PWM IC running long enough to allow the auxiliary winding to start tosupply the power to the PWM IC.

Remark 3.18 The charging resistor shown in Figures 3.18 and 3.19 is con-stantly connected on the circuit. Therefore, even when the switch mode supplyis running, it will still dissipate power. However, this resistor can be made quitelarge so that the power dissipated can be made small – the charging time of thecapacitor is not that important (within reason). The resistor is no longer reallysupplying the current in the turn on phase, as it was with the previous circuit.Alternatively one can use auxiliary circuitry to switch the resistor out, therebyallowing a smaller resistor to be used.

3.3.2 Protection Issues

3.3.2.1 Soft Start

Soft starting refers to generating voltage output very slowly when power isfirst applied. This is required because when power is first applied the control


circuitry will apply the maximum duty cycle to the power stage. This can resultin excessive current flow in the components which can be potentially destructive.In order to prevent this a special mode of operation is required so that the dutycycle ramps up from a very small value to the value required by the controlcircuitry. Soft starting is also used to recover a SMPS from fault conditions.

Soft starting is handled internally in most PWM ICs, therefore it does notrequire any specific action by a designer.

3.3.2.2 Voltage Protection

Most SMPS integrated control circuits have a pin which can be connected to anexternal circuit. This circuit will generate a voltage into the pin of the IC whenthe input voltage rises above a certain value. Most ICs also contain circuitrythat detects under voltage conditions. Internally the shutdown circuitry usuallystops the internal latch from functioning and sets the outputs into a non-drivingstate.

A block diagram of the Unitroder 1825 switch mode PWM generator chipis shown in Figure 3.20. Notice that the “Output Inhibit” is activated for lowvoltage to the chip itself, as well as from the Ilim/SD input (i.e. pin 9). Thelater is activated by external circuitry to detect over voltage/under voltage tothe power circuit.

3/97

BLOCK DIAGRAM

U DG-92030-2

Figure 3.20: Block diagram of the Unitroder high speed PWM generator.

3.3.2.3 Current Limiting

Current limiting is included in most PWM control ICs to protect the powersupply under short circuit conditions. There are two types of current limiting:

• Constant current limiting.


• Fold-back current limiting.

Constant current limiting, as the name implies, is a form of current limit where constant currentlimitthe current can only go to a particular value and then it will not increase any

more, regardless of the load. Therefore, even under short circuit conditions thecurrent will not increase appreciably above this limit value. This concept isshown in a V0I0 diagram in Figure 3.21. One point to note about this diagramis that the voltage at the output of the converter can be appreciable under thiscondition, depending on the impedance of the load.

Remark 3.19 The constant current limit may not be satisfactory in many ap-plications, since the limit current may, over time, result in the thermal rating ofthe inductor or transformer windings being exceeded. Therefore, if such a limitis to be used, then one must ensure that the windings and power devices cansupport the limit current indefinitely.

Io, rated

Ilimit

Vo1

Vo2

Vo

Io

R RL

=1

R RL

=2

Load lines

Vo, rated

Figure 3.21: Operation of a constant current limit.

A slightly different limit is the fold-back current limit. This limit is motivated fold-back currentlimitby the desire of reducing the currents flowing in abnormal short circuit or near

short circuit conditions. The operation of this current limit philosophy is shownin Figure 3.22. In this case when the current reaches a limit value of Io, limitthen the current limit drops with the output voltage. Therefore under shortcircuit conditions the current is reduced to a much lower value than in theprevious case. The power that is being supplied to the external circuit underthis condition is not nearly as high as in the constant current limit situation.

Remark 3.20 The fold-back current limit does not solve the overheating prob-lem mentioned in the previous remark. If the circuit is operating at Io, limit thenthe problem is the same as in the constant current limit case.


Vo, rated

Io,limit

Io,rated

Io

Vo

Vo1

Vo2

Io, foldback

R RL

=1

R RL

=2

Load lines

Figure 3.22: Operation of a fold-back current limit.

Most PWM ICs implement a two stage current limit. The current throughthe switch is fed through a sense resistor, and the fed into the current limit pinof the PWM IC. If the voltage on this pin reaches a certain value the switchturn on pulse is turned off until the next control cycle. Therefore the currentlimiting is carried out on a switching interval basis. If the voltage goes higherand reaches a second limit, then the controller stops switching and restarts insoft start mode. The power supply can then oscillate in this mode until theshort or the fault is rectified.

Current limiting is actually a little more complicated than has been madeout so far. Consider the situation when one has a converter with a transformerand multiple output windings. If the current sensing is set up on the primary,then the current limit has to be set for the current pulled under full load fromall the windings. However, if all the secondaries, except one, are unloaded, thenif there is a short on this winding the full current of the inverter can go throughthis winding before there is a trip. This situation could result in the destructionof this winding, or destruction of the rectifier components on this winding.

There is no easy way out of this problem. Probably the most economicalsolution is to sense the current limit of each winding individually, and then takethe output of these limit circuits and “OR” them together. This forms the tripsignal to the PWM chip.

3.3.3 Control Architecture of a Switch Mode Power Sup-ply System

3.3.3.1 Voltage Mode Control

Figure 3.23 shows a conceptual diagram of a SMPS system from a control per-spective (as opposed to an implementation perspective). The compensating


amplifier is shown with generic feedback components Z1 and Z2. These com-ponents can contain reactive circuit elements, which allow a variety of differenttransfer functions to be set up in the feedback loop.

Zi

Zf

Vo,ref

+

- PWM

Controller

Power stage

and output

filter

vo

Compensating amplifier

vc d

Vd

Figure 3.23: Conceptual diagram of a control system for a switch mode powersupply.

In general the main objective of the control system of Figure 3.23 is tocontrol the output voltage to be a specific value under varying load conditions.In order to design the feedback compensation, one needs to obtain a model ofthe system suitable for control analysis. This is achieved by using an approachcalled state space averaging. This allows one to obtain a state space model ofthe system, accounting for the switching in the circuit in an average sense [2].We shall not look at the detail of the process. The net result of this modelingprocess is that one can obtain a small signal linearised model of the converterand its control of the form shown in Figure 3.24. This figure shows each ofthe converter components as a transfer function. In this form one can applystandard classical control system design techniques to the system.

Whilst switching power supplies seem to be very simple circuits, their oper-ation from a control viewpoint is more complex than one might initially expect.Consider, for example, the flyback and boost converter. Because these two con-verters store energy in the magnetic field of an inductor before transferring it tothe load they exhibit an effect caused by having a right half plane zero in theirtransfer function. Such systems are known as non-minimum phase systems. Forthe non-control literate reader, a right half plane pole corresponds to a responsethat tends to go in the wrong direction to correct a disturbance. non-minimum

phaseConsider the following example of a right half plane zero effect. If we have aflyback converter, and there is a sudden decrease in the output voltage due toan increased output load on the converter. The natural reaction of the controlsystem is to increase the duty cycle, D, so that more energy is transferred tothe load to restore the voltage. However, due to the above-mentioned energystorage operation principle of this converter, the initial increase in the dutycycle can result in a further decrease in the output voltage. This is due to the


PWMcontroller

Power stageand output

filter

S

Compensatingerror

amplifier

~ ( ),

v so ref +

-

~ ( )v serr~ ( )v sc

~( )d s ~ ( )v so

T sd s

v sm

c

( )

~( )

~ ( )? T s

v s

d sp

o( )~ ( )~( )

?

T sv s

v s

o

c

1( )

~ ( )~ ( )

?

Figure 3.24: Linearised model of a switch mode power supply.

fact that increasing D instantaneously delays the next delivery of energy fromthe magnetic field to the load, as compared to what would have happened ifthere had been no change in D. One can see that if the feedback is very highbandwidth then this will result in a further increase in D, and the process willrepeat. We effectively have positive feedback. Of course the process will stopwhen we get to the limit of the duty cycle (this is a non-linear effect that is notaccounted for in our linear explanation). The presence of a right half plane zeroin these converters limits the control bandwidth of these types of converters.

Figure 3.23 shows a basic diagram for a switch mode control system. Manyreal systems actually use a hierarchical control system consisting of two nestedcontrol loops. The inner most of the control loops is a current control loop, andthe outer control loop is the traditional voltage control loop. The advantages ofusing the current control loop will be discussed in detail in a following section.Suffice to say that the disturbance rejection properties of the controller areimproved using this structure. A block diagram of this hierarchical controlsystem appears in Figure 3.25. Notice that the voltage vc appears as a currentreference to the section of the circuit that controls the current.

Power stages andoutput filters

H s( )

S+

-

Voltage loopfeedback

compensator

G s( )

iL

vo

vo

iL

Comparatorand latch

vo,ref v

o,err vc

Switchingsignal

Figure 3.25: Block diagram of a nested loop control system for a switch modepower supply.


3.3.3.2 Voltage Feed-forward PWM Control

All of the diagrams for control of the SMPSs thus-far have relied totally onfeedback control. However, in the case of input voltage fluctuations one can feed-forward the change of input voltage to the controller so that it can be accountedfor before it would affect the output. This is usually achieve in practice byfeeding the input voltage into the PWM IC. This chip usually accounts for thesupply variation by altering the amplitude of the triangular waveform that isused internally to generate the PWM. One can see from (2.7) that if vst isincreased (corresponding to an increase in the peak of the triangular waveform)then the duty cycle decreases. Therefore if this value is controlled by the inputvoltage then it is possible to get near perfect input disturbance rejection. input disturbance

rejection3.3.3.3 Current Mode Control

Current mode control is a term used in the SMPSs literature to refer to a nestedloop control system, such as that depicted in Figure 3.25, where the inner loopcontrols the inductor current, and the outer loop controls the output capacitorvoltage.

There are a number of very good reasons for complicating the control struc-ture of the addition of the current control loop:

• Switch current limiting. It was mentioned in Section 3.2.1.1.2 that one ofthe problems with the push-pull converter was that small differences in theswitching times of the switching devices could cause eventual saturationof the transformer. Employing current mode control the peak switchingcurrents in the two switches of such converters can be balanced so thatthis phenomena does not occur. Note that the current mode control inthis situation would be from each of the two switches.

• Simplified converter dynamics. Current control effectively removes thepole introduced by the output inductor. This simplifies the dynamics ofthe converter system, effectively allowing the bandwidth of the controlloop to be increased (because of the increased gain and phase marginachieved). This is especially useful in converters that have a right halfplane zero in their response.

• Simplified paralleling of converters. The presence of the current controlloop allows the possibility of paralleling of several SMPSs, with each powersupply contributing the same amount of current to the load. This isachieved by feeding each of the supplies with the same control voltage.

• Automatic voltage feed-forward. The desirable properties of voltage feed-forward are implicitly achieved when current mode control. If the inputvoltage increases, the current will reach the current limit sooner. Thereforethe duty cycle will decrease with out the delay of waiting for the voltageto vary at the output.

In a current mode controlled SMPS, as depicted in Figure 3.25, the controlvoltage vc, which is derived from the error between the desired output voltageand the actual output voltage, represents a desired inductor output current, ora switch current. This is achieved in a number of different ways [2]:


a. Tolerance band control.

b. Constant “off” time control.

c. Constant frequency control with turn-on at clock time.

Let us look at how each of these schemes works in a little more detail. Intolerance band con-trol tolerance band control the inductor current is kept within a band, and the

control voltage is effectively controlling the average value of the current. Thewidth of the band is a design parameter, and by choosing it the designer isalso influencing the switching frequency of the converter (which is also relatedto other parameters of the converter). Tolerance band control is essentially aclassical hysteresis or bang bang type of control strategy.

The operation of tolerance band control is depicted in Figure 3.26. The ∆iLvalue is one of the design parameters for the controller. If ∆iL is very smallthen, for the same converter parameters, the frequency of switching will be muchlarger. The other important point to note is that the switching frequency isrelated to the voltage appearing across the inductor (which changes the slope ofthe currents). Therefore if the input voltage increases, then so will the switchingfrequency. This is not a desirable property – it makes the losses of the switchdifficult to predict.

t

iL

vc

IL

DiL

/ 2

DiL

/ 2

Switchturnson

Switchturnsoff

Switchturnson

toff

ton

Figure 3.26: Waveforms for tolerance band current control.

Another problem with the tolerance band controller is that it only reallyworks properly in continuous mode operation. If the current becomes discon-tinuous, then the desired average inductor current can become negative. If thecurrent is discontinuous then the lower switch on limit would have to be zero –the circuit has to be designed to handle this. If the controller is not speciallydesigned, the controller will respond to driving the inductor current to zero, andit will then stay there. There is also a problem of very high switching frequenciesat low current values, this corresponding to a very small hysteresis band.


Constant “off” time control controls the peak current in the inductor. In thisstrategy the control voltage specifies the maximum or peak current. When thispeak current is reached the switch is opened for a fixed period of time. It is thenclosed again and the process repeats. This situation is depicted in Figure 3.27.This control strategy also suffers from the problem that the switching frequencyis dependent on the input voltage and the converter parameters. constant “off” time

control

t

iL

vc

$IL

Switch

turns

onSwitch

turns

offSwitch

turns

on

ton

toff

ton

toff

Constantoff

t

Figure 3.27: Waveforms for constant “off” time control.constant frequencywith turn-on clocktime control

The constant-frequency with turn-on at clock time control is the controlstrategy most commonly used. This is due to the fact that the switching fre-quency is user definable in the strategy. One is effectively trading off the ripplecontrol achievable with tolerance band control for the constant switching fre-quency. This allows one to control more accurately the losses in the switchingdevices, and makes the design of the output filter much simpler. Figure 3.28shows the waveforms that occur with this control. The switch is closed at atime determined by a clock signal. The switch remains on until the currentlimit is reached, and then it turns off until the beginning of the next controlperiod. The process then repeats. The fact that the switch only turns on at thebeginning of a clock pulse means that the frequency is fixed by the clock period(which of course is user definable).

There is a problem with straight current mode control that we have notmentioned in the discussion thus-far. If the converter duty cycle exceeds 50%the converter output will possibly oscillate at a subharmonic of the switchingfrequency – specifically at half the switching frequency. This occurs because subharmonicsthe current control loop works by turning off a switch when the current reaches


t

iL

vc

$IL

ton

toff

ton

toff

Clock Clock Clock

Ts

Ts

Constant period

between clock

pulses

Figure 3.28: Waveforms for constant frequency with turn-on at clock time con-trol.


a particular value. It is possible if the duty cycle is larger than 50% that thecurrent will not return to the value at the beginning of the control interval.Therefore in the next control interval the current will reach the desired valuesooner (since it is starting off with an offset). Therefore the switch will turn offsooner than it otherwise would, and consequently the “off” time will be longer.Therefore at the end of this interval the current may be lower than the desiredvalue. This would result in the control deciding to turn the switch on longer,since we are now starting from a negative offset compared with the correctvalue if this phenomena were not occurring. One can see that the period of theoscillation caused by this jitter in the duty cycle results in a frequency that ishalf the switching frequency.

In addition to the subharmonic oscillation problem, one also has a form ofopen loop instability with current mode control [6]. The following discussion is open loop instabilitywith reference to Figures 3.29(a), (b) and (c). Consider Figure 3.29(a) showsthe effect of a perturbation of the inductor current (dashed line) away from thenominal current (the solid line). Notice that the perturbation dies away in thiscase. The effective duty cycle changes due to the way that current mode controlworks.

Figure 3.29(b) shows a similar situation, but in this case the duty cycle islarger than 0.5. One can see that instead of the error between the nominalinductor current and the perturbed version getting less, it actually increaseswith each successive control interval. Therefore, there is effectively positivefeedback in this case.

3.3.3.3.1 Slope Compensation Many of the problems with current modecontrol can be overcome by using the technique called slope compensation. Thistechnique involves adding a sawtooth waveform to the current feedback wave-form, or alternatively subtracting a sawtooth from the voltage error signal fedto the current mode controller comparator.

Figure 3.29 shows the effect of slope compensation. In this case the sawtoothwaveform is subtracted from the error voltage, Ve coming from the voltage erroramplifier. This effectively forms a new reference for the current control section ofthe loop. In this case, even though the duty cycle is larger than 0.5 the perturbedcurrent returns to the nominal current (as was the case for D < 0.5). Theadded ramp has a constant value, and therefore the sensitivity of the feedbackto variations in the current measurement becomes less. To understand how thisworks one can look at the extreme case when the current in the load is very lowand the ramp is added to the current measurement. In this situation the controlvoltage from the error amplifier is being compared to the slope compensationvoltage, and hence the circuit is essentially operating in the normal triangularwave comparison mode of voltage control. Therefore, the addition of the slopecompensation brings in some features of voltage control into the current modeloop, and under the situation of low currents it effectively behaves as voltagecontrol (and therefore would have the dynamics of voltage control).

Let us consider this situation in a little more detail. One can see fromFigure 3.30 that the current perturbation error at the beginning of a controlinterval, ∆i0, is related to the current perturbation error at the end of the next


Ve

Ve

Ve

t

t

t

(a) Duty cycle < 0.5

(b) Duty cycle > 0.5

(c) Duty cycle > 0.5, slope compensation

m1

m2

-m

Compensated voltagereference

D

D

D

iL

DiL

DiL

m1

m2

m1

m2

Di0

Di0

Di0

Figure 3.29: Open loop instability of current mode control. (a) stability withduty cycle < 0.5; (b) instability with duty cycle > 0.5; (c) stability with dutycycle > 0.5 and slope compensation.


control interval, ∆i1, as follows:

∆i1 = −∆i0

(m2

m1

)(3.50)

Remark 3.21 Equation (3.50) shows that if |m2| > |m1| then |∆i1| > |∆i0|– i.e. the error has increased after one control interval. This situation wouldcontinue.

This situation correlates to D > 0.5, since for the circuit to be in steadystate, i at the beginning of the interval, must be equal to the value at the end.This implies that |m2| > |m1|. Therefore the two conditions are synonymous.

Di0

Di1

m1

m2

xi

m=

D0

1

xi

m=

-D1

2

t

Figure 3.30: Geometrical relationship of the current waveform slopes when thereis a current perturbation.

As mentioned above the compensation can be carried out by adding theslope compensation waveform to the current, or subtracting from the voltage.The techniques can be shown to be equivalent. Therefore, assuming that we areadding to the current we can modify (3.50) by adding the slope compensationto give:

∆i1 = −∆i0

(m2 +m

m1 +m

)(3.51)

If the duty cycle is near 100% then the slope m1 ≈ 0. Furthermore, we wishthat ∆i1 < ∆i0 for the error to be decreasing over successive control intervals.Using these facts we can write the following:

−∆i0

(m2 +m

m1 +m

)< ∆i0 (3.52)

∴ −(m2 +m

m1 +m

)< 1 (3.53)

implying m > −1

2m2 (3.54)


Remark 3.22 Equation 3.54 shows that the slope of the ramp that must beadded to the current or subtracted from the voltage error must be greater thanhalf the magnitude of the down slope of the inductor current.

If one considers (3.51), and consider it to be a discrete iterative expression, thenthe inductor current behaves as though it is an underdamped RLC circuit. Thisis shown in Figure 3.31. This RLC response can be damped out (akin to criticaldamping) by choosing m = −m2. The effect of this is shown graphically inFigure 3.32.

D Di im m

m mn n

= -+

+

F

HGI

KJ-( )1

2

1

2T1T 3T 4T 5T

t

Figure 3.31: Inductor current response of current mode converter.

m2

- =m m2

t

m1

Ve

Dio

Figure 3.32: Optimal slope compensation to eliminate RLC type oscillations.

Chapter 4

Introduction to PracticalDesign of Switch Mode PowerSupplies

4.1 Introduction

In this chapter we shall briefly look at the most important aspects of the physicalcomponent design of a switch mode power supply (SMPS). The approach takenis a very practical one, with some theory where appropriate.

The design of a switch mode power supply, like most electronics design, iscomplicated because of the large number of design trade-offs that are available.This fact means that this presentation is far from exhaustive, nevertheless thesalient issues in making design choices will be emphasised. The design of SMPSsis complicated even further by the fact that virtually all SMPS’s use magneticsin their design. Consequently much of this chapter will be concerned with thedesign of these magnetics.

The first section of this chapter will consider issues related to the selectionof the electronic components of a SMPS. The second section of the chapter willlook in some detail at the design of SMPS magnetics. Much of the material inthis chapter is closely based on [5].

4.2 Component Selection

The information on the selection of components for SMPSs is usually materialthat ends up in vendor’s application notes (if one is lucky), or in the mind of adesigner. This information therefore is often very inaccessible to a new designer,and is often attained by many disappointing design exercises. In this sectionwe shall attempt to highlight some of these hard-to-find selection criteria for avariety of components: resistors, capacitors, Schottky diodes, rectifier diodes,BJTs, MOSFETs, op amps, and comparators.

4-2 Introduction to Practical Design of Switch Mode Power Supplies

4.2.1 Resistors

The resistor is probably the most ubiquitous of all electronic components. Con-sequently most electronic designers don’t pay a lot of attention to details otherthan its value and power rating.

4.2.1.1 Values

There is a practical maximum value for a resistor that is used on a PCB. Thispractical limit occurs for several reasons:

• Large resistor values are not commonly available (although they can beobtained for specialised applications).

• If a very large value of resistor is used, then the resistance across the PCBbetween the resistor legs may be comparable or less than the resistor value.Therefore the resistor is ineffective.

• Using large resistor values makes the circuit very susceptible to electri-cal noise. A large value of resistance means that very small capacitivelycoupled currents can result in large coupled voltages.

Remark 4.1 Don’t use large values of resistance in your designs if at all possi-ble. Even values of 220kΩ can cause significant noise pickup problems, especiallyin switching applications which are inherently noisy in any case.

4.2.1.2 Resistor Types

Obviously choosing the correct resistor for the job is necessary in electronicsdesign. There are several resistor choices, depending on the application.carbon composite

The oldest style of common resistor is the carbon composite resistor. Onecan usually tell these resistors by the large size for their power rating. One maystill find these resistors in a hobbyist store, but for professional circuit designthey are no longer used, as there are much smaller, lower cost, and more reliableresistors available.Another interesting point about carbon resistors is that thepreferred values made were far fewer than the more modern resistors (only 12per decade).metal film

The most commonly used resistor today is the metal film resistor. These areavailable in a wide range of values, and low to moderate power ratings (severalwatts).As noted in the previous paragraph, there are a lot more preferred valuesin these resistors (48 to 96 values per decade, depending on tolerance).wire wound

For higher power rating applications there are several choices. The wirewound resistor is the one that most people would be familiar with (a heatingradiator element is an extreme form of this type of resistor). They are gener-ally available in power ratings from 1W to approximately 1kW (and sometimeslarger values for special applications such as regeneration banks in large in-verter systems). One problem with wire wound resistors is that they have highinductance, which makes a conventional wire wound resistor unsuitable for highfrequency applications. Fortunately, it is possible to wind the resistor with equalturns in two different winding directions so that the inductance can almost beeliminated (the flux produced from each winding direction cancels). Variable

4.2 Component Selection 4-3

resistance wire wound resistors are called Rheostats. These are most commonlyused in laboratories for experiments, rather than in commercial products.shunt

Another common type of resistor used for current sensing applications is thecurrent shunt. This resistor type usually has a very low, but precisely knownvalue. One can detect the voltage across the resistor, and then use Ohm’s Lawto deduce the current through the shunt. The shunt itself is made of metalsthat have a very low temperature coefficient. A low cost shunt can be createdusing a PCB track itself. This should only be considered where cost is theprimary consideration, since the accuracy of such a shunt is not very good. Itshould be noted that shunts provide a non-isolated measurement of current.In many applications this is all right, but in other applications where isolationis important then additional measures must be used to gain isolation of themeasurement. Table 4.1 summarises these comments.

Type Suggested Applications

Carbon composite Not commonly used anymoreMetal film General purpose – replace carbonWire wound (inductive) and rheostat Used for high power load resistorsWire wound (non-inductive) Used in high frequency applicationsShunt Used for measuring large currentsPCB track Used for low cost measurement of currents

Table 4.1: Resistor application selection guide

4.2.1.3 Tolerance

One important attribute of a resistor is its accuracy. Many years ago the “gardenvariety” resistor had a tolerance of 5%, and the exotic resistors had a toleranceof 1%. These days the default tolerance of resistors is 1%, and at slightly higherprice one can have resistors with 0.1% tolerance.

4.2.1.4 Selecting Values

In many designs the specific value of a resistor does not matter (although insome it does as well). If this is the case then only the ratio between resistorsis important. Therefore, in order to minimise the number of components thatneed to be ordered it is better to try an choose the same values of resistor wherepossible. For example, if sections of the circuit rely on resistor ratios, thenchoose one resistor out of the two to be say, 10kΩ. One can then choose theother to satisfy the ratio requirement.

4.2.1.5 Maximum Voltage

Voltage ratings are not a parameter that immediately comes to mind whenthinking of resistors. However, in the case of surface mount resistors, the spacingbetween the ends of the resistor means that voltage rating must be considered.In SMPS circuits one can be dealing with voltages anywhere from 10s of volts


to 100s of volts, and at the top end of this range resistor voltage rating can beimportant.

4.2.1.6 Temperature Coefficient

Most modern metal film resistors have a very small temperature coefficient ofthe order of 50–250ppm/C. Wire wound resistors however, depending on thematerial they are made from, can exhibit substantial changes of resistance withtemperature. This is especially a problem with these resistors, since by defini-tion they will undergo large temperature changes. Shunt resistors, as mentionedin Section 4.2.1.2, are purpose designed to exhibit very low temperature coeffi-cients. They also usually have a very low value so that power dissipation is lowin the resistor, and hence temperature rise is kept to a minimum.

4.2.1.7 Power Rating

All resistors have a maximum power rating. However, a resistor should not beoperated at its maximum power rating, since it is severely stressing the compo-nent. This severe stress usually results in a high failure rate of components.half power opera-

tion In order to ensure high reliability of resistors it is recommended that a re-sistor, at worst, is operated at half its nameplate power rating. It is probablybetter to be even more conservative than this and operate the resistor at ap-proximately 1/3rd of its power rating.

Practical issue 4.1 Select resistor power ratings so that they are operating atapproximately 1/3rd of the device specified power rating.

pulsed powerThe above comments are implicitly for continuous power dissipation. However,one can modify them in relation to pulses of power, especially for wire woundresistors. Manufacturers of these resistances will sometimes give a table ofpulsed powers for pulses of less than 100msec.

Practical issue 4.2 Power ratings for non-wire wound resistors should be strictlyadhered to. It is alright to have power pulses up to the maximum rating of theresistor for short durations (say less than 100msec) providing the repetition rateis not too high.

RheostatA Rheostat is a variable power resistor, as opposed to a Potentiometer which is avariable signal level resistor. Rheostats usually consist of a wire wound resistorthat has a sliding contact. The power rating for the device is for the wholeresistor. Therefore if the sliding contact is halfway along the resistor, so thatonly half the resistor is being used, then the power rating is half the nameplatevalue (so that the maximum temperature of each of the wire turns is the same asfor the full resistor). One must be particularly careful with using these resistorson a voltage source, as it is easy to move the slide around so that the maximumpower rating of the active section of the Rheostat will be exceeded. One can puta current meter in the circuit to make sure that the current rating of the deviceis not exceeded as adjustments are made, or alternatively another resistor canbe put in series with the Rheostat to prevent overload.


4.2.1.8 Shunts

Whilst a shunt is a resistor, it is not used for the normal application of theresistor, which is to somehow limit current flow. With a shunt one wishes toimpede the current flow as little as possible.

A shunt is generally constructed of a near zero coefficient metal such asmanganin, attached to heavy duty terminal blocks made of brass. Shunts comein a variety of sizes, ranging from very low current shunts, up to shunts thatcan handle thousands of amps. Typically a shunt is designed to produce either50mV or 100mV at its rated current. Shunts are generally used if one wishes tomeasure low frequency or DC currents. In AC applications, current transformersare often used instead since they offer isolation.

Remark 4.2 It should be noted that the use of shunts in high power PowerElectronic applications is not very common these days. For example, it is notcommon for shunts to be used to measure the currents in inverter systems. In-stead Hall Effect transducers are used, since they have good frequency responseand offer isolation.

Consider a 100A shunt with a 100mV output. This means that the resistance ofthe shunt is 100mV / 100A = 1mΩ. In addition to the resistance of the shuntthere is a parasitic inductance. For a 1in shunt, this inductance is of the orderof 10–20nH. If we assume 20nH, then we have an AC model for the shunt asshown in Figure 4.1. Obviously the impedance of this circuit is Rshunt+jωLshuntwhich is frequency dependent. Clearly there is a zero in the impedance frequencyresponse, and hence above a certain frequency the voltage across the shunt willincrease due to the effect of the inductance.

Rshunt

Lshunt

Figure 4.1: Equivalent circuit model of a current shuntinductance effects

We found above that the value of resistance for a shunt is usually low. There-fore, even though the parasitic Lshunt is low, the frequency at which the zerooccurs can also be relatively low. If we use the specific values from the pre-vious paragraph, then we have that the zero in the impedance occurs whenωLshunt/Rshunt = 1 which gives f = 1mΩ/(2π × 20nH) = 8kHz. In many realapplications for shunts the currents will contain frequencies above 8kHz, andhence one would be getting erroneous current readings.

Remark 4.3 One way to raise the frequency at which the impedance zero occurswith the shunt is to raise the resistance of the shunt. However, in high currentapplications this is not feasible.

An alternative strategy is to lower the inductance of the shunt by making itfrom stacked layers of metal, instead of a single piece. There are practical limitson how far this can be taken.

A control person would immediately think of another solution to the shuntfrequency response problem – try and arrange a pole-zero cancellation so that


infinite frequency response can be obtained. The obvious way to do this is toplace a capacitor in parallel with the shunt – i.e. in parallel with the equivalentcircuit of Figure 4.1. The impedance function with the capacitor can be easilysown to be:

Zeq =Rshunt + jωLshunt

(1− ω2CcompLshunt) + jωCcompRshunt(4.1)

where Ccomp , the compensating capacitor value.If we make the assumption in (4.1) that ω2CcompLshunt 1 then:

Zeq ≈Rshunt(1 + jω Lshunt

Rshunt)

1 + jωCcompRshunt(4.2)

Clearly for pole zero cancellation we require:

CcompRshunt =Lshunt

Rshunt(4.3)

which means that:

Ccomp =Lshunt

R2shunt

(4.4)

Substituting in the values for the 1mΩ shunt one gets:

Ccomp =20nH

(1mΩ)2= 20, 000µF (4.5)

Clearly this is not a practical value of capacitance. Fortunately there is a wayto achieve the same effect in the op amp amplifier circuit that is required toamplify the current shunt voltage signals. The value of capacitance used in thiscircuit are much more reasonable values (usually in the nF range) [5].

4.2.1.9 PCB Track Resistors

If one is looking for a budget priced version of the shunt one can use the resis-tance of a PCB track. This type of shunt will have poor accuracy because itrelies on the accuracy of the track width and thickness, and the temperature co-efficient for copper is very poor (0.4%/C). However, this type of current sensecan be used for over-current protection.

Practical issue 4.3 The resistance of a trace is approximately given by theformula [5]:

R = 0.5mΩlengthwidth

(1 oz. copper) (4.6)

at room temperature. Two-ounce copper has half this value.

4.2.2 Capacitors

Just as there are different types of resistors, there are different types of capaci-tors. In any design it is usually not possible to use just one type of capacitor –the correct capacitor technology must be used for the application.


4.2.2.1 Types of Capacitors

Capacitor types are defined by their construction technology. The main typesof capacitors in common use are:

Electrolytic This is one of the most common types of capacitors used forlarge capacitance. There are a variety of choices available, with the mostcommon being the aluminum electrolytics. These capacitors can havevery large values – well into the millifarad range, and many hundredsof volts. Note that these capacitors are physically very large. Thereare also tantalum electrolytic capacitors, which are available in solid andwet varieties. These capacitors tend to have maximum sizes that aresmaller than those attainable in the aluminum electrolytic variety, butthey have better high frequency performance. A distinguishing feature ofall electrolytic capacitors is that they have a polarity.

Ceramic These are the flat, disc like capacitors that home hobbyists wouldbe familiar with. They are used for timing and bypass purposes. Theyare available in values from a few picofarads to 1µF. New in this rangeof capacitors are the multilayer ceramic (MLC) variety, which have verylow effective series resistance and larger maximum values (several hundredmicrofarads) as compared to the older ceramics.

Plastic These capacitors can withstand very high dv/dt across them, particu-larly the polypropylene variety. They are used in circuits such as quasi-resonant SMPSs. Another variety, Polystyrene, are more specialised, andare used where very low leakage is required, such as in sample-hold appli-cations.

Type Suggested Applications

Aluminum Electrolytic Used when large capacitance needed. Low frequencies. Bulky.Tantalum Electrolytic Use for moderate capacitances. Medium frequencies. Less bulk.Ceramic Timing and bypass applications.Multilayer ceramic High frequency bypass, low leakage applications.Plastic Use for high dv/dt applications. Low leakage current applications.

Table 4.2: Capacitor application guide

The information in the above description is summarised in the Table 4.2.

4.2.2.2 Standard Values

Capacitors do not have the same range of values as modern resistors do – in factthe preferred values are basically the same as those available in the old carbonresistor ranges: 1.0, 1.2 1.5, 1.8, 2.2, 2.7, 3.3, 4.7, 5.6, 6.8, 8.2. Note that 5.6and 8.2 are not always available.

One can get away with this crudely spaced set of values because the toler-ances for capacitors are generally not all that accurate anyway. Also, in manyapplications, it is the value of a capacitor in relation to a resistor that is the


important quantity. Therefore, one can adjust the resistor to get the desiredresult.

Practical issue 4.4 Just as large resistor values should be avoided, one shouldalso avoid the use of capacitor values less than approximately 22pF. The reasonfor this is that capacitance exists between any parallel plates, and consequentlyparasitic capacitances on a PCB can swamp out the designed low values of ca-pacitance.

4.2.2.3 Tolerance

The tolerances on capacitors are usually very poor – typically ±20%. Elec-trolytic capacitors can have even worse tolerances than this. The other variableto consider is the temperature range that the capacitor will operate over. Thecapacitance value can vary substantially with temperature, e.g. some types ofcapacitors can loose 80% of their capacitance at -40C.

4.2.2.4 ESR and Power Dissipation

The equivalent series resistance (ESR) of a capacitor is a very important vari-able, since it determines the performance of the capacitor in many applications,and is also closely related to the power dissipation in the capacitor. Most man-ufacturers quote the ESR at 100 or 120Hz. The reason for this is that theyimagine that the capacitor is being used in power supply smoothing applica-tions. These values of ESR are useless in determining the ESR at say 100kHz(which is necessary in power electronics applications). Therefore, if you are us-ing a capacitor in a power electronic application with high frequency currents,make sure that you have a relevant value of ESR.

Remark 4.4 The ESR resistive can have a very important effect on the voltageripple from a capacitor. For example, if one is pulling 1 Amp of ripple current at100kHz from a capacitor, and the ESR is 100mΩ, then there is 100mV of rippleintroduced by the voltage drop across this internal resistance. Therefore, if onerequires 50mV of ripple maximum, then one would need at least two capacitorsin parallel, and we have not even taken into account the amount of capacitancerequired to supply the charge to the load. The situation in relation to the ESRcould be even worse if the capacitor has to operate over a wide temperaturerange.

4.2.2.5 Aging

Aging of capacitors, especially in relation to electrolytics, can be very impor-tant. Electrolytic capacitors may have a life time figure associated with a certaintemperature of operation. Values could be 1000 hours, 2000 hours, or even bet-ter 5000 hours. When a capacitor approaches its design age the capacitancedecreases, and the capacitor will be out of specification. In the worst circum-stances the capacitor may fail.

Fortunately, for every 10C drop in temperature, a capacitors life doubles.For example, is a capacitor is rated at 2000 hours at 85C, then if it is operatedat an average temperature of 25C, then it will last 2000× 26 = 128, 000 hours,or 16 years.


Remark 4.5 The use of the average temperature the capacitor is subjected inthe above calculation is important.

4.2.2.6 dv/dt Rating

There are two forms of dv/dt rating for capacitors depending on the applicationand the technology of the capacitor. Electrolytic capacitors, for example, usuallyhave a rating on the amount of rms ripple current that they can tolerate. Thisrating is related to the average i2R lose in the ESR resistor, and the thermalproperties of the capacitor package.

Metallised plastic capacitors used in resonant and quasi-resonant convertershave a dv/dt rating. In these applications these capacitors can sometimes besubject to very rapid rates of change of voltage across them. This in turn leadsto very large current flows via the expression i = C(dv/dt). These large peakcurrents can cause instantaneous heating in the capacitor, which can result inthe destruction of the capacitor if the rating is exceeded.

Remark 4.6 Depending on the application the ripple current or the dv/dt rat-ing may be important. Ripple current tends to be the appropriate measure whenthe capacitor is being used in an application where the voltage across the capaci-tor is relatively constant. dv/dt is relevant with the voltage across the capacitorundergoes large and rapid transients.

4.2.2.7 Series Connection of Capacitors

Sometimes capacitors are series connected in order to get the required voltagerating. However, if precautions are not taken one will find that one of thecapacitors will be supporting more of the voltage than the other. This is due tothe fact that the capacitance of so-called identical capacitors are not the same.Since the same current flows into each capacitor, then one will inevitably havea higher voltage than the other.

The way to force better sharing of the voltage across the capacitors is toparallel resistors with the capacitors, as shown in Figure 4.2. This arrangementwill keep the capacitor voltages equal at DC, but depending on the values of theresistors and capacitors, there may be some degree of imbalance in a situationwhere there is a large ripple.

4.2.3 Diodes

There are two main types of diodes used in SMPS circuits – normal rectifierdiodes, and Schottky diodes. We shall see in Section 5.2.1 that there are specialPN junction diodes required for very high powered applications, but we shallnot be considering these here.

4.2.3.1 Schottky Diodes

Schottky diodes are constructed using a metal-semiconductor junction, as com-pared to a normal diode which has a semiconductor-semiconductor PN junction.The special property of the Schottky diode is that it does not have the chargestorage problems that normal PN diodes have. Consequently these diodes will


+

+

Figure 4.2: Method of voltage sharing for series capacitors.

turn off almost instantly when a reverse voltage is applied to them. The otheradvantage if the Schottky diode, as compared to the PN diode, is that the for-ward voltage drop is much lower – approximately 0.2V for the Schottky, and0.6V for the PN diode.

There are a few caveats associated with Schottky diodes – they can onlyoperate at fairly low voltages, up to about 100V; the higher voltage Schottkydiodes tend to have a forward voltage that is approaching a PN diode; theinternal space charge capacitance of a high voltage Schottky diode can be high,thus resulting in reverse current when the capacitance is charging as the diodeis reverse biased.

4.2.3.2 PN diodes

These are the conventional diodes. They are available in many different types,from “slow” rectifier diodes, to ultrafast signal diodes. The latter are more akinto the diodes used in SMPS circuits. The ultrafast refers to the reverse recoverycharacteristics of the diode. The fast diodes have the ability to get the storedminority charge out of the diode very rapidly when the device is reverse biased.Whilst the stored charge is disappearing the diode is able to conduct current inthe reverse direction. This phenomenon is known as reverse recovery.reverse recovery

+ -

i i

+-

Forward current Reverse recovery current

v v

Figure 4.3: Reverse recovery in a converter secondary circuit.


+

Forward current

Reverse recovery

current

Figure 4.4: Reverse recovery in a boost converter circuit.

Reverse recovery can have a variety of effects from poor converter efficiency,to destruction of power devices. These two situations are illustrated in Fig-ures 4.3 and 4.4.

In Figure 4.3 one can see that when the voltage across the diode reverses,the diode will conduct current for a short period of time. This current couldpotentially be very large since the impedance opposing it would be small, andthe voltage driving it large (a combination of the output filter capacitor voltagein series with the voltage appearing across the secondary of the transformerwinding, which would now aid the reverse current flow). Clearly this situationis not good for converter efficiency, and the rapid rate of change of the reverseflowing current through the diode would result in a lot of EMI being produced.

Figure 4.4 is a basic schematic of the boost converter circuit. When theMOSFET turns on energy is stored in the inductor, and the diode is reversebiased. When the MOSFET turns off the current has to continue flowing, andthe diode immediately becomes forward biased. The current then flows throughthe the load and its filters. The reverse recovery problem occurs in the nextevent. The MOSFET again turns on to store more energy in the inductor.However, because the inductor has been forward biased it has stored minoritycarriers in it. When it becomes reverse biased, these minority carriers resultin the diode conducting reverse current as well as it did when forward biased.The only limitation to the current flow is the impedance of the circuit, whichis very low in this case. Consequently, in some circumstances the MOSFETmay receive too much current and destroy itself. Even if this does not happenthere will be excessive power dissipated in the device, and large amounts of EMIgenerated.

Practical issue 4.5 Most converters will use either ultrafast diodes, or Schot-


tky diodes to prevent reverse recovery problems.

Remark 4.7 Synchronous rectifiers are a very low loss rectifier employing aMOSFET. Even with these devices a Schottky diode is placed in parallel withthe MOSFET to take the instantaneous currents that need a path when theMOSFET is not on during the forward bias period. The body of a MOSFEThas a parasitic diode around the device, but this diode is very slow. A Schottkydiode in parallel with the device prevents the internal diode from being used.

Remark 4.8 Ultrafast diodes themselves generate a lot of EMI. This occursbecause an ultrafast diode still has reverse recovery current, the ultrafast bitbeing that it only last for a short period of time. However, as the diode rapidlydecreases the reverse current, it generates a very rapid rate of change of current,and consequent EMI.

4.2.4 The BJT

I shall not spend much time on describing the practical issues of using BipolarJunction Transistors (BFTs), since they are not commonly used today. For smallto medium power SMPSs MOSFETs have large enough current and voltagerange for most applications. For very high power applications, Insulated GateBipolar Junction Transistors (IGBTs) are more commonly used. We shall notlook at these devices here since they will be described in detail in Section 5.2.4.

Power BJT transistors were the device of choice for SMPS applications some15 to 20 years ago. They are not used today because of the difficulty in usingthe devices. For example, power BJT transistors have a very low current gain(typically known as the β of the device), especially in higher voltage applications.This means that considerable current must be supplied to the base of the deviceif there is a large current from the collector to emitter. This may not be aproblem for small converters, but it is an issue at larger powers. The consequenceof this high current is a complex and expensive base drive circuit.

A second problem is the voltage drop across the device. Even when a tran-sistor is turned hard on the collector to emitter voltage is approximately 0.2volt. Therefore the power lost in the device is approximately icvce. A MOSFETon the other hand would have a much lower voltage drop, and therefore muchlower power loss.

A final problem with the BJT is turning the device off. As with the diode,the BJT is a minority carrier device. Therefore it also suffers from chargestorage problems. Consequently, when the device is turned off it will continueto conduct current from the collector to the emitter until the stored chargedisappears. Special base drive circuitry must be used to get rid of the storedcharge as quickly as possible.

4.2.5 The MOSFET

As mentioned in Section 4.2.4, the MOSFET is by far the most common tran-sistor used in SMPS systems. There are two main types of MOSFETs used –n-channel devices (the most common ones), and p-channel devices – useful incertain situations. The n-channel device turns on when there is a positive volt-age exceeding the threshold voltage, between the source and gate of the device.


The p-channel device is the dual of this, and turns on when the gate has avoltage that is negative compared to the source. If the source of the p-channeldevice is connected to the positive supply rail of a system, then the device canbe turned on by simply connecting the gate to ground.

Remark 4.9 One could consider the p-channel MOSFET to be a device thatturns on with an active low signal, whereas the n-channel device requires anactive high signal.

Remark 4.10 The n-channel device is more commonly used because the resis-tance of these devices is less for the same size die. Consequently the cost for agiven current rating is less.

4.2.5.1 Bi-directional Conduction

It should be noted that MOSFETs can conduct current in both directions –i.e. from drain to source, and source to drain. We have seen this fact used insynchronous rectifiers in Section 2.4.9.

4.2.5.2 Power Losses

There are three sources of losses in MOSFETs used in switching applications:

Conduction losses These are the losses in the MOSFET resistance when itis on. The calculation of this loss is simple – P = I2RDSon . However,one should be aware that the MOSFET has a positive temperature coef-ficient, so as the device heats up its RDSon increases based on the typicalexpression:

R(T ) = R(25C)× 1.0078e(T−25) (4.7)

Therefore to calculate the power, one must first work out an initial powerusing the 25C value of RDSon , and then work out the temperature rise(using the package thermal resistance), and recalculate the power. Thisprocedure is carried out iteratively until the power value converges to avalue.1

Gate Charge Losses This is not really a loss in the MOSFET, but a lose in thegate drive circuitry driving the MOSFET. This is due to the fact that thegate of a MOSFET looks like a capacitor. Therefore in order to get thevoltage of the gate to rise quickly a substantial current must momentarilyflow into the gate. Many data sheets give the total charge to bring the gatevoltage to a certain voltage level, Qg. If the voltage level you are using isdifferent then a reasonable approximation is to multiply the Qg data valueby the ratio of your voltage to the data sheet voltage. The power can thenbe calculated by using P = QgV fs where fs is the switching frequency.

Switching Losses This is a loss that is dissipated in the MOSFET itself. Whena hard switching converter is turned off there is a period of time wherethe MOSFET is conducting a substantial current and is supporting a sub-stantial voltage. During this period there is substantial power dissipation

1Usually this calculation only requires one or two iterations. The thermal resistance is apoorly known parameter, and if convergence does not occur then one is probably dissipatingtoo much power.


in the device. Clearly the more times the device is switched per unit time,then the more average power will be dissipated in the device. In orderto roughly calculate the losses due to switching one can assume that asthe device turns off or on that the voltage rises or falls as a linear func-tion of time. Whilst this is happening the current through the device ismore or less constant. Therefore the expression for the power dissipa-tion for one on-off event would be the average voltage times the current –i.e. P ′ = IpkVpkts/2, where ts is the time for the on-off switching event.Therefore the total power dissipated over a one second interval (i.e. the to-tal energy dissipated in the device per second) is the energy dissipated perswitching event multiplied by the number of switching events per second– i.e. P = IpkVpktsfs/2

Remark 4.11 By calculating the conduction and switching losses, and usingthe thermal resistance of the MOSFET package one can come up with an esti-mate of the temperature rise of the device. This estimate is a good measure ofwhether the device is going to run hot or cool.

4.2.5.3 MOSFET Gate Resistors

You should always put a resistor in series with the gate of a MOSFET. This isrequired because the gate capacitance in series with the gate lead inductanceforms a high Q series LC resonant circuit. These circuits can oscillate at fre-quencies in the 100s of MHz range. They result in excessive heating of theMOSFET and the emission of copious EMI radiation from the circuit. Theinclusion of the gate resistor provides the necessary damping to lower the Q ofthe resonant circuit so that any oscillations are damped out quickly.

Practical issue 4.6 If you have two MOSFETs in parallel you should put anindividual resistor in series with each of the gates. If a single resistor is sharedbetween two gates then oscillations can occur between the two MOSFET gates.

4.2.5.4 Maximum Gate Voltage

Some designers decide to make the gate-source voltage very high in order to getthe gate voltage past the threshold voltage of the MOSFET in the minimumtime. If the gate-source voltage exceeds approximately 20 volt, then the MOS-FET is likely to be damaged. To turn a device on the most important thing isto have a very low impedance gate drive so that the current can be sourced tocharge up the gate capacitance.

4.2.6 Operational Amplifiers

Operational amplifiers are used extensively in SMPS control systems. We havebriefly considered control aspects of SMPS in Section 3.3. This discussion how-ever, did not consider some of the practical issues involved in using Op Amps.These practical issues are related to the non-ideal behaviour of Op Amps. Muchof the following discussion is relevant to general usage of Op Amps, and is notparticular to their use in SMPSs.


4.2.6.1 Offsets

There are two main types of offsets in Op Amps:

a. Input Offset Voltage. This is effectively a voltage between the + and− terminals of the Op Amp. It is a result of manufacturing differencesbetween the electronics of the input circuitry of the Op Amp. The offsetvoltage is usually a small value – i.e. mV or µV.

b. Input Offset Current. The input impedance of a real Op Amp is not infin-ity. Therefore current will flow into the terminals. Due to manufacturingtolerances, the current in the + and − terminals can be different. Theinput offset current is very small in absolute terms – usually of the orderof nAmp.

Considering the small values for the offset voltage and current one might betempted to say; “What is the problem?”. The problem with the offsets is dueto the fact that an Op Amp has a very high open loop gain, which is usuallygreater than 106. Therefore, if one has, say a 2mV offset voltage at the input,then the output would be 2× 10−3× 106 = 2× 103. Most Op Amps operate ona power supply of 12 to 15 volt. Therefore the offset voltage would result in theoutput of the Op Amp being saturated to the supply rail.

The immediate retort to the above paragraph is that Op Amps are neveroperated in open loop, but have feedback around them that lowers the effectgain. However, even with feedback, the gain can still be quite high, resulting insignificant output offset voltage. Similar arguments can be mounted with offsetcurrent when there are resistances in series with the inputs.

+

-

100k

10k9.09k

LM2902

Figure 4.5: Operational amplifier circuit for discussion of offsets.

4.2.6.1.1 Input Offset Voltage The following discussion is with referenceto the circuit of Figure 4.5. This shows a typical Op Amp circuit, with the non-inverting input shorted to ground. If the Op Amp was ideal then the outputvoltage would be zero under these conditions. However, the offset voltage fora LM2902 Op Amp is approximately 2mV. This means that there is effectively


2mV between the + and − terminals. The gain of the amplifier is 10 in thiscase, making the output with a zero input voltage equal to ±2mV ×10 = ±0.02volt. In many applications this may not be a problem. However, if the gain was1000 then the output offset would be 2 volt, which is clearly unacceptable.

Remark 4.12 Note that the output offset due to input offset voltage is not adirect function of the resistors used, but is related to the gain of the amplifier.

4.2.6.1.2 Input Offset Current The following discussion is also with re-spect to Figure 4.5. In this case we shall assume that the offset voltage is zero.Because the inputs to a real Op Amp take slightly different currents, then thevoltage at each of the input pins can be slightly different due to the differingvoltage drops across the resistors. For example, in the case of the LM2902, thedifference between the input currents can be as much as 5nA. Therefore the volt-age difference between the two terminals can be 9.09× 103 × 5× 10−9 = 45µV.This voltage, in turn, is amplified by the gain of the amplifier to give 450µVoutput voltage. As with the offset voltage case, in many applications this is notserious, but if the gain is high, or very high precision is required, then the effectof the input current offset may cause significant output voltage offset.

Remark 4.13 The effects of input current offset occur simultaneously with in-put voltage offset, therefore the output offsets have to be added together.

Remark 4.14 Input current offset will become more pronounced if larger resis-tance values are used.

Remark 4.15 More expensive amplifiers are laser trimmed internally in orderto lower the input offset current.

4.2.6.1.3 Input Bias Current The input bias current is the current thatflows into the input terminals even if there is no input offset current effect.The input bias current can cause offset problems if the resistances in the inputterminal leads are mismatched. In the case of Figure 4.5 we have been carefulto choose the resistors so that the effective resistance through which the biascurrents flow is the same. However, if there is a mismatch in the resistancevalues due to resistor tolerances, or alternatively due to other external circuitconsiderations, then there will be different voltage drops across the input circuitresistors. This results in the generation of different voltages on the input pinsto the Op Amp.

As a specific example, if we assume that the resistor to ground from thenon-inverting terminal is 19.09kΩ, and the input bias current for the LM2902 is90nA, then the difference in the resistance seen by the two bias currents is 10kΩ.Consequently the bias current offset voltage is V = 90nA×10kΩ = 900µV. Thisvoltage in turn is amplified by the amplifier gain of 10, giving an output offsetof 9mV.

Remark 4.16 Clearly, one should try and get the resistance in series with theOp Amp inputs to be the same values to eliminate the effect of bias currents onthe output.


Summary 4.1 Given the above discussion, we can develop and expression forthe output offset:

V = [Vos + IosR+ Ib∆R]Acl (4.8)

where Vos , the input offset voltage, Ios , the input offset current, Ib , theinput bias current, R , the average value of the input resistors, ∆R , thedifference between the values of the resistors, and Acl , the closed loop gain ofthe amplifier.

Remark 4.17 One can see from (4.8) that in order to minimise the outputoffset one must:

• Keep the resistor values as small as feasible to minimise the effect of theIos current.

• Make sure the input resistor values are closely matched so that ∆R ≈ 0 .

• Choose an amplifier with a very small Vos. Note that a low Vos Op Ampoften has a lower gain-bandwidth product.

4.2.6.2 Limits on Resistor Values

+

-

10kW

10MW

10kW

Figure 4.6: Conventional inverting Op Amp circuit with a gain of 1000.

It has been previously mentioned in Section 4.2.1.1 that it is not desirablein general to choose large values of resistors. In Op Amp circuits there is oftena temptation to do this when one is endeavoring to get a high gain feedbackamplifier. Let us consider the specific example circuit shown in Figure 4.6. Thisis a conventional inverting Op Amp circuit, and the resistors have been chosenso that the feedback gain of the circuit is 1000. The other requirement is thatthe input impedance of the circuit is 10kΩ. Consequently the feedback resistoris 10MΩ. This value of resistor is far too large to be practical. Besides theproblem that it will pick up a lot of electrical noise, it may not even be effectivesince the leakage impedance across the PCB is probably lower than this value.2


+

-

R1

R2

R1

R3

R4

vin

vo

Figure 4.7: Inverting Op Amp circuit with alternative feedback network.

An alternative circuit that can be used in this situation is shown in Fig-ure 4.7. In this case the feedback voltage is lower by the inclusion of the voltagedivider network comprised of R3 and R4. This result of this network is thatthe output voltage has to be higher in magnitude than it otherwise would be toget the full input current (vin/R1) to flow through the R2 resistor. The benefitthat one obtains is that there is much more freedom to choose the resistors sothat one can keep reasonable values and obtain the required gain.

If one calculates the gain of the Op Amp circuit of Figure 4.7 then it can beshown that it is:

vovin

= −R2R4 +R3R4 +R2R3

R1R3(4.9)

Let us consider the specific example of a gain of 1000. If we assume that theinput resistance of the circuit has to be 10kΩ, then this makes R1 = 10kΩ.Let us then choose R3 = 1kΩ, which will result in a significant voltage divisioneffect through the feedback network without having the other resistor valuestoo large. We still have two other resistor values to choose – R2 and R4. Letus arbitrary choose R2 = 100kΩ. The denominator of (4.9) now has a value of10MΩ, which means that the numerator must have a value of 1010Ω to achievethe required 1000 gain. The only unknown now is R4. Substituting the knownvalues into the numerator expression of (4.9), and equating to 1010, one cancalculate that R4 = 98kΩ. Therefore, to summarise, the resistor values are:R1 = 10kΩ, R2 = 100kΩ, R3 = 1kΩ, and R4 = 98kΩ. We have achieved therequired gain from the circuit without having to resort to any resistor valuesgreater than 100kΩ. This would reduce the noise pick of this amplifier circuitconsiderably.

Remark 4.18 A similar feedback resistor arrangement can be used for invertingamplifiers. However, in this case one is not constrained by the input impedance

2If one did not have the input impedance constraint then a smaller value for the inputresistor could be chosen so that the feedback resistor would be less than or equal to 1MΩ.


requirement, and therefore one has more freedom to choose the resistors in theconventional non-inverting feedback amplifier.

4.2.6.3 Gain-Bandwidth Product

log f

Gain (dB)

Gain bandwidthproduct

Aol

Acl

0

fcl-3db

fol-3db

funity

Figure 4.8: Gain-bandwidth product of an Op Amp.

Consider Figure 4.8 which shows a typical frequency response of an amplifier.The open loop gain, Aol, of the amplifier is very high – a gain greater than 106

is normal. However, the open loop frequency response rolls off at a very lowfrequency, usually 1 to 2 Hz. Since Op Amps are not designed to be used in openloop this is not a concern. Eventually the open loop gain of the amplifier goes toone. The frequency at which this occurs is the gain-bandwidth product of theamplifier. This figure is a constant for the amplifier. Therefore, if one appliesfeedback around the amplifier, this will lower the gain to say Acl. Thereforethe roll-off frequency of the amplifier will be increased. The frequency of the-3db roll-off multiplied by the gain at this point is equal to the gain-bandwidthproduct. Therefore Aolfol−3db = Aclfcl−3db = funity.

The importance of the gain-bandwidth product is that it indicates whetherone can simultaneously achieve the gain and bandwidth specifications from anOp Amp circuit design. There are many different Op Amps available, withwidely varying gain-bandwidth products. In SMPS applications one can findthat high gains are required to moderate bandwidths – for example a gain of300 and an bandwidth of 20kHz. In this case one would need an amplifier with again-bandwidth product of 300×20×103 = 6MHz. Whilst this is a very modestgain-bandwidth product for a discrete Op Amp, it may actually be larger thanthat of an integrated Op Amp that is inside a PWM IC. The effect of exceedingthe gain-bandwidth product of the amplifier on the performance of the SMPSsystem may be poor disturbance rejection, or even worse instability (due toexcessive phase shift in the feedback).


4.2.6.4 Phase Shift

Phase shift is related to the frequency response of the amplifier circuit shownin Figure 4.8. It is well known from control theory that at the -3dB pointof a single pole frequency response the phase shift from input to output is−45. At approximately a decade above this the phase shift has convergedto approximately −90. In an Op Amp circuit the situation is often morecomplicated than this due to the effects of internal compensation within the OpAmp itself. This can result in even more phase shift due to the introduction ofmore poles in the higher frequency areas of the frequency response.

The only way to accurately determine the phase shift characteristics of anOp Amp is to actually measure them over the frequency range of interest. Itis not always true that amplifier with higher gain-bandwidth product will haveless phase shift.

Remark 4.19 Excessive phase shift through an error amplifier in a feedbackloop can result in a degraded phase margin. The result on the performance isringing when there are step changes in the system, or marginal stability.

4.2.6.5 Slew Rate Limits

Slew rate limits are a non-linear effect related to the current limitations on theoutput stages of an Op Amp. Any Op Amp has a maximum rate at which theoutput can change. This is different from the gain-bandwidth product whereone is assuming that the high frequency signals are very small in amplitude, andtherefore do not encounter slew rate limit problems.

Consider the situation where an Op Amp circuit is being driven by a sinewave. The maximum rate of change of the sine wave occurs when it goesthrough zero. The slope of the sine wave at that point is given by its deriva-tive, Vmω cosωt, evaluated when ωt = nπ, n = 0, 1, 2 · · · . One can see that themaximum slope increases with both frequency and amplitude of the sine wave.Therefore, if the amplitude is increased at a given frequency then it may bepossible to exceed the slew rate limit of the amplifier.

If one had an amplifier of gain 10, with a 1 V p-p input sine wave input, thenthe output would be 10 V p-p. If the frequency of the input is 200kHz, thenthe maximum rate of change of the output would be 10× 2× π × 200× 103 =12.6V/µsec. Many low power Op Amps cannot slew their output this fast.When the slew rate limit is hit, the output tends to increase as a straight lineat the slew rate.

The slew rate becomes important in high-bandwidth SMPSs. When there isa rapid transient at the output, the error amplifier will see a large input. If theoutput slew rate of this amplifier is hit, then it will effectively introduce a phaselag in the feedback. This can result in poor disturbance rejection. It could alsoaffect phase margins.

4.2.7 Comparators

A comparator is a special type of Op Amp specialised for comparison applica-tions. In relation to voltage and current offsets the same principles apply to thecomparator.


4.2.7.1 Hysteresis

Almost always whenever a comparator is being used it should incorporate hys-teresis in the input. This is to prevent false triggering and potential oscillationof the device.

+

-

R1

R2

Vref

vin

vo

Figure 4.9: Comparator with hysteresis.

Figure 4.9 shows a comparator circuit with hysteresis established by thejudicious application of positive feedback. If one carries out a little analysis onthis circuit then one can see:

v+ = vin

(1− R1

R1 +R2

)+

(R1

R1 +R2

)vo (4.10)

where v+ , the voltage on the ‘+’ terminal of the comparator.To understand how this works, let us consider a specific example. Assume

that R1 = 1kOmega and R2 = 100kΩ, which means that R1/(R1 +R2) ≈ 0.01.Under this condition:

v+ = 0.99vin + 0.01vo (4.11)If v+ < v−, then vo = −V , the negative supply voltage. If this is substitutedinto (4.11) and the expression is rearranged, then for v+ = Vref we have:

vin =Vref + 0.01V

0.99(4.12)

Therefore the input voltage, vin, has to be greater than the reference approx-imately by 0.01V (it is actually a little more than this). At this input thecomparator would switch so that the output voltage would become +V . Wecan then repeat (4.12) for this case and get:

vin =Vref − 0.01V

0.99(4.13)

As we can see the input voltage has to be less than the reference voltage, again byapproximately 0.01V for the comparator to reach the switching state. Thereforewe have implemented classic hysteresis by the process, with the hysteresis bandbeing approximately 0.01V around the nominal reference voltage.


4.2.7.2 Comparator Interfacing

Comparators that have a single supply rail often don’t pull the output rightdown to the ground rail when the output should be zero. This can have adramatic effect if the device is driving a BJT or a logic gate. For example, somecomparators are only guaranteed to have a low output of approximately 0.6-0.7V when sinking 6mA of current.

Practical issue 4.7 If the comparator output does not pull to near zero at thecurrent level the output will be operating at, then the output voltage under thelow condition must be accounted for when calculating the resistors for hysteresis.

+

-

+V

+V

10kW

Figure 4.10: Interfacing a comparator to an NPN transistor.

Figure 4.10 shows a technique for interfacing a comparator to a NPN tran-sistor. If the comparator only pulls down to say 0.7V, then the 0.7V drop acrossthe diode will ensure that the transistor is still off. The 10kΩ resistor ensuresthat the base of the transistor is firmly connected to ground when the diode isturned off. For the comparator to turn the transistor on the output needs to begreater than 1.4V.

4.3 Introduction to Magnetics Design

The design of magnetics for a real application is a complex task. there aremany application specific decisions that have to be made – the core material,core style, type of conductor etc. There is usually no correct answer, since theparticular solution that a designer ends up with depends on the criteria used todecide the optimal solution.

The following discussion is far from an exhaustive treatise on the designof magnetic for SMPSs. The presentation closely follows that in [5], and willconcentrate on some of the main practical issues. A more detailed treatment ofthe design on magnetics for SMPSs can be found in [4].

4.3 Introduction to Magnetics Design 4-23

4.3.1 Review of the Fundamentals

Before looking a the specifics of SMPS magnetics design, it may be opportuneto review the fundamental concepts and expressions that are required.

4.3.1.1 Ampere’s Law

The law that connects the magnetic field intensity and mmf produced. It alsoconnects the magnetic field intensity and the flux produced. The normal integralequation for Ampere’s Law in a physics or electromagnetics text is:

F =

∮H · dl (4.14)

where boldfacing means that the quantity is a vector, and F , the mmf inAmpere-turns, H , the magnetic field intensity vector in Ampere-turns/metre,and dl , an incremental path length vector. The direction of the H vector isthe same as the direction of the flux vector in a isotropic medium. The directionof the magnetic flux density vector, B, can be determined by other techniques,but is defined for practical purposes by the right hand rule.

Let us consider the application of (4.14) to a single strand of wire. We knowa-priori that the F value in this case is I, the current being carried in the wire.Since the H and dl vectors are coincident around a circular path of integration(since the H vector is in the same direction as the B vector), and the total pathlength is 2πr, then one can conclude that:

H =I

2πr(4.15)

where r , the radius of the path of integration.

Remark 4.20 Equation (4.15) implies that the magnetic field intensity can bedefined as:

H =mmfl

=F

l=NI

l(4.16)

The relationship between Ampere’s Law and the magnetic field intensity isdefined by the following:

B = µrµ0H = µH (4.17)

where µr , the relative permeability, and µ0 , the permeability of free space.Equation (4.17) allows Ampere’s Law to be recast into a flux density form:

F =1

µ

∮B · dl (4.18)

In certain circumstances Ampere’s Law can be used to evaluate the magneticfield intensity, and under some circumstances the magnetic flux density. Fortu-nately, the design of transformers is one of the applications where the geometryis constrained in such a way that Ampere’s Law can be successfully applied ina simple fashion.


4.3.1.2 Faraday’s Law

Faraday’s Law is one of the fundamental laws of electricity. It was origi-nally determined experimentally, and later derived from the more fundamentalMaxwell’s equations, and subsequently from relativity theory. Every electricalengineer should know Faraday’s Law, but we will restate it here for complete-ness.

B(t)

Area Av(t)

Figure 4.11: A loop of wire enclosing an area of time varying flux density.

Figure 4.11 shows a typical situation where Faraday’s Law is active. Herewe have a loop of wire, and orthogonal to the surface of the loop there is a timevarying flux density, B(t).3 A voltage, v(t) is generated between the ends ofthe wire under this circumstance. Faraday’s Law tells us the magnitude of thevoltage under this condition:

v(t) =dλ

dt= N

dφ

dt= NA

dB

dt(4.19)

where λ , the flux linkage, φ , the flux, and N , the number of turns of thecoil.

4.3.1.3 Inductance

We know from Ampere’s Law that a wire produces magnetic field intensity, andconsequently magnetic flux density. The inductance of a coil is a number thattells us something about how well the physical configuration of the coil producesflux density. For example, if a coil has more turns on it then it would have moreinductance, if a coil has a large area then its inductance is larger, and it a coilis wrapped around a high permeable core material then its inductance will behigher. In all these situations, a higher inductance indicates that the coil isbetter at producing flux.

3If the magnetic flux density vector is not orthogonal to the surface area, then it is thecomponent that is that contributes to the Faraday voltage effect.


The fundamental definition of inductance is:

L =dλ

di(4.20)

In the case of linear magnetic materials (i.e. the flux density varies linearly withthe current through the coil) this expression can simply be written as:

L =λ

I(4.21)

Remark 4.21 A verbal definition of inductance is that it is the flux linkageproduced though the coil per unit current flowing through the coil.

Remark 4.22 Equation (4.20) is evaluated around some point of operation.Strictly speaking this definition is called the incremental inductance, since it isoperating point dependent (i.e. dependent on the values of λ and i).

Equation (4.21) can be used to develop the expression for the inductance interms of the physical parameters of a coil. From (4.21) one can write:

L =Nφ

I=NAB

I(4.22)

Since B = µH = µNI

l

∴ L =µN2A

l(4.23)

where l , the length of the magnetic path.

Remark 4.23 One can see from (4.23) that the inductance is defined entirelyin terms of the physical characteristics of the coil. Note that the inductance isrelated to the square of the coil turns.

Remark 4.24 In the case of a high permeability material as the coil the lengthof the magnetic path is easy to determine in (4.23).

One can develop Faraday’s Law in terms of inductance using the flux form ofFaraday’s Law and (4.22). From (4.22) one can write:

NAB = Li (4.24)

where the lower case i indicates that the current is changing. Substituting thisinto (4.19) one can easily see that:

v =dLi

dt= L

di

dtfor L constant (4.25)

which is the familiar voltage relationship from circuits.

Remark 4.25 Note that the L constant is not correct when the core materialin a ferro-magnetic material which saturates.


4.3.1.4 A Note on Units

Unfortunately the area of magnetics is permeated with inconsistent units. Thissituation exists for largely historical reasons. Most of the unit confusion occursbetween the mks system of units, and the cgs system. Just to make things evenmore confusing imperial units are also sometimes thrown in as well. Whereverpossible I will use mks units in these notes.

4.3.1.5 The Three R’s

In magnetic circuits three terms beginning with the letter R are often used –Reactance, Remanence and Reluctance. We shall briefly review these (mostelectrical engineering students should already know what they are).

4.3.1.5.1 Reactance This is a quantity similar to resistance that is usedwhen a circuit contains reactive elements such as inductors and capacitors. Thereactance can be used in a generalised form of Ohm’s Law.

For an inductor the magnitude of the reactance is Zl = 2πfL where f isthe frequency of the voltage across or the current through the inductor. Thevoltage across the inductor is related to the reactance by Vl = ZlI, where Vland I are AC phasors. A similar situation occurs with capacitance, where themagnitude of the reactance is Zc = 1

2πfC .If both resistance and reactance are both present, the impedance magnitude

is:|Z| =

√R2 + Z2 (4.26)

where Z is the generic impedance of the reactive element.

H

B

Bm

Br

Figure 4.12: A BH loop for a magnetic material.

4.3.1.5.2 Remanence Figure 4.12 shows a BH loop for a ferro-magneticmaterial. Notice that if the H is applied so that b = Bm and then driven backto zero there is some remnant flux still in the core. The level of this flux is theremanence of the core, and varies depending on the material. If the core is air,then the remanence is zero.


Remark 4.26 Remanence is important as it relates to core utilisation andlosses. For example a core with high remanence used in a uni-fluxed SMPSwill have a lower core utilisation. If use in a flux reversing type of SMPS thehysteresis losses will be high.

4.3.1.5.3 Reluctance Reluctance is often used in circuit analogies of mag-netic systems. Reluctance can be used in a way that is analogous to resistancein conventional circuit theory. Just as with resistance, the reluctance of a “mag-netic circuit” is related to the physical attributes of the circuit.

One way of developing the magnetic circuit analogy is to consider the mmfin a similar way to voltage is considered in a conventional circuit. This makessome intuitive sense because one can consider that the mmf is the driving forcethat produces the flux. We can substitute (4.16) into (4.17) to give:

B = µH =µNI

l(4.27)

Multiplying both sides of (4.27) by the area of the core, A, gives:

φ = BA =µANI

l(4.28)

This expression can be rearranged to make the mmf the subject of the expres-sion:

F = NI =l

µAφ (4.29)

From (4.29) we can then identify the reluctance term as:

R =l

µA(4.30)

Therefore (4.29) can be written as:

F = Rφ (4.31)

where the flux, φ, is analogous to the current in a conventional circuit.

Remark 4.27 “Magnetic circuit” analogies are particularly useful in transformerapplications because the magnetic paths are very well defined and their reluc-tances are known.

Remark 4.28 Notice that the reluctance defined in (4.30) obeys the same in-tuition as resistance of wires. For example, if one doubles the cross-section ofthe core (i.e. doubling A) then the reluctance drops, just as resistance would ifa wire diameter is doubled. Similarly, if the length of the core is increased thenthe reluctance increases. A similar effect also occurs with resistance.

4.3.2 The Ideal TransformerIt is beyond the scope of these notes to give a full treatise of transformers.Therefore we shall concentrate on the basic properties that are required tounderstand their design and operation in SMPS applications. We shall begin beconsidering the ideal transformer, since this is a useful concept to understand


Core

Secondary coilPrimary coil

N1

turns N2

turns

Figure 4.13: Circuit symbol for a transformer.

the operation of transformers. In addition, ferro-magnetic cored transformersare a reasonable approximation to the ideal transformer.

Figure 4.13 shows the conventional circuit symbol for an iron cored trans-former. The primary winding is the winding that is being driven by the source,and the secondary winding is usually connected to a load of some description.The dots on the ends of the coils indicate the way that the wire is wound onthe core. If current is injected into the lead at the dotted end of the primarywinding, then the flux produced in the core will have the same direction as thatproduced by the secondary winding if current is injected into its dotted terminal.From a voltage viewpoint, if a positive voltage appears on the dotted terminal ofone of the windings, then a positive voltage will appear on the dotted terminalof the other winding.

An ideal transformer is a transformer that has a core material of infinitepermeability. This means that no mmf is required to set up a flux in the core,since the reluctance of the core is zero (regardless of its length or area). Theinfinite permeability has the implications that there will be no leakage flux inthe transformer – i.e. all the flux produced by the primary winding will link tothe secondary winding.

We can calculate some of the basic properties of ideal transformers by apply-ing Faraday’s Law using the properties mentioned in the previous paragraphs.Consider the voltage on the primary side of the transformer:

v1 = N1A1dB1

dt(4.32)

Similarly for the secondary we can write:

v2 = N2A2dB2

dt(4.33)

Since both windings are wound on the same transformer core, then A1 = A2.Furthermore, since there is no leakage of flux density from the primary to the


secondary (and vice-versa), then B1 = B2. Consequently we can write:

dB1

dt=dB2

dt=

v1

N1=

v2

N2(4.34)

Remark 4.29 Notice that the implication of (4.34) is that the volts/turn of thetransformer are constant for both the primary and the secondary.

Since the ideal transformer requires not mmf to establish flux in the core, wecan write:

N1i1 +N2i2 = 0 (4.35)

which implies:i1N2

= − i2N1

(4.36)

Remark 4.30 Equation (4.36) could also be deduced using conservation of en-ergy together with (4.34):

v1i1 + v2i2 = 0 (4.37)

Using (4.34) one can write:

v2N1

N2i1 + v2i2 = 0

∴N1

N2i1 = −i2

ori1N2

= − i2N1

(4.38)

Remark 4.31 The negative sign in (4.38) indicates that the secondary currentdirection is opposite to the primary current direction.

Remark 4.32 The implications of (4.34) and (4.38) are that if the voltage isstepped up between the primary and the secondary then the current steps down(and vice-versa).

4.3.3 Real TransformersReal transformers do not have core materials composed of infinite permeabilitymaterial. The relative permeability of iron based laminations is in the range of1000-2000. Many of the power based core materials, which are widely used inSMPS applications, have permeabilities in the low hundreds range. The conse-quence of having finite permeability core materials is that not all the flux that isproduced by one winding is linked to the other winding. Another consequenceis that it takes mmf to produce flux in the core, since the core has reluctanceto be overcome.

Models of real transformers are often based on taking the ideal transformerand adding some extra elements around it to account for the non-ideal be-haviour. Consider the flux required in the core to induce voltages in the sec-ondary winding. If the secondary winding is open circuit, and if we apply avoltage to the primary, then the voltage across the primary is related to therate of change of flux in the primary inductance. A small proportion of theprimary flux does not link the secondary winding, and this is called the leakage


flux. The inductance associated with this flux is called the leakage inductance.Most of the flux produced by the primary links to the secondary winding, andthis is called the magnetising flux, and the inductance associated with it is calledthe magnetising inductance.

Lm

Ll

Ideal transformer

Magnetising

inductance

Leakage inductance

Figure 4.14: Simplified model of a real transformer.

If the secondary winding has a circuit connected to it, then the voltageinduced in the secondary by the magnetising flux will cause a current to flow inthis circuit. Consequently there will be flux produced by the secondary winding.This flux will be in such a direction in the core that it will tend to cancelthe magnetising flux. However, the flux in the primary is fixed by the appliedvoltage and its frequency (via Faraday’s Law), therefore this cancellation of fluxwill result in more current being drawn from the primary circuit to compensatefor the cancelled flux. This is effectively the load current on the secondary beingreflected back into the primary circuit. These arguments lead to the diagram ofFigure 4.14. Notice that the magnetising inductance effectively shunts currentaway from the ideal transformer. Therefore the magnetising current is “wasted”in the sense that it does not contribute to the output current.4 Similarly, theleakage inductance will support voltage across it, and this voltage does notappear across the primary of the ideal transformer, and will therefore not betransformed to the secondary.

4.3.3.1 Core Materials

As mentioned in the previous section real core materials have finite permeability.In addition they also exhibit properties such as saturation, eddy current andhysteresis losses. These practical issues manifest themselves in different waysin different applications. Table 4.3 summarises that main types of materialsavailable, and their relative merits and uses.

4The magnetising current is usually large so that the magnetising current is only a fewpercent of the load current of the transformer.


Material Consideration

Air Pro Air core magnetics cannot saturate.

Con The relative permeability of air is one, so one cannot getlarge inductances. Furthermore, the leakage of an air coretransformer would be very high.

Usage Primarily find application in rf circuits. Not used in SMPSapplications.

Ferrite Pro Ferrite magnetic materials are very widely used in both elec-tronic and SMPS applications. They have very high perme-ability and therefore can be used to produce large values ofinductance. These materials are usually relatively low cost.A variety of different materials are available for differentfrequency bands (to help control the losses).

Con Ferrites usually saturate hard. Poorly controlled initial per-meability.

Usage Ferrites are often used in power transformers and noisefilters.

Molyperm (MPP) Pro Soft saturation. Wide variety of different permeabilities, andthere values are well controlled by the manufacturer.

Con Higher losses than ferrites at a particular switching fre-quency.

Usage Used for inductors and noise filters at high DC currents.Powdered iron Pro Lower cost than MPP cores.

Con Slightly harder saturation than MPP, and lower permeabil-ity generally than MPP.

Usage Same applications as MPP where cost is a more importantconsideration than size.

Steel laminations Pro Very high saturation flux density, allowing the production ofvery high inductances.

Con Comparatively expensive, heavy. Saturates hard, and hashigh losses, especially at high frequencies. New amphorousiron overcomes some of the deficiencies in relation to losses.

Usage Low frequency transformers, power inductors.

Table 4.3: Core materials and their uses.


4.3.3.2 Saturation

Saturation is a phenomena in ferro-magnetic cores which causes the permeabilityof the core to change from the normal high value to a value near the permeabilityof air as the flux density in the core increases. Another way of stating this isthat when the core saturates an increase in the current in the winding aroundthe core results in only a very slight increase in the flux density in the core.

Saturation is usually a phenomena that one is wishing to avoid, since theincremental inductance of the core decreases dramatically as the core saturates.If the core inductance is restricting current flow in the circuit, then this decreasein inductance could result in a catastrophic increase in the current.

There are two types of saturation associated with cores – hard saturation,and soft saturation. Hard saturation refers to a rapid saturation – i.e. a smallincrease in the flux density results in a very rapid change in the permeability.Ferrites and steel laminations fall into this category. Soft saturation is wherethere is not a clearly defined saturation flux density, but instead the permeabilitychanges gradually with increased flux density. MPP cores display this saturationcharacteristic.

Remark 4.33 A core is said to be saturated if the current flow in the windingof the core has reduced its permeability to 20% of its permeability at very lowcurrents.

4.3.3.3 Other Core Limitations

4.3.3.3.1 Curie Temperature This is the temperature where the corelooses all its magnetic properties. When the core reaches that temperaturethe thermal agitation of the core domains is so severe that the domain align-ment is destroyed, and hence the permeability of the material decreases. Oncethis starts then there is a form of positive feedback occurring, and the collapseof the field continues. As the field collapses the domains have less field to keepthem aligned, and therefore the thermal agitation becomes even more dominant.

For many of the magnetic core materials the Curie temperature is of theorder of 200C. This temperature is so high that the wire insulation and bobbinmaterials would be damaged it it were reached. Some inductors may not havea bobbin, and employ special high temperature wire insulation. In this case theCurie temperature could be an important limitation.

4.3.3.3.2 Core Losses Changing flux in any ferro-magnetic material resultsin losses in the material. These losses are in two different forms – Eddy currentlosses, and hysteresis losses.

Eddy current losses are due to induced current in the core by the changingflux. These currents result in resistive losses. A general expression for Eddycurrent losses is [7]:

pe = keω2B2 W/m2 (4.39)

where ke is a constant related to the particular type of material.The expression for hysteresis loss is [7]:

ph = khωBn (4.40)


where kh and n are empirical constant dependent on the type of material. Typ-ical values of n are 1.5 < n < 2.5 for conventional lamination steel materials.

Remark 4.34 Notice from (4.39) that the Eddy current loss is dependent in asquared sense on the applied frequency, whereas hysteresis loss in only linearlydependent on the frequency. Therefore it is very important to have a high resis-tivity for the core material in high frequency applications. The bonded type corematerials such as ferrite, MPP, and iron powder to designed to achieve this.

Let us assume that we have a magnetic structure, such as an inductor, that isdriven by a sinusoidal voltage source. It is easy to show that the maximum fluxdensity in the magnetic structure is:

B =V

NAω(4.41)

where V , the amplitude of the sinusoidal voltage source, and ω , its frequency.N and A are the turns of the coil and area of the core respectively.

Remark 4.35 One can immediately see from (4.41) that if B is to be madesmaller, then N or A must be made bigger.

Consider the situation where the power loss in the core of our magnetic structureis less than the total copper losses. Based on (4.39) and (4.40) we can seethat we must increase the peak flux density experienced by the core, giventhat the excitation frequency is fixed, and the core dimensions are fixed. FromRemark 4.35 one can deduce that this means that the number of turns woundonto the core must be decreased. This will result in a lower inductance for thecore, and hence for a fixed supply voltage, a larger peak current. Therefore,even though the wire resistance would have dropped, the higher rms currentinto the core will result in higher copper losses.

4.3.4 Optimal Design IssuesIt can be shown that minimum power loss is obtained in a combined electrical/-magnetic structure if:

• The core losses are equal to the copper losses.

• The primary copper loss is equal to the secondary copper loss.

Remark 4.36 The core losses equal to copper losses equality for minimumoverall losses applies equally well to electrical machines as to inductors andtransformers.

Remark 4.37 Core losses equal to copper losses equality for minimum losses isanalogous to the maximum power transfer theorem in circuit theory. You mayrecall that this theorem says that the load resistance should be equal to the sourceresistance for the maximum power to be transferred to the load from the source.Therefore, in this case one has the same losses in the source resistance and theload resistance.5

5In the case of maximum power transfer one is trying to maximise the power. In electri-cal/magnetic systems the power is minimised.


Assuming that one has a transformer type of structure, consider the followingscenario. The power loss in the magnetics is less than that in the copper.Therefore, we wish to increase the power loss in the core and reduce the lossesin the copper. The power losses in the core can be increased if the number ofturns on the primary winding are decreased. This can be seen if we assume thatthe structure in being driven at a voltage source:

v(t) = V sinωt

∴ B(t) =1

NA

∫v sinωt dt (from Faraday’s Law)

=V

NAωcosωt

⇒ B =V

NAω(4.42)

which is the same as the expression mentioned in (4.41).

Remark 4.38 Equation (4.42) shows that the peak flux density in the core isincreased if the number of turns in the coil are lowered.

If the number of turns in the primary coil are lowered, then the length of thecopper wire is lowered, and hence the wire resistance. If the turns in the primaryis lowered, then the turns of the secondary are lowered to maintain the sameturns ratio. If we maintain the same amount of copper under this condition, thenwe can increase the diameter of the wire, this again decreasing the resistance ofthe primary and secondary windings. These two effects mean that the overalllosses of the secondary will be reduced, since maintaining the same turns ratiomeaning that the secondary current would not change.6 One can mount asimilar argument if the losses in the core are larger than the copper losses. Inthis case the turns on the primary are increased.

To help keep the primary and secondary winding losses approximately thesame one should allocate similar area to the primary and secondary windings.If the secondary has more turns, it must have proportionately smaller wire.If there are multiple secondaries, allocate their winding area by output power(higher getting more winding area).

If one is designing an inductor, then the magnetic losses can be traded offagainst the copper losses by adjusting the cross-section of the core. For example,if the magnetic losses are low, then they can be increased by decreasing the corecross-section and therefore increasing the flux density. The total losses in thecore are related to the losses per unit volume, and of course the volume ofthe core. If the cross-sectional area is decreased then the core volume dropsin proportion to the decrease. The flux density increases in proportion to thedecreased area. However, the total losses will increase since the losses per unitvolume are related to the peak flux density squared.

Example 4.1 Assume that the core cross-section of the typical transformer corehas been halved. This will mean that the volume of the core has been halved. Theresult of the area increase, assuming that the mmf is the same and the core is

6Note that in this discussion we are assuming that the losses in the primary due to themagnetising current can be neglected. The losses due to this component of the current actuallyincrease with the reduction in the number of turns of the primary.


not saturated, is that the peak flux density will double. The Eddy current lossesper unit volume in the core are proportional to B2, therefore the losses per unitvolume increase by 4. The total losses would therefore by 1/2 × 4 = 2 timesthose before the change in core area.

4.3.5 Design of an InductorIn this section we shall proceed through the practical design of an inductor. Thereason for this is that this is the simplest magnetic structure that is useful ina SMPS design. For example, inductors are required in the buck converter forthe output filter. In the following design we shall be referring to graphs from[8, 9], which is a data manual and selection guide for products by Ferroxcube,formerly Philips. The specifications for the inductor are shown in Table 4.4.

Parameter Specification

Inductance 35µHDC current 2 AmpMax power dissipation 300mWOperation frequency 250kHzAverage voltage 10V

Table 4.4: Inductor specifications.

From Table 4.4 we need to calculate a few other values that will aid in theselection of a core material. We know from the maximum power dissipationspecification that:

R <Pmax

I2=

300× 10−3

22= 0.075Ω (4.43)

Remark 4.39 Equation (4.43) does not account for losses in the magnetic ma-terial. Therefore this value is simply an upper bound on the winding resistance.

Let us check to see if we can consider this application to be a DC inductorapplication. The input voltage to the buck converter is 15V and the outputvoltage is 5V. Using (2.3) one can deduce that the duty cycle is 33% or 1/3.The switching period, T , is 4µsec. Using the circuit expression for the voltageacross an inductor we can write:

di =VL dt

L=

10× 4µsec× 13

35µH= 0.381Amp pk-to-pk (4.44)

Remark 4.40 The di in (4.44) is relatively small compared to the DC currentof 2A, therefore the inductor can be considered to be fulfilling the function of theDC choke.

Remark 4.41 The implication of (4.44) is that the permeability of the mag-netic material should be fairly low to prevent the magnetic system from saturat-ing. The other alternative is that a high permeability core be used with an airgap.


Figure 4.15: Ferrite choice (from [9]).

Figure 4.16: Initial permeability with respect to frequency for 2P iron powderFerroxcube material (from [8]).

Given that the inductor can be considered a DC power inductor (or a DCchoke) one can consult [9] to find out what magnetic types are suggested forthis application. The relevant table from [9] is shown in Figure 4.15. Thissuggests that the 2P range of iron powder cores are suitable for this application,since the operating frequency is less than 500kHz. One could also choose the3C range of cores – these cores have much higher initial µi compared to the2P range. Since the inductance that we desire is not very high then we can


Figure 4.17: Incremental permeability as a function of magnetic field strengthfor 2P iron powder Ferroxcube material (from [8]).

afford to use a low permeability material. Another advantage of this is that onewould not have to consider introducing a air gap to prevent core saturation.Figure 4.16 shows the initial permeability for a selection of different 2P ironpowder materials with respect to frequency of operation. Notice that the relativepermeability of the 2P90 material is approximately 90 over the frequency rangeof interest. Another important, and related figure, is Figure 4.17, which showsthe incremental permeability of the material versus magnetic field strength. Theincremental permeability is the permeability of the material for small variationsof the magnetic field strength on a DC bias field. This is precisely the situationthat occurs in a filter inductor of the type we are designing.

Given that we have decide to use a 2P type material from Ferroxcube, wefirstly have to make an estimate of the number of turns required to obtain thedesired inductance. An important parameter supplied by the core manufacturersis the AL value. This value is the inductance per turn for a particular core.Therefore, if we assume the initial value of permeability then we can come upwith a first estimate of the number of turns required.

Another important value that we have not considered as yet is the size of thecore we are to use – for any given material there are a number of different coresizes. Factors that influence the core size are the wire diameter and number ofturns required,7 and the maximum flux density that is allowed in the core.

7The combination of the wire size influence the core size to the extent that the core mustbe big enough to physically allow the windings to fit on the core.


4.3.5.1 Key Magnetic Parameters

A few notes on key parameters that appear in the data sheets and selectionguides for magnetics would be opportune at this juncture. The following dis-cussion is based on the parameters described in [8]. Note that we will notdescribe all the parameters in these sheets, but will concentrate on those thatare most useful for the job at hand.

4.3.5.1.1 Initial Permeability This is the relative permeability at verylow magnetic field intensity. It is formally defined as:

µi =1

µ0

∆B

∆H(4.45)

where ∆H → 0.

4.3.5.1.2 Effective Permeability This is the effective permeability of thematerial when an air gap has been introduced in the magnetic circuit. Its valueis dependent on the initial permeability of the material and the effective air gap.The expression for the effective permeability is:

µe =µi

1 + µiGle

(4.46)

where:

G , the air gap length.

le , the effective magnetic circuit length.

This expression is only valid for relatively small air gaps. For larger air gapsfringing effects will raise the value of µe above that calculated by the aboveexpression.

4.3.5.1.3 Amplitude Permeability This is relationship between the fluxdensity and field intensity at high field strengths with the presence of a biasfield. The expression is:

µa =1

µ0

B

H(4.47)

Clearly the value of this parameter depends on the applied field strength dueto the non-linear nature of the materials.

4.3.5.1.4 Incremental Permeability This is the small signal permeabilitywhen it is superimposed on a DC biased field. It is formally defined as:

µ∆ =

[1

µ0

∆B

∆H

]HDC

(4.48)


4.3.5.1.5 Effective Core Dimensions Many magnetic cores have irregularshapes. In order to allow design calculations on these structures the manufactur-ers supply a set of effective dimensions for the core. These effective dimensionsare the dimensions of the toroidal core that will produce the same magneticproperties of the original core. The effective dimensions supplied are Ae , theeffective cross-sectional area, le , the effective length of the core material, andVe , the effective volume of the core.8

Given the above values then the effective reluctance of the core can be writtenas:

Re =leµAe

(4.49)

In many data sheets (e.g. in [8]) (4.49) is usually written as:

Re =1

µ

∑(l

A

)(4.50)

where the term∑(

lA

)is known as the core factor. core factor

Using the core factor one can calculate the inductance of the core using thefollowing expression:9

L =Nφ

I=N2

Re=

µ0N2

1µe

∑(lA

) (4.51)

If the magnetic structure is being driven by a sinusoidal source then it issimple to show that the peak flux density in the core is: peak flux with sinu-

soidal excitation

B =V

NωAe(4.52)

If the driving waveform is a square wave with a peak of V volts, then the peakflux density is given by: peak flux with

square wave excita-tionB =

πV

2NωAe(4.53)

Similarly the peak magnetic field intensity can be worked out using the effectivelength: peak magnetic field

intensityH =

NI

le(4.54)

Remark 4.42 The above calculations assume that Ae is uniform throughout thematerial. However, in many magnetic structures this is not the case. Thereforethe peak flux density is calculated using the minimum cross-section area Amin.Most cores are designed so that Ae ≈ Amin so that there is no significant increaseof flux density due to the physical core design.

4.3.5.1.6 Inductance Factor The inductance factor for a core is the in-ductance of a single turn coil for the particular core. This is related to the

8All the measurements are assumed to be in MKS units.9Note that we are using the expression NI = φRe from magnetic equivalent circuits [10].


magnetic properties of the core – i.e. namely the permeability. The definitionof the inductance factor can be simply obtained from (4.51):

AL =1

Re=

µ0µe∑(lA

) =4π × 10−7µe∑(

lA

) Henry (4.55)

Usually AL is quoted in terms of nH, therefore (4.55) is written as:

AL =1256.7µe∑(

lA

) nH (4.56)

The inductance factor is obviously related to the total inductance by theexpression:

L = N2AL (4.57)

which means that for a given desired inductance the number of turns can easilydetermined by rearranging (4.57) to give:

N =

√L

AL(4.58)

4.3.5.2 Details of Inductor Design

Figure 4.18: Core type selection table (from [8]).

Now that we have reviewed some of the key parameters that are requiredto understand magnetics data sheets we can now return to the design of theinductor.

The material was previously chosen to be Ferroxcube 2P. The next step isto choose a core type and size. We shall use a toroidal or ring core. One can seefrom the table in Figure 4.18 that this is a favourable choice for this application.

Many manufacturers provide tables to aid in the selection of a particularcore. These tables not only allow a first guess at the core selection material,


but also suggest a specific core. This then gives one an initial core size to base adesign on.10 This initial core selection for cores that have a DC current throughthe windings is often based on a graph that uses the energy stored in the core –i.e. 1

2LI2. The L and I terms in this expression are both related to the size of

the core, L via the core length and area, and the current by size of the area toput the windings in. Figure 4.19 shows the core size data and AL parametersfor Ferroxcube iron powder 2P cores. Unfortunately the Ferroxcube selectionguide does not have such a table for the iron powder cores.

We shall select an initial core from the table in Figure 4.19 and then calculatethe number of turns required. We shall use this, together with the specificationon the power dissipation to work out the amount of area required in the centreof the core for the winding. Depending on the result of this we may have toselect another core. One other criteria for the selection of the core that was notpreviously mentioned was that one would generally want the core to be as smallas possible, since this usually correlates to minimum cost.

Let us arbitrarily choose core TN17/9.8/4.4 2P90 from Figure 4.19. As canbe seen from this figure AL = 42, therefore using (4.58) one can get:

N =

√35× 10−6

42× 10−9= 28.9 turns (4.59)

This has to be rounded up to an integer number of turns, so let’s make it 29turns.

The next thing to consider is the amount of wire required for this. Theturns have to be wound around the toroid, so that the copper passes throughits centre. The size of the centre of the toroid places a limit on the number ofturns for any gauge of wire used. Taking into consideration the difficulties ofwinding the core, as well as the amount of space taken by wire insulation, thetypical winding fill factor is 45–50% – i.e. only 45–50% of the available spacefor the winding can practicably be used.

To select the wire we need to consider the amount of current that it has toconduct, and the amount of power that will be dissipated in its resistance. Theskin effect should not be that important in this case since the high frequency ACcurrents are relatively small compared to the DC current flow. A first selectionof the wire can be made from a wire table. We shall use the table printedin [5], which is itself a reprint of a table produced by Magnetics Inc. in theirliterature.11 One candidate size is AWG18 wire, which nominally has a currentcapacity of 2.17 Amp. The resistance of the wire per metre is 0.02096Ω/m, andits wire area (including insulation) is 9.83× 10−3cm2, or 9.83× 10−7m2.

Referring to Figure 4.19 we can work out the length that the wire has to goaround the core (approximately) as 19.5mm or 0.0195m. However, this valuedoesn’t take into account the fill factor which effectively extends the length ofeach turn. An approximate expression for the length of a turn for a toroidalcore is [5]:

lt = D + 2H (4.60)

10Often this initial selection may prove to be inadequate in some detail. The designer mayhave to choose a larger or smaller core dependent on the nature of the inadequacy.

11The Magnetics Inc Web site, http://www.mag-inc.com, has a free program that can bedownloaded for the design of filter inductors.


Figure 4.19: Core data for toroidal cores using powdered iron (from [8]).


where D and H are as defined in Figure 4.19. Using (4.60) the length of a turnis 0.0181 + 2× 0.0053 = 0.0287m.

Using the number of turns calculated in (4.59) we can calculate the resistanceas 29×0.0287×0.02096 = 0.01744Ω. Therefore the power loss in the windings isapproximately I2R = 4×0.01744 = 70mW. This is well within the specificationof less than 300mW total power loss, and leaves 230mW for the core losses.

The other issue to examine is whether the wire can be wound on the core– i.e. will it fit in the hole in the centre. The total wire area, including theinsulation, is 29× 9.83× 10−7 = 2.85× 10−5m2. The total area available in thecentre of the core is πd2/4 = 6.65 × 10−5m2. A fill factor is 0.5, therefore thearea available for the wire is 0.5× 6.65× 10−5 = 3.325× 10−5m2. Therefore itis possible to wind the wire on the core.

Remark 4.43 One must also take into account the thickness of the wire. If wireis too thick then there will be trouble bending it around the core. In addition,the act of bending it around the core may also fracture the core, since ferriteand iron powder materials are very brittle.

We now need to check the core flux density. This can easily be done using (4.51)and the Ae value from Figure 4.19 to give:

B =LI

NAe=

35× 10−6 × 2

29× 15.8× 10−6= 152mT (4.61)

Remark 4.44 The maximum flux density is not related to the losses in thissituation, since it is primarily a constant flux density which does not causelosses. However, there is a ripple in the voltage across the inductor, that resultsin a ripple in the inductor current, and consequently an AC component sittingon top of the DC flux density. It is this component of the flux that is relevantto the loss calculations.

Remark 4.45 The DC flux density is important because of the effect that ithas on the permeability of the material.

If we consider the BH characteristic for the 2P materials (from [8]) shownin Figure 4.20 one can see that the flux density level is far below saturation.

Figure 4.21 shows the losses for 2P material at various peak flux densitiesand frequencies. These plots are very difficult to read with any accuracy. Thebest approach is to form an equation for the relevant line on the graph.

The equation for a line on the graph is of the form:

Pv = aBx (4.62)

where a and x are unknowns to be found. Since we have two unknowns thenwe need two independent equations to find them.12

Considering Figure 4.21 we can write the following two expressions by ex-amining the 200kHz curve:

28× 103 = a× (4× 10−3)x (4.63)

800× 103 = a× (20× 10−3)x (4.64)12Even using this technique it is difficult to get accurate results since it is hard to read off

the points to develop the simultaneous equations.


Figure 4.20: Typical BH characteristic for 2P magnetic material (from [8]).

Figure 4.21: Losses in 2P material with respect to flux density and frequency(from [8]).


Multiplying (4.63) by (800×103)/(28×103) and equating to (4.64) we can write:

800

28a× (4× 10−3)x = a× (20× 10−3)x (4.65)

Canceling out the common expressions, and taking logarithms of both sides ofthis expression we can write:

log(28.57) + x log(4× 10−3) = x log(20× 10−3) (4.66)

which can be solved to give x = 2.0829. We can then substitute this intoeither (4.63) or (4.64) to give a = 2.766 × 109. The resultant equation can bemultiplied by 250/200 = 1.25 to account for the fact that it has been derived fora frequency of 200kHz (this is a crude extrapolation). Therefore the resultantexpression for the losses is:

Pv = (3.4575× 109)B2.089 W/m3 (4.67)

at a frequency of 250kHz.13We are now in a position to calculate the losses. However, before doing this

we must calculate the AC component of the flux density in the material (asnoted earlier). Recall from (4.44) that the current ripple through the inductoris 0.381 Amp. Therefore the AC magnetic field intensity is:

HAC =NIACle

=29× 0.381

0.0402= 274.85A/m (4.68)

Assuming that the core relative permeability stays at 90 then we can work outthe peak to peak flux density as a result of the ripple current:

BAC = µ0µeHAC = 4π × 10−7 × 90× 274.85 = 0.031Tesla (4.69)

We can now work out the losses by using the B value from (4.69) in (4.67) to givePv = 2.439e6W/m3. For the volume of material in the core (Ve = 635×10−9m3)the loss is PvVe = 1.54W. This power dissipation is outside the specification forthe inductor by a factor of 5 times. Therefore we must go back to the drawingboard with this design.14

In order to lower the losses in the core we need to go to a larger core size.Let us try the TN24/15/7.5 core. We shall quickly go through the same designprocess as carried out above. In this case the AL = 61nH, and consequently:

N =

√35× 10−6

61× 10−9= 23.95 turns (4.70)

Therefore we will make the turns equal to 24.Given the turns we can now work out the maximum AC flux density variation

as:

BAC =LIACNAe

=(35× 10−6)(0.381)

(24)(32.8× 10−6)= 0.0169 Tesla (4.71)

13This expression is only going to give a ball park figure for the losses. To get accuratevalues measurements must be taken.

14The above design closely follows that in [5] which uses a similar permeability and sizecore. However, the resultant losses found in [5] are approximately 1/10th those found above.The Lenk analysis uses a complex mix of units, so I am assuming that there has been an errorin one of the units conversions. I have been unable to find an error in the design calculationsabove.


Substituting this into (4.67) gives Pv = 690, 162 W/m3. Therefore the totalpower dissipation is PT = PvVe = 690, 162× 1895× 10−9 = 1.3 Watts. This isless than in the previous case, but is still approximately 4 times the specification.One might suspect that we will have trouble satisfying the specification fromthe small change in the losses for the change in the core. Indeed, if one choosesthe largest core in Figure 4.19, TN33/20/11, we will still have trouble satisfyingthe specification. If this is carried out the core losses are of the order of 0.7Watts, which is still twice the specification.

The question is now what can we do. If we are to stick with the frequencyof operation we need to find a core material with lower core losses. However,if the frequency of operation is part of the design mix then we can make thislower. This will also have the effect of increasing the ripple in the current, sothe inductance value would have to be varied to allow this specification to besatisfied.

Let us briefly consider a drop in the frequency to 100kHz. If we want thesame ripple of 0.38 Amp in the 2 Amp DC current then the inductance valuecan be found to be 87µH using (4.44). The turns can now be found to be 32turns using (4.58) and the value for AL = 87nH (for the TN33/20/11 core).Therefore BAC = 0.012 Tesla using (4.71) with the new values. Reading off theapproximate value for the losses per m3 from Figure 4.21 we can see that it isapproximately Pv = 70W/m3. The core volume is 5200 × 10−9m3, and hencethe total core losses are PT = PvVe = 0.364 Watts. This is still outside theoriginal specification in relation to the losses, but it is much closer than thosecalculated previously. A further improvement can be made in relation to thelosses by lowering the frequency further, but the number of turns required toachieve the higher inductances mean that check would have to be made to seeif there is enough winding area.

Remark 4.46 The fundamental problem with the above design is that the ma-terial chosen has too high a power dissipation per unit volume. The specificationis much easier to satisfy if a lower loss material is chosen. For example, the2P material we chosen has a lose of approximately 200kW/m3 at 10mT fluxdensity. The 3C material by the same manufacturer has losses so low (of theorder of 1 rightarrow 2 kW/m3) that the manufacturer has not plotted thembelow approximately 10mT. Therefore the specification would have been satisfiedif this, or a similar low loss material had been chosen at the outset. For exam-ple, in [5] the same design is carried out using MPP material manufactured byMagnetics Inc.. This material has a loss of 18.2kW/m3 at 10mT flux density.In this design the core losses turn out to be 140mW.

Remark 4.47 The frequency of operation of this inductor would mean that Litzwire should probably be used. This would change the wire area calculations above.The skin effect at 250kHz needs to be considered. In fact if the frequency is above50kHz the skin effect must be considered.

4.3.5.3 Issues in Forward Converter Transformer Design

We shall not go through a complete design of a forward converter transformer,but instead we shall highlight a few of the major issues that need to be con-sidered. We shall do this in the context of the paper design. The following is


based on an example in [5]. The basic design of a forward converter is shown inFigure 3.2.

The input voltage to the forward converter is 48VDC, and the output voltageis 5VDC at 100 Watts. This implies that the output current is Io = 100/5 = 20Amps. This is obviously a very high current, therefore it is important that theresistive losses are kept low for efficiency reasons. This means that the numberof turns on the secondary should be low, and the wire should be a thick gauge.

Let us consider the issues involved in selecting the turns ratio for the trans-former.

4.3.5.3.1 Turns Ratio = 1:1 This would imply that when 48VDC is ap-plied across the primary there is 48VDC across the secondary (ignoring theleakage inductance of the transformer). The problem with this voltage is thatone cannot obtain Schottky diodes above about 45 volt with a low forward volt-age drop. One would require a diode with a voltage rating significant higherthan 48 volt, therefore the forward voltage drop will be high.

Remark 4.48 For high current outputs forward voltage drop is important. Theloss is VfIo, and this is being dissipated in the rectifier diode, or the free-wheelingdiode. One can use synchronous rectifiers to overcome this problem, but thisrequires a significant increase in the complexity of the circuit due to their driveand control requirements.

For the diode loss reason given above the choice of a 1:1 turns ratio is not agood one.

4.3.5.3.2 Turns Ratio = 2:1 The primary has twice the turns of the sec-ondary, meaning that there is 24VDC on the secondary. This means that theduty cycle of the converter is approximately Vout/Vsec = 0.21. The currentthrough the primary of the transformer (assuming that there is a constant 20Amp current in the load) is 0.5 × 20 = 10 Amp. This quite a bit of cur-rent for a MOSFET switch. The losses in the MOSFET are approximately102 ×RDSon × 0.2. These losses may result in an expensive MOSFET, or alter-natively a large heat sink.

4.3.5.3.3 Turns Ratio = 3:1 In this case the secondary voltage is 16 voltand the primary current is approximately 7 Amp. The duty cycle is 0.31. There-fore the losses are 72 × RDSon × 0.31, which is substantially lower than in theprevious case.

4.3.5.3.4 Turns Ratio = 4:1 The secondary voltage in this case is 48V DC/4 =12V DC. Therefore the duty cycle is Vout/Vsec = 5/12 = 0.42. This duty cycleis very close to the limit cycle of many of the popular PWM ICs (which arelimited to duty cycles of 0.45). If there is any variation in the input voltage,and if the diode drops are accounted for, then it is possible for this limit to behit.

The conclusion of the above turns ratio scenarios is that a turns ratio of 3:1is probably the best one to choose.

The remainder of the design of the forward transformer involves the choiceof the core material and the magnetising current. The magnetising current is


important, since this current does not contribute to the load current, but doescontribute to the losses in the converter. The magnetising inductance is alsoimportant from the point of view of losses in the core. Fortunately, lowering themagnetising current involves increasing the primary turns (whilst maintainingthe 3:1 turns ratio), which in turn also lowers the flux density in the core (fora fixed input voltage). There is a limit to how far this can be taken, since themore turns requires more copper in both the primary and secondary. Hence thisimpacts on the size of the transformer.

4.3.6 Design of Manufacturable MagneticsMagnetic components are usually custom made in a factory, unlike most otherelectrical components which are mass produced in an automated fashion. Thismeans that when we design some magnetics for a product that will be massproduced we need to take into consideration how easy it is to manufacture, andalso how repeatable the specifications will be in a manufacturing environment.

4.3.6.1 Wire Gauge

The general rule in relation to wire gauge is simple – don’t select wire that istoo thick or too thin.

Practical issue 4.8 It is best to limit the wire gauges to a maximum of #20(i.e. 7.91 × 10−7m2) and an minimum of approximately #38 (i.e. 0.132 ×10−7m2). For wire gauges thicker than #20 some machine cannot wind thecores, and above #18 there is a risk of fracturing the core as the wire is woundaround it.

Wire gauges thinner that #38 can still be machine wound, but it is difficultto build prototype cores with wire this thin – it is as thin as a human hair.Therefore it is best to use #38 wire even if you can get away with thinner wire.

Another aspect of wire gauge to consider is that one should try and limit thenumber of different wire gauges being used. This will allow some volume-of-purchase economies to be obtained.

4.3.6.2 Wire Gauge Ratio

If you are winding different wires onto a magnetic structure, and these arelayered on top of each other, then try and keep the wire gauges close together.This helps prevent the thinner wire from finding its way into the crevices of thethick wire – the different windings do not form nice layers. When this happensit can effect the leakage and coupling of the magnetic circuit.

Practical issue 4.9 Try to keep the wire gauges in a magnetic structure within10 of each other.

4.3.6.3 Toroidal Core Winding Limits

If a toroid is going to be machine wound then the only limit on the windings isthe size of the winding area and the size of the wire. However, if one is to handwind these cores there is a practical limit set on a human’s ability to concentrateand count.


Practical issue 4.10 Hand winding a toroidal core is a real pain. If one isgoing to wind a prototype one by hand it is best the keep the number of turnsbelow approximately 200. It is very easy to forget the number of turns on thecore (even for this number).

4.3.6.4 Tape versus Wire Insulation

For safety reasons tape is often used between the primary and secondary wind-ings of a transformer. When there are high voltage differences between theprimary and secondary a flanged bobbin may be used, which divides the wind-ing area into two pieces with a piece of plastic.

In many designs there is substantial voltages between the secondaries. There-fore insulation is required between these to prevent arcing. In the case of highvoltage secondaries there may need to be insulation between the layers of thesame secondary winding.

Practical issue 4.11 Adding tape insulation layers should be avoided if possi-ble. The tape takes up a lot of area, and even more importantly it usually mustbe put on by hand.

Remark 4.49 In many cases it may be better to go to thicker and higher classwire insulation instead of using tape. It is less labour intensive and can lead toa more compact design.

4.3.6.5 Layering of Windings

The windings should be wound from the left of the bobbin to the right and thenback from the right to the left for each of the layers (except for a toroid).

The windings should take into account where the connection pins are, andshould be designed so that a winding does not terminate half way up the bobbin.If this does happen then one would have to take the end connection to the topor bottom of the bobbin to connect to the end pins. Any other layer will thenhave a lump in it where it goes over the top of this end connection.

Practical issue 4.12 One should take into account where windings will endwhen selecting the wire gauge. One should ensure that the winding does notterminate in the middle of layer.

The other issue in relation to the windings is the coupling. The windings shouldbe bifilar wound in order to maximise the coupling and minimise the leakageinductances if there are no safety considerations. In order to do this the wiresshould be twisted together. This is often carried out with multiple secondarywindings to improve the cross-regulation.

The primary and secondary windings should be interleaved if possible. Thisenhances the inter-winding coupling from primary to secondary, and also helpsin relation to cross-regulation with respect to multiple secondary windings. Fig-ure 4.22 shows the basic structure of an interleaved winding transformer that hasalso been designed to achieve good isolation between the primary and secondarywindings.


High dielectric sleeving

Mylar tape

Bobbin

Secondary

winding

Primary

winding

Primary

winding

Figure 4.22: Winding interleaving for high-dielectric isolation and good primaryto secondary coupling.

4.3.6.6 Number of Windings

Magnetic coupling issues limit the number of windings that can be practicallywound on a core. In addition the layering becomes more difficult. Finally, mostwinding bobbins only have 8 to 12 pins available for the end connections.

Practical issue 4.13 Most magnetic designs should be limited to a maximumof four to six windings.

4.3.6.7 Potting

Potting is the process of filling up a volume surrounding a magnetic structurewith a thermally conductive compound for the purpose of improving heat re-moval by providing a better thermal path. It also strengthens the structure,and prevents the incursion of environment factors that may affect the life ofthe magnetic structure. The potting can also be utilised to provide mechanicalmounting points for the structure.

There can be some problems with potting – it makes the unit heavier, theshrinkage of the potting mix as it cures can result in changes to air gaps ingapped cores, and some magnetic materials (e.g. MPP) are strain sensitive,and their permeability can change as the potting shrinks.

4.3.6.8 Safety Requirements

If one has high voltage and low voltage windings wound on the same core thenit is important from a safety perspective to ensure that the high voltages cannever get to the low voltage windings. Figure 4.23 shows a transformer designwhich satisfies requirements for isolation. There is a 2mm creep distance fromthe end of the insulation tape to ensure that the windings can never come intocontact. In addition, leads that pass through other windings must have a highvoltage insulation rating. The windings are insulated from the core material.All these requirements take up space, therefore a transformer satisfying theserequirements will be larger.


Core

Creepage distance (4mm)

Insulating tape

High voltage sleeving

Insulation layer

PrimarySecondary

Figure 4.23: A transformer design to satisfy safety requirements.

Part II

Line Commutated Convertersand High Power Inverters

Chapter 5

Introduction to High PowerConverter Technology

5.1 Introduction

This part of the course is an overview of power electronics that is focused onhigh power applications. The previous two parts of the course were primarilyconcentrating on very low power digital switching, and small to medium powerswitching primarily related to dc-dc power supplies.

The term high power is not a precise term, and the distinction betweenswitch mode power supplies and some of the circuits in the following chapters areblurred. It will be assumed that the circuits in the following chapters are used forpower levels greater than 1.5 to 2kW, with the top power levels being open ended.For example, the power electronics used in high voltage dc power transmissioncan be handling many hundreds and possible thousands of megawatts. Theother feature that distinguishes many of the circuits in the higher power areaare that they rely on natural commutation to turn off the power devices – thismeans that they cannot be explicitly turned off using a gate signal, but rely incertain external circuit conditions to cause them to turn off.

The subject material for a course on this topic is huge, and more thanenough to fill an entire course in its own right. Therefore we shall be lookingbriefly at a subset of the possible topics, concentrating on the fundamentalconverter types and operational principles. Specifically we shall look at thepower devices that are used in the high power area, since they have a largeinfluence on the circuits, topologies and applications. The next major part ison the line frequency uncontrolled and phase controlled rectifiers and inverters.Next we look at hard switched dc-ac inverter technologies. The final part willconsider the application of these devices in electric machine drive systems. Thereare many references for this work, but the primary ones used for this course are[2, 3, 11, 12].

5.1.1 Applications of Power Converter Technology

Power electronics is becoming increasingly important in the modern world. Theability to control and transform power to forms suitable for particular appli-

5-2 Introduction to High Power Converter Technology

cations is fundamental for the operation of any technological society. The in-creasing emphasis on efficiency is spawning even more activity in the PowerElectronics area, as new techniques are needed to minimise the production ofgreen house gases. The developments in the power semiconductor area are al-lowing the application of power electronics in areas that, only a few years ago,were impossible.

Examples of modern applications of power electronic converter systems are:

• Electric vehicle propulsion systems. These systems are one of the veryhigh profile applications of modern power electronics. They incorporateinnovative electrical machines coupled with inverter, computer and bat-tery/generator technologies.

• Electronic washing machines. A current example of is the Fisher-PaykellSmartdriver washing machine, which utilises a direct drive 48 pole perma-nent magnet motor driven by a computer controlled inverter. The MaytagNeptuner washing machine in the US uses an electronically controlledswitch reluctance machine.

• Photovoltaic (PV) grid interfaces. In order to convert the power producedby photovoltaics into a form suitable for domestic use or to export intothe grid, power electronic conversion is required. The application of clevercontrol techniques can optimise the amount of power that can be suppliedfor given illumination levels.

• High voltage dc transmission (HVDC) systems. These systems allow largeamounts of power to be transferred in undersea cables. For example, thepower connection between the north and south islands of New Zealanduse a HVDC link. Similarly for connections from Norway and mainlandEurope. HVDC links are also used to isolated the dynamics of large powersupply systems. For example a HVDC link is used for the NSW to Queens-land interconnection so that there is not interaction between the two dif-ferent grid systems.

• Frequency wild wind and hydro power applications. Conventional windturbines rotate at a constant speed regardless of the wind speed. In orderto extract maximum energy from the wind variable pitch blades are used.However, if the turbine is allowed to vary in speed (without the complexvariable pitch bladed) then it is possible to extract even more energy fromthe wind. By interposing an inverter system between the generator andthe grid supply, it is possible to do this, since the inverter converts thefrequency wild input into the grid frequency output. The same issuesapply to hydro turbines.

• Power system static VAR compensators. These are power electronic de-vices that are able to supply the VARs required for inductive loads onpower systems. They are commonly used to improve power factor and toaid in the stability of the power system.

• Active filters. Modern power electronic devices on the power supply gridcan generate harmonics into the grid supply. These can cause problemswith other devices connected onto the grid. An active filter is another

5.2 Review of Power Semiconductor Devices 5-3

power electronic device that is capable of canceling out the harmonicsproduced by these other devices.

• Flywheel and superconductor energy storage. These two storage tech-niques will possibly be important in future energy systems. Power Elec-tronics plays a pivotal role in the operation of these systems, as it isrequired in order to get energy into and out of the energy storage system.

• Aerospace power systems. Power electronics, because of the weight sav-ings, play an important role in the power systems for both aircraft (civilianand military) and space systems. These applications of power electronicstend to be the leading edge of the technology.

• Uninterruptible power supplies (UPS). These are power electronic systemsthat allow battery systems to be used as power backup for mains operatedsystems in critical applications.

• Load proportional modulated air conditioning systems. Instead of turn-ing air conditioning compressors on and off to maintain a desired averagetemperature, and inverter driven compressor motor provides variable con-tinuous output. The saving are due to the fact that the compressor outputdoes not match the energy input for a considerable time after the com-pressor is first started. Energy savings up to 30% are achievable using thistechnique.

• Electronic fluorescent lamp ballast. These ballasts are based purely ona high frequency inverter of some type (no magnetic components). Theyoffer energy savings over magnetic ballasts. Furthermore, external lightcompensation can also be incorporated into the design.

The above examples are only a selection of the industrial and residential ap-plications of power electronics. This technology is not always obvious to theuser, but is being incorporated into a larger variety of products. Therefore anunderstanding of at least the basics of the technology is essential for the modernelectrical engineer.

5.2 Review of Power Semiconductor Devices

At this point it is beneficial to review the current state of semiconductor devicesused for high power applications. This is required because the operation of manypower electronic circuits is intimately tied to the behaviour of various devices.

5.2.1 Diodes

Figure 5.2 shows the basic conceptual diagram for a diode. This diagram isvalid for a general purpose diode, but power diodes have a different structure inorder to improve the voltage blocking capability of the device and at the sametime keep the on-state resistance as low as possible.

The iv characteristics of conventional and power diodes are much the same,and a generic diagram is shown in Figure 5.1. Note the offset voltage of ap-proximately 1 volt. It is this voltage that leads to the majority of the power


dissipation. Also note the slope on the characteristic as the voltage across thedevice increases above 1 volt – this represents the effects of the bulk resistanceof the device. Whilst the 1 volt offset is virtually intrinsic in the operation of thediode, the bulk resistance contribution to the power losses can be minimised bychanging the doping of the semiconductor materials. The breakdown voltage,vBD, is a very important parameter in power diodes. Much of the design ofthese diodes is related to improving vBD.

» 1V

vBD

iD

vD

Figure 5.1: The current-voltage characteristic of a diode.

Figure 5.3 shows the conceptual structure of a power diode. Note that themain difference between this structure and that of Figure 5.2 is that there isa n− region interleaved between the normal p+ and n+ regions. This regionis known as the drift region, and under reverse bias is the region where thedepletion region lies.

At first the presence of the n− region in the device would seem to be alittle silly, since it must add to the bulk resistance of the device. Under certaincircumstances this is indeed true, but by careful control of the doping profilesthis effect can be minimised. This region is in the device to improve the voltageblocking capability. We shall not look at the equations that prove this, butheuristically the reason is that if one supports a voltage over a longer distance,then the volts per metre must be smaller than if the voltage is supported overa shorter distance. Therefore, when the device is in reverse bias, the depletionregion almost exists entirely in the n− region1, and consequently the electricfield in the semiconductor material is lowered because of its length.

As mentioned previously the problem with having the n− region would ap-pear to be that the bulk resistance of the diode would appear to increase. This

1The depletion region supports the reverse voltage.


p+

n+

Anode

Anode Cathode

Cathode

Figure 5.2: Conceptual structure of a conventional diode.

p+

n-

n+

Anode

Anode Cathode

Cathode

Wd

Drift Region

vD

+ -

iD

Forward biasvoltage andcurrentdirections

Figure 5.3: Conceptual structure of a power diode.


is true depending on how the diode is designed. There are two forms of structurein Figure 5.3:

a. The non-punch through diode.

b. The punch through diode.

The non-punch through diode refers to a diode where the depletion region liesnon-punch throughdiode entirely in the n− region under reverse bias. Therefore the depletion region does

not punch through the n− region. On the other hand the punch through diodehas a the n− region a little narrower and more lightly doped. This structuralchange has two effects:

a. The same length n− region can support a larger reverse voltage.

b. The bulk resistance of the device is lower than that of a non-punch throughdiode because of the shorter length n− region. This gives lower on-statelosses.

punch throughdiode We shall not concentrate on the former effect, suffice to say that his is achieved

by keeping the peak electric field intensity lower in the device [2]. The lowerbulk resistance is achieved because of a conductivity modulation effect, thisoccurring because there is injection of carriers into the n− material not onlyfrom the p+ material, but also from the n+ material during forward bias. Theseextra carriers create in the n− region lower the bulk resistance of the region inforward bias.

The other important property of diodes, and especially power diodes, isthe reverse recovery. This refers to an effect when the diode can conduct areverse recoveryreverse current for a small period of time under reverse bias, after it has beenforward biased. This effect is due to stored minority carriers that accumulatein the device under forward bias conditions. These carriers must be removedbefore the device can block voltage, and it is the removal of these carriers thatconstitutes the reverse recovery current.

Figure 5.4 shows a typical reverse recovery characteristic of a diode. Initiallythe diode is forward biased and carries a forward current (i.e. anode to cathode).However as the current goes to zero it continues to flow in the reverse directionthrough the diode as the charge is removed from the device. Eventually all theminority carriers are removed, and the current then starts to decrease as thereverse voltage rises across the device. During this phase the depletion regionsare being established. Eventually all the charge has been removed and the diodethen stops conducting and it supports the full reverse voltage. The shaded arearepresents the total stored charge removed from the device.

Remark 5.1 Charge storage and the associated reverse recovery has importantpractical consequences in power electronic circuits.

Alterations can be made to the semiconductor additives in power diodes in orderto minimise the reverse recovery time. These diodes are known as fast recoverydiodes. The recovery time of a normal diode can be 4 to 6µsecs, whereas a fastfast recoveryrecovery power diode can have a recovery time of 1 to 2µsecs. Unfortunatelyfast recovery diodes have a relatively large forward voltage drop (≈ 1.5 volt).

The other main type of diode that is used in power electronic applications isthe Schottky diode. Because this diode uses a metal-semiconductor junction as


iD

t

Qrr

Charge storage

removal

Depletion region

formation

Diode begins to

support reverse

voltage

trr

Reverse recovery time

Figure 5.4: Typical reverse recovery characteristic for a diode.


1D

2D

3D

1R

2R

3R

1C

2C

3C

Figure 5.5: Series connection of diodes to support higher voltage.

the basis for the diode it does not have a charge storage problem. Furthermore,the forward turn-on voltage of the device is much lower than a conventionaldiode – of the order of 0.2 to 0.3 volt. One is tempted to ask the question “whyaren’t Schottky diodes used everywhere in power electronics?”. The answerto this is that the Schottky diode cannot support large reverse voltages, andtherefore is only suitable for low voltage applications (up to approximately 100volt).

5.2.1.1 Series Diodes

Diodes can be put in series to achieve higher blocking voltages. However, onemust statically balance the reverse voltages, as well as dynamically balancethem.

Static balancing is required because of differing reverse bias leakage currents.Parallel resistors are used, the values of the resistors are chosen so that theircurrent dominates the leakage currents (similar to capacitor balancing).

Dynamic balancing is required in order to account for different charge storagein the diodes. This is achieved by parallel capacitors whose value is chosen sothat they dominate the stored charge. The arrangement with static and dynamicbalancing is shown in Figure 5.5.

Remark 5.2 The presence of the parallel capacitors means that the switchingtransistor may have to handle more reverse recovery current.

5.2.2 Thyristors

The thyristor, or silicon controlled rectifier (SCR) is essentially a controlledturn-on diode in terms of its external characteristics. They are the oldest of thesemiconductor power electronic switches (invented in 1957 at General Electricresearch labs), but nevertheless, because of their characteristics, they will havecontinuing application in power electronics. They also have the highest powerrating out of all the power electronic devices.

Figure 5.6 is a conceptual diagram of a thyristor’s structure and its circuitsymbol. Notice that the device is a three terminal structure, with the addition


of a gate terminal. This diagram also shows that the device is a three junctionstructure, consisting of what appears to be two diodes in series. It should benoted that this linear semiconductor diagram is not really representative of howthe device is physically laid out in silicon.

p1

n1

( )n-

p2

n2

( )n+

Anode Cathode

Gate

iA i

K

iG

J1

J2

J3

Anode CathodeGate

Figure 5.6: Conceptual diagram of a thyristor.

To understand how the device works one can develop the approximate modelfor the device shown in Figure 5.7. This diagram shows that the thyristorconsists of a feedback structure consisting of a PNP and an NPN transistor.From ones knowledge of the behaviour of the transistor one can see that if acurrent is fed into the gate (terminal G) then transistor Q2 will turn on. Thiswill result in the PNP transistor, Q1 turning on. Because the collector of Q1is connected to the base of Q2, the current from Q1 forms the base current forQ2. If the current gain around the loop of the two transistors is greater thanone then the initial turn gate current can be removed and the device will remainon.

Under blocking conditions one wants the gain around the loop consistingof the two transistors to be less than one. This corresponds to α1 + α2 beingsmall (which means that the transistor current gain product β1β2 < 1), whereα1,2 = iC1,2/iE1,2, . This is the normal state of the transistor.

The thyristor is turned on by changing the effective α’s for the two transis-tors. This is achieved by changing the depletion region across the J2 junction,which effective modulates the width of the bases of the two transistors. There-fore as a larger positive voltage is applied at the anode with respect to thecathode, the depletion region grows. Eventually the α’s will get to a pointwhere the leakage currents across the junctions are enough to supply a currentwhich will begin the regenerative process. This will cause the thyristor to turnon without any gate current. The voltage that has to be applied across thedevice to cause this to happen is known as the forward break over voltage. forward break over

voltageIf a gate current is applied it is possible to cause the device to enter thepositive feedback region prior to the forward break over voltage. The gatecurrent causes carriers to be injected across J3 and diffuse to the depletionregion at J2. Here they are swept by the electric field of the depletion region


Anode

Cathode

GateJ

3

J2

J1

iG

iK i

E2

i iA E,

1

iC 2

iB1

iB2

iC1

Q1

Q2

Figure 5.7: Transistor model of the thyristor.

into n1. The result is that the depletion region at J2 widens to account for theminority carriers injected. This is due to the fact that more donor atoms haveto be uncovered to account for the electrons injected from p2. The net resultis that the effective bases of the two transistors narrow, and consequently theα’s increase. Once these reach the critical value then the positive feedback willagain occur and the device will latch on. The main point to note is that thegate current has achieved this at a lower voltage than the break over voltage. Ifthe gate current is higher, then the lower the forward voltage can be when thedevice will latch on.

The above discussion is captured in the iv characteristic of a generic thyristorshown in Figure 5.7. There are several points to note about this characteristic.If the gate current is zero, and a forward voltage is applied, then if the voltagereaches the level of vBO the thyristor begins to conduct. This is known as thebreak-over voltage. Once the device begins to conduct, the voltage across thedevice falls to a low level dependent on where the load line crosses the forwardcharacteristic.

Similarly if the thyristor is reverse to a level of vRWM , the maximum reverseworking voltage, then the device will begin to conduct (as will a diode if reversebreakdown occurs). The vRWM voltage usually has about the same magnitudeas the vBO voltage (by design).

The most interesting aspect of the thyristor characteristic is the fact thatthe effective vBO voltage can be lowered by the application of a gate current.It is this fact that makes the thyristor behave as a switch. Once the device has“broken over” the device enters a negative resistance region prior to entering theforward on-state region. For the device to enter the forward on-state conditiona minimum current, iH , must be flowing through the device. This is knownas the holding current. If this current cannot be sustained then the device willholding currentre-enter the forward blocking state.

Remark 5.3 Thyristors are still the device of choice for very high power ap-plications. They are capable of withstanding very high voltages (of the order of6-7kV) and can conduct currents in the range of 2-3kA.


vAK

iA

iH

iBO

vH

vBO

iG

= 0

Forward on-state

vRWM

Forward blocking

state

Increasing iG

Figure 5.8: Typical characteristic of a thyristor.

Remark 5.4 Another important characteristic of the thyristor is that the gatecurrent does not have to be maintained after the current through the devicereaches the holding current. However, on the downside, the gate current cannotbe used to turn the device off. The device can only be turned off if the externalcircuit conditions allow the current in the device to fall below the holding current.

There are two external aspects of the transient performance of these devicesthat are practically very important – the turn-on and turn-off limitations.

5.2.2.1 Turn-on Transient

Figure 5.9 shows a typical turn-on transient for a thyristor. There are severalpoints that can be made about this diagram. After the gate pulse is appliedthere is a delay before the thyristor turns on (td). This is due to the time thatit takes the minority carriers to build up in the p2 material shown in Figure 5.6.After td the device starts to enter positive feedback and begins to turn on. Thecurrent in the device builds up with a slope of diA/dt, this being determined bythe voltage and the external circuit inductance. Notice that during this periodthe voltage across the device is starting to fall quite rapidly, but there is stilla substantial voltage across the device. Consequently there can be substantialpower dissipation in the device during this phase. After the rise time period hasfinished there is a further period of voltage drop across the device known as thespreading time, ts. This is the time required for the current density to becomeeven across the device cross-section.

The diA/dt time is important, since if a maximum value is exceeded thedevice can be damaged. This damage occurs because there is uneven current


iG

t

iA

vAK

t

t

di

dt

A

td

tr

ts

IA

Figure 5.9: Typical turn-on waveforms for a thyristor.


distribution in the thyristor during turn on, and if the current is increasing tooquickly hot spots may develop in the device (because there is not enough timefor the current to spread adequately over the cross-section of the device).

5.2.2.2 Turn-off Transient

To turn-off a thyristor it must be reverse biased by actions of the external circuitfor a minimum period of time. In general this minimum time is considerablylonger than the turn-on time.

Figure 5.10 shows a typical turn-off transient. The current decreases at arate of diR/dt, this rate being determined by the external circuit. As with adiode, the stored minority carriers in the four regions of device result in currentflowing in a reverse direction through it. The voltage across the device remainspositive until either the junction J1 or J3 become reverse biased. Usually J3

becomes reverse biased first, this occurring at time t2 in Figure 5.10. At thispoint the voltage across the device starts to have a reverse voltage across it.

The J3 junction cannot support a very large reverse voltage (20-30 volt) dueto the high doping levels in the n2 and p2 junctions. Therefore this junctiongoes into avalanche breakdown. However shortly after the t2 the J1 junctionstarts to become reverse biased, and at this point the current through the devicestarts to decrease.

The large reverse over-voltage is due to the effects of external inductancesin the circuit. As the current through the device becomes zero, then the reversevoltage across the device becomes the steady state reverse voltage as imposedby the external circuit.

In power diodes when the reverse recovery current reaches some nominalvalue of irr/4, then the device was said to have turned off. However, in the caseof the thyristor there is still a substantial number of minority carriers in theinterior n1 and p2 regions. If a forward voltage is then applied to the device at arate of change of dvF /dt then a forward current can again occur as these carriersrecombine and are swept through the device by the growing forward fields inthe device. This current can produce an effect similar to the reapplication of agate pulse, and the device can once again turn on.

In order to prevent the device from turning on with the application of aforward voltage the following precautions must be taken:

a. If the device has been forward biased then it must be held in reverse biasfor a minimum time of tq, a time specified by the manufacturer. This timeis at least several minority carrier line times long.

b. The rate of change of the reapplied voltage, dvF /dt, must be kept belowa certain value specified by the manufacturer.

Remark 5.5 The maximum dvF /dt for slow thyristors is of the order of 100V/µsec.For devices intended for high frequency operation the dvF /dt is of the order ofseveral thousand volts per µsec.

5.2.3 Gate Turn-off ThyristorsThe Gate Turn-off Thyristor (GTO) is essentially a thyristor that can be turnedoff by the application of a negative gate current. This makes the usage of the


t

t

t1

t3

Turn - off time tq

vAK

iA

irr

t2

vREV

dv

dt

F

di

dt

R

irr

4

trr

Figure 5.10: Typical thyristor turn-off waveforms.

GTO in dc supply situations much simpler, as compared to the thyristor.2 Thereare significant internal structure changes made to the thyristor in order to makeit behave as a GTO. We shall not consider these in detail in this course.

The GTO works essentially the same as the thyristor. Therefore we shallconcentrate on the mechanism that effects the turn-off. If one considers Fig-ure 5.7 it can be seen that:

iB2 = α1iA − i′G (5.1)

where i′G is the negative of the normal gate current. From Figure 5.7 it is clearthat by increasing i′G one can bring Q2 out of saturation.

The collector current for the Q2 transistor, iC2, is given by:

iC2 = (1− α1)iA (5.2)

2If a thyristor is used in a dc supply application it must be turned off using a forcedcommutation technique. These techniques will be considered in a later section.


using KCL at Q1.In order for the structure to turn off we need the following so that Q2 can

no longer supply the necessary current to keep the total loop gain greater thanone:

iB2 <iC2

β2(5.3)

where β2 = α2/(1 − α2). Using (5.1), (5.2) and (5.3) one can develop thatfollowing expression:

i′G >iA

βt_off(5.4)

where the parameter βt_off is the turn off gain given by:

βt_off =α2

α1 + α2 − 1(5.5)

Remark 5.6 From (5.4) one can see that the βt_off value should be as largeas possible to keep the i′G value as small as possible. This implies that α2 → 1and α1 should be small. Therefore the semiconductor regions in the GTO aredesigned to achieve this objective.

5.2.3.1 Snubbers and GTO Thyristors

Consider the circuit shown in Figure 5.11. This is a step down converter using aGTO and the switching element. There are several points that should be notedabout this diagram:

• The circuit symbol for the GTO (as compared to that of the thyristor).

• The Ls_on inductor and associated parallel resistor and diode form a turn-on snubber3 circuit.

• The Cs_off capacitor,associated resistor Rs_off, and diode Ds_off, forma turn-off snubber circuit. The Lσ inductance is an unwanted parasiticinductance.

turn-on snubberThe turn-on snubber is required to protect the GTO from the large currentsthat can flow through it because of the reverse recovery of the freewheelingdiode Dfw, which is usually a slow device at the power levels that GTOs areused at. The presence of the series inductance Ls_on limits that rate of rise ofthe current through the GTO. The resistor and diode components that are inparallel with Ls_on are to dissipate the energy stored in Ls_on when the GTOis turned off. These should be designed so that the energy in the inductor isdissipated before the next turn on of the GTO.

When the GTO is turned off the voltage across the device would go to Vdalmost instantaneously without the presence of a turn-off snubber. If the dv/dtacross the device is too large then it will turn on, as was the case for the thyristor.The purpose of the snubber is to ensure that this cannot occur, since the voltageacross Cs_off cannot change instantaneously.


+

+

iL

Dfw

Ls_on

Vd

Cd L

s

Rs_off

Ds_off

Cs_off

GTO

Rs_on

Ds_on

Turn-on snubber

Turn-off snubber

Parasitic

inductance

Load current

Figure 5.11: An example of a dc chopper circuit using a GTO thyristor


Remark 5.7 The use of a turn-off snubber with the GTO is absolutely essen- turn-off snubbertial. If the device is turned on prior to all the internal stored charge beingdissipated, then there is a very poor distribution of the turn-on current, result-ing in local heating and possible destruction of the device. This occurs becauseof the particular internal construction of the GTO. The presence of the turn-offsnubber prevents the “automatic” re-turn-on of the device when the voltage risesacross it too quickly.

5.2.3.2 GTO Turn-on

We shall briefly look at what is required to turn on a GTO. Consider Figure 5.12.The turn-on is instigated by a pulse of gate current. The diG/dt and the peak iGshould be large so that the device turns on rapidly and the current distributedevenly in the device. The gate pulse should last of the order of 10µ secondsor so to ensure that the turn-on process is complete. After this period a smallgate current should be maintained to ensure that the device does not turn offagain under low anode current conditions.4 This current is often known as the“back-porch” current.

The other point to note in Figure 5.12 is the effect of the series inductanceLs_on on the anode current during turn-on. Notice that diA/dt is limited bythis inductance so that the current is distribute evenly across the device, andthe voltage across the device is shared with the inductor during turn-on. Thisinductor also stops the otherwise large reverse recovery currents in the circuitdue to the recovery characteristic of the freewheeling diodes. The reverse re-covery actually results in the current overshoot represented by the overshootduring turn-on.

5.2.3.3 GTO Turn-off

Next we briefly consider the turn-off waveforms for the GTO. It should be notedthat the effect of the snubbers cannot be ignored for the GTO, since it is essentialthat they are used under normal operation (as mentioned in Remark 5.7).

In order to turn the GTO off then the gate current must be negative. Themagnitude of this current is approximately 1/5 to 1/3 of the anode current beingturned off. Therefore in high power applications this current can be substantialin magnitude. Fortunately the duration of the current is short.

Figure 5.13 shows the waveforms during turn-off. The negative diG/dt shouldbe kept large, but it should not be made too large or undesirable tail currentsoccur in the anode current, and there is the possibility of device destruction.Therefore the diG/dt should be kept within the specifications supplied by thedevice manufacturer. The diG/dt value can be controlled by the design of theinductance in the gate drive circuit and the negative voltage applied to turn-offthe device.

During the time interval t1, the growing negative gate current is removingcharge stored in the two regions of the device. When enough of this is removed

3A snubber circuit is an auxiliary circuit that is designed to protect the main switchingelement from excessive current or voltages.

4This unwanted turn-off condition could also damage the device due to uneven distributionof the current in the device if there is a sudden increase in anode current.


t

t

t

t

vGK

vAK

iA

iG

iGT

“Backporch” current

td

tw1

0

0

0

0

Figure 5.12: Turn on waveforms for a GTO thyristor.


t

t

t

t

vGK

vAK

iA

iG

0

0

0

0

iGT

io

t1

t2

t3

t4

ttail

dv

dt

dv

dt<

max

vGG-

Vd

Inductive spike due to parasitic in

the snubber circuit.

L

Figure 5.13: Turn-off waveforms for a GTO thyristor.


the regenerative action is stopped, and the device starts to turn-off (i.e. theanode current begins to fall). The growing difference between the anode currentand the constant load current io flows into the snubber capacitor. There is arapid rise of the voltage across the GTO due to the parasitic inductance of thesnubber circuitry (this stray inductance has to be kept to the absolute minimumto kept this voltage small). After time t2 enough carriers have been swept out ofthe device for the gate-cathode junction to regain its reverse blocking capability.

As the gate-cathode junction recovers it reverse blocking capability, the volt-age across it starts to go negative, and the negative gate current starts to de-crease. The inductance in the gate circuit tries to keep the gate current constant,and this results in avalanche breakdown of the gate-cathode junction during thetime t3 – i.e. the gate-cathode junction is operating as a zener diode. Thisbreakdown serves to remove further minority charge from the device. The t3interval should be kept below a manufacturer specified value to prevent destruc-tion of the gate-cathode junction.

After the t3 period there is a continuation of anode current flow as the finalstored charge is removed from the device. This is known as the anode tailcurrent, and flows for time ttail. During this time the voltage across the deviceis growing at the rate of:

dvAKdt

≈ ioCs

(5.6)

and contributes a lot to the turn-off losses in the device.GTO minimum onand off times Remark 5.8 A GTO should not be turned on too soon after it has been turned

off because of the potential for poor current sharing in the device due to residualcharge storage. The same applies for turn-off after turn-on.

turn-off failureunder short circuitconditions

Remark 5.9 If the anode current becomes too large there is the possibility thatthe gate current may not be able to turn the device off (there is a limit to themagnitude of the gate current, determined by the semiconductor properties ofthe device). This is a particular problem under short circuit conditions, sincethis is an abnormal condition that would not be designed for.

Remark 5.10 Over-current protection can be achieved by using a “crowbar” toblow the fuse in the circuit if the current becomes too large. This concept isshown in Figure 5.14. The SCR across the dc link is fired, resulting in a shortcircuit on the link, and consequently the fuse will blow and protect the circuit. Ifthe GTOs are used in an inverter structure then all the devices in the invertercan be fired simultaneously to carry out the same function.

It should be noted that in Figure 5.14 we have not included the turn-onsnubber. It is this snubber that gives the SCR the extra time to turn-on prior tothe GTO destroying itself.

Remark 5.11 One problem with the crowbar protection technique is that thepresence of a fuse in the dc link introduces inductance in this part of the circuit.This can result in significant over-voltages when the main GTO is turned off.

Remark 5.12 There are several variants to the classical GTO that are be-ing championed by different manufacturers. For example, Asea-Brown-Boveri


Load

Short circuit

Fuse

Crowbar SCR

Figure 5.14: GTO thyristor circuit with additional “crowbar” SCR

(ABB) has the IGCT - the Integrated Gate Commutated Thyristor. This is es-sentially a modified GTO with tightly coupled gate drive circuitry built onto acard with the GTO power device. It is a high power device – 4.5kV and 3kA. Theonboard GTO has low conduction losses and does not require a turn-off snubber.The better gating allows higher switching frequencies as compared to standardGTOs (of the order of 1000Hz). Rockwell/Allen-Bradley have a similar devicecalled the SGCT – the Symmetrical Gate Commutated Thyristor.

5.2.4 Insulated Gate Bipolar Transistors (IGBTs)One of the more recent devices that has become pervasive in the lower to mediumpower area is the IGBT – the Insulated Gate Bipolar Transistor. This deviceis essentially a specialise MOSFET – in fact the input is a MOSFET input.The main advantage of these devices is that they can be easily turned off bycontrolling the devices gate, but unlike the GTO this turn-off process does notrequire large currents.

The basic structure of the n-channel IGBT5 is shown in Figure 5.15. Onecan see that the structure of the device is nearly identical to the MOSFET,the only major difference being the presence of the p+ injection layer. It is thepresence of this layer that results in the injection of minority carriers into thedevice, and leads to the operation of the device being something like a MOSFETfed bipolar transistor. The advantages of the device are:

• The result of the injection of minority carriers in the device is that it cancarry much larger currents as compared to the MOSFET, since the currentis carried in more than the channel of the device.

• The presence of a lengthy diode junction in the device allows it to have asignificantly larger forward blocking voltage as compared to the MOSFET.

• The injection of carriers into the device means that the on-state losses forthis device are lower than those of a comparable power MOSFET.

5The layer types are all reversed for a p-channel device


Remark 5.13 One could consider the IGBT to be a “super” MOSFET. In manyIGBTs the MOSFET part of the device carries the majority (up to 90%) of thecurrent in the device (this is to help prevent a large amount of minority carrierstorage from occurring, which slows down the turn-off of the device).

SiO2

SiO2

n+

n+

p

n-

n+

p+

Source Gate

Drain

Ls

J1

J2

J1

Body

region

Drain drift

region

Buffer

layer

Injecting

layer

Parasitic

SCR

Figure 5.15: A schematic diagram of the basic structure of the IGBT.

The n+ layer between the p+ drain layer and the n− drift region is notessential for the operation of the device. As with the diode considered earlier,one can have punch-through and non-punch-through IGBTs. The n+ layer isrequired for the punch-through devices to prevent the J2 space charge regionfrom going all the way to the p+ drain region. The presence of the n+ layer cansignificantly improve the operation of the IGBT.

Remark 5.14 In Figure 5.15 there is a parasitic SCR shown. This is an unde-sirable feature of the structure, and design efforts must be made to ensure thatthe loop gain of the SCR is not greater than one so it does not turn on.

The circuit symbol for the IGBT appears in Figure 5.16(c) and (d). Note thatthe symbol in (c) is very nearly the same as that for the n-channel MOSFET,except that there is an arrow on the drain connection indicating the direction ofthe current due to the injection of carriers here. Figure 5.16(d) shows a symbolthat is emphasising the similarity of IGBT with the NPN bipolar transistor.

5.2.4.1 IGBT Operation

We shall briefly consider the salient points of IGBT operation. The followingdiscussion is with reference to Figure 5.17.


vDS

iD

vRM

vDS

brk

Increasing vGS

» 0 7. V

vGSv

GS th

iD

Drain

Source

Gate

Drain

Source

Gate

(a)

(b)(c) (d)

Figure 5.16: The IGBT voltage and current transfer characteristics and circuitsymbol: (a) output characteristic; (b) transfer characteristic; (c) and (d) n-channel IGBT circuit symbols.


Figure 5.17(a) shows the current flows in the device when it is turned on.When the gate voltage exceeds the threshold voltage an inversion layer formsbeneath the gate of the IGBT. This channel shorts the n+ to the n− layer, asoccurs in the MOSFET. The current flow through this channel also results inholes being injected from the p+ region into the n− region. These holes moveacross the n− drift region via drift and diffusion via a number of paths. Thesecarriers reach the p body region (not necessarily where the channel is) and thenare swept through to the source via recombination at the source metallisation.

The junction of the n− region and the p region is called the collector region,since is operates the same as the collector region in a thick PNP transistor.The connection between the layers and parasitic transistors is shown in Fig-ure 5.17(b). Notice that the injection layer, denoted as the p+ layer, acts as anemitter in a BJT transistor, emitting or injecting holes into the n− base regionof the device.

As current flow through the IGBT there are voltage drops in the device dueto the bulk resistance of the semiconductor materials used. These are shown inFigure 5.17 as dashed resistors. These resistance values are important for twodifferent reasons; (i) if the resistances are too high then the device will dissipatemore power; and (ii) if the voltage drops are too high in the resistances thenparasitic thyristor in the IGBT may turn on.

Figure 5.18(a) and (b) shown an equivalent circuit for the IGBT. Figure 5.18(b)is more complete, showing the parasitic thyristor, and the body spreading re-sistance. If the body spreading resistance is too high then the current gain ofthe thyristor may become greater than one, and consequently the thyristor willturn on. Once this happens then the device no longer behaves as an IGBT, andpower must be remove across the device to turn it off. Needless to say, muchdesign effort has gone into ensuring that the parasitic IGBT does not turn on.

5.2.4.2 IGBT Turn-on

Typical turn-on waveforms for the IGBT are shown in Figure 5.19. Thesewaveforms are very similar to those for a power MOSFET.6

We are assuming that the voltage to the input of the IGBT circuit is thevoltage waveform vGG. The voltage across the gate-source of the IGBT is vGS .Note from Figure 5.19 that this voltage is essentially an exponential, due to theinput capacitance of the IGBT, coupled with the gate resistor (which is to limitthe current flowing into the gate of the IGBT to safe levels). The time periodtd(on) is the time required for vGS to reach a voltage where the device starts toturn on. From this point the current through the device rises as it starts to turnon harder. Eventually vDS is of the order of vGS and the current stabilises at avalue determined by the external circuit.

As vDS starts to fall a significant amount of current starts to flow through theCgd capacitance. This is due to the fact that there is a changing voltage acrossthe capacitor, and that the value of the capacitance increases considerably asthe space charge region width decreases (effectively decreasing the plate sepa-ration in a parallel plate capacitor) and the stored charge in the device starts

6Note that the waveforms for turn-on and turn-off are for the IGBT in a step down choppercircuit of the type shown in Figure 5.11, except that the main power device has been replacedby the IGBT and there are no snubbers.


to increase. Consequently the rise of vGS flattens out as this capacitance ischarged, this being the result of the extra current being drawn through the gateresistor. Eventually vGS restarts its exponential rise again when vDS ≈ vGS ,stopping when its value reaches vGG.

The vDS waveform during the tfv2 time in Figure 5.19 is usually observedin IGBTs. It is due to two effects – the above-mentioned increase in Cgd asvDS falls (which also occurs in power MOSFETs), and the slower turn-on of thePNP section the IGBT (as compared to the MOSFET portion), which delaysthe associated conductivity modulation due to the injected carriers.

5.2.4.3 IGBT Turn-off

The waveforms for the turn-off of the IGBT are shown in Figure 5.20. The risein the voltage vDS before iD drops is typical of all step down converter circuits.This occurs because the load is considered to be effectively a current source, andtherefore it continues to supply current into the switch device until the voltageon the switch side of the load reaches the supply. At this point the diode acrossthe load will start to turn on and take the load current.

The initial part of the vGS turn-off transient, td(off), occurs because of thetime constant associated with the RG(Cgd2+Cgs) time constant of the MOSFETpart of the IGBT.7 As the drain-source voltage vDS starts to rise, the Millereffect of Cgd2 starts to take effect. This temporary arrests the decrease of vGSduring the interval trv. When vDS stabilises then this effect stops. The decreaseof vGS now continues, but with a time constant of RG(Cgd1 + Cgs), which issmaller than previously due to the change on the value of Cgd caused by thewidening of the space charge region in the device. During all the phase so-farthe IGBT is behaving as a MOSFET.

The major difference between the IGBT turn-off and the power MOSFETturn-off is observed in the drain current waveform which has two distinct timeintervals. During the tfi1 time the MOSFET is turning off. The second timeinterval tfi2 is due to the stored charge in the n− region of the device. Sincethe MOSFET is off there is no way that these carriers can be swept out ofthe device by a negative drain current. Consequently these carriers diminishby recombination. The punch-through IGBT attempts to minimise this effectby having a small carrier lifetime in the n+ region. This results in an electronconcentration gradient from the n− region to the n+ region, thereby sweepingthe electrons from the device.8 The non-punch-through IGBT attempts to min-imise the tail off current by redesigning the IGBT so that the majority of thecurrent is carried by the MOSFET. This minimises the stored charge.

At the time of writing these notes IGBTs are in a rapid state of development.Currently the most advanced devices are capable of withstanding approximately6kV, and can conduct several thousand amperes. The turn-off times for thesedevices are of the order of 1µsec of less. For medium power systems IGBTs arecurrently the device of choice.

7RG is the gate resistor that is included in the circuit to limit the gate currents to reasonablelevels.

8It is desirable to have long carrier life times in the n− region so that the bulk resistanceis kept low in this region when the device is on.


5.2.5 Other Devices and Developments

Thus far we have concentrated on the devices that are the most important onesin terms of current practice. However there is also significant work going on intonew devices that still have not reached the commercial stage. We shall brieflymention some of these.

5.2.5.1 Power Junction Field Effect Transistors

This device is also sometimes known as the static induction transistor (SIT). Itis effectively a JFET transistor with geometry changes to allow the device towithstand high voltages and conduct high currents. The current capability isachieved by paralleling up thousands of basic JFET cells. The main problemwith the power JFET is that it is a normally on device. This is not good froma start-up viewpoint, since the device can conduct until the control circuitrybegins to operate. Some devices are commercially available, but they have notfound widespread usage.

5.2.5.2 Field Controlled Thyristor

This device is essentially a modification of the SIT. The drain of the SIT ismodified by changing it into an injecting contact. This is achieved by making ita pn junction. The drain of the device now becomes the anode, and the sourceof the SIT becomes the cathode. In operation the device is very similar to theJFET, the main difference being quantitative – the FCT can carry much largercurrents for the same on-state voltage. The injection of the minority carriersin the device means that there is conductivity modulation and lower on-stateresistance. The device also blocks for reverse voltages due to the presence ofthe pn junction.

5.2.5.3 MOS-Controlled Thyristors

The MOS-controlled thyristor (MCT) is a relatively new device which is avail-able commercially. Unfortunately, despite a lot of hype at the time of its intro-duction, it has not achieved its potential. This has been largely due to fabrica-tion problems with the device, which has resulted on low yields. Figure 5.21 isan equivalent circuit of the device, and its circuit symbol.

From Figure 5.21 one can see that the device is turned on by the ON-FET,and turned off by the OFF-FET. The main current carrying element of thedevice is the thyristor. To turn the device on a negative voltage relative to thecathode of the device is applied to the gate of the ON-FET. As a result this FETturns on, supplying current to the base of the bottom transistor of the SCR.Consequently the SCR turns on. To turn off the device, a positive voltage isapplied to the gate. This causes the ON-FET to turn off, and the OFF-FET toturn on. The result is that the base-emitter junction of the top transistor of theSCR is shorted, and because vBE drops to zero. volt it turns off. Consequentlythe regeneration process that causes the SCR latching is interrupted and thedevice turns off.


The P-MCT is given this name because the cathode is connected to P typematerial. One can also construct an N-MCT, where the cathode is connectedto N type material.

5.2.5.4 New Semiconductor Materials

Silicon is presently the only material that is widely used for the fabrication ofthe power semiconductors (and integrated circuits for that matter). The reasonfor this is the ease with which large and very pure crystals can be grown withSilicon. However, there are other materials that have superior properties ascompared to Silicon, especially in high power/high voltage applications.

Gallium Arsenide (GaAs) is a well used material, especially in high frequencyapplications, where its very high carrier mobility allows higher frequency devicesto be constructed. In addition it has a higher band-gap than Silicon, whichmeans that it can support higher voltages than Silicon, and can be operated athigher temperatures (460C and compared to 300C for Si).

Silicon Carbide is a material which is currently attracting a lot of research.It has a significantly larger band-gap than Si (2.9eV as compared to 1.12ev forSi), has excellent thermal conductivity (approximately 3 times that of Si), andcan operate at temperatures of 600C, with a maximum operating temperatureof 1240C. The breakdown electric field strength is approximately 10 times thatof Si, meaning that it can withstand significantly higher voltages. SiC devicesare probably on 3 to 5 years from commercialisation.

Diamond is the ideal material for power semiconductors. It can operate atvery high temperatures (similar to SiC), it can withstand fields approximately100 times larger than Si, it has thermal conductivity 5 times larger than SiC (andtherefore 15 times larger than Si), and it has electron mobility approximatelytwice that of Si. Unfortunately there is much research to be done before we seecommercial diamond based power electronic devices (15-30 years).

One can see that there are many exciting developments occurring in the areaof power electronic devices. These new devices then open up new applications,that previously were not feasible.


SiO2

SiO2

n+ n+

p

n-

n+

p+

Source Gate

Drain

+++++ + + +

--

Channel

Lateral bodyspreadingresistance

i

i

Minoritycarrierinjection

SiO2

SiO2

n+ n+

p

n-

n+

p+

Source Gate

Drain

i

i

Minoritycarrierinjection

(b)

Collectorregion

Drift regionresistance

(a)

Figure 5.17: Current flows in the IGBT.


Drain

Source

Gate

Drift region

resistanceDrain

Source

Gate

Drift region

resistance

Body region

spreading

resistance

(a) (b)

Figure 5.18: Equivalent circuits for the IGBT: (a) approximate equivalent circuitfor normal operating conditions; (b) more complete equivalent circuit showingthe parasitic thyristor.


t

v vGS GG

/

0

Vd

vDS

iD

Io

vDS(on)

Rg

vDS

vGS

vGG

vGG

td(on)

tri

t

t

Cgd

C gsDefinitions

tfv1

tfv2

vGS

Figure 5.19: Typical turn-on waveforms for an IGBT.


t

v vGS GG

/

0

Vd

vDS

iD

Io

vGG

t

t

vGS

vGG

vGS Io,

vGS(th)

td(off)

trvt

fi1

tfi2

MOSFET

current

BJTcurrent

0

0

Figure 5.20: Turn-off waveforms for an IGBT.

Anode

Cathode

A

K

Gate

G

OFF-FET

ON-FET

Figure 5.21: Schematic and circuit symbol for the P-MCT.

Chapter 6

Line Frequency UncontrolledRectifiers

6.1 Introduction

The power input into most power electronic devices is derived from 50/60Hz acsine wave supplies provided by the electricity authorities. This supply generallyis converted into a dc supply before being used or converted into another form.The traditional and simplest way of achieving the ac–dc conversion is via anuncontrolled rectifier based on diodes. Such rectifiers only allow power to flowfrom the ac to the dc side. The vast majority of power electronic applicationscurrently use such rectifiers to do the ac–dc conversion, although this situa-tion may change in the future due to mains harmonic requirements (which aredifficult to meet using conventional rectifiers).

This chapter shall look at the basic operation single phase and three phaseuncontrolled rectifiers. Some analysis will be carried out (based on the as-sumption of ideal diodes) to ascertain the harmonic performance of the variousrectifiers. Before doing this there is some concepts that we will need to intro-duce.

6.2 Some Mathematical Preliminaries

One of the characteristics of diode rectifier circuits is that the produce non-sinusoidal currents in the ac mains. Therefore consideration of non-sinusoidalwaveforms is relevant to carrying out analysis of these types of circuits. Muchof the analysis is carried out assuming that the circuits are in steady state,and then calculating the Fourier components in the current (and in some casesthe voltage) waveforms. We shall therefore quickly review Fourier analysis asapplicable to power electronic waveforms.

6-2 Line Frequency Uncontrolled Rectifiers

6.2.1 Fourier Analysis of Repetitive WaveformsIn general, a non-sinusoidal waveform, f(t), which repeats with an angularfrequency of ω, can be expressed as [13]:

f(t) = F0 +

∞∑n=1

fn(t) =1

2a0 +

∞∑n=1

an cos(nωt) + bn sin(nωt) (6.1)

where F0 = 12a0 corresponds to the average value of the waveform (or the dc

component), and the coefficients in (6.1) are:

an =1

π

∫ 2π

0

f(t) cos(nωt) d(ωt) (6.2)

bn =1

π

∫ 2π

0

f(t) sin(nωt) d(ωt) (6.3)

Note that the F0 term is calculated if the harmonic number starts from 0 insteadof 1 – i.e.:

F0 =1

2a0 =

1

2π

∫ 2π

0

f(t)d(ωt) =1

T

∫ T

0

f(t)dt (6.4)

which is the average value of f(t) as noted previously.Each component of the waveform can therefore be written as:

fn(t) = an cos(nωt) + bn sin(nωt) (6.5)which can be simplified using the following trigonometric identity:

A cos θ +B sin θ =√A2 +B2 cos(θ ± φ) (6.6)

where tanφ = ∓BA . Since via (6.6) equation (6.5) can be written as a cosfunction, then we can eliminate the frequency component of the waveform andwrite the expression as a phasor:

−→F n = Fne

jφn (6.7)

where:

Fn =

√a2n + b2n√

2(6.8)

tanφn =(−bn)

an(6.9)

In many situations in power electronics the waveforms do not have a dc compo-nent. This coupled with the symmetry that is present can considerably simplifythe generation of the Fourier coefficients. These are shown in Table 6.1 forseveral of the common symmetries.

If the definition of the rms value1 of a waveform f(t) is applied to the functionwhen expressed in terms of its Fourier components, it can be easily shown thatthe rms amplitude is:

F =

√√√√F 20 +

∞∑n=1

F 2n (6.10)

1Definition of the rms value of a quantity is xrms =√

1T

∫ T0 x(t)2 dt.

6.2 Some Mathematical Preliminaries 6-3

Symmetry Condition Required Fourier CoefficientsEven f(−t) = f(t) an = 2

π

∫ π0f(t) cos(nωt) d(ωt) bn = 0

Odd f(−t) = −f(t) an = 0 bn = 2π

∫ π0f(t) sin(nωt) d(ωt)

Half-wave f(t) = −f(t+ 12T ) an = bn = 0 for even n

an = 2π

∫ π0f(t) cos(nωt) d(ωt) for odd n

bn = 2π

∫ π0f(t) sin(nωt) d(ωt) for odd n

Even quarter-wave Even and half-wave an =

4π

∫ π/20

f(t) cos(nωt) d(ωt) for odd n0 for even n

bn = 0 for all nOdd quarter-wave Odd and half-wave an = 0 for all n

bn =

4π

∫ π/20

f(t) sin(nωt) d(ωt) for odd n0 for even n

Table 6.1: Fourier coefficient formulae with symmetry.

6.2.1.1 Measures of Waveform Distortion

Consider Figure 6.1 which shows the voltage and current waveforms in a situ-ation where a power electronic device is connected to the grid supply [2]. Thecurrent waveform shows significant distortion.2 The voltage on the other handis shown without distortion, since it usually does not display the same amountof distortion as the current. This is the case because the voltage distortion arisesfrom the current causing a voltage drop across the line impedances.3

wt

v i,

vs

is

is1

idis

f1

0

Figure 6.1: Line current waveform distortion.

Let us assume that the supply voltage can be represented as:

vs(t) =√

2Vs sinω1t (6.11)

2The distortion in this current waveform is typical of that one would expect from a dioderectifier connected to the grid.

3The undistorted voltage assumption makes the analysis simpler in this section.


The input current is represented by its Fourier components:

is(t) = is1(t) +

∞∑n 6=1

isn(t) (6.12)

where:

is1 , the fundamental line current

isn , the harmonic components of the line current

We can write (6.12) in an expanded form as follows:

is(t) =√

2Is1 sin(ω1t− φ1) +

∞∑n 6=1

√2Isn sin(ωnt− φn) (6.13)

where:

φ1 , the phase angle of the fundamental (6.14)ωn = nω1 (6.15)ωnt = nω1t = nθ1 (6.16)

∴ φn = nφ1 (6.17)

Is, Isn , rms value of the relevant harmonic (6.18)

The rms value of the current can be calculated using the general expressionnoted in footnote 1. If expression (6.12) is substituted into this, the cross-product terms all integrate to zero due to the orthogonality property of cos andsin functions. The rms current therefore becomes:

Is =

√√√√I2s1 +

∞∑n 6=1

I2sn (6.19)

The total distortion of waveforms in general is usually measured by a parametercalled the total harmonic distortion, which is abbreviated as the THD.total harmonic dis-

tortion The distorted component of the current is essentially all the componentsof the current except the fundamental component. Therefore using the timedomain expressions for the currents we can write the distortion component as:

idis(t) = is(t)− is1(t) =

∞∑n6=1

isn(t) (6.20)

This current is shown schematically in Figure 6.1.Therefore, using (6.19), the rms value of the distortion section of the current

can be written as:

Idis =√I2s − I2

s1 =

√√√√ ∞∑n 6=1

I2sn (6.21)


The THD of the current defined as:

%THD = 100× IdisIs1

(6.22)

= 100×√I2s − I2

s1

Is1(6.23)

= 100×

√√√√ ∞∑n 6=1

(IsnIs1

)2

(6.24)

6.2.1.2 Power and Power Factor

Clearly the purpose of a power electronic system is to convert electrical energyin different ways to allow energy (or power) to be effectively and efficiently used.Therefore it is relevant to briefly review the concept of power, and then to lookat a generalisation of the concept of power factor to systems with non-sinusoidalwaveforms.

Let us begin with single phase power expressions. Consider the followingtime domain expressions for current and voltage flowing into some arbitrarynetwork:

v = V cosωt (6.25)i = I cos(ωt+ θ) (6.26)

Using the definition of instantaneous power we can write:

P = vi (6.27)= [V cosωt][I cos(ωt+ θ)] (6.28)= V I cosωt[cosωt cos θ − sinωt sin θ] (6.29)

= V I cos2 ωt cos θ − V I cosωt sinωt sin θ (6.30)

Using cos2 ωt =1

2[1 + cos 2ωt] one can write (6.31)

P =V I cos θ

2[1 + cos 2ωt]− V I sin θ cosωt sinωt (6.32)

Using the trig relation:

cosωt sinωt =1

2sin 2ωt

we can modify the last term of (6.32) as follows:

P =V I cos θ

2[1 + cos 2ωt]− V I

2sin 2ωt sin θ (6.33)

=V I

2cos θ +

V I

2cos θ cos 2ωt− V I

2sin θ sin 2ωt (6.34)

Using cos(x+ y) = cosx cos y − sinx sin y, this can be written as

P =V I cos θ

2︸︷︷︸Average Real power

+V I

2cos(2ωt+ θ)︸︷︷︸

Oscillatory component

(6.35)


The oscillatory power component represents the power flowing into and out ofthe storage element of the particular circuit.4 The average real power componentessentially causes an offset in this oscillation component so that there is anaverage value of power over a complete cycle.

The other way of representing the power expression for sinusoidal steadystate systems is in the form of the complex power:complex power

−→S =

−→V−→I ∗ (6.36)

where ‘∗’ represents the complex conjugate, and the −→x means that x is a phasor.Let us assume that:

−→V = Vrmse

jα (6.37)−→I = Irmse

jβ (6.38)

where Irms and Vrms represent the current and voltage RMS values.Substituting (6.38) and (6.37) into (6.36) we can write:

−→S = VrmsIrms cos θ + jVrmsIrms sin θ (6.39)

where θ = α− β.5Equation (6.39) is broken up into two components:

P = VrmsIrms cos θ (6.40)Q = VrmsIrms sin θ (6.41)

One can see the vector relationship of these components in Figure 6.2. Noticethat the use of the complex conjugate in the complex power expression meansthat the angle used is effectively the angle of the voltage phasor with respect tothe current, despite the fact that the convention is that the currents phase ismeasured relative to the voltage.6

r

V

r

I

Real

Imag

α

β

θ

I cosθ

I sin θ

Q VI= sin θ

P VI= cosθ

Figure 6.2: Phasor relationship for complex power.4As we shall see later this component consists of two different parts, one belonging to the

real power and the other to the imaginary power.5The angle θ is the angle from the current vector to the voltage vector.6It is possible to define complex power as

−→S =

−→I−→V ∗. In this case the angle is the current

with respect to the voltage in the power expression. The meaning of the sign of the complexpower changes with this definition.


The correspondence between (D.8) and the average real power componentof (6.35) is easy to see. However, the correspondence between (D.9) and theoscillatory power part of (6.35) is not immediately obvious. Clearly Q is relatedthe component of the voltage that is orthogonal (in a temporal sense) to thecurrent, multiplied by that current. This correspondence is more easily seenfrom (6.34):

P =V I cos θ

2+V I cos θ

2cos 2ωt︸︷︷︸

Real power component

− V I sin θ

2sin 2ωt︸︷︷︸

Reactive power component

(6.42)

where V and I are the peak values of the voltage and current.We can see from this expression that the real power actually oscillates (with

the oscillation being unipolar), and has an average value of (V I/2) cos θ. Thereactive power component on the other hand does not have an offset term and itsaverage value is zero. The amplitude of this term is equal to the Q term in thecomplex power expression. Therefore the reactive power component correspondsto power that is flowing into the circuit and out again per half cycle of thefundamental voltage (or current). These components are shown in Figure 6.3for a phase angle of 30. This plot is of the normalised power, the normalisationfactor being VrmsIrms. Notice the reactive power component has no average dccomponent.

0 1 2 3 4 5 6 7-0.5

0

0.5

1

1.5

2

q [rad]

Nor

mal

ised

pow

er

Total power

Real power

Reactive power

Average power

Figure 6.3: Diagram of the normalised single phase power components with a30 phase angle – the power is normalised by dividing by VrmsIrms.

Remark 6.1 The presence of reactive power is generally undesirable because itcontributes to the current in the circuit (and therefore the size of the conductorsrequired) without carrying any average power to the load.


Remark 6.2 With an inductive load the current lags the voltage (or the voltageleads the current). Therefore in the complex power expression the angle θ ispositive, and consequently Q is positive. Therefore an inductive load absorbsreactive power, which is given the units of VARs (Volt Ampere Reactive). Thisis called absorbing lagging VARs.

Conversely, a capacitive load results in the current leading the voltage (orthe voltage lags the current). Therefore in this case the θ angle is negative, andtherefore a capacitive load draws negative VARs from the supply (called leadingVARs). It can also be said that the capacitor supplies positive VARs to thesupply.

Let us now briefly consider the concept of three phase real and reactive power.three phase real andreactive power We shall assume that the phase currents and voltages in a star connected system

are:7va = V cosωtvb = V cos(ωt+ 2π

3 )vc = V cos(ωt− 2π

3 )ia = I cos(ωt+ θ)ib = I cos(ωt+ 2π

3 + θ)ic = I cos(ωt− 2π

3 + θ)

(6.43)

These voltages and currents can be multiplied together to give the three phasepower expression:

P = vaia + vbib + vcic

=3V I cos θ

2+V I cos θ

2(cos 2ωt+ cos(2ωt− 2π

3) + cos(2ωt+

2π

3))

− V I sin θ

2(sin 2ωt+ sin(2ωt− 2π

3) + sin(2ωt+

2π

3)) (6.44)

Terms two and three in (D.12) are zero because the cosine and sine terms eachadd to be zero. Therefore the power expression becomes:

P =3V I cos θ

2(6.45)

which is simply three times the average power in (D.10) (as one would expect).

Remark 6.3 The interesting aspect about the three phase real power is that it isconstant – i.e. the total real power flowing into a three phase system is constantdespite the fact that the individual powers in the phase are oscillating.

Let us consider the last part of (D.12). Rewriting this term one can see that:

− V I sin θ

2sin 2ωt =

V I sin θ

2

[sin(2ωt− 2π

3) + sin(2ωt+

2π

3)

](6.46)

which means that the reactive power in one phase is being absorbed by twoother phases. Therefore the reactive power is cycling around between the threephases, and hence is not seen on the external three phase power (although thereis obviously still the single phase reactive power there in each of the individual

7The star connection means that there are no zero sequence currents flowing.


phases). The reactive power of three phase systems is considered to be thereactive power of an individual phase, whereas the real power of a three phasesystem is three times the real power of an individual phase.

Now that we have consider the concepts of real and reactive power for singleand three phase systems, let use now revise the concept of power factor forsinusoidal systems. We know from (D.8) that the real power is: power factor

P = VrmsIrms cos θ (6.47)

where θ is the angle from the current to the voltage phasor. If the current andthe voltage were in phase then the power is obviously VrmsIrms. This is themaximum possible power. It is also known as the apparent power in a systemwhere there is a phase difference between the voltage and the current. Thepower factor is a measure of how close the actual real power is to the apparentpower – i.e.:

PF = cos θ =P

VrmsIrms(6.48)

The next step is to generalise the power factor expression to the case where thecurrent is not sinusoidal. We begin with the basic definition of average power: generalised power

factor

P =1

T1

∫ T1

0

p(t) dt =1

T1

∫ T1

0

vs(t)is(t) dt (6.49)

where T1 is the period of the fundamental waveform.

Remark 6.4 Mathematical preliminary: Using cos θ cosnθ = 12 cos(θ + nθ) +

12 cos(θ − nθ), where n = 2,3,. . ., one can write:∫ 2π

0

cos(θ) cos(nθ) dθ =

∫ 2π

0

1

2[cos((n+ 1)θ) + cos((1− n)θ)] dθ (6.50)

=1

2

[∫ 2π

o

cos(n+ 1)θ dθ +

∫ 2π

0

cos(1− n)θ dθ

](6.51)

=1

2

[sin(n+ 1)θ

n+ 1

]2π

0

+

[sin(1− n)θ

1− n

]2π

0

(6.52)

=1

2

sin(n+ 1)2π

n+ 1− sin0

n+ 1+

sin(1− n)2π

1− n− sin 0

1− n

(6.53)

= 0 (6.54)

Note that if n = 1, then (6.50) becomes:∫ 2π

0

cos(θ) cos(θ) dθ =

∫ 2π

0

cos2 θ (6.55)

=

∫ 2π

0

1

2[cos 2θ + cos 0] dθ (6.56)

=1

2

[sin 2θ

2

]2π

0

+ [θ]2π0

(6.57)

= 2π (6.58)


Remark 6.5 Remark 6.4 above shows that the product terms involving differentfrequencies integrate over the fundamental frequency to zero, whereas terms atthe same frequency integrate to give a non-zero term.

Substituting in (6.11) for vs and (6.13) for is, and noting from Remark 6.4 thatthe the integral of the cross-product terms are zero, we can write:

P =1

T1

∫ T1

0

√2Vs sinω1t ·

√2Is1 sin(ω1t− φ1)dt = VsIs1 cosφ1 (6.59)

Remark 6.6 Equation (6.59) shows that the harmonic currents DO NOT con-tribute to the average (real) power drawn from the source. Therefore, one canconsider that the harmonics contribute to the reactive power drawn from thesource. This is the basis for the generalisation of the concept of power factor.

Note 6.1 The remark immediately above is true if the voltage on the supplyremains purely sinusoidal. However, the presence of the harmonics can alsocause the introduction of harmonic voltages because of the voltage drop acrossthe transmission line impedances. Usually these impedances are reactive (induc-tive), and consequently the induced voltage across then is 90 out of phase withthe current. Therefore the harmonic voltage appearing across the load is zero.Therefore, even under this condition the harmonic power is zero. However, ifthere is substantial resistance in the line, then there can be a harmonic voltageacross the load that is approximately in-phase with the harmonic current. Underthis condition the harmonic real power to the load is no longer zero.

We can generalise the power factor expression by realising that the apparentpower is simply:

S = VsIs (6.60)

where Vs and Is are the true rms values of the voltage and the current (i.e. therms value of a non-sinusoidal current). Therefore, using the same approach asthat for sinusoidal quantities we can write:

PF =P

S(6.61)

Therefore, substituting in the definitions into this expression we can write:

PF =VsIs1 cosφ1

VsIs=Is1Is

cosφ1 (6.62)

Remark 6.7 From (6.62) one can see that with a non-sinusoidal current sourcethat the sinusoidal power factor is modified by the term Is1/Is – i.e. the fun-damental current rms value divided by the total current rms value. Therefore,as the harmonics increase, the rms value of the current will increase, but thefundamental will not. Therefore the power factor will decrease.

The normal power factor expression is given a new name in this context – it iscalled the displacement power factor (DPF):

DPF = cosφ1 (6.63)

6.3 The Half Wave Rectifier Circuit 6-11

Therefore the power factor with the non-sinusoidal current is:

PF =Is1Is

DPF (6.64)

Using (6.24) it is possible to write the power in terms of the total harmonicdistortion:

PF =1√

1 + THD2i

DPF (6.65)

6.3 The Half Wave Rectifier CircuitWe shall start our study of uncontrolled rectifiers by looking at the simplestpossible rectifier circuit – a single diode rectifier.

6.3.1 Pure Resistive LoadThe simplest possible load for the simplest possible rectifier is a pure resistiveload. The circuit and input and output current and voltages and shown inFigure 6.4. The operation of this circuit is very straight forward and does notwarrant much further discussion. In addition, this circuit is not generally usedbecause of the very high ripple in the output voltage and current. Because theoutput load is a pure resistance there is not output filter, and consequently theoutput voltage is not a very good dc voltage at all.

R

+ -

vdiode

i

vd

+

-

vs

t

v vs d,

i

i vd

, v vs,

diode

vdiode

Figure 6.4: Half wave rectifier with a resistive load.

6.3.2 Inductive LoadThe case of a half wave rectifier with a inductive-resistive load is more interestingthan the previous case. With inductance in the load the current is more filtered


than the previous case. The following discussion is with reference to the circuitshown in Figure 6.5. The output plots have been generated by putting thecircuit of Figure 6.6, with L = 200mH and R = 50Ω, into the Saberr, andrunning the simulation.

+ -vL

vdiode

vout

+

-

+

-

vs

+ - iL

L

R

Figure 6.5: Half wave rectifier with an LR load.

The first point that one notices in Figure 6.6 is that the current continues toflow even when the source voltage has gone negative. When the energy storedin the inductor reaches zero then the current stops flowing. If the resistor valueis made smaller then the current will flow further into the negative half cycle.If the resistance was zero then the current would continue to flow for the wholeof the negative half cycle.

Let us analyse the situation in Figure 6.6. At t = 0 then the diode becomesforward biased and current begins to flow. Assuming an ideal diode then thecircuit whilst the current is flowing is:

vs = Ri+ Ldi

dt(6.66)

At time t1 the current through the inductor reaches its peak value, since fromt = 0 to t1, vL = vs−vout is positive. Notice that after t1 vL becomes negative asthe source voltage decreases, and hence the current through the inductor startsto decrease. At time t2 vs becomes negative. However, the current throughthe inductor continues in the same direction due to the stored energy in theinductor. Eventually at t3 the energy in the inductor is exhausted and thecurrent drops to zero.

Because the current is zero at t = 0 and t3, we can use the inductor currentequation to write:

∆i = i(t3)− i(0) =1

L

∫ t3

0

vL dt = 0 (6.67)

since i(0) = i(t3). This means that the total area under the voltage curve acrossthe inductor is zero (which it must be for the circuit to be in steady state). Theintegral in (6.67) can be written as follows:∫ t1

0

vL dt+

∫ t3

t1

vL dt = 0 (6.68)

6.3 The Half Wave Rectifier Circuit 6-13

(V)

-60.0

-40.0

-20.0

0.0

20.0

40.0

60.0

t(s)0.0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

(A)

-0.2

0.0

0.2

0.4

0.6

0.8

t1 t

2t3

iL

vs v

out vL

vdiode

Due to simulation numerics

Area A

Area B

Figure 6.6: Plots for a half wave rectifier with an LR load – L = 200mH andR = 50Ω.

which means that:Area A−Area B = 0 (6.69)

Remark 6.8 To get the exact times for t1, t2 and t3 one needs to solve (6.66).

6.3.3 Inductive Load with Back EMF

Another case of interest is the inductor feeding a back emf scenario. This isshown schematically in Figure 6.7. The voltage source Ed could represent alarge capacitor, for example. The result of the presence of this voltage source isthat the turn-on time for the diode is change as compared to the previous case.

One can see the difference in the performance of the circuit from the Saberrsimulation plots shown in Figure 6.8.

One can see from Figure 6.8 that the inductor current iL has much thesame shape as that shown in the Figure 6.6, but the magnitude of the currentin smaller. This is an obvious result, since the voltage that can increase thecurrent through the inductor is much smaller in this case because of the Edvoltage. In addition the time for the current to build up is also smaller. Theother notable difference between this case in that of Figure 6.6 is that the diodereverse voltage is substantially larger in this case.


+ -vL

vdiode

+

-

vs

+ - iL

L

+

-E

d

Figure 6.7: Half wave rectifier circuit with an inductor and back emf.

(V)

-60.0

-40.0

-20.0

0.0

20.0

40.0

60.0

t(s)0.0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

(A)

-0.2

0.0

0.2

(V)

-100.0

-80.0

-60.0

-40.0

-20.0

0.0

20.0v

diode

vs

vL

EdArea A Area B

t1

t2

t3

iL

Figure 6.8: Plots for a half wave rectifier with an inductor and back emf as aload.

6.4 The Concept of Current Commutation 6-15

6.4 The Concept of Current CommutationBefore looking at a practical single phase rectifier circuit we shall briefly lookat the concept of current commutation in power electronic circuits. Althoughwe shall be looking at this in terms of naturally (or self) commutated circuits,the same principles also apply to force commutated circuits.

Up until this point we have not had to consider commutation issues becausewe have been dealing with a single diode circuit. Current commutation refersto the transfer of the current in a circuit from one power electronic device toanother, as one device starts to turn off and the other turn on. In the case of adiode circuit the turn on occurs because the device becomes forward biased, andthe turn off because a device becomes reverse biased. If one is dealing with anideal circuit, then the current would transfer instantaneously from one deviceto another, but if there is inductance in the circuit then this does not occurinstantaneously.

In order to study current commutation consider the test circuit in Figure 6.9.

D1

D2

Id

vs

+

-

Ls

is

vL+ -

t

v vs d,

vd

is

vd

Waveforms with Ls

= 0

vD

1

Figure 6.9: Test circuit used for current commutation discussion.

The following discussion is with respect to Figure 6.10. Prior to t = 0 theinput voltage vs < 0, and therefore the diode D2 is conducting the outputcurrent Id. At t = 0 vs becomes positive and the diode D1 becomes forwardbiased and turns on. However, due to the inductance Ls the current iD1 does


not instantly go to Id. The rise in the current in Ls is limited by the value ofLs and the voltage across it.

Eventually the current in Ls will rise to the value if Id. During this risethe current iD2 will be falling at the same rate as the increase in iD1, so thatthe current to the current source is maintained at Id. When iD1 = Id then thecommutation process is complete, and the current iD2 = 0, turning off D2.

Id

vd

= 0

D1

D2

Ls

+ -vL

vs

+

-I

d

is

iD1

iD2

Id

v vd s

=

D1

D2

Ls

+ -vL

= 0

vs

+

-

is

i Is d

=

(a) During commutation

(b) After commutation

Figure 6.10: Circuit configurations during current commutation of the circuitin Figure 6.9.

Let us analyse this situation as little more closely. Consider the situationwhen the input voltage vs initially becomes greater than zero. The voltage onthe load side of the inductor is zero because D2 is on. Therefore the currentacross the inductor is:

vL =√

2Vs sinωt = Lsdisdt

0 < t < tc (6.70)

where tc , the time when commutation is complete.We can rearrange (6.70) and integrate both sides to give:

√2Vs

∫ tc

0

sinωt dt = Ls

∫ Id

0

dis (6.71)

6.4 The Concept of Current Commutation 6-17

which becomes:Aθc =

√2Vs(1− cosωtc) = ωLsId (6.72)

where Aθc , the volt-second area under the inductor voltage.Rearranging this expression we can write:

cos θc = 1− ωLsId√2Vs

(6.73)

where θc , ωtc, the commutation angle.

Remark 6.9 Equation (6.73) confirms our previous assertion that if Ls = 0then the commutation occurs immediately the diode D1 turns on – i.e. cos θc =1⇒ θc = 0. Also note that as Ls increases the commutation angle increases (asone would intuitively expect), and as Id increases the angle increases due to thefact that it will take longer before iD1 = Id.

Remark 6.10 Another interesting effect of the commutation is that the aver-age voltage produced at the output of the circuit is lower due to commutationnotches. These “notches” result in sections of vs not appearing at the output. commutation

notchesWaveforms for the commutation of the current are shown in Figure 6.11. Thesewaveforms are the outputs of a Saberr simulation. These plots clearly showthe commutation notches in the output voltage, vd. The commutation notchesappear as the voltage across the Ls inductor. The area of these commutationnotches, where the horizontal axis is θ = ωt, was evaluated in the expression(6.72). The plots of Figure 6.11, however, are on the time axis. Therefore,under this condition it can be shown that the expression for the area underthe inductor notch is LsId (the ω term is omitted). Examination of the notchintegral plot of Figure 6.11 shows that the area is 0.0050081 – in other wordsLs, which it should be since Id = 1.

It is clear from Figure 6.11 that the commutation notches lower the outputvoltage. We can calculate voltage loss analytically. Firstly we can calculate theaverage output voltage as follows:

Vd0 =1

2π

∫ π

0

√2Vs sinωt d(ωt) =

2√

2

2πVs = 0.45Vs (6.74)

In the case where one has commutation notches then the average voltage canbe calculated as:

Vd =1

2π

∫ π

θc

√2Vs sinωt d(ωt) (6.75)

This expression can be rewritten as the average voltage with Ls = 0 minus theaverage voltage of the commutation notches:

Vd =1

2π

∫ π

0

√2Vs sinωt d(ωt)− 1

2π

∫ θc

0

√2Vs sinωt d(ωt) (6.76)

= 0.45Vs −area Aθc

2π(6.77)

= 0.45Vs −ωLs2π

Id (6.78)


(V)

-60.0

-40.0

-20.0

0.0

20.0

40.0

60.0

t(s)

0.0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

(A)

0.0

0.5

1.0

(V)

-20.0

-10.0

0.0

10.0

20.0

(0.020807, -0.022068)

(0.020007, 0.10216)

(V*s

ec)

0.0

0.002

0.004

0.006

(0.020805, 0.0050081)

(V) : t(s)

(A) : t(s)

(V) : t(s)

(V*sec) : t(s)

Notch Area

Comm notchesv

L

i iL s,

Inductor current

vs

vD1

Output vd

Output vd

Figure 6.11: Plots of the currents in the test circuit of Figure 6.9 – vs = 50 sinωt,Ls = 5mH, Id = 1 Amp.

6.5 Practical Uncontrolled Single Phase Rectifiers 6-19

Remark 6.11 From equation (6.78) one can see that the loss of output voltageis:

∆Vd =area Aθc

2π=ωLs2π

Id (6.79)

6.5 Practical Uncontrolled Single Phase Recti-fiers

We have now carried out some preliminary analysis on half wave rectifiers todevelop some techniques to analyse rectifier circuits. We shall now apply thesetechniques to a practical single phase rectifier. These circuits are very important,as they form the front end of almost all switch mode power supplies used indomestic and computing applications.

Remark 6.12 The prevalence of the single phase rectifier in computer basedequipment is becoming a problem in power systems due to the harmonics thatthey inject into the power supply. This results in poor power factor, and canlead to heating problems in other pieces of equipment, and occasionally causingfalse triggering of frequency controlled equipment on the network.

The circuit which is the subject of this section is shown in Figure 6.12. This istypical of a rectifier used in a linear or switch mode power supply.

+

Ls R

s

vs

+

-

is

vd

Rload

Cd

id

Figure 6.12: A practical single phase rectifier.

If we assume that the current id is discontinuous due to the capacitor voltageresulting in the current going to zero before the end of the half cycle of the inputvoltage (similarly to the waveforms for the circuit in Section 6.3.3), then we don’thave to worry about the current commutation from one diode to another.

We shall generate the analytical equations for the circuit under these condi-tions. We shall not solve the equations, as this is a little complicated, but thesolutions are obtainable. If there is current commutation in the circuit then thesolutions get a little more complicated.


Whilst the diodes are conducting the equivalent circuit is as shown in Fig-ure 6.13. Applying KVL to this circuit we can write the following differentialequation:

vs = Rsid + Lsdiddt

+ vd (6.80)

Similarly one can also apply KCL to the circuit to give:

id = Cddvddt

+vd

Rload(6.81)

Rearranging we can write the following matrix expressions when the diode isconducting: [

diddtdvddt

]=

[−RsLs − 1

Ls1Cd

− 1CdRload

] [idvd

]+

[1Ls0

]vs (6.82)

+C

dR

load

Ls R

s

vs

+

-

id

vd

Figure 6.13: Equivalent circuit of the single phase rectifier when the diodes areconducting.

During the time when the diodes are off (i.e. when the energy in Ls hasbeen expended and vs < vd), the capacitor is discharging into the load resistor.Therefore there is an exponential decay of the output voltage. The expressionfor this time is (using KCL):

Cddvddt

+vd

Rload= 0 (6.83)

⇒ dvddt

= − vdCdRload

(6.84)

Remark 6.13 Using equations (6.82) and (6.84) one can solve for the completeanalytical solution for the currents and the voltages in this circuit.

We shall not attempt to solve (6.82) and (6.84), but instead we shall simulatethe circuit of Figure 6.12 using Saberr. The plots in Figure 6.14 are the outputwaveforms of this circuit. In particular notice the very “spikey” current flowinginto the rectifier, and the ripples on the output voltage due to this, and thedischarge time when all the diodes are off and the output is disconnected fromthe input.


(V)

-60.0

-40.0

-20.0

0.0

20.0

40.0

60.0

t(s)

0.0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2

(V)

0.0

20.0

40.0

60.0

80.0

(A)

-20.0

0.0

20.0

40.0

(V) : t(s)

(V) : t(s)

(A) : t(s)

vs

vd

is

Figure 6.14: Waveforms for the practical single phase rectifier circuit of Fig-ure 6.12.


If one evaluates that harmonics on the current waveform the plot shown inFigure 6.15 is obtained. One can see that the output voltage has a dominantdc component (as it should) which has an amplitude of approximately 47 volts.There is also a harmonic at 100Hz corresponding to the fundamental of theripple on the dc output voltage.

The main harmonic in the current is at 50Hz, but there are also significantharmonics at 150, 250 and 350Hz as well (i.e. the 3rd, 5th and 7th harmonics).One can treat each of the harmonics in the current as a phasor (as in (6.7)).The amplitudes of the real and imaginary components of these phasors can befound using the waveform analysis tools in Saberr, and these are plotted inFigure 6.16.

Mag

(V)

0.0

20.0

40.0

60.0

f(Hz)

0.0 50.0 100.0 0.15k 0.2k 0.25k 0.3k 0.35k 0.4k 0.45k 0.5k 0.55k 0.6k 0.65k 0.7k

Mag

(A)

0.0

2.0

4.0

6.0

Mag(V) : f(Hz)

Mag(A) : f(Hz)

is

vd

Figure 6.15: Input current and output voltage harmonics in a single phaserectifier.

In Figure 6.16 one can see the amplitude of the fundamental real and imag-inary harmonics – a1 = −0.40077 and −b1 = −4.6573.8 Therefore using the

8In Saberr the b coefficient is called the imaginary coefficient. It is the negative of theactual b coefficient as appears in a normal Fourier series. Hence we have written the coefficientas −b1.


f(Hz)

0.0 50.0 100.0 0.15k 0.2k 0.25k 0.3k 0.35k 0.4k 0.45k 0.5k 0.55k 0.6k 0.65k 0.7k

Im(A

)

-6.0

-4.0

-2.0

0.0

2.0

4.0

Re(

A)

-2.0

-1.0

0.0

1.0

Im(A) : f(Hz)

Re(A) : f(Hz)

(50.0, -4.6573)

(50.0, -0.40077)

is

is

Fourier components generated before 140msec and 180msec

Figure 6.16: Real and imaginary components of the harmonic phasors for theharmonics single phase rectifier harmonics plotted in Figure 6.14.


definitions associated with (6.7) one can see that:

F (1) =√a2

1 + b21 = 4.4745 Amp (6.85)

φ1 = tan−1 −b1a1

= 265.08 = −94.92 (6.86)

Comparison of (6.85) with the fundamental shown in Figure 6.15 indicates thatthe value appears to be correct. The phase in (6.86) is the phase of a coswaveform (which is the time domain representation of a phasor).

The harmonics in Figure 6.15 and Figure 6.16 were taken by looking atthe input current over two fundamental periods of the input voltage startingat 120msec and ending at 180msec. This was done so that the rectifier wasoperating in steady state, and the transients that can be seen in Figure 6.14would not affect the harmonic analysis. This also means that the phase in(6.86) is with respect to the voltage input waveform. Consequently we can usethe value in (6.86) to get the phase (and hence power factor) of the currentfundamental. Realising that the time domain form of the phasor is:

fn(t) = Fn cos(nω1t+ φn) (6.87)

one can write the time domain expression for the fundamental current as:

i1(t) = I cos(ω1t+ φ1) (6.88)= 4.47 cos(100πt− 94.92) (6.89)

Using the trigonometric identity cos(x) = sin(x+ 90) then we can write:

i1(t) = 4.47 sin(100πt− 4.92) (6.90)

Hence there is a phase shift of the fundamental from the input voltage of −4.92.Consequently, from (6.63) we can see that the DPF is:

DPF = cosφ1 = cos(−4.92) = 0.996 (6.91)

Remark 6.14 From a fundamental current view point the power factor of thesystem is very good. The presence of harmonics is the main contributor to poorpower factor.

The non-sinusoidal power factor is defined by (6.64). Therefore if we can cal-culate the rms value of the non-sinusoidal current then we can calculate thenon-sinusoidal power factor. From Figure 6.15 one can see that the harmonicsamplitudes and rms values are as shown in Table 6.2.

Using (6.24) we can now calculated the THD for the input current waveform.Calculating the distorted current using (6.21) we get:

Idis =

√√√√ 13∑n 6=1

I2sn = 3.1076 (6.92)


Harmonic Amplitude RMS value1 4.6775 3.30543 3.6788 2.60135 2.1911 1.54937 0.87625 0.61969 0.30301 0.214311 0.29773 0.210513 0.18 0.1273

Table 6.2: Current harmonic amplitudes.

Therefore the input current THD is:

THD = 100× IdisIs1

= 100× 3.1076

3.3054= 94% (6.93)

Remark 6.15 The value in (6.93) shows that the harmonic distortion of theinput current is quite high.

We can now also calculate the non-sinusoidal power factor using (6.62):

PF =Is1Is

cosφ1

=3.3054√

3.10762 + 3.30542× 0.996

= 0.73 (6.94)

using (6.19).

Remark 6.16 From (6.94) one can see that the power factor has been loweredby the presence of the harmonics. Compare this to the DPF which is 0.996.Therefore the presence of the harmonics in the input current waveform is amajor contributor to the poor power factor of this circuit.

Remark 6.17 Single phase full wave rectifiers such as depicted in Figure 6.12are present in large numbers on the power supply grid (e.g. in computer powersupplies). Therefore the cumulative affect of this could result in a very pooroverall power factor. Techniques for improving the power factor of this rectifiersare now being used.

6.5.1 Unity Power Factor Single Phase RectifierThe requirement for unity power factor (which implies low harmonic content) forsingle phase rectifiers connected to the grid has spurred research into techniquesto modify the standard single phase full wave rectifier.

One of the standard techniques to filter supply current waveforms is to usepassive filters at the input of rectifier. These passive filters usually consisted ofcombinations of L or LC components. An example of a circuit with this type


of filtering is shown in Figure 6.17 [2]. This particular circuit has filters at theac input and the dc output. The input filter is a classic ‘T’ low pass filter.This filter basically filters out the higher order harmonics in the input current.The filter in the dc link needs a little explanation. Clearly it is also a low passfilter, and appears to have the classic π structure. The choice of the size ofthe components is important from another point of view. The capacitor Cd1 ischosen to be small so that there is considerable ripple in the vd1 voltage. Thiscauses the current to flow in smoother fashion from the supply via the diodes.The extra ripple in vd1 is then filtered via the low pass filter formed by Ld andCd. The Cd capacitor is much larger than Cd1.

+

Lf 1

vs

+

-

is

vd

Rload

Cd

id

+ +v

d1C

d1C

f

Lf 2

Ld

Figure 6.17: Single phase rectifier with input and dc link filters.

Remark 6.18 The passive circuits have a limited capacity to smooth the inputcurrent. The filtering achieved is capable of improving the power factor theacceptable levels. However there are some shortcomings:

a. The output voltage is lowered due to the presence of the inductors.

b. There is an obvious disadvantage in the cost of the filters, size, losses anddependence of the output voltage on the load current drawn.

The limitations cited in Remark 6.18 have led to the investigation of activecurrent shaping techniques to improve the power factor of the rectifiers. Thesetechniques also have the advantage that they extend the range of operation ofthe rectifier – i.e. the input voltage can vary but the output voltage will stayconstant. For any current shaping circuit to be of practical use it has to havethe following attributes:

• The current shaping circuit should be of low cost and small size.

• It should enable the input power factor to be near unity.

• The circuit should be simple to control.

• It should allow the rectifier to provide the correct voltages under over-voltage as well as under-voltage conditions.


Given these specifications the obvious circuit to provide this functionality is theboost converter. This circuit is the most suitable for the following reasons:

a. The circuit is capable of producing an higher voltage at the output thanat the input. Therefore as the input voltage falls the output voltage canbe kept constant.

b. If the converter is set-up to provide an output voltage, that is say 10%higher than the nominal peak input voltage, then the circuit can cope withover-voltages of up to 10% without altering the output voltage.

c. The boost converter configuration maintains a continuous current throughthe input inductor (if operating is continuous conduction mode). There-fore the current can be kept continuous through the diodes on the circuit.This intrinsically allows better input power factor to be achieved.

Remark 6.19 Note that the buck converter is in general not suitable for thisapplication because the input current is highly discontinuous. This is due to thefact that the switch in the circuit disconnects the output of the diodes in therectifier from the input to the converter during normal operation.

Figure 6.18 shows the basic structure of a single phase rectifier with a boostconverter for current shaping.

+

Ls R

s

vs

+

-

is

Rload

Cd

id

Boost converter

Ld

iL

ic

iload

vs v v

d s( )>

Figure 6.18: Circuit for the a single phase rectifier with current wave shapingboost converter.

As can be seen from Figure 6.18 the circuit is simply a conventional rectifierfollowed by a conventional non-isolated boost converter. The boost converteris usually controlled so that the output voltage is approximately 10% higherthan the nominal rated voltage of the rectifier. This allows the circuit to workcorrectly if the supply is up to 10% higher than the nominal voltage. Oneimplicitly gets a circuit that can operate with low voltages because of the boostconverter. How low the voltage can go depends on the design of the boostconverter and the load current and voltage required.


The key to the operation of the unity power factor rectifier is the control ofthe boost converter. Before considering the general principles of the control wefirstly need to clarify the requirements for the control. If we want unity powerfactor, than we need a sinusoidal input current which is in phase with the inputvoltage and does not have any significant harmonics. The desired waveformsare shown in Figure 6.19(a) and (b). One can see that the waveforms in theboost converter section of the circuit are sinusoidal in nature.

vs

is

wt

(a)

vs

iL

wt

(b)

Figure 6.19: Waveforms for a single phase rectifier with active current wave-shaping – (a) the input current and voltage; (b) the boost converter inputvoltage and inductor current.

Remark 6.20 Examination of the waveforms in Figure 6.19 indicate that therewill be a ripple voltage on the output filter capacitor (as there is in the conven-tional rectifier). The capacitor has to be designed to be large enough to keep thisripple below acceptable limits.

Ignoring power losses in the boost converter we can apply some basic analysisto the circuit of Figure 6.18 with the waveforms of Figure 6.19. Define Vs =√

2Vs, and Is =√

2Is – i.e. Vs and Is are the rms values of the voltage andthe current. Clearly the instantaneous power flowing into the circuit is (usingsin2 x = 1

2 (1− cos 2x)):

pin(t) = Vs sinωtIs sinωt = VsIs − VsIs cos 2ωt (6.95)


which is similar to (6.35), except that this was calculated for cos waveformswith a θ phase difference between them.

If we assume that the output capacitor is large then the voltage ripple acrossit will be minimal, and consequently the output power can be written as:

pd(t) = Vdid (6.96)

where Vd , the average output voltage = vd. The current flowing into the loadand the capacitor is:

id(t) = Iload + ic(t) (6.97)

Assuming that the switching frequency is very high then the inductor can benegligibly small. This allows one to use the simplifying assumption that on aninstantaneous basis that:

pin(t) = pd(t) (6.98)

and therefore we can write:

VsIs − VsIs cos 2ωt = Vdid(t) (6.99)

∴ id(t) = Iload + ic(t) =VsIsVd− VsIs

Vdcos 2ωt (6.100)

One can see from this expression that:

Id = Iload =VsIsVd

(6.101)

ic(t) = −VsIsVd

cos 2ωt = −Id cos 2ωt (6.102)

Even though the assumption was made that the voltage across the capacitorwas constant, we can use (6.102) to get an approximate value of the voltageripple across the capacitor:

vd,ripple(t) ≈1

Cd

∫ic(t) dt = − Id

2ωCdsin 2ωt (6.103)

Remark 6.21 From (6.103) it can be seen that if Cd is made large then vd,ripplecan be arbitrarily small.

The key to the correct functioning of this circuit is the control. Two control loopsare required in order to achieve the required control – a voltage control loop sothat the output voltage stays are the correct value despite load variations, anda current control loop to provide the input current wave-shaping. These twoloops have to work cooperatively.

We have previously encountered both voltage and current control loops,arranged in a hierarchical or nested structure, in relation to switched modepower supply control. A similar arrangement is used here, the main differencebeing the desired reference value for the current.

Figure 6.20 shows a block diagram of the basic structure of the control forthe unity power factor single phase rectifier. This block diagram is almost thesame as that shown in Figure 3.25. The major difference is the inclusion ofthe multiplier of the error by the absolute value of the supply voltage, whichresults in a sinusoidal rectified inductor current reference waveform. This is


then fed to the current control algorithm. The current control algorithm can beimplemented in a variety of ways (see Section 3.3.3.3), but the most commontechnique is the “constant frequency with turn-on at clock time” controller.

´PI

Regulator

Vd ,measured

Vd

*

e V Vd d

= -*

,measured

vs

iL,measued

iL

*

Current

mode

control

Switch

control

signal

Figure 6.20: Block diagram of the control system for a single phase rectifierwith active current wave-shaping.

With this control strategy the net result is that the sinusoidal referencecurrent amplitude is modulated by the output voltage error – the larger thevoltage error the larger the amplitude of the sinusoidal current pulse.

Some other points to note about this circuit:

a. A resistor in series with the Ld inductor is often used to limit the inrushcurrent at start-up. This resistor is usually shorted out by a SCR (largevoltage drop with this though), a relay or a MOSFET once the circuitstarts to operate normally.

b. A small filter capacitor is usually placed across the output of the diodebridge to prevent the switching noise from entering the grid supply.

c. The output filter capacitor only has to be about half the size of that in anuncontrolled rectifier, for the same ripple. Therefore the active rectifiercircuit saves on weight and space.

d. The energy efficiency of a typical active current controlled signal phaserectifier is 96%. An uncontrolled conventional rectifier has an efficiency ofapproximately 99%.

6.5.2 Effect of Current Harmonics on Line Voltages

We have seen in Section 6.5 that the single phase rectifier can produce manyharmonics in the current. In the subsequent analysis of the power factor of thecircuit it was assumed (for simplicity reasons) that the voltage was unaffectedby the presence of these harmonics. However, in a real network this is not thecase.

Consider the circuit shown in Figure 6.21. Here we can see a conventionalsingle phase rectifier connected to the grid supply via a source resistance andinductance. Note that the inductance is divided into two sections, the sectionbetween them being the so called “point of common coupling” (PCC). The PCCis the nearest point to the rectifier where other equipment can be connected


to the grid supply. Note that there is an additional inductance, representingthe inductance of the grid supply, between the PCC and the grid supply voltagesource. It is the inductance of this impedance that causes the current harmonicsto affect the supply voltage seen by other devices connected to the grid supply.

+

Ls1 R

s

vs

is

vd

Rload

Cd

id

Ls2

Other equipmentconnected to the

supply

Point of common coupling (PCC)

+

-

vPCC

Figure 6.21: Single phase rectifier showing the point of common coupling.

The voltage across other equipment at the PCC is:

vPCC = vs − Ls1dis1dt

(6.104)

where vs is assumed to be an ideal sinusoidal voltage source.The current is1 contains the harmonic currents of the single phase rectifier

(as well as the harmonics drawn by the other equipment). These harmonics willcause a voltage drop across the Ls1 inductance. This drop can be considerable,since the impedance of an inductor increases with increased frequency.

One can break the current into a sinusoidal component and the distortedcomponents as follows:

vPCC =

(vs − Ls1

dis1dt

)− Ls1

∑h6=1

dishdt

(6.105)

Clearly the fundamental component is:

vPCC1= vs − Ls1

dis1dt

(6.106)

and the distortion component is:

vPCCdis = −Ls1∑h6=1

dishdt

(6.107)

6.5.3 Voltage Doubler Single Phase RectifiersThe circuit shown in Figure 6.22 is sometimes used in cost conscious commercialproducts to produce voltage doubling without the use of a transformer. Depend-ing on the position of the switch the rectified dc voltage is either approximately


the peak of the sinusoidal input voltage, or alternatively it is twice this peakvoltage.

vd

C1

C2

D1

D2

Double

pos

vac

Figure 6.22: Single phase rectifier voltage doubler.

If the switch is closed then on a positive half cycle of the input voltagecurrent flows via D1, capacitor C1, and the switch back to the supply. On thenegative half cycle the current flow via the switch, capacitor C2 and diode D2

back to the supply. The result is that the two capacitors have the peak supplyvoltage across them, and their voltages sum. If the switch is open, then thecircuit behaves as conventional bridge rectifier.

6.5.4 The Effect of Single Phase Rectifiers on Three Phase,Four Wire Systems

In large commercial buildings the primary loads are of a single phase nature,even though the building as a whole is supplied with a three phase power system.These single phase loads are usually distributed as evenly as possible betweeneach of the three phases and the neutral of the system, as shown in Figure 6.23.If the loads on the system are linear loads then such a strategy will lead toa neutral current that is approximately zero. However, if the loads are largelysingle phase rectifiers, the non-linear nature of these loads can lead to substantialneutral currents.

Assume that the diode rectifiers in each of the phases are identical. Wecan therefore write the currents in the phases as a combination of the funda-mental and harmonics currents (which are the odd harmonics, since, as shownpreviously, the even harmonics are zero):

ia = ia1 +

∞∑h=2k+1

iah (6.108)

=√

2Is1 sin(ω1t− φ1) +

∞∑h=2k+1

√2Ish sin(ωht− φh) (6.109)


ia

ib

ic

a

b

c

Single phase rectifier

loads

in

n

Figure 6.23: Single phase rectifiers loads in a three phase, four wire distributionsystem.


In a similar manner to (6.109) one can write the other currents in the phases(assuming they are of similar form):

ib =√

2Is1 sin(ω1t− φ1 − 120) +

∞∑h=2k+1

√2Ish sin(ωht− φh − 120h)

(6.110)

ic =√

2Is1 sin(ω1t− φ1 − 240) +

∞∑h=2k+1

√2Ish sin(ωht− φh − 240h)

(6.111)

Applying Kirchhoff’s current law to Figure 6.23 we can write:

in = ia + ib + ic (6.112)

If one substitutes (6.109), (6.110) and (6.111) into (6.112) then all the non-triplen and fundamental harmonics add to be zero. The triplen harmonics onthe other hand add to give:

in = 3

∞∑h=3(2k−1)

√2Ish sin(ωh − φh) (6.113)

which can be written in rms terms as:

In = 3

∞∑h=3(2k−1)

I2sh

1/2

(6.114)

Therefore the third harmonics add together in the neutral, and the neutralcurrent therefore becomes:

In = 3Is3 (6.115)

The third harmonic current in the lines can be quite significant with single phaserectifier loads, and consequently the neutral current can be large. In fact underconditions of highly non-linear loads, the neutral current can be as much as√

3Iline. Therefore, the neutral should be a conductor that can at least carry asmuch as the lines.

6.6 Three Phase, Full Bridge RectifiersWhilst single phase rectifiers predominate in domestic and computer rectifi-cation applications, industrial rectification is carried mainly with three phaserectifiers. This is due to their lower voltage and current ripple, and their higherpower carrying capabilities. These devices naturally balance the loading on eachof the phases, and therefore do not require any planning action in this respect.Furthermore, no triplen harmonics can flow in these circuits since there is noneutral connection.

The fundamental circuit for the conventional six pulse three phase rectifieris shown in Figure 6.24.

In order to understand the operation of this device we shall firstly look ata simplified model of its operation. Assume that the load is not modeled as an

6.6 Three Phase, Full Bridge Rectifiers 6-35

a

b

c

Ls

Ls

Ls

D1

D3

D5

D4

D6

D2

+C

dR

load

id

vd

ia

ib

ic

n

+

+

+

Figure 6.24: Basic three phase, six pulse, full wave rectifier circuit.

RC as in Figure 6.24, but as a constant current sink. This is an approximationto a highly inductive load. The plots of the phase currents and output voltagesof this converter are shown in Figure 6.25.

As can be seen from this diagram, the output voltage consists of 6 segmentsper input voltage period. Therefore this rectifier is often known as a six pulserectifier.


Graph0

(V)

0.0

200.0

400.0

600.0

t(s)

0.0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09

(V)

-400.0

-200.0

0.0

200.0

400.0

(A)

-5.0

0.0

5.0

(A)

-5.0

0.0

5.0

(A)

-5.0

0.0

5.0

(V) : t(s)

output_voltage

(V) : t(s)

v(v_sin.phase_a)

v(v_sin.phase_b)

v(v_sin.phase_c)

(A) : t(s)

i(v_sin.phase_a)

(A) : t(s)

i(v_sin.phase_b)

(A) : t(s)

i(v_sin.phase_c)

Figure 6.25: Waveforms of a three phase rectifier with a constant current sourceload.

Chapter 7

Introduction to Other PowerElectronic Devices andApplications

7.1 Introduction

This chapter briefly introduces several other high power, power electronic switch-ing devices and applications that are industrially important. The presentationhere is brief and introductory in nature, and by no means comprehensive. Itis intended to introduce the student to other power electronic circuits, hithertonot considered, and some of their applications. The applications chosen are,hopefully, those that are interesting to the readers. Those who wish to researchinto any of the circuits and applications presented are encouraged to follow upthe topics in the references.

The remainder of this chapter will consider the following:

• Inverters and applications

• Multilevel converters and applications

• Matrix converters

7.2 Inverters and Applications

In the previous chapter we briefly considered rectifiers. A rectifier is the namegiven to a power electronic device which accepts AC voltage at its input, and“rectifies” this to DC voltage at the output. The power flow is considered to befrom the AC to the DC side. The term rectifier refers to the operational functionof the power electronic hardware, but not the configuration of the hardware.This distinction is demonstrated by the cycloconverter. The cycloconverteruses power electronic hardware that is virtually the same as that of a phasecontrolled rectifier and generates AC output voltages from AC input voltages.Power can flow bidirectionally in these devices.

7-2 Introduction to Other Power Electronic Devices and Applications

P

P

Rectifier mode

Inverter mode

AC DCCONVERTER

Figure 7.1: Definition of rectifier and inverter modes of operation [2].

An inverter, is the dual of the rectifier, in that it accepts DC input andgenerates an AC output – i.e. power flow is from the DC to the AC side of thepower electronic device. As with the rectifier, this definition does not define thehardware configuration, since it is possible to have the same hardware acting asan inverter and rectifier.

The above is summarised in Figure 7.1. Consider, for example, the rectifierconsidered at the end of Chapter 6, i.e. Figure 6.24. In this circuit that mainelectronic components are diodes. Diodes can only conduct current in one di-rection. Therefore, if the output voltage is only allowed to be one polarity, thenpower cannot be transferred from the DC side to the AC side of the converter,as current cannot flow in the reverse direction through the diodes. It is this factthat defines this circuit to be a rectifier.

Converter 1 Converter 2

Energy

Storage

Element

Input Output

Figure 7.2: Generic power processing block [2].

Many power electronic systems have the configuration shown in Figure 7.2.Converter 1 transforms the input to DC. There is a storage element that isable to accept the energy. Converter 2 then converters to DC to the desiredoutput. The energy storage element is typically a capacitor or inductor. Itspresence means that the instantaneous input power does not have to equal toinstantaneous output power, thereby providing a degree of decoupling of theinput from the output, and allowing a degree of independence in the control

7.2 Inverters and Applications 7-3

and operation of the two converters.

+Converter 1 Converter 2

DC link

AC

Motor

Utility

ACAC

Figure 7.3: Block diagram of a generic AC drive system.

Figure 7.3 shows a less abstract version of Figure 7.2 for one form of an ACdrive system. Notice that in this particular case to energy storage element is acapacitor. Both the input and the output is AC. Therefore, in this applicationthere is inherently an inversion process, since one way or another power mustgo from the DC to AC side.

In many actual implementations of Figure 7.3 Converter 1 is a rectifier, andConverter 2 is an inverter. This means that power can only flow from the utilityto the motor, and not in the reverse direction since the rectifier cannot transferpower back to the utility. Depending on the details of the implementation ofConverter 2, it is possible that it can act as a rectifier, and power can from themotor (which is now acting as a generator, the mode being called regeneration)back to the DC link. In this case the capacitor can accept the energy, butone must be careful to ensure that not too much energy is transferred, else thecapacitor will experience over-voltage and be destroyed.

If a motor is going to be regenerating for a significant percentage of timeduring operation, then both Converter 1 and Converter 2 need to be able toact as both a rectifier and an inverter. If this is the situation then regeneratedenergy can be transferred back to the utility supply, and the capacitor voltagecan be controlled to remain within bounds.

Remark 7.1 It is possible to further classify inverters based on the type of tech-nology used to implement the inverter – forced commutated converters, resonantlink converters. We shall not look a these differences in detail here.

Figure 7.4 shows a specific implementation of an inverter. The main differ-ence between this and Figure 6.24 is that the diodes in the circuit are in parallelwith a switch. Most modern small to medium power inverters these days useIGBTs as the switch. The arrows on the switches in Figure 7.4 indicate thatthis is the direction that current can flow through the switch.

The presence of the parallel switches across the diodes makes a major dif-ference to the operation of this circuit. By appropriate switching of the sixswitches an AC voltage (in an average sense) can be synthesized on the threephase outputs of the inverter. The presence of the diodes, of course, meansthat the circuit can always operate as a rectifier. In fact, this very circuit is nowcoming into use as the rectifier front end to large drive systems. Its ability to al-low bidirectional power flow means that this rectifier allows a fully regenerativesystem.


+DC

Z

Z

Z

3 phase AC load

DC link

a

b

cn

R

R

g

Artificial ground

vag

vbg vcg

Figure 7.4: Specific implementation of an inverter.

7.2.1 Pulse Width Modulation

Thus far we have only considered one form of the hardware for an inverter.In order for an inverter to work, there has to be a strategy for controlling theswitches. In section 1.3.2.2 on page 1-10 the essential ideas behind a triangularwave PWM modulator was briefly discussed. Furthermore, in section 2.4.2 onpage 2-11 we considered how to generate a Pulse Width Modulator based onsawtooth modulation waveforms to produce a desired average output voltagefor a switched mode power supply. Therefore this section, is to some degree, abrief rehash of this material. The reader is referred to the sections 1.3.2.2 and2.4.2. The essentials of this technique are shown in Figure 2.11 on page 2-13.The same technique can be used for three phase systems.

If we consider just one leg of the three phase converter of Figure 7.4, thenthe technique outlined in sections 2.4.2 on page 2-11 and 1.3.2.2 on page 1-10can be applied directly. When the reference waveform exceeds the triangularwaveform then the top switch in the leg is turned on, and the bottom leg off.When the reference waveform is less that the triangular waveform, then thebottom transistor is turned on and the bottom transistor is turned off. Thewaveforms produced when the centre of the DC link is used as the referencepoint for the voltage are shown in Figure 7.5.

Remark 7.2 Note that the fact that the load is referenced to the centre of theDC link allows true AC voltage and AC current to be applied to the load. Thisis similar to the situation in the three phase inverter.

In the case of a three phase inverter to see how the waveforms appear is alittle more complex, and not quite as obvious. As in the single leg case oneneeds to establish a reference point to define the voltages, and similarly themid point of the DC link is often chosen. Therefore, if the top switch of aleg is closed (meaning that the bottom switch is open) then the voltage on thephase output terminal is 1

2VDC where VDC is the total voltage across the DC


+Z

e

DC link

Modulator

Reference waveform

+

Approximate

fundamental

Carrier waveform

Figure 7.5: Single leg of inverter and the PWM waveforms.


link. Similarly if the bottom switch is closed (meaning that the top switch isopen), then the voltage on the phase output terminal is − 1

2VDC . Therefore, theoutput of a single leg has two values. Therefore with three legs we have 23 =8 possible unique output voltage combinations, corresponding the 8 differentpossible switching combinations.

A notation that we shall use is that the leg switching states are representedby a binary value – a ‘1’ denotes that the top switch of a leg is closed, andthe bottom switch is open, and a ‘0’ denotes that the top switch is open andthe bottom switch is closed. Therefore, the possible switching combinations,with the phase leg voltages with respect to the mid link ground point (denotedas “g”), and the line-to-line voltages across a three phase load (such as that inFigure 7.4) are shown in Table 7.1.

Switch pattern abc vag vbg vcg vab vbc vca

0 0 0 − 12VDC − 1

2VDC − 12VDC 0 0 0

0 0 1 − 12VDC − 1

2VDC12VDC 0 −VDC VDC

0 1 0 − 12VDC

12VDC − 1

2VDC −VDC VDC 00 1 1 − 1

2VDC12VDC

12VDC −VDC 0 VDC

1 0 0 12VDC − 1

2VDC − 12VDC VDC 0 −VDC

1 0 1 12VDC − 1

2VDC12VDC VDC −VDC 0

1 1 0 12VDC

12VDC − 1

2VDC 0 VDC −VDC1 1 1 1

2VDC12VDC

12VDC 0 0 0

Table 7.1: Switching combinations and associated phase and line-to-line volt-ages.

Remark 7.3 Note from Table 7.1 that the line-to-line voltages always add to-gether to be zero (similar to line-to-line voltages in a sinusoidal three phasesystem).

Remark 7.4 Note also from Table 7.1 that two of the switching states lead tozero line-to-line voltages. These two states correspond to all the top switcheson, or all the bottom switches on. These switching combinations lead to a shortcircuit across the three phases.

The phase voltages – i.e. van, vbn, vcn are also of interest. Let us considerswitching state 001 as an example. In this case we have:

vab = van − vbn = 0 (7.1)vbc = vbn − vcn = −VDC (7.2)vca = vcn − van = VDC (7.3)

One can immediately see from (7.1) that van = vbn. However, these equa-tions are not independent, and therefore one cannot solve for the phase voltages.

If one considers the three phase load to be a passive one of the form shownin Figure 7.4, then one can write, using Kirchoff’s voltage law, the followingexpressions:

vag = iaZ + vn (7.4)vbg = ibZ + vn (7.5)vcg = icZ + vn (7.6)


Adding these equations together we can write:

vag + vbg + vcg = (ia + ib + ic)Z + 3vn (7.7)

Because the load is star connected then we know that:

ia + ib + ic = 0 (7.8)

and hence (7.7) becomes:

vag + vbg + vcg = 3vn (7.9)

∴ vn =1

3(vag + vbg + vcg) (7.10)

Using (7.10) one can therefore write the following expressions for the phase-to-neutral voltages:

van = vag − vn =2

3vag −

1

3vbg −

1

3vcg (7.11)

vbn = vbg − vn =2

3vbg −

1

3vag −

1

3vcg (7.12)

vcn = vcg − vn =2

3vcg −

1

3vag −

1

3vbg (7.13)

Using equations (7.11), (7.12) and (7.13) together with the values for the volt-ages vag, vbg and vcg in Table 7.1 one can write all the values for the phasevoltages that can be produced by the inverter. These appear in Table 7.2.

Switch pattern abc vag vbg vcg van vbn vcn

0 0 0 − 12VDC − 1

2VDC − 12VDC 0 0 0

0 0 1 − 12VDC − 1

2VDC12VDC − 1

3VDC − 13VDC

23VDC

0 1 0 − 12VDC

12VDC − 1

2VDC − 13VDC

23VDC − 1

3VDC0 1 1 − 1

2VDC12VDC

12VDC − 2

3VDC13VDC

13VDC

1 0 0 12VDC − 1

2VDC − 12VDC

23VDC − 1

3VDC − 13VDC

1 0 1 12VDC − 1

2VDC12VDC

13VDC − 2

3VDC13VDC

1 1 0 12VDC

12VDC − 1

2VDC13VDC

13VDC − 2

3VDC1 1 1 1

2VDC12VDC

12VDC 0 0 0

Table 7.2: Switching combinations and associated phase and phase-to-neutralvoltages.

Remark 7.5 Adding together equations (7.11),(7.12) and (7.13) one gets:

van + vbn + vcn =2

3(vag + vbg + vcg)−

1

3(vag + vbg + vcg)−

1

3(vag + vbg + vcg)

(7.14)

∴ van + vbn + vcn = 0 (7.15)

Therefore the phase voltages always add to be zero, regardless of the appliedvoltages, when the three phase load is passive. It can be shown that this alsoapplies if there are three phase sinusoidal voltage sources in the load as well.


Remark 7.6 The neutral voltage of the three phase load moves around relativeto the ground at the mid point of the DC link. Consider the extreme cases ofswitching patterns 000 and 111. For 000, using (7.10) and substituting for thevoltages from Table 7.2 one can see that vn = − 1

2VDC . Similarly for the caseof 111 we get vn = 1

2VDC . Therefore the neutral voltage has moved around byVDC . These large voltage excursions in the neutral can cause bearing currentsto flow when electrical machines are the load on the inverter.

7.2.1.1 Space Vectors and PWM

If an electrical machine is used as the load on an inverter, then space vectorscan be used to represent the phase voltages. These phase voltages are appearingacross the phases of the machine. Almost all AC machines are wound so thattheir windings are sinusoidally distributed in space. This fact allows a “spacevector” concept to be used to represent currents, fluxes, mmfs, and voltages inthe machine. Refer to [14, 2] for more detail.

In this concept, currents, voltages, fluxes and mmfs are considered to besinusoidally distributed in space. As an example, if one has a sinusoidally dis-tributed winding in an AC machine, and this winding is fed with a DC current,then the mmf is sinusoidally distributed around the periphery of the AC ma-chine.

Remark 7.7 It can be shown that if we have three phase sinusoidally spatiallydistributed windings, fed with three phase temporal sinusoidal currents, thenone ends up with a spatially sinusoidally distributed resultant mmf that movesaround the machine at the electrical supply frequency. This can be representedas a single vector that is rotating with an angular velocity of ω (the electricalsupply frequency).

The reason for introducing the space vector concept here is because it isconvenient to use this concept to represent the output voltages for an inverter.Figure 7.6 shows the space vector diagram for the various switch positions forthe inverter. The length of the space vector corresponds to the maximum phase-to-neutral voltage for each phase – i.e. 2

3VDC . Notice that there are six activevectors that can be spaced around a machine every 60 electrical.

Remark 7.8 Although the space vector concept comes about because of the spa-tial properties of machine windings, it is often used in situations where thisdoes not exist. For example, in Figure 7.3 we have a passive load consisting ofimpedances, and we can use the space vector concept to represent the voltageson this circuit. I will not, in this brief introduction, go into detail as to why thiscan be done, suffice to say that it is due to the very close relationship betweenspace vectors and temporal phasors in circuits.

Space vectors can be used as a basis for a different type of PWM, called SpaceVector PWM (SVPWM). The basis of this PWM strategy is the realisationthat three phase temporal sinusoidal voltages lead to a spatially rotating volt-age vector in a three phase sinusoidally wound machine (as noted previously).However, with an inverter we do not have infinitely variable voltages that wecan apply to each phase, and therefore we can switch the inverter so that at anyinstant of time we can, in an average sense, produce a desired voltage vector.


(100)

(110)(010)

(011)

(001) (101)

1V

2V3V

4V

5V 6V

(000)(111)

7V

8V

av

bv

cv

dcV

ABC

A B C

1

2

3

4

5

6

Figure 7.6: Switch positions and the resultant voltage space vectors.

T

T/2 T/2

0

1

0

1

0

1

A

B

C

0 0

0 00 0

0 00 00 0

1 11 11 1

1

1

1

1

1 1

t0

t1

t0

t0

t0

t1

t2

t2

Figure 7.7: Switching waveforms for double edge pulse width modulation.


In order to develop a PWM strategy using space vectors let us define α as theduty cycle for a vector. Consider Figure 7.7 which shows the switching wave-forms to generate a particular voltage vector. One can see from this diagramthat the same switching pattern is generated symmetrically around the centre ofthe PWM period. By reading vertically one can determine the switching statesfor this switching sequence – they are 000, 100, 110, 111, 111, 110, 100, 000– i.e. we are switching between vectors V8, V1, V2, V7, and then the reverse.The vector nomenclature appears in Figure 7.6. As one can imagine this wouldlead to an average vector somewhere in between V1 and V2, the length of thevector being controlled by the duration of the zero vectors V7 and V8. The dutycycle for each of the vectors is simply the total time of the vector divided bythe control period time T . For example, the duty cycle for the V1 vector is:

α1 =2t1T

(7.16)

Similarly one can defined the duty cycle for V2. Using this notation, if onlythis vector and the zero vector was switched during an interval of T then theaverage voltage vector magnitude produced over the interval is α1VDC volts.

Note 7.1 Space vectors are defined (for reasons that I shall not elaborate onhere) as 2

3 the amplitude of the resultant vector in the machine. For a threephase machine this means that the maximum voltage vector magnitude is thesame as the peak voltage that occurs across the phases. It is this correspondenceof the voltage vectors with the phase voltages that is one of the main reasons forusing this convention.

Remark 7.9 A further comment on note 7.1 – one can resolve the space vectoronto three axes 120 apart and get the instantaneous value of the voltage on therespective three phase axes. The same logic applies to the current vector.

One of the very convenient features of vectors is that one can take orthogonalcomponents of them – i.e. one can not only resolve the vectors onto the 120

axes but one can also resolve them onto 90 axes.Consider the situation depicted in Figure 7.8. This shows a desired voltage

vector. Note that we have not considered what limits there are on the length ofthe voltage vector that can be produced by this system. We do know that thelimit if the voltage vector lies on one of the natural vectors that can be producedby the inverter is 2

3VDC .One can consider the vector in Figure 7.8 is a normalised vector (i.e. divided

by 23VDC), and hence αd and αq are the normalised orthogonal projections onto

a set of orthogonal dq axes. If we apply vector V1 for 2t1 seconds, and V2 for 2t2seconds then the desired normalised vector, in an average sense, is obtained.

Let us now calculate the actual switching times. In order to do this let usdefine the normalised voltage vector lengths:

α1 =2t1T

(7.17)

α2 =2t2T

(7.18)


d

q

1

Desired voltage

vector

V1

ad

aq

V2

21

t

22

t

60o

Figure 7.8: Switching time determination.

where T , the switching period, and α1 and α2 are effectively the normalisedvoltage vectors in Figure 7.8.

Using trigonometry on this Figure one can clearly write:

αd = α1 + α2 cos 60 (7.19)

= α1 +1

2α2 (7.20)

αq = α2 sin 60 =

√3

2α2 (7.21)

Using the definitions for α1 and α2 we can write:

αd =2t1T

+1

2

2t1T

=2t1T

+t2T

(7.22)

αq =

√3

2

(2t2T

)=

√3t2T

(7.23)

∴ t2 =αqT√

3(7.24)

Substituting into the expression for αd and making t1 the subject of the expres-sion we can write:

t1 =1

2(αdT − t2) =

1

2(αdT −

αqT√3

) (7.25)

∴ t1 =T

2(αd −

αq√3

) (7.26)

Thus t1 and t2 calculate the active vector times. One can now calculate thezero time by realising the there are four t0 periods in one switching period due


Condition for sector Firing order t0 t1 t2

Sector 1 αd > 0; αq ≥ 0; αq <√

3αd V8V1V2V7V7V2V1V8T4

(1 − αd −αq√

3) T

2(αd −

αq√3)

αqT√3

Sector 2 αq > 0; αq ≥√

3∣∣αd∣∣ V8V3V2V7V7V2V3V8

T4

(1 −2αq√

3) T

2(αq√

3− αd)

T2

(αd +αq√

3)

Sector 3 αd < 0; αq ≥ 0; αq <√

3∣∣αd∣∣ V8V3V4V7V7V4V3V8

T4

(1 + αd −αq√

3)

αqT√3

−T2

(αd +αq√

3)

Sector 4 αd < 0; αq < 0; αq >√

3αd V8V5V4V7V7V4V5V8T4

(1 + αd +αq√

3) −

αqT√3

T2

(−αd +αq√

3)

Sector 5 αq < 0;∣∣αq ∣∣ ≥ √3

∣∣αd∣∣ V8V5V6V7V7V6V5V8T4

(1 +2αd√

3) −T

2(αd +

αq√3) T

2(αd −

αq√3)

Sector 6 αd > 0; αq < 0;∣∣αq ∣∣ < √3αd V8V1V6V7V7V6V1V8

T4

(1 − αd +αq√

3) T

2(αd +

αq√3) −

αqT√3

Table 7.3: PWM firing times for various sectors

to the centred PWM algorithm. Therefore:

4t0 = T − (2t1 + 2t2) (7.27)

= T − Tαd +Tαq√

3− 2αqT√

3(7.28)

∴ t0 =T

4(1− αd −

αq√3

) (7.29)

It is possible to show, from the geometry of this situation, that for a given setof normalised orthogonal vectors αd and αq the switching times for the vectorsin sector 1 of the PWM star are:

t1 =T

2(αd −

αq√3

) (7.30)

t2 =αqT√

3(7.31)

t0 =T

4(1− αd −

αq√3

) (7.32)

where the various t values are defined in Figure 7.7. If a similar analysis iscarried out for all the sectors then one can get a complete set of switching timesas shown in Table 7.3.

Another important aspect that was eluded to earlier was that there is limitingof the resultant space vectors. For example, one cannot ask for αd = 1 andαq = 1, since this would be asking for a resultant space vector that is larger thanthat which can be obtained given the vectors that the inverter can produce. Ifone applies the expressions from Table 7.3 to such a situation then this problemmanifests itself by the condition [15]:

2t1T

+2t2T

> 1 (7.33)

or:αd +

αq√3> 1 (7.34)

in the case of sector 1 limiting. Clearly (7.33) means that the total switchingtime of the active vectors exceeds the total control period.

It can be shown that the limitations imposed by the available firing timesresult in a hexagon limit. This is shown in Figure 7.9. If a desired vector exceedsthe limit hexagon, then it has to be limited to the hexagon [15].


(100)

(110)(010)

(011)

(001) (101)

(000)(111)

2

3 1

6

5

4

Limit hexagon

Limit circle

V1

V2V

3

V4

V5 V

6

V7

V8

Figure 7.9: Voltage limit hexagon.

If the times are to be scaled so that they add to give one, then we require:

γ

(2t1T

+2t2T

)= 1 (7.35)

or:γ =

1

αd +αq√

3

(7.36)

Remark 7.10 Note that the use of the γ on both the total times means that theangle of the resultant vector is preserved.

The new limited firing times for sector 1 are now:

2t1lim= 2t1γ (7.37)

2t2lim= 2t2γ (7.38)

The 1/γ values for all the sectors are summarised in Table 7.4.

Remark 7.11 Space vector based PWM is particular amenable to implemen-tation in digital form. This can be contrasted with carrier wave based PWM,which was originally devised for analogue implementation. Of particular impor-tance is that this technique does not involve the solution of any transcendentalequations, and it does not involve the use of any trigonometric functions.


Sector 1/γ

1 αd +αq√

3

2 2αq√3

3 αq√3− αd

4 −(αd +αq√

3)

5 − 2αq√3

6 αd − αq√3

Table 7.4: Voltage limit γ’s

Remark 7.12 Another interesting feature of space vector PWM is that themaximum amplitude of the fundamental that can be produced by the techniqueis larger, by approximately 15%, than that produced by carrier based sinusoidalPWM. A similar effect can be obtained in sinusoidally PWM by putting a thirdharmonic in the reference waveform.

7.2.2 Dead-time IssuesAn important practical issue that arises with “totem pole” inverter legs is theproblem of “shoot through”. This term refers to the phenomena of both the topand bottom device being momentarily on when there is a switching transitionfrom the top to the bottom device, or vice-versa.

Remark 7.13 The “shoot through” problem also exists in low power digital cir-cuits. One may recall from your studies of logic families that CMOS and TTLboth suffer from “shoot through”. In the case of digital systems the shoot throughis a very short period of time, and the power levels involved are low. Conse-quently the problem can be tolerated. However, in high power inverter systemsthe devices will fail if “shoot through” occurs.

Shoot through is overcome by making sure that the outgoing device is turnedoff before the incoming device turns on. This is achieved in practice by manip-ulating the device signals that turn the devices on and off.

The turn off of a power device is not instantaneous due to the phenomenaof charge storage in the devices. In order to give the device time to turn offbefore turning on the other device in the a small delay (typically of the orderof 3 to 4µsecs for todays IGBT devices) is allowed between the turning off ofone device and the turning on of the other. This delay results in a differentvoltage being applied to the machine compared to that being demanded by thecontrol. This is due to the fact that the dead-time delay results in a shift of theswitching edges.

The dead-time error problem is a little more complicated than I have out-lined above. The presence of the dead-time switching delay is actually variabledepending on the direction of the current through the inverter leg. The follow-ing discussion is with reference to Figures 7.10 and 7.11. Figure 7.10 shows twolegs of an IGBT based inverter, with the current flowing out of leg A and intoleg B. Figure 7.11 shows the effects of the current direction on the actual time of


ThreePhase

Input/Output

DCBus

Input/Output

+

-

Phase ALeg

Phase BLeg

Phase CLeg

Initial current

Final current

iai

ibi

iaf

ib

f

Figure 7.10: Inverter showing the initial and final current flow after a leg isfired.

switching. As can be seen when current flows out of a leg (i.e. leg A) the actualtime of switching is the desired time of switching. Therefore the dead-time ofthe inverter does not cause a problem. However, when current is flowing into aleg (i.e. leg B) then the switching time is delayed by the dead-time.

Therefore, if one wishes to compensate for the dead-time so that correctswitching always occurs, one should sense the current direction and compensatethe switching time as appropriate. However, because the compensation of theswitching time has to occur in the control interval before the interval it is goingto be applied, then there is the possibility that the current direction may beincorrect. This situation only occurs around the times that the fundamentalcurrent is about to change direction. The result of incorrect compensation isthat the cross-over of the current through zero may be considerably distorted –even more than if compensation is not being applied. This issue has not beenresolved.

7.2.3 Some Inverter Applications

In this subsection we shall consider some of the applications for inverters. Thepresentation is by no means exhaustive, and the more common applications willbe highlighted.

7.2.3.1 Variable Speed Drives

One of the most common applications of inverters are in AC variable speeddrives. These drives are most commonly based on the use of induction machines.

Figure 7.3 shows the generic layout of an AC drive. As mentioned in sec-tion 7.1 Converter 1 in this figure is often a uncontrolled three phase rectifier(although if the supply is single phase then one could have a single phase recti-fier). Converter 2 is a conventional inverter, much as shown in Figure 7.4. Atlow powers and voltages the power devices in the inverter can be MOSFETs.At small to medium powers, the IGBT has become the device of choice. Therange of operation of the IGBT is extending all the time in terms of the currentsand voltages that can be handled. At the time of writing these notes IGBTs


Leg Bcurrents

Leg Acurrents

Leg Bswitching

Leg Aswitching

Top

Top

Top

Top

Bot

Bot

Bot

Bot

On

On

On

On

Off

Off

Off

Off

ibi

iai

i ib b

f i

=

i ia af i

=

0

0

0

0

Dead - time Td

Dead - time Td

Desired switching pointand actual switching point

Desired switching point

Actual switching point

Figure 7.11: Example of dead-time induced switching error in an inverter.


are available with maximum voltages of 6kV, and current capabilities in thethousand of amps range.

Variable speed AC drives are becoming ubiquitous devices these days. Theycan be found in anything from domestic air conditioners, washing machines andmicrowave ovens, right through to large drives in power station bag houses androlling mills. If better power sources are found, then AC drives will become veryprevalent in vehicular transportation. They are currently widespread in traintransportation.

The main driving factors towards the increasing use of inverters are:

a. The simultaneous arrival of low cost high performance microprocessors,as well as reliable, robust and reasonable cost power electronic devices inthe since the mid 1990s.

b. The refinement of the control algorithms for AC machines allowing highperformance from AC drives.

c. A community demand for more efficient use of energy.

Let us briefly consider a few of the applications mentioned above. It is notuncommon to hear in advertisements for air conditioners that they are inverterair conditioners. The inverter in these air conditioners are being used to drivethe compressor in a variable speed mode. Normally an air conditioner is drivenin an on-off mode, controlled by a thermostat. The reason for going to a variablespeed mode is that the compressor is much more efficient in this mode. When acompressor starts for the next 30 to 60 seconds it is not really pumping any heat,but simply compressing the refrigerant. If the compressor is being started andstopped on a regular basis this non-productive time will be a significant part ofthe total operating time of the compressor. Under variable speed operation thethermostat simply controls the speed of the compressor, but it does not stop.Therefore the refrigerant does not have to be re-compressed, since it does notdecompress whilst the compressor is running, albeit more slowly. Inverter airconditioners can be up to 30% more efficient as compared to the traditional on-off air conditioner (depending on operating cycle of the on-off air conditioner).

Another domestic appliance that now has an inverter in it is the microwaveoven. The inverter is used to supply variable voltage to the magnetron, andtherefore get true variable power instead of pulsed on-off 100% power as in aconventional oven. This is main motivated by better cooking performance at lowpower levels. In actual fact the so-called inverter circuit in a microwave oven ismore like a flyback switch mode power supply circuit. The switch mode supplycan be operated at high frequency, and therefore allow a smaller high frequencytransformer to be used. In addition, the output voltage and/or current can becontrolled allowing completely variable, constant power from the magnetron.

7.2.3.2 Grid Connected Applications

As the power electronic devices improve in voltage rating, grid connected ap-plications of inverters are becoming more common. The classic example of theuse of an inverter in a grid connected application is interfacing photo-voltaicsto the grid.


Inverter

DC AC

Utility

supply

Controller

Photo-voltaic

solar cells

Domestic

load

Figure 7.12: Generic non-battery based photo-voltaic supply system.

In a photo-voltaic interface, the solar cells are producing DC voltage whicheither has to be converted into AC to feed the utility grid, or converted to AC tosupply domestic AC appliances. Both of these are classic inverter applications.In some situations the output of the solar cells will firstly be fed to a bank ofbatteries for storage. It is then the DC in the batteries that is converted to AC.In other situations, the DC from the solar cells may be fed directly into the gridwithout the intermediate batteries (see Figure 7.12). This is the situation thatis common for non-remote properties that are connected to the main utility gridsupply. The inverter is its associate controller can either deliver power to thegrid, or take power from the grid, depending on the insolation falling on thesolar cells. In the case of remote properties, there in many cases will not be autility supply, and the inverter would be powering the household appliances.

A more industrial application of inverters is the static var compensator(SVC). A compensator is a device that can be connected to the power sys-tem to provide voltage support for the supply, especially at the end of longtransmission lines. This is achieved by the compensator being a variable ca-pacitor. Traditionally this was achieved by using a synchronous machine, andvarying the excitation to vary the apparent capacitive load represented by themachine. Later banks of switchable capacitors were used, the switching beingachieved by thyristors. More recently a traditional inverter has been used. Thiscircuit has the significant advantages over the previous techniques – injects lessharmonics into the supply, very rapid bumpless changes can be achieved, cancompensator for general power factor (i.e. can perform an active filter func-tion). Figure 7.13 shows some variants of the static compensator (STATCOM)offered by the Siemens company. Some of these devices do more than simplestatic var compensation, and are capable of real power flow control as well asreactive power flow control. AC transmission systems that include these powerelectronic devices are known as Flexible AC Transmission Systems (FACTS).

See the next chapter for much more details on grid connected applicationsrelated to renewable energy.


Statcom

Static Synchronous SeriesCompensator (SSSC)

Unified Power Flow Controller (UPFC) Back-to-Back Statcom

Figure 7.13: Some grid connected FACTS units offered by Siemens.


Figure 7.14: Conceptual diagram of a matrix converter.

7.3 Multilevel Converters and Applications

This section still has to be written

7.4 Basic Introduction to Matrix Converters

7.4.1 Introduction

Matrix converters are a converter type that does not have an intermediate en-ergy storage element. It is a converter that allows direct conversion of an ACwaveform of one frequency and magnitude, to a waveform of another frequencyand magnitude using only semiconductor switching elements.

The essential idea behind the matrix converter is that one has an arrayof switches that allow any input phase to be connected to any output phase.Figure 7.14 shows a conceptual diagram of a matrix converter. Note that theswitches in this figure have to conduct current bidirectionally and have to beable to block current in both directions. Currently most semiconductor switchesconduct current in both directions, but can only block current in one direction.Fortunately it is possible to combine these switches so that the composite switchbehaves as a bidirectional bi-blocking switch.

Remark 7.14 The fact that the matrix converter allows any input phase to beconnected to any output phase means that there is a lot of freedom with respectto the connections that can be made with this converter. However, this alsomeans that there are many ways that a short circuit can be created.

7.4 Basic Introduction to Matrix Converters 7-21

Figure 7.15: Reconfigured conceptual diagram of the matrix converter.

It is possible to reconfigure the switch arrangement shown in Figure 7.14 onpage 7-20 to that shown in Figure 7.15. This particular figure more graphicallyshows the “matrix” property of this converter.

Remark 7.15 Note that the gaps in the wires in Figure 7.15 are actually con-tinuous lines that run over the crossing line.

7.4.2 Switching Rules

There are 29 = 512 different combinations of the 9 possible switches. Howeverone has to restrict the combinations for electrical reasons. Typically the inputto a matrix converter is a voltage source, and the output load of the converter isan inductive load. Therefore the switching if the converter cannot short circuitthe input, and at the same time cannot attempt the open circuit the output.The rules that guide these restrictions can be summed up as:

• DO NOT connect two different input lines to the same output line. Thisis to prevent a short circuit between two or more phases.

• DO NOT disconnect the output lines – inductive currents will result invery high voltages across the switches.

Remark 7.16 The latter of these two rules means that output lines must beconnected to an input line at all times.

Remark 7.17 The fact that the output lines have to be connected to an inputline under all circumstances means that the state of the matrix converter can besymbolised with only three input values. For example, ‘ACC’ means that phase‘A’ is connected to ‘a’, phase ‘C’ is connected to ‘b’ and phase ‘C’ is connectedto ‘c’. Therefore the symbols used in this notation have positional relevance.

If the switching rules above are applied then the 512 possible switch states aredecreased to 27 permitted switch states, which have the following properties:


a. 3 states produce forward rotating space vector voltages. These states cor-respond to each output phase being connected to a different input phase.Therefore a space vector is produced that rotates at the mains frequency.

b. 3 states produce reverse rotating space vector voltages. This is the reversephase sequence of the previous set of states.

c. 18 states produce stationary space vector voltages of various amplitudes.This group occurs if two output phases are connected to a common inputphase, and the third output phase is connected to a different input.

d. 3 states produce zero space vector voltages. This corresponds to all threeoutputs being connected to the same input line.

Remark 7.18 Most modulation techniques for matrix converters have used thestates associated with points c and d above because of the difficulty of dealingwith the rotating vectors with the control techniques traditionally employed.

7.4.3 Switching – Some More Detail

7.4.3.1 Alesina/Venturini Modulation Algorithm

The information in this section mostly comes from a review paper on matrixconverters[16], and is reproduced here much as it is written, but with someadditional explanation where appropriate.

One can define the switching function for a single switch as:

SKj =

1, switch Skj closed0, switch SKj open

(7.39)

where K = A,B,C and j = a, b, c.The constraint above can be expressed mathematically as:

SAj + SBj + SCj = 1 (7.40)

which means that there always has to be a switched closed onto output phasej (i.e. no open circuits) and there can only be one switch closed onto outputj (i.e. no short circuits). This restriction leads to the 27 valid switching statesmentioned previously.

Remark 7.19 Equation (7.40) has to be true if the switches are truly bidi-rectional in current flow when they are closed. However, as we share see it ispossible to violate this condition if the switches have controlled bidirectional cur-rent flow – i.e. the switches are bidirectional, but via control the current flowdirection can be selected.

If the load and source voltages are referenced to the incoming supply neutralpoint (assuming that the supply is star connected), then the input and outputvectors can be expressed as:


vi =

vA(t)vB(t)vC(t)

(7.41)

vo =

va(t)vb(t)vc(t)

(7.42)

The relationship between the load and the input voltages using these definitionscan be expressed as follows: va(t)

vb(t)vc(t)

=

SAa(t) SBa(t) SCa(t)SAb(t) SBb(t) SCb(t)SAc(t) SBc(t) SCc(t)

vA(t)vB(t)vC(t)

(7.43)

vo = Tvi (7.44)

where T is the instantaneous transfer matrix.Similarly the relationships between the input and output currents can be

defined as:

io =

ia(t)ib(t)ic(t)

(7.45)

ii =

iA(t)iB(t)iC(t)

(7.46)

and:ii = T−1io (7.47)

where T−1 is the inverse transfer matrix.

Remark 7.20 Equation (7.43) essentially says that the output voltages of thematrix converter are simply related to the value of one of the input voltages. Notethat (7.40) indicates that at any point of time only one of the input voltages,vA,vB or vC can be connected to the output lines.

Remark 7.21 The obvious question to ask with respect to (7.43) is what is theswitching function to make the vo vector equation to the desired vref

o . Thereforea modulation strategy has to be defined.

Figure 7.16 shows the typical form of the switching for the matrix converterswitches [16]. Notice that each output phase is connected in order to one ofthe input phases in a repeating sequence. This means, for example, that inputphase A is connected to output phase a then input phase B is connected andfinally input phase C is connected, each one for a specific period of time definedby the modulation strategy.


Output

Phase a

Output

Phase b

Output

Phase c

SAa = 1 SBa = 1 SCa = 1

Repeats

SAb = 1 SBb = 1 SCb = 1

SAc = 1 SBc = 1 SCc = 1

Tseq (time sequence)

tAa tBa tCa

tAb tBb tCb

tAc tBc tCc

Figure 7.16: General form of switching pattern [16].

Let us define the duty cycle modulation function of one of the switches as:

mKj(t) =tKjTseq

(7.48)

where can take on the following values:

0 ≤ mKj ≤ 1 K = A,B,C, j = a, b, c (7.49)

One can now define a low frequency transfer matrix as:

M(t) =

mAa(t) mBa(t) mCa(t)mAb(t) mBb(t) mCb(t)mAc(t) mBc(t) mCc(t)

(7.50)

this matrix being a matrix of duty cycles.

Remark 7.22 Equation (7.50) is called a low frequency matrix because if weuse it to calculate the output then we are implicitly assuming that the outputvoltage is related to the duty cycle multiplied by the input voltage – i.e. we areconsidering the average output voltage over the control cycle of the converter(over Tseq).

Using (7.50) we can define the average output voltage vector as:

vo = M(t)vi(t) (7.51)

and the low frequency component of the input current is:

ii = M(t)T io (7.52)


Remark 7.23 One can see from Figure 7.16 on page 7-24 and the definition ofthe switch duty cycle in (7.48) that this means that the sum of the duty cyclescan only be one for any particular output line, i.e.

mAa(t) +mBa(t) +mCa(t) =tAaTseq

+tBaTseq

+tCaTseq

= 1 (7.53)

If this is expressed in matrix form it becomes:

M(t)1 = 1 (7.54)

where 1 is a column vector of ‘1’s. Note that this condition, together with thevalid switch condition (7.40) means that there is always a connection a particularinput line to an output line.

Summary 7.1 Summarising so far, the key expressions which the modulationmatrix must satisfy are:

v0 = M(t)vi (7.55)

ii = M(t)T io (7.56)M(t)1 = 1 (7.57)

If vi is not proportional to the vector 1 then (7.55) and (7.57) provide two in-dependent conditions on every row of the matrix M(t) while (7.56) provides onecondition on every column of M(t) [17]. Two more equations can be providedfrom Kirchoff’s current law and assuming that the converter is lossless:

iiTvi = io

Tvo (7.58)ioT1 = ii

T1 (7.59)

We have 9 unknowns in the form of the modulation functions. The input volt-ages and output currents are known measured variables, and the output voltagevo is a desired output voltage (if the objective is to obtain this desired outputvoltage). Between all of the equations above it is possible to get 9 independentequations, and therefore the system is solvable.

Let us consider a three phase system. Let the sinusoidal voltages at theinput be:

vA = Vi cos(ωit) (7.60)

vB = Vi cos(ωit+2π

3) (7.61)

vC = Vi cos(ωit+4π

3) (7.62)

and the assumed output sinusoidal currents:

ia = Io cos(ωot+ φo) (7.63)

ib = Io cos(ωot+2π

3+ φo) (7.64)

ic = Io cos(ωot+4π

3+ φo) (7.65)


Remark 7.24 Note that both the input voltages and the output current aremeasured and assumed respectively. The output current is assumed, because ifthe converter is driving a passive circuit then the output current is a functionof the output voltages, which are what we are trying to calculate.

The desired input currents are defined as follows:

iA = Ii cos(ωit+ φi) (7.66)

iB = Ii cos(ωit+2π

3+ φi) (7.67)

iC = Ii cos(ωit+4π

3+ φi) (7.68)

and the desired output voltages:

va = Vo cos(ωot) (7.69)

vb = Vo cos(ωot+2π

3) (7.70)

vc = Vo cos(ωot+4π

3) (7.71)

There is an existence theorem in [17] that defines the relationship betweenthe input voltage amplitude and the amplitude of the output voltage, and theamplitude of the output current and the input current. it states (fairly obvi-ously) that::

Vo ≤ Vi2

(7.72)

Ii ≤Io2

(7.73)

These relationships are related to the fact that the input voltages and outputcurrents are three phase 120separated sine waves, and the cross-over point ofthe sine waves is one half the amplitude of the sine waves. Since the waves canbe selected by the modulator at any time, this limits the output voltage to onehalf the amplitude of these waveforms.

The condition in (7.58) can be written as:

VoIo cosφo = ViIi cosφi (7.74)

∴VoVi

=Ii cosφiIo cosφo

(7.75)

Taking into consideration all these conditions the (7.55), (7.56)and (7.57)can be solved to give the modulation functions for this converter[17]:

M(t) =1

3α1

1 + 2qCS(0) 1 + 2qCS(− 2π3 ) 1 + 2qCS(− 4π

3 )1 + 2qCS(− 4π

3 ) 1 + 2qCS(0) 1 + 2qCS(− 2π3 )

1 + 2qCS(− 2π3 ) 1 + 2qCS(− 4π

3 ) 1 + 2qCS(0)

+

1

3α2

1 + 2qCA(0) 1 + 2qCA(− 2π3 ) 1 + 2qCA(− 4π

3 )1 + 2qCA(− 2π

3 ) 1 + 2qCA(− 4π3 ) 1 + 2qCA(0)

1 + 2qCA(− 4π3 ) 1 + 2qCA(0) 1 + 2qCA(− 2π

3 )

(7.76)


where:

CS(x) = cos(ωmt+ x)

CA(x) = cos[−(ωm + 2ωi)t+ x]

ωm = ωo − ωi

α1 =1

2[1 + tan(φi) cot(φo)]

α2 = 1− α1 =1

2[1− tan(φi) cot(φo)]

q =VoVi

with the added conditions:

α1 ≥ 0

α2 ≥ 0

0 ≤ q ≤ 1

2

The question that arises from the above analysis is: “How does one usethe expressions in (7.76) to come up with a switching strategy. It should beremembered that the modulating functions have been derived in the sense thatthe converter switching is at such a high rate that the duty cycles of the switches(i.e. them values in the matrix M) are a continuously changing set of values. Inreality this is not the case, and there is a finite switching frequency. However, asdiscussed in Chapter 1 on page 1-1 converters only work because of the averagingaction of the loads that the converter is connected under the assumption thatthe switching frequency is high enough that the switching harmonics producedare filtered by the load.

Based on these assumptions, the switching time for each of the switches can matrix converterswitching timebe written as:

δtKjk = TmKj(kT ) (7.77)

where δtKjk denotes the switching on time for switch Kj for the interval k. Notethat:

T jk =

n∑K=1

δtKjk (7.78)

which is simply a restatement of the condition in (7.57) saying that all the switchtimes for a particular output phase can only add up to be the switching period.

Remark 7.25 As mentioned in the previous discussion (7.77) only gives thecorrect output if the switching frequency satisfies:

fT =1

T ωi

2π,ωo2π

Remark 7.26 The equations presented immediately above are those originallydeveloped by Alesina and Venturini [17] and are for a system limited to an outputvoltage magnitude that is half the input voltage magnitude – i.e. Vo ≤ 0.5Vi.


This is quite a restriction on these systems. Fortunately it was subsequentlyshown that the output voltage could be improved by adding third harmonics of improved output

voltagethe form

vo3rd = −1

6cos(3ωot) +

1

2√

3cos(3ωit) (7.79)

to the reference voltages. If this is done then it was shown in [18] that:

Vo ≤ 0.87Vi (7.80)

and this is the theoretical maximum output voltage that can be obtained from adirect AC-AC converter system regardless of the converter architecture.

Remark 7.27 The solution of (7.76) is reasonably complicated, and is onereason why this technique is regarded by many as too complex. Nevertheless thetechnique presented in [17] is the foundation of all the subsequent work in thisarea.

7.4.3.2 Space Vector Modulation Techniques

Space vector modulation (SVM) is a well known modulation technique in con-ventional PWM inverters. It has the nice attribute that it is very amenableto digital implementation. As mentioned previously in point c and point d onpage 7-22 there are a total of 18 active stationary vectors that can be producedby the converter, and 3 zero vectors, giving a total of 21 useful vectors for theSVM application. The output voltage space vector and the input current spacevector are defined as[14]:

vo =2

3(va + avb + a2vc) (7.81)

ii =2

3(iA + aiB + a2iC) (7.82)

where a = ej2π3 and a2 = ej

2π3 . The nomenclature is as follows: ABC means

that input phase A is connected to output phase a, input phase B is connectedto output phase b and finally input phase C is connected to output phase c. Ascan be seen there is an implied positional dependency of the nomenclature, withthe first position being the connection to output phase a, the second to outputphase b, and the third position to output phase c. This compact notation canbe used because the input and the output have to be connected at all timesdue to the requirement that the current flow through the converter cannot beinterrupted.

In order to calculate the output voltage and the input currents for a partic-ular switch situation one has to apply the above definitions for the voltage andcurrent space vectors to the various 21 stationary vector switch configurations.

As an example of this consider the situation of the switches being ABB – i.e.input phase A is connected to output phase a, input phase B is connected tooutput phase b and input phase B is connected to output phase c. This meansthat input phase C is not connect to anything, and therefore there is no currentflow in this input phase. The output voltage phasor is defined by (7.81), andwith the ABB switch configuration then we can say that va = vA, vb = vB , and


vc = vB , therefore (7.81) can be written as:

vo =2

3(vA + avB + a2vB)

=2

3[vA + (−0.5 + j

√3

2)vB + (−0.5− j

√3

2)vB ]

=2

3(vA − vB)

∴ vo =2

3vAB (7.83)

Similarly one can calculate the input current for this switch configuration byapplying the definition of the input current space vector defined in (7.82) andrealising that for the ABB switch setting that iA = ia, iB = ib+ ic, and iC = 0,and that ia + ib + ic = 0:

ii =2

3(iA + aiB)

=2

3[ia + a(ib + ic)]

=2

3[ia + (−0.5 + j

√3

2)(−ia)]

=2

3(3

2− j√

3

2)ia

=2√3

1√3

(3

2− j√

3

2)ia

=2√3

(

√3

2− j 1

2)ia

∴ ii =2√3iae−j π6 (7.84)

Similar results can be obtained for all the other switch configurations. Table 7.5on page 7-30 shows these vectors and the output voltage and input current vectorangles for them.

These space vectors can be placed on a traditional space vector hexagon.These appear in Figure 7.17.

Remark 7.28 As can be seen from Figure 7.17 the hexagons are similar tothose for a conventional PWM inverter. However, one point that is not clearfrom these diagrams is that the length of the vectors are dynamic and dependenton the various instantaneous line-to-line voltages. Similarly the current vectorsare variable length and dependent on the instantaneous line currents.

Let us consider a situation where the desired voltage vector vo is in sector 1and the angle of the current vector ii is βi as shown in Figure 7.17. As we shallsee, in order to generate the average vo vector the switching vectors ±7,±8,±9


Switchingconfiguration

list

Switch connections vo αo ii βi

01 AAA 0 - 0 -02 BBB 0 - 0 -03 CCC 0 - 0 -+1 ABB 2

3vAB 0 2√3ia −π6

-1 BAA − 23vAB 0 − 2√

3ia −π6

+2 BCC 23vBC 0 2√

3ia

π2

-2 CBB − 23vBC 0 − 2√

3ia

π2

+3 CAA 23vCA 0 2√

3ia

7π6

-3 ACC − 23vCA 0 − 2√

3ia

7π6

+4 BAB 23vAB

2π3

2√3ib −π6

-4 ABA − 23vAB

2π3 − 2√

3ib −π6

+5 CBC 23vBC

2π3

2√3ib

π2

-5 BCB − 23vBC

2π3 − 2√

3ib

π2

+6 ACA 23vCA

2π3

2√3ib

7π6

-6 CAC − 23vCA

2π3 − 2√

3ib

7π6

+7 BBA 23vAB

4π3

2√3ic −π6

-7 AAB − 23vAB

4π3 − 2√

3ic −π6

+8 CCB 23vBC

4π3

2√3ic

π2

-8 BBC − 23vBC

4π3 − 2√

3ic

π2

+9 AAC 23vCA

4π3

2√3ic

7π6

-9 CCA − 23vCA

4π3 − 2√

3ic

7π6

Table 7.5: Switching values used in SVM.


§1;§2;§3

§4;§5;§6

§7;§8;§9

vo

®o

1

2

3

4

5

6

(a)

ii

¯i1

23

4

5 6 §1;§4;§7

§2;§5;§8

§3;§6;§9

(b)

Figure 7.17: (a) Direction of the output line-to-neutral voltage vectors for theactive switch configurations. (b) Directions of the input line current vectorsgenerated by the active switch configurations.


Output voltage sector1 or 4 2 or 5 3 or 6

Inputcurrentsector

1 or 4 +9 +7 +3 +1 +6 +4 +9 +7 +3 +1 +6 +42 or 5 +8 +9 +2 +3 +5 +6 +8 +9 +2 +3 +5 +63 or 6 +7 +8 +1 +2 +4 +5 +7 +8 +1 +2 +4 +5

I II III IV I II III IV I II III IV

Table 7.6: Selection of switching configurations for combinations of output volt-age and input current vectors.

and ±1,±2,±3 must be used. However, for the current vector to be a angle βithen vectors ±3,±6,±9 and ±1,±4,±7 must be used. In order to achieve thissimultaneously then only the vectors that are common to the two objectives canbe used, which is in this case ±7,±9,±3,±1. The ±8,±2,±6,±4 vectors arenot common between the two control objectives, and therefore cannot be used.If a similar process is carried out for all desired voltage vectors and currentvector angles then the active vectors in each sector can be compiled into a tableso that the vectors that can be used to control the current and the voltage canimmediately be seen. This appears in Table 7.6.

Remark 7.29 Note that only the positive vectors are listed in Table 7.6. Thishas implications on the calculated duty cycle times for the switches which allowsthe correct switches to be chosen under conditions where the negative vectorshave to be used.

Let us consider the use of this table by an example of the generation of aparticular output voltage vector and a particular input current angle.

Remark 7.30 The magnitude of the current is determined by the output voltageand the load that this voltage is applied across. The input current angle can becontrolled by the length of time that we switch onto each of the current vectors.We are able to satisfy both of these requirements because we have four availablevectors and four unknown lengths of time that these vectors are going to beswitched. Note that in the case of the voltage vectors, there is also the zerovector which is used to control the magnitude of the output voltage (and byimplication the input current).

The following discussion is with reference to Figure 7.18, which is a detailedpicture of sector 1 of Figure 7.171. This diagram shows the desired voltagevector vo being resolved onto the vectors that are obtainable from the switchingof the converter. As with all PWM type systems the vo is obtained in an averagesense by switching the converter to produce a vector of average length of |v′o|and |v′′o |. These two vectors in turn, as can be seen from Figure 7.18 result inan average vector vo as required. The vIo, vIIo , vIIIo , and vIVo vectors correspondto the vector numbers defined in Table 7.6, and are valid for the voltage andcurrent vectors both in sector 1.

In order to calculate the switching times we must firstly calculate |v′o| and|v′′o |. This is carried out using relatively simple trigonometry, which is repro-duced here so that the reader can see the process in detail. Let us firstly calculate

1We are also assuming that the current vector ii lies in sector 1 for this example.


vo

vIII

o; vIV

o

vI

o; vII

o

v0

o

v00

o

Sector 1

®o¼=3

±x

y

Figure 7.18: Derivation of the voltage components for a desired voltage spacevector.


|v′o| . We can write:

y = |vo| sinαo (7.85)

δx =|vo|√

3sinαo (7.86)

∴ |v′0| =δx

cos π3= 2δx =

2√3|vo| sinαo (7.87)

Using the notation of [19] this is expressed in terms of αo which is the angle ofthe vector relative to a reference axis that bisects the sector that the vector liesin. Therefore, we can write:

αo =π

6+ αo (7.88)

and substituting this into (7.87) and manipulating gives:

|v′o| =2√3|vo| cos(αo −

π

3) (7.89)

Similarly, for |v′′o |we can write:

|v′′o | = |vo| cosαo − δx

= |vo| cosαo −|vo|√

3sinαo

= |vo| (cosαo −1√3

sinαo)

=2√3|vo| (

√3

2cosαo −

1

2sinαo)

=2√3|vo| (cos

π

6cosαo − sin

π

6sinαo)

∴ |v′′o | =2√3|vo| cos(αo +

π

6) (7.90)

Using (7.88) we can write (7.90) as:

|v′′o | =2√3|vo| cos(αo +

π

3) (7.91)

Equations (7.89) and (7.91) allow us to write the space vectors for thesevectors, not only for sector 1, but also for the other sectors as:

v′o =2√3|vo| cos(αo −

π

3)ej[(Kv−1)π3 +π

3 ] (7.92)

v′′o =2√3|vo| cos(αo +

π

3)ej[(Kv−1)π3 ] (7.93)

where Kv = 1, 2, 3, · · · , 6 and −π6 < αo < π6 , and the ej[(Kv−1)π3 +π

3 ] andej[(Kv−1)π3 ] and unit vectors in the direction of the respective space vectors.

Let us define the duty cycle of a particular applied voltage space vector:

mγ =tγ

T(7.94)


where γ , I, II, III, IV . Thereforemγ is the duty cycle of one of the particularswitching vectors for the matrix converter.

As can be seen from Figure 7.18, v′o and v′′o are composed by switching onthe output vectors vIo and vIIo (for v′o) and vIIIo and vIVo (for v′′o) 2for certainperiods of time over the switching period. Realising this we can write thealternate expression for these vectors as:

v′o = vIomI + vIIo m

II (7.95)v′′o = vIIIo mIII + vIVo mIV (7.96)

Remark 7.31 Clearly substituting (7.92) and (7.93) into (7.95) and (7.96) onehas two equations with four unknowns (the m duty cycles). The other two equa-tions come from considering the angle of the current. Note that the magnitudeof the current is controlled by the output voltage and the load.

Now let us consider the control of the input current angle. Since we are onlycontrolling the angle of the current, and not its magnitude, then we have toformulate an expression in terms of the desired current angle.

Remark 7.32 The principle used to get the equations for the current angle isthat the duty cycle equations for each for the switched current vectors has to leadto a zero orthogonal component of current to the desired angle of the current.If this is the case then the only components of current must be in the desireddirection of current. The magnitude of the current (as mentioned previously) isnot, and cannot be controlled.

Firstly let us write the duty cycle expressions for the switching components ofthe current vector ii:

i′i = iIimI + iIIi m

II (7.97)i′′i = iIIIi mIII + iIVi mIV (7.98)

where iI,II,III,IVi are the current vectors for the particular sector as defined inTable 7.6. The direction of the desired current vector is defined by the unitvector ejβi . Therefore the vector that is orthogonal to the desired vector isjejβi . Therefore we have to ensure that both i′ijejβi and i

′′i je

jβi are zero, or inother words: (

iIimI + iIIi m

II)jejβiej(Ki−1)π3 = 0 (7.99)(

iIIIi mIII + iIVi mIV)jejβiej(Ki−1)π3 = 0 (7.100)

where βi is measured from the reference axis that bisects the sector that thecurrent vector lies in, and Ki = 1, 2, · · · , 6.

We now have with equations (7.95), (7.96), (7.99) and (7.100) four indepen-dent equations with four unknowns – the mI,II,III,IV duty cycles. The ma-nipulations to solve these equations are tedious and messy, and the end result

2These are the vectors as defined in Table 7.6.


is[20]:

mI = (−1)(Kv+Ki+1) 2√3q

cos(αo − π3 ) cos(βi − π

3 )

cosϕi(7.101)

mII = (−1)(Kv+Ki)2√3q

cos(αo − π3 ) cos(βi + π

3 )

cosϕi(7.102)

mIII = (−1)(Kv+Ki)2√3q

cos(αo + π3 ) cos(βi − π

3 )

cosϕi(7.103)

mIV = (−1)(Kv+Ki+1) 2√3q

cos(αo + π3 ) cos(βi + π

3 )

cosϕi(7.104)

where ϕi is the desired phase angle between the current vector and the inputvoltage vector (which is measured), and q ,the instantaneous voltage transfer

ratio, which is q =|vo||vi|

. Therefore ϕi = αi − βi where αi is the angle of the

input voltage relative to the bisecting reference on the current vector hexagon.

Remark 7.33 One can see from the (−1)(Kv+Ki+1) and (−1)(Kv+Ki) that oneof the duty cycles can be positive and the other negative. A negative duty cyclemeans that the negative vector is chosen (e.g. -9 instead of +9 if in sector 1 forthe voltage).

Remark 7.34 Another constraint on the feasibility of the strategy is that thesum of the absolute values for the four duty cycles must be lower than unity – inother words the one times for the various vectors have to be less than the controlperiod. This can be written mathematically as:∣∣mI

∣∣+∣∣mII

∣∣+∣∣mIII

∣∣+∣∣mIV

∣∣ ≤ 1 (7.105)

If this condition is less than one, then the remainder of the time is filled byapplying a zero voltage vectors.

If (7.101)–(7.104) are substituted into (7.105) and some manipulations are car-ried out one can get the following expression:

q ≤√

3

2

|cosϕi|cos βi cos αo

(7.106)

which is the theoretical maximum instantaneous voltage transfer ratio. There-fore at any point of calculating the duty cycles one cannot be demanding avoltage transfer ratio larger than this value. In the case of balance supply volt-ages and output voltages, the maximum transfer ratio occurs when (7.106) is aminimum (which implies cos βiand cos αo are equal to 1, which in turn impliesthat the power factor of the load is unity) which gives:

q ≤√

3

2|cosϕi| (7.107)

which has the theoretical maximum value for matrix converter of 0.866 underthe condition of unity power factor.


Remark 7.35 Having the ability to control the input power factor to be otherthan the output power factor comes at the price of decreased output voltage. Onecan see from the denominator of (7.106) that if cos βi = cos αo = 1 this meansthe ˜αo−βi = π/6 then the output power factor is unity (i.e. cosϕo =

√3/2 =

0.866). If the input power factor is also unity then cosϕi = 1 and thereforeq ≤

√3

2 . This demonstrates that it is the change of the input power factor thatresults in the loss of the voltage transfer ratio. If other input power factors arerequired then the voltage transfer ratio will decrease from this value.

Once the duty cycles have been calculated then the firing sequence of the deviceshas to be determined. Consider the situation that we have investigated as anexample above – i.e. the desired output voltage vector and in the input currentvector lie in sector 1. We shall assume that the active switching sequence isto achieve the desired output voltage and input current power factor is +1, -3,-7, +9. The other vectors that come into play here, depending on the outputvoltage magnitude, are the zero vectors. It can be verified that there in only oneswitching sequence characterised by one one switch commutation for each switchchange, and that is 03,−3,+9, 01,−7,+1, 02. If one uses this switching sequencein a double sided symmetrical switching pattern (as is done for traditional PWMinverters), then the switching pattern is simply this switching pattern reversedfor the second half of the cycle. Figure 7.19 shows the switching pattern andthe associated duty cycles and switches used. Note that in this diagram theswitching times for the particular vectors are denoted as tζ where ζ is the vectornumber – i.e. 3, 9, 7 etc. As can be seen from the figure there are 12 switchingover one control cycle. This switching technique is called a symmetrical SVM,and utilises all of the zero switching sequences. An alternative is to use anasymmetrical switching sequence which only uses one of the switching sequences.In this sequence the switches of one of the columns in Figure 7.15 on page 7-21 do not change state, and the number of switch commutations in each cycleperiod is reduced to 8 (SAa, SBa, SCa are always on).

7.4.4 Implementation Issues

Thus-far we have considered issues related to the modulation strategies for thematrix converter. Throughout this discussion the interested reader has probablybeen asked themselves the questions: “but how does one implement all of this”?There are a number of different aspects that must be addressed to answer thisquestion. We shall probably present the most important of these.

7.4.4.1 Bidirectional Switches

The switches used in matrix converters are bidirectional as discussed in theinitial introduction. Most of the common semiconductor switches available onthe market are only capable of blocking current in one direction. In order toimplement a matrix converter one must have a bidirectional switch.

There are several ways to design bidirectional switches using technologiesthat can only block in one direction. Figure 7.20 shows a technique that involvesthe use of only one switch, but required four diodes. The function of the diodesis to direct the current only into the collector of the IGBT so that it is alwayspresented with a positive voltage at this terminal.


T

2

T

2

03 ¡3 +9 01 ¡7 +1 02 02 +1 ¡7 01 +9 ¡3 03

t03

2T

t2

2T

t9

2T

t01

2T

t7

2T

t1

2T

t02

2T

t02

2T

t1

2T

t7

2T

t01

2T

t9

2T

t2

2T

t03

2T

C

C

C

C

C C

a

b

c

Output

phase

A

A A

A A A A B

A B B B

BA B

B

B

B

A

B

B

A

B

A A

A

A C

A

A

C

C

A C

C

C

mCa

2

mAa

2

mBa

2

mCb

2

mAb

2

mBb

2

mAa

2

mAc

2

mBc

2

mBa

2

mAa

2

mCa

2

mBb

2

mAb

2

mCb

2

mBc

2

mAc

2

mAa

2

Figure 7.19: Double sided switching sequences for a matrix converter over onecontrol cycle.

Figure 7.20: Diode bridge bidirectional switch cell.


Common emitter Common collector

Body diode

Figure 7.21: Common emitter and common collector back-to-back bidirectionalswitches.

Remark 7.36 The diode switch cell has the advantage that only one switchingdevice is required. This minimises the number of gate drivers required for thesystem. However there are two significant disadvantages of this arrangement:

a. When the device is on there are three series devices – i.e. two diodes andthe IGBT switch itself. Therefore the losses in the switch are higher thanother strategies.

b. When the switch is turned on there is no way of controlling the directionof the current through the cell – i.e. the cell operates as a normal switch.The inability to control the current direction has implications with respectto commutation strategies.

The above two disadvantages are important enough that this cell is not commonlyused.

The common emitter and common collector switch cells are shown in Fig- common emit-ter and commoncollector switchcells

ure 7.21. This cell arrangement consists of two diodes and two switches con-nected in anti-parallel. The diodes are required to provide the reverse blockingcapability.

Remark 7.37 There are several advantages of the common emitter /collectorswitching cells compared to the diode based cell:

a. There are only two devices in the conduction path, therefore the switchesare more efficient.

b. The current direction through the device can be controlled. This occursbecause the appropriate switch has to be turned on for current to conductin the forward direction for this switch. This ability is used in the com-mutation algorithms as we shall see later.


The most obvious disadvantage of these cells relative to the diode cell is thatthey have two active devices.

The choice of the use of the common emitter version of the switch cell versusthe common collector version is no immediately obvious. In the case of thecommon collector version, the emitters of the switching devices are connectedto the incoming and outgoing lines of the converter. Therefore one needs threeisolated power supplies with the common for each of the supplies connectedto one of the three incoming lines, and three isolated power supplies with thecommon of each of them connected to the one of the three outgoing lines.

Practical issue 7.1 In practice the use of only six isolated supplies for thecommon collector bidirectional switch is not viable because of the need to min-imise stray inductance.

The common emitter version of the switching cell requires on isolated powersupply for each switching cell (i.e. a total of nine). The common emitters formthe ground point for the supply. The common emitter cell is the one mostcommonly used.

The above discussion has been with respect to implementing the bidirectionalcells using discrete components. It is also possible to build an integrated matrixconverter module, similar to the intelligent power modules used for three leginverter systems. This has been done by EUPEC using devices connected in thecommon collector configuration, and is now commercially available. this type ofpackages has distinct advantages relative to discrete layouts in the lower strayinductances.

The switching devices (IGBTs) discussed thus-far, due to the presence ofparasitic internal diodes, do not have reverse blocking capability. However,devices such as the MOS turn-off thyristor (MTOs) do have reverse blockingcapability, and therefore the bidirectional switch can be built using two devicesin anti-parallel.

7.4.4.2 Current Commutation

Basic switching rules were outlined in Section 7.4.2 on page 7-21 which reducedthe possible 512 switching combinations down to 27. These switching rulesarose from electrical considerations of various switch combinations. Howeverthese same electrical considerations also have an influence on the commutationfrom one switch combination to another.

Remark 7.38 “Reliable current commutation between switches in matrix con-verters in more difficult to achieve than in conventional VSIs since there are nonatural freewheeling paths”[16].

To understand the issues consider Figure 7.22 which shows two different situa-tions of two input phases and one output phase and commutation is occurringfrom one input phase to another. In Figure 7.22(a) both the switches havebeen closed onto the same output leg. Clearly this will result in a short circuitcommutationbetween the two input phases and consequent destruction of the switches. Fig-ure 7.22(b) shows the alternative situation where both the switches have beenopened. If the switches were carrying current at the time that were opened theinput and output inductances would result in a very large voltage spike anddestruction of the switch.


SW1

SW2

Load

SW1

SW2

Load

(a) (b)

Figure 7.22: Short and open circuit situations that can occur during commuta-tion.

Practical issue 7.2 Any practical commutation strategy has to avoid both thesituations shown in Figure 7.22.

In order to avoid the situations that are shown in Figure 7.22 a number ofdifferent commutation strategies have been devised. Two obvious ones are:

• break before make approach – the outgoing switch is opened before theincoming switch is closed. This prevents the short circuit situation, butbecause there is an overlap period when both switches are open (to accountfor the charge storage turn-off delays of the semiconductor switches) thenhigh voltages can occur due to inductive effects. Extra clamping circuitryis required to prevent these voltages from getting too high.

• make before break approach – this is the dual of the previous case andresults in a momentary short circuit between the phases. One needs inter-phase reactors to prevent the short circuit during the switching transient.These inter-phase reactors can be quite large.

These two strategies, whilst they work, are not all that satisfactory for thereasons cited above. This lead to the development of the 4 stage commutationprocess, with the step being:

a. Turn off the off-going non-conducting switch. This prevents current re-versal, which could otherwise occur during the rest of the commutationprocess.

b. Turn on the on-going conducting switch. At this point one has the off-going conducting switch on, and the on-going conducting switch on. Ashort circuit is not generated because the process is utilising the fact thatone can control by the choice of device in the switch cell to activate thedirection of the current that can flow through the switch cell.

c. Turn off the off-going conducting switch. The on-going conducting switch,


VA

VB

SAa1

SAa2

A

B

Load

SBa1

SBa2

iLa

Va

Figure 7.23: Two phase switching matrix example.

if it wasn’t already conducting the current3, will now be forced to conductthe load current.

d. Turn on the on-going non-conducting switch. This then allows naturalcurrent reversal to occur through the switch if required.

In order to understand this process in more detail consider Figure 7.23 of twoswitching cells connected to two phases and a single output line. The state andtiming diagram for the commutation process is taken directly from [16], andappears in Figure 7.24. The nomenclature iL > 0 means that the current isin the direction shown in Figure 7.23. Once can see from Figure 7.24 that theswitching sequence proceeds through the four steps outlined above. Notice thatthere is a point where SAa1 ad SBa1 are both closed. However, a short circuitcannot develop because the SXa1 switches can only carry the iL current in thedirection shown in Figure 7.23. Therefore if VA > VB then the diode in serieswith SBa1 will ensure that the device is turned off and no short can develop.SBa2 is already off as we have not turned it on. Similarly if VB > VA then SAa1

will be off, and SAa2 has not been turned on.

Remark 7.39 One can see that the four stage commutation process exploitsthe fact that the switches have the extra degree of freedom at that direction ofcurrent flow through the switch is under direct control.

Remark 7.40 One variant of this technique is to only gate the conducting de-vice. By doing this the sequence can be shortened since the initial (1100) stateis not there, but instead it is (1000). Similarly the final state in the exampleof Figure 7.24 becomes (0010). Therefore only the top path of two transitionsoccurs.

3The on-going conducting switch may not have been conducting current because the voltageacross the on-going switch device may be been such that the device is effectively reverse biased.


SAa

SBa

SAa1

SAa2

SBa1

SBa2

td

1

1

0

0

1

0

0

0

1

0

1

0

0

0

1

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

0

1

0

0

0

1

0

1

0

0

0

0

1

0

1

0

0

0

1

0

1

Transitional statesSteady

state

Steady

state

iL > 0

iL < 0

X

X

X

X

)

SAa1

SAa2

SBa1

SBa2

Timing diagram iL > 0

State transition diagram

1

10

0

Figure 7.24: Four step commutation process between bidirectional switch cellsin Figure 7.23.


Practical issue 7.3 One practical issue with the four stage and two stage com-mutation sequences is that they rely on accurate knowledge of the current direc-tion in order to determine which devices to turn on. This is particular the casewith the two stage process, as there is no natural current reversal in this se-quence (i.e. the two anti-parallel devices in the switch are no both actively gatedat the same time). One simple technique used to prevent problems is to no carryout any commutation when the absolute value of the current is below a certainvalue. This prevents ambiguity of current direction form upsetting the commu-tation. However this technique results in distortion at low currents. There areother techniques using voltage measurements across the devices that solve thisproblem

7.4.4.3 Input Filters

Filters are required at the input of a matrix converter in order to reduce theswitching harmonics present in the input current. This filter must have thefollowing characteristics[16]:

a. have a cutoff frequency lower than the switching frequency of the con-verter;

b. minimise it reactive power at the grid frequency;

c. minimise the volume and weight for capacitors and chokes;

d. minimise the filter inductance drop at rated current in order to avoid areduction in the voltage transfer ratio.

The matrix converter was originally envisaged as a pure silicon converter solu-tion, however in reality the passive filtering components become a significantpart of the design. It has turned out in some converter designs that the LCcomponents of the filter have been comparable in size to those required for aconventional DC link based inverter.

An addition issue related to the input filters is that they can cause transientover-voltages on start-up due to ringing of the filter. In order to prevent thisseries resistors are used during the start-up phase, and these are shorted oncethe converter is running. Figure 7.25 shows a matrix converter with the LCinput filters. Notice the damping resistors at the input.

7.4.4.4 Over-voltage Protection

Over-voltages can occur in matrix converters for the following reasons:

• input voltage transients interacting with the input filters;

• interruption of over-current faults when the load has inductance.

The usual solution to this problem is to connect a diode based clamping cir-cuit to the input and output of the converter. Figure 7.26 shows this generalconfiguration. As can be seen it is simply a rectifier circuit. Because a con-ventional converter already has such a circuit as an implicit part of its design,there is no need for an explicit protection circuit. There are some other “moreclever” strategies that are employed that try to achieve the same result with lesscomponents.


SAa SAb SAc

SBa SBb SBc

SCa SCb SCc

A

B

C

a b c

Figure 7.25: Matrix converter input filters and damping resistors.

Motor

+

Matrix

Converter

Diode clamp circuit

50Hz

supply

LC filter

Figure 7.26: Matrix converter with over-voltage diode clamp protection.


7.4.5 CommentsAfter almost three decades of research the modulation and commutation strate-gies and control methods for the matrix converter are reasonably mature. Twoearly drawbacks of the converter were the lack of a suitably packaged bidirec-tional switches and the large number of semiconductor switches required. Overrecent years these limitations has largely been overcome with the introductionof power modules which include the complete power circuit. A remaining issueis the size of the passive filtering components in the converter – the dream of apure silicon converter has not been realised. Research is continuing on reducingthe size of the filtering components.

When introduced approximately 30 years ago the matrix converter has thepotential to be a superior converter, in that one had a bidirectional converterwhich could control harmonics at the input and output, as well as the inputpower factor. However, in the intervening years other converters did not standstill, and the active front end (AFE) on the conventional inverter also offers thesame capabilities. This is a variant of a very mature technology. In addition theAFE inverter also has implicit ride through capability when there are supplydips due to the presence of a DC link capacitor.

As it stands at the moment the matrix converter is used for niche applica-tions. The US military are investigating its use in the electric tank, where itscompact size and robust because of the absence of a DC link capacitor may bean advantage. A motor and drive manufacturer has also integrated a matrixconverter into a motor frame, where again the lack of a large DC link capacitoris an advantage.

Chapter 8

Grid Connected Convertersand Renewable EnergySystems

8.1 Introduction

An excellent resource for this chapter is the new book [21]. This book concen-trates specifically on issues related to the use of converters to interface photo-voltaics and wind turbines to the electricity grid. Although it has been writtenfrom a European perspective, nevertheless most of the material is relevant toAustralia. Much of the material in this Chapter is based on content from thisbook.

The clean production of energy is becoming increasingly important. In factthe production of low cost, environmentally friendly energy is probably thegreatest challenge of our time. The consensus amongst creditable climate sci-entists is that man made greenhouse gases are a significant contributor to thecurrently measured rise in global temperature. Therefore low or zero emissionproduction of energy is going to become increasingly important as we move intothe future. Even if one is skeptical about the climate science, the sustainableuse of the earth’s resources is a worthy goal in its own right.

The availability of low cost energy and a system to distribute this energy isa key contributor to the lifestyle that we enjoy. It will also be a key factor inchanging the lifestyles of those in the 2nd and 3rd world as they move towardsthe lifestyle which we enjoy. Therefore the current issues surrounding clean lowcost energy are not going to go away – to the contrary they will be exacerbated.We can all see this happening with the rapid development of China and India.These factors mean that the issues that will be discussed in this Chapter are ofincreasing importance.

This Chapter will not be attempting to consider the complex economic fac-tors that surround the transformation of the worlds energy production systemsaway from fossil fuels, and towards sustainable sources. Instead it will concen-trate at a much lower level on the technical issues of how to interface renewablesources to the electricity grid. Issues associated with the control of an electricity

8-2 Grid Connected Converters and Renewable Energy Systems

grid with high renewable penetration will only be considered in the form of gridcodes that are still under development.

The remainder of this section will consider the current statistics related tothe use of wind power and photovoltaics.

8.1.1 Wind Power

Wind power is a fairly mature technology for renewable generation. The nicefeature about this technology is that energy can be available at all times of theday (although wind resources tend to be more available during the day time).This technology developed first because, in principle, the technology requiredhas been known for a long time – blade design, induction generators, towers.The use of power electronics in wind power has been a more recent developmentas power electronics became cheaper, and the demands on the wind turbinesmotivated the exploration of the use of this technology.

Even though wind power is a mature technology, the cost of the energy haslimited its penetration in many countries. Without subsidies it was simply tooexpensive compared to the fossil fuel technology. This is particularly the situa-tion in Australia. The situation is Europe has been somewhat different, wheresubsidies have been available for many years in countries such as Denmark. Gov-ernment support for wind power technology lead to the development of a windturbine industry in Denmark that is now selling turbines on the internationalmarket.

8.1.2 Photovoltaics

Photovoltaics is also a fairly mature technology for renewable energy. Havingsaid that, its degree of penetration is nowhere near that of wind, although itis growing. Surprisingly, Europe has a fairly high penetration of photovoltaicseven though in many parts of Europe there resource is not that good. Of theEuropean countries, Germany has the most PV systems installed.

Australia has excellent solar radiation resources, but as yet has not exploitedthis to the extent that the resource availability would indicate. However, this ischanging as more domestic photovoltaic systems are being installed (supportedby generous government subsidy schemes), and some large scale solar arrayprojects are in the offing.

8.1.3 Outline and Scope of this Chapter

This chapter, by virtue of the fact that it is only a small part of a general courseon power electronics, is limited in scope and depth. Having said that, it willattempt to at least cover, to some degree, the key issues in the use of convertersto interface photovoltaics and wind turbines to the grid.

It should be noted that this Chapter concentrates on the technical aspectsof grid interfacing, and the politics and economic aspects of renewables is notthe main focus.

Note 8.1 The presentation in this chapter is limited to grid interfaced systems.The other class of systems that use renewables are microgrid systems. These aredistinguished by the fact that they operate separate from a large infinite bus that

8.2 Photovoltaic Inverters 8-3

is the grid system. This fact leads to a lot of interesting control issues, some ofwhich are:

• getting converters to share load on the grid;

• issues related to handling the variable input energy available in wind andsolar systems when there is not the large reverse of the gird there to bufferout these variations;

• reliability and security of supply;

• power quality issues.

There are also broader issues involved in these systems as well. Because oneis not constrained by the grid then, for example, consideration can be given towhether the underlying system of the microgrid is DC voltage based. n

With both photovoltaic and wind turbine interfacing the same topics will becovered. Grid requirements, as legislated, will be briefly introduced and theirsignificance highlighted. Then the specific issue of synchronizing the controlstrategies to the grid system will be introduced. This is very much a specific de-tail, but of great practical importance for the development of high performancecontrol strategies. Basic control strategies for grid connected power electronicsystems will be introduced, and some of the higher level control strategies thatsit on top of the basic algorithms will be introduced (such as Maximum PowerPoint Tracking for Photovoltaic systems).

This Chapter will hopefully give you a feeling for how power electronics isan enabling technology for the introduction of renewable energy systems.

8.2 Photovoltaic Inverters

8.2.1 Review of Power Electronic Configurations for GridConnected Converters

There are a number of possible topologies that can be used for photovoltaicconverters. These topologies can be divided into two broad categories based onwhether they are:

• Three phase converters – generally used in high power photovoltaic appli-cations

• Single phase converters – generally used in domestic and lower powerapplications

These two categories can then be further divided into two main types of con-verter topologies:

• Galvanically isolated converters

• Non-galvanically isolated converters

Galvanic isolation is typically achieved by either using a mains frequency trans-former on the mains frequency side of the converter, or alternatively using a highfrequency transformer as part of a DC-DC converter in the midst of the overall


converter structure. Sometimes a boost converter is required in a photovoltaicconverter system (if the voltages from the panel are no sufficient to connect tothe mains), and consequently galvanic isolation is achieved as a byproduct ofthis.

In Australia up until relatively recently most domestic scale photovoltaicconverters were galvanically isolated – usually with a mains frequency trans-former placed on the grid side of the output filter. This was the general practicebecause of the obvious safety benefits associated with isolation of the PV arrayfrom the mains supply that occurs with such an arrangement. In Europe thesituation is different, with non-isolated domestic PV converters being common-place for some 15 or more years.

One obvious question to ask at this juncture is: “What are the pros and consof galvanic versus non-galvanic isolated converters?” The obvious pro of thetransformer based systems is the safety that ensues from its inclusion. Howeverthere is (literally) a price to pay for this, namely:

• Higher cost for the converter.

• The unit is bulky and heavy.

• The converter loses about 1% to 2% in efficiency due to transformer losses.

The safety issue is still there, but set against this is the fact that transformerlessconverters have been used safely in Europe for over 15 years, and their voltagesare in many case similar to ours. So the balance of safety versus economicand efficiency gains has seen the increased use of transformerless systems inAustralia [22].

In addition to the particular hardware architecture of the inverter there isa hierarchical control structure to control. A generic hardware and controlstructure block diagram is shown in Figure 8.1. Not all PV systems will haveall of the hardware components. For example, if the PV string can produce highenough voltages then the boost converter stage may not be required, and as wehave noted some converters are directly connected to the grid, and thereforethere is no transformer present.

The main hardware components of the PV system are fairly obvious. Ofcourse there are the PV panels themselves. They are usually connected togetherin a string so that an appropriate voltage is generated from the array. Whatis an appropriate voltage? In many cases this will be a voltage that will givesufficient headroom in voltage to allow a DC-AC conversion to the grid withouthaving to have a boost converter. The presence of the boost converter obviouslyleads to extra complexity and lowers the efficiency of the system.

The boost converter, as eluded to in the previous paragraph, is required ifthe PV string voltage is below the voltage required for the DC-AC conversion.There may be a variety of reasons for this being the case, and depends on theapplication.

The next component in the hardware structure is the DC-AC converter.There is a variety of structures that can be used for this component of thesystem, the details of which are the main subject of most of this Chapter.Whatever the DC-AC converter is, the next component is a filter. In the case ofthe diagram it is shown as an LCL filter as it is the most common filter used forthis application. The filter is the purpose of removing the switching harmonics


from the output waveforms so that grid harmonic standards are satisfied. Noticethat the AC feedback measurements occur after the filter so that there are noswitching harmonics to corrupt them.

Remark 8.1 It should be noted that the LCL filter is a more elaborate filter. Insome cases a simple inductor suffices in order to achieve the filtering required.The use of this has the added advantage that the dynamics introduced by thefilter are less complex, which simplifies the control. n

The control structure in Figure 8.1 is quite complex, and is one of the featuresof PV power electronic systems that set then apart from variable speed drives.The control in the PV case in some senses is more complex than variable speeddrive control – the PV systems have a deeper hierarchical structure.

The PV control is divided into a number of sub-blocks:

Basic grid control This block as the name implies, provides the basic controlfunctions to interface the inverter onto the grid. It allows synchronizationof the converter output voltages to the grid voltage, controls the DC linkvoltages so that enough voltage is available for the current control to work.These functions have a lot of similarity to variable speed drive convertercontrol functions.

PV specific functions This block contains a number of control functions thatare unique to the PV application – MPPT (Maximum Power Point Track-ing) is the name given to a class of algorithms that control the currentfrom converter so that the maximum power is obtained from the PV ar-ray under all irradiation conditions; anti-islanding protection is requiredto detect if the a circuit breaker has been opened on the grid isolating thesection of the grid where the PV array is. The PV array should discon-nect under this condition; and finally some monitoring functions of thePV array itself to check on cell performance.

Ancillary functions These are high level functions that may or may not beperformed depending on the sophistication of the PV system. For ex-ample active filtering of harmonics can be performed; micro-grid controlfunctions such as control of Vars or power factor at the connection pointto the grid.

Note 8.2 In this chapter we shall only be considering in detail the basic con-verter functions in this control hierarchy. n

8.2.1.1 How do photovoltaic devices work?

In this section we will briefly consider the basic mechanism that allows a semi-conductor diode to generate a voltage, conduct current, and ultimately generatepower. This is provided simply as background material, and is not really essen-tial to know with respect to the power electronics side of the system. However,as a philosophical point, engineerings should not be considering systems to beblack boxes, and hopefully your natural curiosity will have you asking the ques-tion as to how this all works. You should have enough background from yourbasic semiconductor Physics courses to understand the basic principles of oper-ation.


PVPanelsstring

DC-DCBoost

converter

DC-ACPWM-VSI

LCLLowPassfilter

X’formerandGrid

VDCcontrol

Gridsynchronization

Currentcontrol

Basic grid connected converter functions

MPPTAnti-islanding

protectionGrid/PV plant

monitoringPV specific functions

Active filter functions

Micro-grid control

Grid support (V/F/Q)

Ancillary functions

IPV VPV PWM PWMVDC

Ig

Vg

+

Figure 8.1: Block diagram of a generic PV system [21]

Remark 8.2 Even though I have just stated that knowing the fundamental op-erational principles of photovoltaics is not really necessary for this course, theseprinciples have a profound influence on the control strategies used for photo-voltaic systems. The VI relationship of a solar cell, which is irradiation depen-dent, is non-linear. It means that there is a optimal point of operation to get themaximum power out of a cell for a particular irradiation level. The algorithmsto find this point at called Maximum Power Point Tracking (MPPT) algorithms,and they are used to determine the current set points for the power electroniccontrollers that interface to PV array to the grid or load. n

Remark 8.3 Another influence that the basic operation of a solar cell has onthe design of a power electronic system is related to the number of convertersin a large system. The irradiation on large arrays of solar cells in many caseswill not be uniform due to partial shading from clouds for example. Partiallyshaded cells become a loading on the other cells in a series string, and reducethe efficiency of the system. This can be partially catered for if the cells areconnected together into smaller arrays where maximum power point trackingcan be applied to each subsystem separately. n

Figure 8.2 shows the band gap diagram of a pn junction (i.e. a diode bandgap). As can be seen from the diagram the doping to produce the p and nmaterials effectively moves the Fermi level of the semiconductors. Since the pand n materials are connected together then the only stable situation is thatthe Fermi level is constant on both sides of the junction. This is forced bydiffusion which is a consequence of the different concentrations of holes andelectrons in the materials due to the doping. As a result of this diffusion processand electric field is developed in the material which drives the carriers in theopposite direction to the diffusion process. The equilibrium is reached when the


Fermi level

Centre ofjunction

Spacechargeregion

n semiconductor p semiconductor

Photon

Valence band

Conduction band

Hole

Electron

ForbiddenEnergy

gap

Metalohmic

contacts

Metalohmic

contacts

Figure 8.2: Band gap diagram of a solar cell (pn junction).

drift due to the space charge equals the diffusion current. The voltage producedby the electric field ε is the contact potential of the diode, and is typically 0.6to 0.7 volts for Silicon.

Remark 8.4 Normally the contact potential cannot be seen from the outsideof the diode. If one places, for example, a voltmeter on the diodes terminalsone will not see any voltage and no current will flow. The metal-semiconductorcontacts of the probes on the semiconductor essentially cancel the internal elec-tric field. This should not be a surprise, because if there was an external voltagethen a current could flow and energy could be extracted. This would violate theconservation of energy, as there is no source of energy in the diode. n

If photons from a radiation source can incident on the pn junction aroundthe space charge region as shown in Figure 8.2, and if the energy of the photonis larger than the band gap (forbidden gap) energy for the particular semicon-ductor material (the energy of a photon is E = hf where h is Planck’s constant,and f is the frequency of the radiation), then an electron can be excited fromthe valence ban into the conduction band of the material. This process forms ahole in the p type material, and an free electron is generated in the p material.If this occurs in the space charge region, or near it, then the electron will besweep by the space charge electric field towards the n material. It effective rollsdown the potential gradient as shown in the figure. In this situation current canflow in an external circuit, and energy can be provided as the energy is comingfrom the photons striking the junction area and generating the carriers.


8.2.1.2 Equivalent Circuit of a Solar Cell

As can be seen from the previous explanation the mechanisms within a solarcell are quite complex, and when it comes to the fine detail, it involves quantummechanics. In order for electrical engineerings to have a simpler way of explain-ing the properties of a solar cell or array of solar cells, and equivalent circuitmodel is needed. This model can be developed from the normal equation forthe current through a diode.

The normal diode equation is [23]:

ID = I0(eqV

nkTK − 1) (8.1)

where:

ID , the diode current -positive when forward biasedI0 , diode the reverse saturation currentq , the charge of and electron = 1.6× 10−19C

k , Boltzmann’s constant = 1.38× 10−23J/K

TK , the temperature in Kelvinn , the diode ideality factor 1→ 2

V , the voltage across the diode - positive for forward bias

Under normal non-illuminated circumstances when the diode is reverse bi-ased then the reverse saturation current is the only current that flows. This canbe seen from (8.1) when V is negative and the expression becomes:

ID =I0

eqV

nkTK

− I0 ≈ −I0 (8.2)

Remark 8.5 The I0 current is essentially the current due to the generation ofhole-electron pairs within the Lp and Ln distances of the space charge region.The Lp and Ln are the average distance a hole and electron respectively candiffuse as minority carriers before recombining. Therefore if minority carriersare generated within Lp,n distances of the space charge region then they canmake it to the space charge region and be swept across the junction by the spacecharge electric field there. n

We shall briefly go through the development of the basic equations for a solarcell, and this will lead onto the equivalent circuit for the device. This presenta-tion is not comprehensive and the interested reader is encouraged to look at thereference (or other texts on semiconductor physics) to find out more details.

The following discussion is with respect to Figure 8.3. This diagram showsa junction that is optically irradiated. The junction in Figure 8.3(a) is reversebiased and is being irradiated with energy that is greater than the band-gap ofthe material. Therefore electron-hole-pairs (EHP) will be generated.

Figure 8.3(b) shows a section of the n material on the right side of thejunction. As mentioned previously Lp is the mean diffusion distance of holesin the material before recombination. Therefore if the irradiation is generatinggop holes/cm3/sec then these carriers will be able to diffuse to the space charge


p n

RE

W

n

AV

(a) (b) (c)

Figure 8.3: Optical generation of carriers in a pn junction.

region and then be swept to the p side of the junction by the electric field inthe space charge region. The number of carriers involved in this current isALpgop. Similarly in the p material we have ALngop electrons generated persecond within Ln of the space charge region. Therefore the total current flowingdue to this optically generated current is:

Iop = qAgop(Lp + Ln) (8.3)

Remark 8.6 If there are gop excess EHP (Electron-hole-pairs) are being gener-ated within say n material, then these excess carriers will diffuse in both direc-tions – i.e. 50% will go in one direction, and 50% in the other if one assumes,for simplicity, a two dimensional diffusion process. However, if the n materialis being uniformly illuminated then this will clearly balance out as this diffusionin each direction is occurring at all points in the material, and therefore thereis no net diffusion. However, due to the boundary at the space charge regionthis countering of the diffusion in one direction with diffusion in the other nolonger occurs. In the case of Figure 8.3(a) all of the hole carriers within Lp ofthe space charge region can diffuse to the space charge region without a countergroup of holes from Lp to the left of the beginning of the space charge regioncountering the hole flow. The problem with this last statement is ‘all of thehole carriers’. We have just said that 50% go in one direction and 50% in theother. This would mean that only 50% of the holes generated within Lp of thespace charge region would be contributing to the current.

This is true if both diffusion directions are feasible. In the case of the holesat the extreme right edge of the n material the holes cannot diffuse to the right asthere is no material to diffuse into. Therefore all of the hole have to be diffusingto the left.

At the space charge region boundary holes are being swept across the region.We do not have the same end effect here that is occurring at the right ohmiccontact – there is somewhere for the left diffusing holes to go. The push-backhole current flow from the right edge of the material affects the overall net holeflow from left to right in the material. If the material is in steady state then thehole flow to the space charge region if the normal 50% probability base flow plusthe 50% push-back effectively from the other end of the material. Therefore all


of the carriers in the ALp volume are being swept across the space charge regionboundary for the material concentrations to be in a steady state under opticalexcitation. n

Using this expression we can augment (8.1) as follows:

ID = I0(eqV

nkTK − 1)− qAgop(Lp + Ln) (8.4)

Remark 8.7 The gop rate is directly related to the number of photons of thecorrect energy hitting the Lp,n are from the junction. As can be seen from (8.4)the qAgop(Lp + Ln) is effectively a current source whose value is related toillumination. n

If the diode is short circuited then V = 0 in (8.4), and therefore there is areverse current flowing of Iop. If the diode is open circuited then ID = 0 andtherefore (8.4) can be rearranged as:

Voc =nkTKq

ln

(qAgop(Lp + Ln)

I0+ 1

)(8.5)

Remark 8.8 If would appear from (8.5) that Voc can increase without limit asgop is increased. However this is not the case. The reverse saturation currentis due to the thermal creation of minority carriers within the Lp,n distances ofthe space charge region. Therefore:

I0 = qA

(Lpτppn +

Lpτnnp

)(8.6)

where pn is the steady state minority concentration of holes in the n material,and np is the steady state minority concentration of electrons in the p material,and τp and τn are the respective minority carrier lifetimes. Now pn and np aredetermined by the doping and the temperature. However the τp and τn termsbecome smaller as the EHPs due to optical generation increase, and therefore theterms pn

τpand np

τnbecome larger. This clearly means that I0 becomes larger and

therefore the term qAgop(Lp+Ln)I0

in (8.5) will stabilise at some value – it does notcontinue to increase. It turns out that this maximum value of Voc, regardlessof the gop value, is V0, the contact potential of a diode (typically about 0.6 V).This makes sense as V0 is the maximum voltage that can appear across a diodein forward bias. n

The above discussions can lead to the following equivalent circuit for an idealsolar cell. Note that this equivalent circuit comes directly from the expressionsdeveloped above. As noted previously, the gop optical EHP generation operatesvirtually like a current source, and its value is basically the short circuit currentof the cell. Secondly the open circuit voltage of the device is limited to thecontact potential, regardless of the gopvalue. This leads to the following idealequivalent circuit shown in Figure 8.4. As can be seen the short circuit currentis IL and the open circuit voltage is V0. Clearly if a load is place across the cellthen as it is increased more of the irradiation current will be diverted into thediode. The current through the diode is related to the output voltage by (8.1).

In a real solar cell there are other effects. For example the solar cell has aseries resistance (RS) which is related to the resistance of the semiconductor


V

I

Figure 8.4: Equivalent circuit of an ideal solar cell.

V

I

Figure 8.5: Equivalent circuit of a non-ideal solar cell.

materials as the current flows from the cell out of it terminals and into theload. There is also a shunt resistance (RSH) which is related to leakage currentsaround the cell. We want RS to be as small as possible, and RSH to be as largeas possible. Figure 8.5 shows the non-ideal model of the solar cell that includesthese components.

From Figure 8.5 one can write the following expressions for the current andvoltage:

I = IL − ID − ISH (8.7)

and the current through the diode and the shunt resistor is governed by thevoltage that appears across them, namely:

VD = V + IRS (8.8)

We can determine the current through the diode from (8.1), and the currentthrough RSH is:

ISH =VDRSH

(8.9)

Therefore the solar cell output current is:

I = IL − I0(e

(q(V+IRS)

nkTK

)− 1

)− V + IRS

RSH(8.10)


+

-

Solar cellSolar cell series

array

Figure 8.6: Circuit symbols for a solar cell and a series array of solar cells.

Remark 8.9 Equation (8.10) cannot be solved in closed form, and has to besolved numerically for I. In addition the parameters in the equation cannot bedirectly measured, and usually have to be estimated from terminal measurementsof the device under various test conditions. n

Remark 8.10 The temperature of the cell also has important effects on itsoperation. If the temperature increases then the Voc of the cell will decrease.This in turn decreases the maximum possible output power. Therefore one wantsthe cell to operate at lower temperatures rather than high temperatures. n

Practical issue 8.1 One thing that can be surmised from the model is that ifsolar cells are connected in series (as they usually are to increase the outputvoltage), and if one or more cells are not illuminated as much as others, thencurrent will be forced up through RSH and RS resulting in a loss of power forthe series array, and heating of the poorly illuminated solar cell. The reversevoltage from this current can result in the breakdown of the pn junction. Thevoltage for this is from 10 to 30 volts. Therefore one shaded cell can absorb thevoltage produced by 20 or more unshaded cells. Reverse voltage diode clamps areusually place around practical solar cell arrays to prevent this from occurring.n

The circuit symbols for an individual solar cell and a series array of cells areshown in Figure 8.6.

The other important aspect of the operation of solar cells and arrays is howto extract the maximum power from the devices. The IV characteristics ofa solar cell can be gleaned from Figure 8.3(c) by inverting the curves in thebottom right hand quadrant (this is the quadrant that the system operates inwhen the cell is generating power). Redrawing this section of Figure 8.3(c)we get Figure 8.7, which also shows the power diagram and the figure-of-meritpower rectangle (shown in grey). The larger this rectangle the more power thecell can produce (as the area is IDV ). The theoretical ideal power would beIscVoc.

Also drawn on this diagram is the power that the cell develops at variouscurrents and voltages for the IV characteristic drawn. One can see that thepower reaches a maximum value as the voltage from the cell increases, and thenit begins to fall to zero as the current from the cell decreases.

For your information a data sheet for a typical PV panel appears in Ap-pendix F.2.


V

Figure 8.7: Maximum power diagram for a solar cell.

Remark 8.11 The IV characteristic shown in Figure 8.7 varies depending onthe temperature and illumination of the cell and the series and shunt resistancesof the cell. The load line shown on the diagram (the 1

RLlines) assumes a value

of the effective load resistance on the cell of RL. The 1RLo

line crosses throughthe IDV curve at its maximum power value, and therefore the load would bereceiving the maximum power that the cell can produce. The RLo value is theoptimal load resistance for the condition drawn. The two other load lines onthe diagram are for values of load resistance that are smaller than the optimalvalue ( 1

RL1) and larger than the optimal value ( 1

RL2). As can be seen from the

diagram in both cases (P1 and P2) the power produced by the solar cell will beless than the maximum value (Po). n

Remark 8.12 As mentioned in the previous remark, the IDV characteristics ofthe solar cell change with illumination and temperature. In order for the correcteffective resistance to be place on the solar cell under varying conditions themaximum power point has to be found. This is achieve in practice by MaximumPower Point Tracking (MPPT) algorithms. Most of these algorithms work bycarrying out a small perturbations in the current supplied to the load and thenmeasuring the change in the power. If the power gradient is positive then anotherperturbation occurs in the same direction. If not then a perturbation in theopposite direction occurs. This approach assumes that the power electronics isoperating as a programmable current source. n

Summary 8.1 The main issues that arise from this section that are related tointerfacing PV systems to a load or the grid are:

• A solar cell can be modeled as a current source in parallel with a forwardbiased diode.


• The current source current value is related to the irradiation of the solarcell.

• Solar cells are usually connected in series to get higher voltages (the voltageof a single cell is about 0.5 V).

• If some cells in a series connected array are shaded their current source isnot as large as the others. This can result in excessive power dissipationin the shaded cells, and lowers the efficiency of the array.

• Shading effects mentioned in Practical Issue 8.1 can be handled by chang-ing the power electronic architecture so that small groups of cells have theirown power converter. This will allow power optimisation for the shadedcells, and prevents the effects mentioned in the previous point. Clearlythere are cost implications involved in this solution.

• In order to extract the maximum power from the solar array the powerelectronic controller has to emulate the optimal load resistance. This valuechanges dynamically as irradiation and temperature changes. A MPPTalgorithm is required to achieve this. n

8.2.1.3 Traditional PV Inverter Topologies

In this section we shall consider in a little more detail the common topologies forPV inverters. These were briefly introduced in Section 8.2.1 when the invertersystems were broadly categorised into three phase, single phase, and galvanicallyisolated and non-isolated topologies. As also mentioned previously, galvanicallyisolated power electronic topologies have, until the last few years, been the maincategory of PV inverters that have been installed in Australia. This was prob-ably due to the inherent safety of these systems, and the conservative approachAustralian regulation authorities tend to take when systems are to be installedinto a domestic premise. However, the non-galvanically isolated topologies havebeen popular in Europe for a number of years now, and over the last few yearsthey have started to become popular in Australia. The reason for this increasein popularity can readily be seen in Figure 8.8 (which is taken from [24]). Thisfigure compares the different inverter topologies that would be used in domesticapplications on the basis of efficiency, weight, and volume. As can be seen, itis fairly clear that the non-isolated inverters win in all these categories – thisis the driving motivation for their introduction in Australia. It is also clearthat within the isolated category the high frequency transformer offers smallerweight and size, but it does not necessarily have better efficiency than the lowfrequency transformer design. The fact that there have not been major safetyissues with transformerless systems in Europe appears to have allayed the fearsof the regulation authorities in Australia1. Other issues such as DC injection tothe grid, that can occur with directly connected systems, can also be handledwith appropriate control.

Three phase systems are usually involved in PV systems with large powers,and can be used to interface a DC bus being fed from a number of PV arraysto the AC grid supply. These three phase inverter systems are fairly standard

1It should be noted that isolation is a requirement in the United States.


Figure 8.8: Relative merits of different inverter topologies for PV systems [24].


and are in wide use in the AC variable speed drive industry. They are treatedelsewhere in these notes, and this will not be repeated here.

Two structures that are used in larger power systems are the one phasemulti-string converter. This type of system breaks the PV array into sections,each with a DC-DC converter that implements the MPPT algorithm. TheseDC-DC converters feed onto a common DC bus which in turn feeds into a singlephase DC-AC converter. Usually these are arranged as three systems, witheach of the DC-AC converters feeding into separate phases. Figure 8.9 showsthe general configuration of this arrangement. Figure 8.10 shows a detailedview of one of the three modules. As can be seen the DC-DC converters arenon-isolated, therefore they have low losses (as compared to an isolated highfrequency converter based system). The grid interfacing is taken care of by thetotem pole output converter.

Remark 8.13 One of the best features of the topology shown in Figure 8.9 isthat the MPPT and voltage control can be taken care of by the DC-DC convertercontrollers, and the grid interfacing control by the control unit (CU) shown.The DC bus essentially isolates these two control algorithms. This allows thecontrollers for these different output objectives to be designed independently. n

Remark 8.14 Another advantage of the multi-DC-DC converter based topologyis that each DC-DC converter can implement its own MPPT algorithm, therebytaking into consideration the particular circumstances of the solar panel arrayconnected to the converter. This allows the possibility of different panels beingin different orientations, and also accounts for differential shading across thearray. n

An alternative arrangement of this is to use a single three phase converter insteadof the three single phase ones. This configuration is shown in Figure 8.11, andthe number of switches involved is the same. The only difference between thesetwo approaches is the control with respect to the grid interfacing – one uses threesingle phase controllers, and the other a three phase control algorithm. In thethree phase inverter case special control strategies would have to be undertakento account for unbalance in the grid voltages (if they exist), whereas in the singlephase case there is no concept of unbalance as the control is implemented on aphase-by-phase basis.

Remark 8.15 Three phase transformerless topologies tend not be be used verymuch. The main reason is the the DC voltage needs to be relatively high – atleast 600-VDC for a 415 VAC line-to-line mains. The DC voltage is limited (inEurope) to 1000-VDC for safety reasons. It is considered that this voltage rangeis too narrow given that there are DC voltage changes due to temperature, andalso the grid voltage can change. Single phase systems on the other hand onlyhave to handle the line-to-neutral voltages. In addition to this reason, manymanufacturers want to make up their three phase systems by using three of theirsingle phase systems. This makes sense from the manufacturing, production andmaintenance point of view. n

The single phase inverters that are commonly used at the domestic level,and with smaller scale PV systems will be the focus of our attention in thissection. A survey of power electronic systems for grid integration can be found


=

=

=

=

=

=

=

CU

Converter 1

N

=

=

=

=

=

=

=

CU

Converter 2

=

=

=

=

=

=

=

CU

Converter 3

Figure 8.9: Single-phase multi-string converter [25].


L

L

L

+ -DC Bus

DC-DC Conv 1

DC-DC Conv 2

DC-DC Conv 3

Utility

Grid

Figure 8.10: Detailed view of a single single phase output module [25].

in [25]. Some of the following discussion will be based on the contents of thispaper together with [21].

Figure 8.12 shows the basic configuration of a modern transformerless PVbridge converter. This circuit forms the basis for most modern converters thatare used in domestic situations. As can be seen from the figure the circuit issimply a basic single phase bridge converter as discussed in other parts of thesenotes. As we shall see, this basic circuit has some problems, that are not allthat obvious, when used in the transformerless PV application.

Remark 8.16 A few things to note from Figure 8.12:

• The PV array is not electrically isolated from the mains supply. Thereforethe PV array is floating at some voltage with respect to the ground (asnoted previously).

• The converter uses a very simple inductor filter.

• The PV array has to have a voltage high enough so that the convertercan operate directly connected to the mains without a boost converter. InEurope, where the voltages are much the same as Australia, the minimumPV array voltage is 350-VDC.

• There is a capacitance between the isolated PV array and the ground witha voltage Vcg across it. If there is an AC component to this voltage acurrent will flow through this capacitance.

• If there is substantial current flow through the Cg parasitic capacitancethere is the possibility of electrical shock to a person touching the array. Inaddition high frequency currents through this capacitance would contributesubstantially to EMI pollution, especially if arrays with this issue werewidely deployed.


=

=

=

=

=

=

=

CU

=

=

=

=

=

=

=

=

=

=

=

=

=

=

=

=

=

=

Figure 8.11: Multi-string converter with a three phase output stage [25].


L

L

L

N

Figure 8.12: A transformerless bridge converter interface for a PV system.

• For safety reasons the PV array and the associated power electronics hasto be double insulated. n

The basics of PWM for a full bridge converter (aka a H-bridge converter) weredeveloped in Sections 1.3.2.2 and 2.4.7 and will not be repeated here, howeveras eluded to previously the modulation strategy adopted with this converter hasprofound affects on its safety and therefore usability in domestic environments.

Let us initially consider bipolar switching. In this mode of switching we havethe following characteristics:

• The two legs are switched so that S1 = S4 = closed or S2 = S3 = closedat a high frequency and the switching is so arranged so that the outputfundamental is some desired fundamental frequency.

• No zero voltage state of the inverter itself is possible (although a zeroaverage output voltage is possible).

The other very interesting aspect of this modulation strategy is that the Vcg(the PV array to ground voltage) only has a small amplitude grid frequencycomponent to it (this will be shown shortly). Therefore the current flowingthrough the parasitic capacitance between the array and the ground is verysmall due to the high impedance of this capacitance at these frequencies.

The following discussion is with reference to Figures 8.13 and 8.14 whichshow the equivalent circuits for the PV H-bridge converter when switches S1

and S4 are turned on, and S2 and S3 are turned on. These are the two stateassociated with bipolar modulation switching. We are interested in what hap-pens to the voltage across the parasitic capacitance between the PV panel andground.

Carrying out KVL around the loop shown in Figure 8.13 we can write:

VPV + 2Ldi

dt− vac = 0 (8.11)

∴ Ldi

dt=

vac − VPV2

(8.12)


L

L

+

i

Figure 8.13: Equivalent circuit for the H-bridge PV converter with S1 and S4

turned on.

L

L

+i


turned on.


Clearly:

Vcg1 = Ldi

dt=vac − VPV

2(8.13)

Similarly one can do the same with Figure 8.14 allowing us to write:

VPV + 2Ldi

dt+ vac = 0 (8.14)

∴ Ldi

dt=−(VPV + vac)

2(8.15)

Therefore, we have the following expression for the common mode voltage underthese switching conditions:

Vcg2 = Ldi

dt+ vac (8.16)

= −VPV2− vac

2+ vac (8.17)

∴ Vcg2 =vac − VPV

2(8.18)

We can now work out the change in the voltage across the parasitic capacitorbetween then two switching positions:

δVcg = Vcg1 − Vcg2 (8.19)

=vac − Vpv

2− vac − VPV

2(8.20)

∴ δVcg = 0 (8.21)

Remark 8.17 This analysis shows that there is no change in the voltage acrossthe parasitic capacitor when switching occurs, and therefore there will be no highfrequency currents flowing through the capacitor. n

If should be noted that the δVcg voltage is the difference in voltage between thetwo switching configurations. The question then remains as to what the actualvoltage is appearing across Cg? Since the difference in the voltages betweenthe two switching instances is zero, then the voltage to ground is simply eitherVcg1 or Vcg2 depending on the time instant. Since, for a grid connected systemvac = V sinωt then the voltage that appears across the capacitor is

Vcg =V

2sinωt− VPV

2(8.22)

.

Remark 8.18 The overall conclusion is that the voltage appearing across theCg capacitor is the grid voltage. Since the supply frequency is low, and the ca-pacitor Cg has a relatively small value, then the leakage current through this ca-pacitor is very small. Therefore the potential for enough current to flow througha person touching the outside (insulated) surface of the PV array and receivingan electric shock is virtually zero. n

Summary 8.2 The PV connected H-bridge has the following properties withbipolar modulation:


• Uses the simple bipolar switching algorithm.

• There are no high frequency switching components in the Vcg voltage. Thismeans that the common mode currents through Cg are very small.

• The common mode voltage is at the grid frequency.

• The bipolar switching means that there is higher ripple relative to unipolarswitching strategies, and this in turn means that the filtering requirementsare increased.

• The filter inductors are subjected to bidirectional flux transitions. Thisincreases the losses in the inductors, and decreases efficiency.

• The ripple in the current results in reactive power exchanges with the ca-pacitor across the PV array. The current flows associated with this resultin extra losses and lower efficiency for this converter.

• The overall efficiency of these converters is of the order of 96.5%.

• The lower efficiency of the converter because of the issues raised abovemeans that bipolar modulated converters are not used in commercial PVinverters. n

Now let us consider the PV H-bridge converter, but this time with unipolarmodulation. Again we are interested in issues related to the current throughthe parasitic capacitance, as well as the efficiency and filtering requirements ofthe converter.

At the outset, we already know that the filtering requirements for a unipolarmodulated system, assuming the same switching frequency, will be less than thatof the bipolar system (this has come from previous work in the notes on thesemodulation strategies). In addition to this it is easy to see that the filteringinductors in the converter will be subject to unipolar flux excursions over aswitching cycle since the voltage is being switched from VPV to zero volts orfrom −VPV to zero volts, depending on the polarity of the output waveform.Therefore, these two properties mean that the losses in the inductors will beless for unipolar operation as compared to bipolar operation.

Let us consider the Vcg voltage with this type of converter. Obviously thesituation with S1 = S4 = closed is the same as in Figure 8.13. In unipolaroperation the zero voltage is produced by shorting the grid supply, and this isachieved by S1 = S3 = closed. This situation in shown in Figure 8.15. Let usanalysis this situation. Similar to the previous analysis we can write:

Ldi

dt− vac + L

di

dt= 0 (8.23)

∴ Ldi

dt=

vac2

(8.24)

We can then write the expression for the voltage across the parasitic groundcapacitor:

Vcg2 = −VPV + Ldi

dt(8.25)

∴ Vcg2 =vac2− VPV (8.26)


L

L +

i


turned on.

We are now in a position to calculate the change in the voltage across Cg dueto the change in the switch configuration. Using (8.13) we can write:

δVcg = Vcg1 − Vcg2 (8.27)

=vac − VPV

2− vac

2+ VPV (8.28)

∴ δVcg =VPV

2(8.29)

Remark 8.19 One can see from (8.29) relative to (8.29) that with unipolarmodulation there is a switching component across the Cg capacitor. This switch-ing component, with an amplitude of VPV /2 will have very fast edges, and there-fore the spectral components in the waveform will have a very high frequencycontent. Consequently, even though Cg is a parasitic capacitor (and would havea relatively small value), a high current can flow through it. In practice currentsas high as 3 to 4 Amps can flow. The exact current depends on the physicallocation of the panel with respect to ground. n

Summary 8.3 The following can be deduced from this analysis of unipolarmodulation:

• The high Cg current under unipolar modulation means that there is apotential for electric shock if a person touches the outside of the array.This situation is likely to increase Cg and therefore the current.

• The fact that the grid supply is disconnected from the PV array and itscapacitor during the zero voltage period means that there is no reactivepower exchange between the supply and the capacitor. This will improveefficiency.

• The filter inductors are only subjected to unipolar flux transitions, and thiswill lower the losses in the inductors, thereby improving efficiency.


• Unipolar modulation generates the same harmonic content as bipolar mod-ulation, but can do so at half the switching frequency. Therefore, the fil-tering requirements of this modulation strategy are less than with bipolarmodulation.

• The efficiency of this type of converter can be up to 98%, which is themaximum efficiency that has been measured for PV inverters.

• Despite the extremely good efficiency of the unipolar modulated H-bridgeit is not used because of the high ground currents and consequent safetyissues. n

An variation to the unipolar modulation strategy is the hybrid modulation strat-egy [26]. In this modulation strategy one of the inverter legs is PWM’ed in thetraditional sense, whilst the other leg is switched at the grid frequency (i.e. at50Hz in Australia). Let us briefly consider this scheme.

Figure 8.16 shows the H-bridge converter for a hybrid switching algorithm.The only difference between this and the previous H-bridge converter of Fig-ure 8.12 is that there is only one inductor in the filter. From a modulationperspective Leg B (i.e. switches S3 and S4) are switched at the grid frequency.The switching occurs in synchronism with the voltage supply – i.e. when Vg > 0then S4 is closed, and when Vg < 0 then S3 is closed. The equivalent circuitsfor these two situations are shown in Figure 8.17.

Remark 8.20 One can see from Figure 8.17 that for both the cases that theequivalent circuit of the H-bridge is that of the traditional DC-DC buck con-verter. If Vg > 0 then S4 is closed and the PWM is carried out by S1 and S2.If Vg < 0 then S3 is closed and again the high frequency PWM is carried out byS1 and S2. n

Remark 8.21 Since the equivalent circuits are buck converters each equivalentcircuit can only operate in one quadrant. There are two equivalent circuits forthe two different switch positions meaning that this circuit can only operate intwo quadrants. n

Remark 8.22 It is clear from the diagrams that the common mode voltage isa square wave that has moves between 0 volts (S4 closed) and -VPV volts (S3

closed). Since these switching are synchronized with the grid frequency then thissquare wave has the same frequency. n

Remark 8.23 The first major spectral component is the switching frequencyof S1,2. Therefore this inverter does not get the 2× frequency benefit that thenormal H-bridge does in unipolar modulation. Consequently it will have morestringent filtering requirements. n

Remark 8.24 The inductors in the circuit are subjected to unipolar flux tran-sitions. This makes the losses in the inductors low, and increases the efficiencyof the system. n

Remark 8.25 During the zero voltage intervals there is no reactive power ex-change between the inductor and the PV capacitor. This increases the efficiencyof the system. n


L

A

B

Figure 8.16: Hybrid Switching H-bridge converter.

Remark 8.26 The lower switching frequency in one of the legs also increasesthe efficiency of the converter by lowering the switching losses. n

Summary 8.4 Summing up, one can see that there are a lot of nice propertieswith this converter. Of particular note is its efficiency, which is of the orderof 98%. However, in the form of Figure 8.16 the converter is not used. Theproblem is the step changes in the common mode voltage. These steps are veryfast, and this can lead to spurts of current through the parasitic capacitance at100 times a second. n

8.2.2 New PV Inverter Topologies

The deficiencies of the transformerless H-bridge converter when used with bipo-lar, unipolar and hybrid modulation mode were investigated in the previoussection. This section will consider some newer inverter topologies, which arebased on the H-bridge, but attempt to address the efficiency issues of bipolarmodulation, and the safety issues that arise with unipolar and hybrid modula-tion. The inverter topologies are currently being used by several manufacturersof commercial inverter systems.

8.2.2.1 H5 Inverter (SMA)

This is an inverter topology patented in 2005 by SMA Solar Technology ofGermany. It consists of a classic H-bridge inverter with an extra switch inthe DC link [21]. The basic circuit is shown in Figure 8.18. The name of theconverter clearly comes from the fact that it is a H-bridge implemented with 5switches.

Similarly to the Hybrid converter, this converter uses a combination ofswitching speeds. Some of the switches are switched at mains frequency, andsome are switched at high PWM frequencies. As with the hybrid H-bridgeconverter this has some efficiency benefits.

Let us consider how this converter works. Essentially the extra switch givesan extra degree of freedom to allow a freewheeling path when zero volts is being


L

+

L

+

i

i

Figure 8.17: Hybrid Switching H-bridge converter equivalent circuit for the twopositions of the low frequency switches.


L

L

A

B

Figure 8.18: H5 H-bridge converter.

applied whilst at the same time isolating the grid supply from the PV array –it is this connection of the PV array to the grid supply during the zero voltagetimes that allows the high frequency switching to appear across the Cg parasiticcapacitance.

Similarly to the hybrid H-bridge, there are two cases that one needs toconsider:

a. Vg > 0; i > 0

b. Vg < 0; i < 0

The reason that the Vg > 0 and i > 0 are coupled together is that the PV arrayis delivering real power, and this is the only condition (and the vice-versa) whenthis will occur.

The other major difference between this converter and the hybrid H-bridgewe previously considered is the switching sequence. Because we want to isolatethe bridge from the grid during the zero vector times we need to ensure thatduring these times the bottom two switches are off (i.e. S2 and S4) and thefreewheeling path is supplied by the top switches. The isolation of the topswitches from the gird is implemented by the new switch S5. This means thatS5 has to be switched every time that the zero vector is produced – i.e. it isswitching at high frequency.

The remainder of the switching can be worked out by realising that weneed to again implement a DC-DC buck converter for both the positive Vg andnegative Vg grid voltages. The following discussion can be visualised with theassistance of Figure 8.19 for the Vg > 0 case, and 8.20 for the Vg < 0. The twofigures in each of these diagrams show the same respective situation for the Vgpolarity. The top figure is the situation where the inverter is delivering powerin the PWM cycle, and the bottom figure is the case during the PWM cyclewhen the inverter is in the zero voltage state.

If Vg > 0 then we can form the first buck converter by closing S1 for thewhole half cycle, and then PWM’ing S5 and S4. When S5 and S4 are closed


L

i

L

L

i

These switches open

A

B

A

B

Figure 8.19: H5 H-bridge equivalent circuit for Vg > 0.

power is being supplied to Vg, and when they open then the current can freewheelvia S1 and S3 (and their associated diodes if required). This is the zero voltageoutput state of the inverter, and obviously no power is being delivered to theload. Since S2 and S4 are open then the bottom rail of the converter is notconnected to the grid side. The top rail is also not connected since, as wehave already said, S5 is also open during this time. Therefore whatever voltagewas on Cg prior to this operation mode will remain there over this zero outputvoltage period (if it is small). Upon the next active switch state any sag in theVcg voltage would be restored.

A similar situation also occurs in the Vg < 0 situation (depicted in Fig-ure 8.20). Switch S3 is closed for the whole negative half cycle, and thereforeconnects point B to the positive PV array rail. This allow S5 and S2 to bePWM’ed into the DC-DC equivalent buck converter. As in the previous casewhen S5 is off so is S2 and the freewheeling occurs around the S1;S3 loop ap-


plying zero volts to the grid. Because S5 is off, as well as S2 and S4 then thegrid voltage is completely isolated from the PV array.

Remark 8.27 One can see that in the H5 converter that the top switches, S1

and S3 are the switches that are switched at the grid frequency. Their purposeis to connect the positive terminal of the PV array to the positive terminal ofthe grid supply. The bottom switches and the extra S5 switch are switched atthe high frequency to produce the PWM. n

The other question that has not been answered at this stage about this circuit is– what is the Vcg voltage? This can be calculated by considering the equivalentcircuits for the various modes of operation. Let us consider the top diagram inFigure 8.19. Carrying out KVL around the loop shown by the dashed line wecan write:

− VPV + Ldi

dt+ Vg + L

di

dt= 0 (8.30)

∴ Ldi

dt=

VPV − Vg2

(8.31)

Clearly:

Vcg = −Ldidt

(8.32)

∴ Vcg =Vg − VPV

2(8.33)

Conclusion 8.1 The conclusion that can be drawn from this analysis is thatunder the active power output condition the voltage appearing across the Cgcapacitor is the value in (8.33). Examination of this expression indicates thatthe voltage is the grid voltage with an offset. n

Conclusion 8.2 The second conclusion that can be drawn from this figure isthat when the zero voltage is being produced, the isolation of the PV array fromthe grid means that the voltage of equation (8.33) is retained (except for whateverleakage that would occur). n

The second situation is shown in the top diagram of Figure 8.20. Again usingKVL around the loop shown by the dashed current direction line we can write:

− VPV + Ldi

dt− Vg + L

di

dt= 0 (8.34)

∴ Ldi

dt=

VPV + Vg2

(8.35)

As previously the Cg capacitor voltage is:

Vcg = Vg − Ldi

dt(8.36)

= Vg −VPV + Vg

2(8.37)

∴ Vcg =Vg − VPV

2(8.38)


L

i

L

L

i

These switches open

A

B

A

B

Figure 8.20: H5 H-bridge equivalent circuit for Vg < 0.


Remark 8.28 Equation (8.38) is the same as (8.33). Note that in this casethe Vg value would be negative since this was derived for this situation. Thesituation for the bottom diagram is similar to that of the Vg > 0 case. The PVarray is again isolated from the mains supply. n

Conclusion 8.3 The overall conclusion from (8.33) and (8.38) is that

Vcg =Vg − VPV

2(8.39)

for all switching positions. This means that there is no high frequency compo-nent, and the voltage across the parasitic capacitance is an offset version of thegrid voltage. This fact means that there is little Cg leakage current and low EMIfrom this inverter. n

Summary 8.5 The H5 inverter has all the advantages of the hybrid inverter,and at the same time eliminates the high frequency components in the Vcg volt-age. It has been shown to have a European Efficiency of 97.7% and a maximumefficiency of 98%. This efficiency is the same as the maximum efficiency of allthe very efficient inverter structures. This inverter is used commercially in theSunnyBoy 4000/5000 TL PV inverter. A data sheet for this inverter can befound in Appendix F section F.1. n

8.2.2.2 HEIRC Inverter (Sunways)

This is another inverter topology that is similar to the previous one. Eventhough it is similar, it is worth having a brief look at this topology as anothervariant. This is also a topology that is patented and commercialised by Sunways(in 2006).

This topology differs from the previous one in that is is formed again froma H-bridge but has a bypass leg in the AC side of the bridge. Figure 8.21 showsthe basic circuit.

Under active power output the operation of this circuit is much the sameas the operation of the H5 converter. However under zero voltage output theswitches S1, S2,S3 and S4 are all turned off and the current is allowed to flowaround a short-circuit path produced by S+, D+ or S−, and D−. Note thatthese switches use unidirectional switches to effectively form a bidirectionalswitch. Which ever switch is chosen remains switched on for the whole halfcycle of the current flow.

Remark 8.29 The main points to make about this configuration [21]:

• The voltage across of the filter components is unipolar (as it was with theH5 topology), and therefore the core losses in the inductors will be lower.

• It has reasonable efficiency (European Efficiency of 95%) relative to othertopologies that prevent reactive power exchange between CPV and the filterinductors.

• The Vcg voltage only has grid frequency components in it, and thereforethere is only a small ground current and the EMI is not large.

• The topology has one extra switch compared to the H5 topology.


L

L

Figure 8.21: The HERIC PV inverter topology (Sunways)

• The HERIC has two switches conducting at the same time, whereas theH5 has three switches conducting. n

8.2.2.3 Full Bridge with DC Bypass (Ingeteam)

This is yet another modified full bridge topology. It has a patent pending byIngeteam in 2010. Figure 8.22 shows the circuit for this inverter. This is aninteresting design in that the switches S1 and S4 are switched on for the positivehalf cycle of Vg , and S3 and S2 for the negative half cycle of Vg. The PWMis carried out using the S5 and S6 switches. The clamp diodes D+ and D−are there to prevent the DC link bypass switches from being subjected to morethan half the DC link voltage.

Due to the similarity in the operation of these converters the operation willonly be briefly described. To deliver an active positive voltage switches S5, S1,S4 and S6 are closed – this essentially again forms the buck converter circuit.To get the zero vector then S5 and S6 are opened and S2, S3 are turned on, andthe current circulates via two paths – D3 and S1 as well as S4 and D2. Againthis is analogous to the freewheeling diode of the traditional buck converter.

Remark 8.30 One nice feature of the inverter is that the switching of S3, S2

during the zero vector production can be undertaken with no current flowingthrough them. Therefore there is no switching losses. n

Remark 8.31 Some remarks about this topology:

• As with the similar topologies the voltage across the filter is unipolar. Thismeans that the magnetic losses will be low.

• The DC bypass switches are rated at half the DC link voltage. The D+, D−diode clamps ensure that this is the case since if the voltage on the H-bridgeside of the bypass switch falls below VPV /2 then the diode will turn on.


L

L

Figure 8.22: The full bridge DC bypass PV inverter (Ingeteam).

• As with all the other modified H-bridge converters there is no reactivepower exchange between the filter inductors and the CPV capacitors duringthe zero voltage period.

• The Vcg voltage only has a grid frequency component which means that theleakage current and EMI are low.

• The inverter has two extra switches and two extra diodes compared to thestandard H-bridge.

• During the active vector there are four switches conducting. This willaffect the overall efficiency.

• European Efficiency is 95.1% and maximum efficiency is 96.5%. Note thatthis figure is a little down compared to the H5 topology for example.

• Commercialised by Ingeteam in the Ingeconr Sun TL series (2.5/3.3/6kW).

Conjecture 8.1 It would seem to me that the proliferation of different topolo-gies for these H-bridge based converters is more about circumventing the patentsof other companies rather than a distinct advantage of any particular topology.It would seem that it is better to accept a slightly less efficient inverter whichmay be more expensive to make rather than pay a royalty to a competitor. n

Up until this point the inverters that we have been looking at have been deriva-tives of the H-bridge. There are a lot of different versions of these, and I onlycovered a few of them. If one considers the PV panel integrated inverters (theinverter and panel come as an integrated set) then the inverter topologies prolif-erate even more. In order to ensure that these notes are not repetitive I shall notconsider anymore of this genre of inverters. Instead in the next section we shallbriefly consider inverters for PV applications that are derived from multi-levelconverter topologies. These are still single phase systems.


8.2.2.4 Neutral Point Clamped (NPC) Half-Bridge Inverter

The neutral point clamped converter is a well known converter in the multi-level converter community. The three level NPC converter (commonly used inmedium voltage three phase variable speed drives) can also be used in singlephase systems as well. Similarly to the H-bridge systems it enables one toproduce two active voltages and a zero voltage. The basic circuit for a classicsingle phase NPC inverter is shown in Figure 8.23.

In order to understand this circuit refer to Figures 8.24 and 8.25. Figure 8.24is for the case where Vg > 0 and i > 0. The top drawing in this figure is for thecase when there is an active voltage delivering power from the PV array to thegrid. As with all the previous cases the switches are turn on so that a DC-DCbuck converter circuit is formed and energy is being delivered to the load (thegrid voltage in this case) as well as the filter inductor (L). The current flow is,as in previous cases, shown as the dashed line. Note that there are two switcheson, S1 and S2, and the complementary switches S3 and S4 are off (as is thenormal case in a totem pole leg). The voltage being produced across the loadis VAB = VPV

2 – the voltage appears across one of the two series capacitors inthe DC link of the inverter.

Remark 8.32 One can see from the figure that the current that is being de-livered to the load is effectively flowing from one of the capacitors. The othercapacitor is has no current flowing through it. n

Remark 8.33 The other obvious difference between this inverter and the pre-vious ones is that the output voltage is half the PV array voltage. This has theimplication that the PV array voltage would have to be twice as big as in theprevious converters if a boost converter is not used as part of the overall con-verter. However, a positive feature is that the devices themselves are subject tothe only VPV

2 . n

Remark 8.34 Under this switching state it is important point to note is thatthe voltage supported across S3 and S4 is VPV . A question that arises is whetherthis voltage is equally supported by these two devices? If the voltage at the topof S4 goes above zero volts (relative to ground) then the diode D− will becomeforward biased clamping this voltage. This means that the voltage across S4 hasbeen clamped at VPV2 . Therefore the voltage across S3 is also effectively clampedat the same voltage. n

Remark 8.35 The voltage sharing described in the previous remark works verywell despite the variations in components for several reasons:

• When the switches are off the reverse currents are essentially thermal cur-rent sources (essentially reverse leakage currents through diodes). There-fore if one of the series elements tends to have an effective impedance thatis lower than the other, then it will be supporting less voltage and there-fore will dissipate less power. The other device on the other hand willtend to dissipate more power, and therefore the reverse current will tendto increase. This will make it effective impedance lower, and thereforean equilibrium will be achieved. Therefore there is a tendency for naturevoltage sharing.


• The diode D− will contribute to the leakage current of S4 in addition tothe leakage current from S3. This will tend to make the voltage across S4

rise, and the diode D− will start to turn on. This will then clamp thevoltage across both devices.

These same ideas are the basis for voltage sharing of series devices in thistype of clamped converters. n

The bottom drawing in Figure 8.24 is when the zero voltage is being produced.One can see from this figure that this is achieved by simply turning S1 off. Thefilter inductor forces D+ to turn on, and the voltage VAB becomes 0 as a shortcircuit is developed across the output terminals of the converter. Thereforewhen Vg > 0 and i > 0 the S1 switch is PWM’ed to produce the desired outputvoltage and S2 remains on for the whole of the grid voltage half cycle.

Note 8.3 It should be noted implicit in this explanation (and the previous onesfor the H-bridges for that matter) is that the output current and voltage are in-phase – i.e. the converter is only producing real output power and no reactivepower. This is the usual case, but there could be circumstances where the PVinverters may form part of a more integrated grid control system and they couldproduce or absorb reactive power as well as real power.

This converter can operate at non-unity power factors. For example, if Vg >0 and i < 0 then for positive output voltage the same switches are closed (S1

and S2 – the current is actually flowing through the parallel diodes) but whenzero volts is produced then S1 opens and S3 closes. The current will then flowvia S3 and D− forming the short circuit across the load terminals.

Similarly if Vg < 0 and i > 0 the positive voltage situation is the same, againwith the parallel diodes around the switches S3 and S4 conducting. To get thezero voltage then S4 is opened and S2 is closed forming a current via S2 D+.n

Figure 8.25 shows the other situation for the inverter switching. A quickperusal of the figure shows that the situation is a virtually identical to theprevious case in terms of the general principle of the operation. Therefore thedetailed description will not be repeated.

Summary 8.6 Summing up we can say the following about this topology:

• The PWM frequency is applied to switches S1 and S4 and the switches S2

and S3 are switched at the grid frequency.

• The converter is able to handle non-unity output power factors.

• The voltage across the filter is unipolar giving low core losses.

• Able to achieve high efficiency (98%) since there is no reactive power ex-change during the zero voltage state.

• The voltage rating of the switches is VPV /2, which is half the voltage ratingof the H-bridge topologies for the same VPV .

• Due to the fact that the peak output voltage VAB = VPV2 then the VPV

voltage will have to be twice that of the H-bridge for the same grid voltage.This means that there is no saving in switch voltage rating with NPC.


L

Figure 8.23: Basic NPC single phase leg.

• Because the centre point of the capacitors is held at zero volts then Vcg =−VPV2 (the voltage across the bottom capacitor). Therefore there is theo-retically no ground current or ground current induced EMI.

• The switching losses between the switches are uneven due to the fact thatS1 and S4 are PWM’ed and S2 and S3 are switched at grid frequency.

• The ground wire from the load to the capacitor centre point has to be verylow inductance to prevent transient common mode voltages from beinggenerated.

The NPC topology has been commercialised in the transformerless TripleLynxPV inverter sold by Danfoss Solar. These are rated at 10, 12.5 and 15 kW. Theyare reported to have a European Efficiency of 97% and a maximum efficiencyof 98%.

8.2.2.5 Some Other Topologies and Issues

Thus far several topologies have been introduced and considered in variousamounts of detail. In this section several other issues will be covered, someof which are relevant to all the topologies presented, as well as a brief discussionof three phase topologies.

Up until now we have considered H-bridge converters without a boost cir-cuit. Depending on the circumstances and application a boost converter maybe required. There are two main ways of achieving the boost:


LAB

LAB

Figure 8.24: NPC with Vg > 0 and i > 0.


LAB

LAB

Figure 8.25: NPC with Vg < 0 and i < 0.


HFTransformer

Boost converter RectifierGrid interface

converterDC link filter

Switching harmonicfilter

PV array

Figure 8.26: Basic structure of a single phase PV interface with a high frequencyisolated boost converter.

• a high frequency transformer.

• a traditional boost converter with a low frequency transformer.

Considering the first case, a traditional high frequency converter solution ap-pears in Figure 8.26. As can be seen if is formed by placing a conventionalH-bridge on the primary side of the a high frequency transformer, followed bya rectifier, filter and another H-bridge on the secondary side. Of course the tra-ditional H-bridges we have in this diagram can be replaced for the H5, HERICetc to get a more efficient circuit.

Remark 8.36 The PV array can be grounded in this circuit since the PV arrayside is completely electrically isolated from the grid supply. There could be stillsome high frequency feed-through from the output side via the capacitance of thetransformer. However if this is carefully designed this can be minimised. n

An alternative to the isolated HF transformer is to use a low frequency trans-former on the output of the PV grid interface inverter and the boost functionis implemented using a conventional non-isolated boost converter. Figure 8.27shows the basic layout of this type of converter. As can be seen from this figurethe transformer is now on the low frequency side of the converter after the fil-ter. Therefore this transformer is a mains frequency transformer, and would bemuch larger and heavier than an equivalent high frequency transformer capableof the same power throughput. However there are three fewer switches in thisdesign as compared to the high frequency converter design.

Remark 8.37 In both these boost converter systems the presence of the twoconverters means that the control for the system can be distributed. The MPPTfor example can be handled by the boost converter, and the grid interface controlissues by the output H-bridge. n

Finally a note on three phase converters. These were very briefly introducedvia Figure 8.11. However most three phase systems are built using single phasemodules – i.e. they are three phase, four wire systems. This has been mainlydone so that existing single phase modules can be used. The are essentiallycontrolled as three single phase systems. An example of a commercial systemthat is built like this is the SMA Sunny Mini Central 8000TL.

Other companies like Conergy, Refusol and Danfoss Solar are building truethree phase inverters in the large power range of 10-15kW. In terms of efficiency,low leakage and performance they are on par with the H-bridge systems we have


PV array Filter Non-isolated boost converter Filter H-bridge

Filter Low frequencytransformer

Figure 8.27: Basic structure of a single phase PV interface with a low frequencytransformer and non-isolated boost converter.

studied. The main problem with three phase systems is the relatively high DClink voltage (minimum of 600VDC for a 400 Volt grid). Taking into accountvariations that must be catered for, this does not leave much headroom to1000VDC, which is the maximum voltage for safety reasons in Europe [21].

8.2.3 Grid Requirements for PV Systems

Because PV inverters are generally (but not always) interfaced to the gird, thenthey have to satisfy certain requirements, known as the grid requirements inorder to comply with the rules of connection. The main issues related to thegrid interfacing are:

Anti-islanding protection An island is formed if the grid is disconnected orfails and one or more PV inverters maintain the supply to the isolatedsection of the grid. The issues that arise with islanding are safety issuesand quality of supply.

Voltage and frequency limits If the grid voltage and/or frequency moveoutside certain limits then the PV inverter should disconnect. Indeedthe movement of grid voltage and frequency is one of the passive methodsto determine when islanding is occurring.

DC current injection There is a possibility of injecting significant DC cur-rents into the grid if the control of the inverter is not very good. Thereforethe control has to be such that the DC injected current remains below acertain value. If a low frequency output transformer is used then DCinjection (except transiently) will not occur.

Power factor The current standard only allows small PV inverters to operateat near unity power factor. There are provisions in most standard to allowfor inverters to operate at power factors other than unity, but this will alsoinvolve some supervisory control of these systems.

Harmonics The inverter output filtering must be such that certain harmonicstandards are satisfied.


We shall now consider these issues in a little more detail. Reference will bemade to European Standards (these comments mainly sourced from [21]) andalso from the relevant sections of the Australian Standards on grid connectedconverters. These are in Appendix F.3 for convenience and if the interestedreader wishes to study them in more detail.

As you can well imagine there is a high degree of commonality between stan-dards from different countries. Obviously the standards committees would lookat overseas standards when beginning to formulate their own. Inevitably thereare differences as well they reflect different perspectives of the committees, dif-ferent electrical conditions, different degrees of safety, and (somewhat cynically)the desire of most committees to justify their existence by doing something dif-ferent. Even with these differences there is a fair degree of collaboration betweencountries in order to get the base of the grid standards the same. This helpsfacilitate equipment manufacturers that sell systems internationally.

From an international perspective the most relevant bodies in relation tostandards are the IEEE in the US, IEC (International Electrotechnical Com-mission) in Switzerland, and the DKE (German Commission for Electrical, Elec-tronic and Information Technologies of DIN and VDE). The later is important,as Germany is a dominant player in the PV market at the moment. StandardsAustralia, who set the Australian Standards, are of course aware of all the over-seas standards, and as shall be seen there is a large degree of similarity betweenthem all.

In the remainder of this section we shall look in a little more detail at thestandards, and compare and contrast those of the US, IEC, VDE and the Aus-tralian Standards. This presentation is by no means exhaustive and complete,but nevertheless it will serve to high the main issues. The international contextof these standards is very important for Australian manufacturers in this areawho intend to export – they clearly have to satisfy the standards of the countrieswhere they intend to export to. Most of the material used to write this chapterappears in a grid standards summary in [21] as well as in the AS4777.2-2005which is titled “Grid connection of energy systems via inverters Part 2: Inverterrequirements” and AS4777.3-2005 titled “Grid connection of energy systems viainverters Part 2: Grid protection requirements”. Relevant excerpts from thesedocuments appear in Appendices F.3.1 and F.3.2. These are provided so thatyou can see how these standards are worded and their general structure. Foryour information the other part of this standard that are not directly relevantto this discussion is AS4777.1-2005 “Grid connection of energy systems via in-verters Part 1: Installation requirements”.

8.2.3.1 Discussion of the International Standards

As mentioned in the previous section the IEEE, IEC and VDE have developedstandards in relation to grid connection of converters. In this section we shallconsider some aspects of these standards.

IEEE Standard 1547, which is titled Standard for Interconnecting DistributedResources with Electric Power Systems is probably the most influential standardin the US these days. This standard is noteworthy in that it is attempting todevelop a single standard that applies to all technologies up to power levels of10MW. It covers issues of the interconnection standards themselves, as well ashow to test that these standards to adhered to.


Underwriters Laboratories Inc. are an important body in the US with re-spect to standardisation. They have developed standards derived from the ear-lier IEEE 929 standard, which is designated as UL 1741 – Standard for Inverter,Converters, and Controllers for Use in Independent Power Systems. The latestversion of this standard also acknowledges the development of the IEEE 1547standard and says that UL 1741 should be used in conjunction with this stan-dard.

The IEC has been working towards bringing together the variety of inter-national standards. For example they have developed IEC 61727 (Dec 2004) –Photovoltaic (PV) Systems – Characteristics of the Utility Interface, and therelated standard IEC 62116 Ed 1 (2005) – Testing Procedure for Islanding Pre-vention Measures for Utility Interactive Photovoltaic Inverters. These standardshave reasonable conformity with IEEE 1547.

Germany in one of the largest PV markets in the world at the moment.Because of this fact any standards developed in Germany take on an impor-tance that transcends the German domestic context. Amongst the plethora ofstandards developed was some about devices for automatic disconnection be-tween generators and the public low-voltage grid. This standard was essentiallyabout the prevention of islanding (an issue that we shall return to in some de-tail later). In its original form this standard stated that the auto disconnectiondevice (which incidentally could be a software “device”) had to be able to detecta jump of 0.5Ω in the grid impedance in power balanced situation. After someexperience with this requirement it was concluded that this standard was tootight – it resulted in too much false tripping of PV systems, especially whena number of PV inverters were connected in close proximity. In addition ac-tive detection techniques had to be used to try and satisfy it (i.e. injectionof test signals in order to determine the grid impedance), and this result in adegradation of the power quality.

The upshot of these problems was that a new revised standard VDE 0126-1-12006 was formulated, and this relaxed the impedance change detection from0.5Ω to 1Ω. It is hoped that this will result in less problems with PV units onthe grid, and at the same time not compromise the safety aspects.

Another aspect to these VDE standards is the passive detection limits –i.e. the detection of under-voltage and over-voltage and the frequency deviationlimits. These limits form a passive detection method for islanding, as well asmaking sure that the inverter is not operating on a dysfunctional grid.

The VDE standard also describes test procedures to determine if a PV in-verter will disconnect from the grid if there is too much DC current injection, orfault currents are exceeded, or there is not sufficient isolation from earth. I willnot go into anymore detail on these issues here – the interested reader shouldlook at the appropriate source for these standards to find the details.

One issue that has not been touched on in the discussion thus-far is har-monics. PV inverters can of course introduce high frequency harmonics into thegrid, and if there are large numbers of them the cumulative effect could be sig-nificant. The most significant standard with respect to harmonics that can beproduced by equipment is the IEC61000 Electromagnetic Compatibility Stan-dard. One specific part of this standard (IEC61000-3-2) is related to currentharmonics for equipment with currents up to 16 Amp per phase. For equipmentwith currents greater than this but less than 75 Amp there is another standardIEC61000-2-12.


There are also corresponding standards for voltage related conditions such asflicker and fluctuations (IEC61000-3-3 and IEC61000-3-11) for the 16 Amp and16 to 75 Amp conditions respectively. They specify limits and test conditionsthat are used to measure the performance of the equipment. These standardsare for the low voltage public network – i.e. 220 to 250 V line to neutral at50 Hz.

Remark 8.38 The IEC61000 standards are related to the EMC of the equip-ment, and specify values of injected EMC from a piece of equipment into thegrid and the means of testing the equipment for compliance. n

The EN50160 are European Standards the related to the voltage quality of thepublic network from the customers perspective.2 For example permissible volt-age ranges are given for the low voltage and medium voltage public networkunder normal operating conditions. These conditions must be met for 95% ofthe mandated test period. Voltage specifications that are of interest to manu-facturers of PV inverter systems are [21]:

• Voltage harmonic maximum THD is 8%. See Table 8.1 for the distributionof these limits amongst the various harmonics.

• Voltage unbalance for three phase is less than 3% (this would be using theEuropean definition of unbalance – Vneg

Vpos.

• Maximum voltage amplitude variation is ±10%.

• Maximum frequency variation is ±1%.

• Voltage dips should be less than 1 second duration and the maximumdepth of the dip is 60% of the nominal voltage.

As will be seen the PV standards exceed most of the above supply requirements.In respect of the voltage dips, there are currently no requirements in Europe forride-through. However as the penetration of PV systems increases undoubtedlythis will come in. Wind turbine systems for example already have to satisfyvery stringent ride-through requirements.

The EN50160 standards are related to normal operation of the public dis-tribution grid. With respect to PV inverters, there are also standards as tohow they should operate under the circumstance of abnormal distribution gridconditions. These standards are in many senses a type of passive anti-islandingstandard. A comparison of the main international standards in respect of PVinverter disconnection when there is a voltage variation is shown in Table 8.2.

Remark 8.39 The “Discon time” in Table 8.2 refers to the maximum lengthof time allowed from the onset of the abnormal voltage condition to the inverterdisconnecting itself from the distribution grid. n

2These standards are about defining what are the “normal” limits for the operating condi-tions for the gird itself. They do not define the performance of the equipment. However, ifequipment was put onto the grid that resulted in these conditions not being met then clearlythere is a problem.


Odd harmonics Even harmonicsNot multiple of 3 Multiple of 3

Order h Relativevoltage %



5 6 3 5 2 27 5 9 1.5 4 111 3.5 15 0.5 6 to 24 0.513 3 21 0.517 219 1.523 1.525 1.5

Table 8.1: EN50160 European standards for public distribution grid voltageharmonics limits.

IEEE 1547 IEC 61727 VDE 0126-1-1Voltage range

(%)Discontime(sec)

Voltage range(%)

Discontime(sec)

Voltage range(%)

Discontime(sec)

V < 50 0.16 V < 50 0.10 110 ≤ V < 85 0.250 ≤ V < 88 2.00 50 ≤ V < 85 2.00

110 < V < 120 1.00 110 < V < 135 2.00V ≥ 120 0.16 V ≥ 135 0.05

Table 8.2: Comparison of US and European Standards on disconnection timesfor PV inverters under abnormal voltage variations.


IEEE 1547 IEC 61727 VDE 0126-1-1Freq range

(Hz)Discontime(sec)

Freq range(Hz)

Discontime(sec)

Freq range(Hz)

Discontime(sec)

59.3→ 60.5a 0.16 fn − 1 < f <fn + 1b

0.2 47.5→ 50.2c 0.2

aFor systems with power < 30kW the lower limit can be adjusted to allow participation infrequency control.

bThe fn is the nominal frequency of the supply.cThe lower frequency limit in this standard means that adaptive frequency synchronization

is required.

Table 8.3: Comparison of European and US standard for disconnection withrespect to frequency deviations.

Remark 8.40 One can see from the above table that the VDE standard foris very stringent. There are very tight bounds on the voltage, and the time ofdisconnection is reasonably fast. This means that good quality instrumentationhas be to used to satisfy this standard. n

Remark 8.41 Even though the inverter power circuit should disconnect due tothe conditions of Table 8.2 the instrumentation for the converter should remainconnected. This is the allow conditions of the supply coming back into specifica-tion to be detected, and resychronisation of the inverter to this supply to allowautomatic reconnection. n

Similarly to the voltage variation disconnection standards there are also stan-dards for disconnection if the distribution grid frequency moves outside certainlimits. These limits, and the time delays associated with them are to help pre-vent nuisance tripping in weak grids, but at the same time satisfy the passiveanti-islanding that is required for safety reasons. A comparison of the main USand European standards are shown in Table 8.3

Tables 8.2 and 8.3 provide the framework for passive anti-islanding of PVsystems. This therefore defines when the PV system should disconnect from thegrid using available measurements n the inverter. The next question that arisesis when should an inverter that has been disconnected under these circumstancesbe reconnected to the grid. Table 8.4 shows a comparison of standards for theconditions required for reconnection after an out-of-limits trip. One can seethat both the voltage and the frequency have to be within certain limits beforethe reconnection can occur. Also note that under the IEC standard that thereis a 3 minute minimum delay before reconnection which is designed to makesure that the inverter is going to be properly synchronized before reconnectionis attempted.

Another aspect of the grid requirements, also from the inverter viewpoint,is the power quality requirements. These requirements fall into two main cate-gories:

• DC current injection limitations.

• Injected current harmonics.


IEEE 1547 IEC 61727 VDE 0126-1-1

88 < V < 100 (%) and59.3 < f < 60.5 (Hz)

85 < V < 110 (%) andfn − 1 < f < fn + 1(Hz) and Minimumdelay of 3 mins.

Table 8.4: European and US reconnection conditions for PV inverter systemsafter a trip [21].

IEEE 1574 IEC 61727 VDE 0126-1-1

IDC < 0.5 (%) of therated RMS current

IDC < 1 (%) of therated RMS current

IDC < 1 A Maximumtrip time of 0.2 sec

Table 8.5: European and US DC current injection limitations

• Power factor.

We shall have a look at the international standards on these two issues. Table 8.5shows various limits for DC injection into the grid from PV inverters. DCinjection is a particular problem for transformerless PV inverters. If a PVinverter has a transformer (as is specified in much of the US) then DC injectioninto the grid cannot occur (since a transformer cannot pass DC in steady state).

Remark 8.42 It should be noted however that one may wish to minimise theDC output to the isolation transformer in transformer based PV inverters be-cause one can also get DC saturation of this isolation transformer. However, theproblem is not as severe as in the grid case because the DC injection is limitedto only the one inverter. n

Remark 8.43 You will notice from Table 8.5 that the IEEE and IEC standardsdo not have any time specified for the trip time if DC trip limit is exceeded,whereas the VDE standard does specify a maximum time that the limit can beexceeded before the inverter should disconnect from the grid. n

We have previously discussed harmonics from the point of view of the grid– i.e. the maximum harmonic levels that are allowed on the grid. The require-ments for the injection of harmonics from the PV inverters is related to but atthe same time separate from this. Clearly the standard for the inverters hasto be set up on the assumption that there will be multiple inverters connectedonto the grid, and therefore there is the potential that the harmonics may becumulative.

Remark 8.44 It should be emphasised that the harmonics for the grid in Ta-ble 8.1 are the voltage harmonics. The standards with respect to the inverters iswith reference to the current harmonics. Clearly the interaction of the currentharmonics with the grid system impedance will lead to voltage harmonics. n

Table 8.6 show current harmonic limits from the IEEE 1547 and IEC 61727standards. These harmonics are usually measured with an ideal grid voltage


IEEE 1547 and IEC 61727a

Individualodd

harmonicorder (h)b

h < 11 11 ≤ h < 17 17 ≤ h < 23 23 ≤ h < 35 35 ≤ h

(%)c 4.0 2.0 1.5 0.6 0.3

aThe THD has to be less than 5.0%bThe even harmonics are limited to 25% of the odd harmonic limits.cThis is the percentage of the fundamental amplitude.

Table 8.6: IEC and IEEE standards for injected current harmonics

Odd harmonics Even harmonicsOrder h I (A) Order h I (A)

3 2.3 2 1.085 1.14 4 0.437 0.77 6 0.39 0.4 8 ≤ h ≤ 40 0.23× 8

h11 0.3313 0.21

13 ≤ h ≤ 39 0.15× 15h

Table 8.7: IEC61000-3-2 current harmonic limits.

(i.e. from an ideal voltage source with no voltage harmonics). The IEC 61727standard has not yet been approved in Europe. The standard currently beingused is IEC 61000-3-2 (for equipment up to 16 A). These limits are shown inTable 8.7

The final aspect of power quality that shall be commented on is power factor.For the most part PV inverters are designed to operate with a power factor ofunity or very close to it. The reason for this as that this power factor willminimise the rating of the power electronics for the real power that is going tobe delivered to the grid. The IEC 61727 standard is the only one that mentionsthat a PV inverter should have an average lagging power factor greater than0.9 when operating at 50% or greater output power. The IEEE 1574 and VDE0126-1-1 standards do not include any specifications about PV inverter powerfactor.

Remark 8.45 As the number of PV inverters on the grid increases, and alsoas the size of some of the installations gets bigger, then the possibility of PVinverters exchanging reactive power with the grid will become more of a prospect.Regulations will have to be developed. Furthermore, communications standardsmay also have to be developed that will allow some decentralised/centralised con-trol of these reactive power sources. The presence of these devices will add a lotmore actuators to the grid for control of voltage, but it will also make the gridcontrol far more complicated. n


8.2.3.2 Anti-islanding Standards

The concept of islanding of PV inverters has been mentioned several times. Justas a reminder, islanding refers to the idea that a PV inverter will continue tooperate and feed local loads even though the area of the grid where the inverteris located has been isolated from the main part of the grid, and the conventionalgrid generation sources.

Islanding is an important issue for two reasons:

• If islanding occurs when the inverter section of the grid is isolated due toa fault or intentional isolation for maintenance, then there is the potentialthat maintenance personnel or a member of the public can be electrocuted.

• If the PV inverter continues to supply energy to the isolated section of thegrid then there is the possibility of damage to equipment if a re-closureoccurs.

As far as the PV inverter is concerned if there is the potential to form an islandthen the inverter has to detect this and isolate itself from the grid. It is requiredthat this task is performed without any supervisory control – i.e. the inverterhas to be able to autonomously determine that islanding has occurred. In orderto do this an anti-islanding algorithm has to be implemented in the inverter. Thedevelopment of such algorithms is a very active research area in PV inverters,as all algorithms developed thus-far have some limitations in terms of the timeto detect islanding, and the conditions under which islanding can be detected.

Let us look at some of the standards to test whether a PV inverter satisfiesthe anti-islanding regulations. IEEE 1547/UL 1741 requires the distributedresource (in our case the PV inverter) to detect the islanding and cease toenergise the area within 2 seconds of the island forming. In order to test whethera PV inverter is compliant with this, a standard test circuit has been established.This test circuit is shown in Figure 8.28. As can be seen a test RLC load issituated between the PV inverter and the grid. This is meant to simulate thelocal load when the grid has been disconnected. The load is set up so that theQ of the circuit is 1 and the natural frequency of the circuit is the nominal gridfrequency fn. If Pn is the nominal output power (i.e. it is very close to therated output power) of the PV inverter, then the values of the RLC load areestablished as follows:

R =V 2

Pn(8.40)

L =V 2

2πfnPnQ(8.41)

C =PnQ

2πfnV 2(8.42)

Remark 8.46 It is clear from (8.40) that the resistor has been chosen so thatthe load pulls the nominal output power of the inverter. n

With the circuit configuration of Figure 8.28 established, then the powerlevel to the grid is established at 2% of the nominal output power by fine tuningthe parameters of the simulated local load. The switch S3 is then opened and


SimulatedElectrical

PowerSystem

RLC load

Equipmentundertest

Figure 8.28: Test set up for testing the compliance of a distributed resourcewith the IEEE 1547 standard in anti-islanding.

the inverter should disconnect in less than 2 seconds to comply. For three-phase four wire PV systems then each phase is tested with the circuit connectedbetween the phase and neutral. For a three-phase three wire system the localRLC load is connected between the phases – i.e. it is a balanced three phaselocal load.

The IEC 62116 standard and test for anti-islanding has many similaritiesto IEEE 1547. The test circuit, for example, is the same, and similar powerbalance conditions are established. One difference is that the tests are carriedout at three different power levels – 100 → 105%, 50 → 66% and 25 → 33%.The voltage also is closely specified. The test is applied for the condition ofno change in the real and reactive power, as well as a set of tests where theseare stepped in increments of 5% in a range of ±10% around the nominal valuefor real and reactive power. Similar tests are applied at the other two powerconditions where the increment in the powers is 1% around a range of ±5% ofthe particular power value. As with the IEEE 1547 standard, the maximumtrip time after islanding occurs is 2 seconds. It should be noted that the IEC“standard” is still in development and is subject to review [21].

The final international anti-islanding standard is the VDE 0126-1-1 Germanstandard. One test in this standard uses a different test circuit to determinewhen the PV system under test can detect a change in the grid impedance anddisconnect itself. This test circuit is shown in Figure 8.29. As can be seenthe circuit employs a local load simulated by a parallel RLC circuit, howeveris this case the Q = 2. The local active and reactive power is balanced usingthe variable RLC circuit, and then the switch S is opened in order to increasethe grid impedance by 1.0Ω. The inverter should detect this change in the gridimpedance and disconnect within 5 seconds. The test is repeated with differentvalues of the simulated grid impedance (R2, L2) in the magnitude range of 1Ωwith a maximum inductive reactance of 0.5Ω.

The second part of the VDE anti-islanding standard uses the same testcircuit as IEEE 1547 – i.e. the circuit of Figure 8.28. The difference is that theQ = 2 as mentioned above and the rest of the parameters are set using (8.40),(8.41) and (8.42). With balanced power the PV inverter should disconnect whenS3 is opened within 5 seconds. This test is carried out for power levels of 25%,


DC-AC inverter

Grid~Se

mic

ondu

ctor

swit

ch

Figure 8.29: VDE 0126-1-1 anti-islanding standard test circuit.

50% and 100% of the nominal inverter output power.

8.2.3.3 Australian Standards

The discussion of the PV grid connection standards thus-far have been with re-spect to the international standards in the US and Europe. As can be seen fromthis discussion, there is a commonality between these standards, but also somesignificant deviations in some aspects. The Australian standards with respectto this are no exception. The relevant standards are included in Appendix F.3.The Australian Standard appears as three related documents – Part 1 is relatedto the installation requirements of PV systems, Part 2 is titled “Inverter Re-quirements” and Part 3 “Grid protection requirements”. Only the last two areincluded in the Appendix.

The inverter requirements relate to limits on certain parameters that theinverter can impose on the grid. For example, there are limits on the odd andeven current harmonics that the inverter can inject, the nominal voltage thatit operates at, the frequency, the power factor range that the inverter shouldoperate at, limits on the transient voltages when the inverter is disconnectedfrom the grid, and so on. These will not be reproduced here as the interestedreader can look at the standards themselves that appear in the Appendix.

A few comments on some of the standards. With respect to the currentharmonics, one can see from comparing Table 8.6 with the equivalent one in Ap-pendix F.3.1 that the Australian Standard is based on the IEEE/IEC standardin this area. The Australian Standard on DC current injection is very similar tothose of the IEEE, IEC and VDE. As can be seen from Appendix F.3.1 the DCcurrent is limited to 0.5% of the rated output current, or 5mA, which ever isthe greater. These limits are to be tested under all the operating power levels.There is no requirement for tripping if this is exceeded in operation, as is thecase with the VDE 0126-1-1 German standard.

One other standard that was not mentioned in the discussion of internationalstandards was the impulse protection standard. This is an important standardtest that an inverter must pass to ensure that it can withstand a voltage impulseon the grid without being destroyed. Such impulses can occur due to circuitbreaker intervention during faults, but also as a result of lightning strikes onthe grid lines. Clearly if an inverter cannot withstand such events then it willhave a very poor reliability. In the case of the Australian standard it resorts toa compliance test based on the IEC 60255-5 impulse testing procedure. Underthe Australian Standard the PV inverter must be able to stand an impulse with0.5 Joules of energy at a voltage of 5kV and and what is known as a 1.2/50


Voltage FrequencyVmin Vmax fmin fmax

1φ: 200→ 230V 1φ: 230→ 270V 45→ 50Hz 50→ 55Hz3φ: 350→ 400V 3φ: 400→ 470V

Table 8.8: Australian Standard voltage and frequency limits.

waveform. This type of waveform is shown in Figure 8.30 with the varioustime definitions on it. The name of the waveform arises from the fact that thenominal rise time tr is 1.2µsec, and the tail time tt is 50µsec.

Remark 8.47 The impulse voltage waveform specification should not be con-fused with transient voltage specification. The later is all about transients thatare produced by the disconnection of the inverter itself, whereas the later is ex-ternally imposed transient voltage waveforms. n

The grid protection section of the standards has to do how the inverter respondsto externally generated conditions such as over-voltage, under-voltage, frequencyvariations and islanding. So the specification says what the anti-islanding be-haviour will be and the basic algorithms that should be used to achieve this,as well as physically how disconnection occurs (i.e. does an electromechanicalswitch need to be used). In the event of anti-islanding disconnection occurringthe standard then specifies the reconnection procedure.

As an example, islanding detection can be passive, which means that theinverters sensors are looking for voltages or frequencies that go outside the gridspecifications. The other type of islanding that has to be present is activeislanding detection. These techniques involve injection of some type of a testsignal and then measuring the results and deducing whether the grid is stillconnected to the inverter. There are a number of different techniques for doingthis, and it is still a very active area of research. For example, one techniqueis to look for grid impedance changes by the inverter injecting a current pulseinto the grid and local load.

The reconnection procedure under the Australian Standard is not dissimilarto the international standards. To under standard the reconnection conditionsone needs to know the limitations on the voltage and frequency for the Aus-tralian system. These are summarised in Table 8.8. Given these definitions wecan now summarise the reconnection procedure as follows:

a. the voltage on the grid has to be maintained within the range Vmin → Vmax

for at least 1 minute; and

b. the frequency of the grid has to be maintained with the range fmin → fmax

for at least 1 minute; and

c. the inverter is phase synchronized with the grid at the time of reconnec-tion.

For more information about the Australian Standards on PV inverters the in-terested reader should read the detailed Standards in Appendix F.3.


Voltage

Time

Figure 8.30: Lightning impulse test waveform.

8.2.4 Grid Synchronization and Related Control for PVSystems

One of the key aspects of making a PV inverter system (or any other renewablesource) operate with the grid is being able to synchronize the output of theinverter with the grid system. This synchronization needs to be very accurate,as small angle differences can result in large transfers of power from the inverterto the gird (or vice-versa). In addition to accurate phase knowledge, the gridvoltage and inverter currents also have to be accurately known. These quantitiesare usually far from idea in nature, and can have considerable harmonic pollutionand noise in them as raw measurements. Therefore any filtering or estimationtechnique has to be capable of rejecting the noise and harmonic pollution, andat the same time achieve reasonable bandwidth so that the PV inverter can seegrid condition changes as quickly as possible.

Grid synchronization is not only required for normal operation of the in-verter, but it is also used as part of passive anti-islanding algorithms. Beingsynchronized to the grid allows accurate determination of the frequency of thesupply, for example, which is one of the key values used for passive island de-tection. Furthermore, many grid synchronization techniques also allow accuratevoltage magnitude to be determined, which again is required for passive island-ing detection.

Most of the techniques for grid synchronization are based on the use of aPhase Locked Loop (PLL), or a closely associated algorithm. The PLL was


Phasedetector

Loopfilter

Voltage controlledoscillator

Signal phase-lockedto the reference

Reference

Figure 8.31: Classic PLL block diagram.

originally a concept from communications – one of the main ways of demodu-lating FM for example is based on the use of hardware PLLs. We shall brieflyreview the concept of the PLL as applied in communication systems, and thenconsider some specific implementations used in PV inverters and other gridconnected distributed generation systems. In addition to PLL methods for de-tecting synchronization, techniques using adaptive filtering will also be verybriefly reviewed.

8.2.4.1 Brief review of PLLs

As mentioned in the previous section PLLs were originally introduced as a com-ponent in communications systems, and had particular application in the de-modulation of Frequency Modulated (FM) signals. The earliest us of the con-cept was with the birth of “coherent communication” in 1932. One of the earliestuses of PLLs was in the horizontal and vertical sweeps used in television wherea continuous clocking signal had to be synchronized with a periodic sync pulse.PLLs were also crucial to the development of colour television in the 1950s. Inapproximately 1965 the first analogue PLL integrated circuit was developed.This made the implementation of PLLs much simpler, and there was an explo-sion in their use. The first digital PLL appeared in 1970. Today PLLs can andare implemented entirely in software using sampled data. Every mobile phone,television, radio, pager, computer as well as many other things include PLLsas part of their circuitry or software. Subsequently they were used in otherapplications in communications. The PLL is essentially a control system, andtherefore has been morphed into a variety of different forms to suit differentapplications. The use of these devices in PV inverters, and inverters in general,is but one of these additional uses.

Figure 8.31 shows the general structure of a classic analogue communicationsPLL. As can be seen from this diagram there are three main components to aPLL – the phase detector, a loop filter (usually a first order low pass filter), anda voltage controlled oscillator. These components are arranged in a feedbackcontrol loop. Strictly speaking this feedback loop is a non-linear feedback sys-tem, however, when the loop is locked it can be analyzed using linear controltheory since the behaviour is then small signal and the operation is essentiallylinear.

The phase detector in Figure 8.31 is usually implemented in hardware with aGilbert Cell, which is essentially an analogue hardware multiplier. The low pass


filter is usually (but does not have to be) a 1st order low pass filter. The voltagecontrolled oscillator (VCO) accepts an input signal and produces a sine waveat a frequency that is proportional to the input voltage. We shall now considerthe operation of the PLL when it is essentially in lock under the condition thatthe PLL has been implemented with analogue components. We shall assumethat the input signal is a sine waveform and the VCO produces a cosinusoidalwaveform under steady state locked conditions.

Assume that the input waveform is:

uin(t) = U sin(ωit+ φi) (8.43)

and the waveform from the VCO is:

y(t) = Y cos(ωot+ φo) (8.44)

Therefore the output of the phase detector is (since it is implemented as ananalogue multiplier):

x(t) = uin(t)y(t) (8.45)= (U sin(ωit+ φi))(Y cos(ωot+ φo)) (8.46)

∴ x(t) =UY

2[sin((ωi + ωo)t+ φi + φo)) +

sin((ωi − ωo)t+ (φi − φo))] (8.47)

Remark 8.48 As can be seen from (8.47) there are two terms in this expres-sion. One has a frequency of ωi + ωo and the other has a frequency of ωi − ωo.Clearly the second one will have a lower frequency than the first. n

The waveform x(t) is subsequently filtered by a low pass filter that is designed tofilter out the higher of the two frequencies present in the waveform. This wouldleave the term UY

2 sin((ωi−ωo)t+ (φi−φo)). The (ωi−ωo)t can be consideredto be a low frequency changing phase denoted by φ(t). There if there is a non-zero (ωi−ωo) term then as t becomes larger then φ(t) will become larger. Thismeans that it is effectively integrating the frequency to get the phase. Of courseif one continues to integrate frequency that the integrated value will continueto increase. Forgetting for a moment the φi−φo term, then this will mean thatthe VCO input would increase (albeit in a nonlinear way because of the sinefunction), and hence the output frequency of the VCO will change in such away that the output frequency ωo will move towards ωi so the the φ(t) term willgo to zero and therefore the integration will stop. Using this approximation wecan write:

UY

2sin((ωi−ωo)t+(φi−φo)) ≈

UY

2sin(φi(t)−φo(t)) =

UY

2sin(φe(t)) (8.48)

where the φ(t) term representing the (ωi − ωo)t term has been folded into theφe(t) term.

Remark 8.49 The implication of the previous paragraph is that the VCO iseffectively acting as an integrator in the feedback loop. Unless the phase of theoutput of the VCO matches at all points in time the phase of the input signalthen there will be a residual phase error that is integrated by the VCO to drivethe phase error to zero. n


+

-

LPF Amplifier

VCO gain

Phase detector gain

Phase detector

VCO

Figure 8.32: Block diagram of a PLL control system when in lock.

Remark 8.50 The φi−φo term in (8.47) does not necessarily go to zero as thereis no time term in this expression. Therefore this component of the phase erroris not integrated and is only decreased by the loop proportional gain. Thereforewhen ωi − ωo = 0 then there can still be a static phase error. This means thatthe frequency of the VCO will match the input frequency, and the two waveformsare phase locked, albeit with a static phase error. n

Remark 8.51 One will also note from (8.44) that the output of the VCO isa cosine waveform, whereas the input waveform is a sine waveform. Thereforethere is a constant phase difference due to this alone of π2 radians. n

Remark 8.52 Since the output frequency of the VCO is locked to the inputfrequency by the feedback process of the PLL then if the input frequency is mod-ulated by audio for example, then in order for the PLL to remain locked thefrequency of the VCO must track the modulated frequency changes. Thereforethe input to the VCO will not be zero or a constant value but will track thefrequency changes of the input. Therefore in an FM system this input if thedemodulated signal. n

When locked and the frequency related phase error is zero or very close to itthe model of an electronic PLL becomes that shown in Figure 8.32. As can beseen in this figure there are gains associated with the phase detector and theVCO. Strictly speaking the loop is still non-linear since the term from the phasedetector is still that in (8.48). However if the φe(t) term is small then we knowthat sin θ ≈ θ if θ is small, therefore we can represent the output of the phasedetector as θe.

Remark 8.53 It should be recognised that the above description of how thePLL works is only valid if ωi ≈ ωo. If this is the case then the assumption thatφe =

∫ t0(ωi − ωo)dt+ (φi − φo) is valid. This integration is where the integrator

comes from in the block diagram of Figure 8.32. Since the φe is driving theVCO until the frequency error becomes zero, and the φe value is effectively ω× t(and t is increasing as time does), then the VCO implicitly has an integrator init (as mentioned previously). Incidentally this is not obvious. n


Remark 8.54 One aspect of VCO operation that we have not touched on is thefact the the VCO is set initially to output a non-zero frequency. This frequency iscalled the centre frequency, and it is usually set to be close to the expected inputfrequency. Classic PLLs have a capture range around this frequency, wherethe capture range is the maximum input frequency deviation from the centrefrequency where the PLL will pull into lock. The process of capture is highlynon-linear. We shall not discuss this here any further, but the interested read isencouraged to look further in the wealth of literature available on PLLs. n

The following linear analysis of the PLL is essentially taken from [27]. We shalldefine the centre frequency of the VCO to be ωo. Therefore the output frequencyof the VCO would be:

ωosc = ωo +KoVo (8.49)

Clearly the block diagram in Figure 8.32 is a classic feedback control system,and the transfer function is of the form:

Y (s)

U(s)=

G(s)

1 +G(s)H(s)(8.50)

where the G(s) = KDAF (s) and H(s) = Kos . Therefore the transfer function

can be written as:

Vo(s)

φi(s)=

KoAF (s)

1 +KDAF (s)Kos(8.51)

∴Vo(s)

φi(s)=

KoAF (s)s

s+KDAF (s)Ko(8.52)

In communications applications one is usually interested in the response of thePLL to frequency inputs – i.e. how fast can the loop track loop variations. Theabove transfer function can be modified by realising that:

ωi =dφidt

(8.53)

⇒ ωi(s) = sφi(s) (8.54)

∴Vo(s)

ωi(s)=

1

s

Vo(s)

φi(s)=

KoAF (s)

s+KDAF (s)Ko(8.55)

Remark 8.55 If F (s) = 1 the (8.55) is clearly a first order low pass filter.Loops with F (s) = 1 are therefore called first order PLLs. If should be notedthat these loops cannot be used in practice as the double frequency componentwill not be filtered out and will disrupt the locking of the loop. n

If (8.55) is made a 1st order loop, then the transfer function for the loop be-comes:

Vo(s)

ωi(s)=

(Kv

s+Kv

)(1

Ko

)(8.56)

where Kv = KoKDA

Remark 8.56 Equation (8.56) has a single -3db point of Kv rad/sec (in otherwords a time constant of 1

τ secs), and a DC gain of 1Ko

. Therefore the outputvoltage will response as a 1st order function with respect to a step change in theinput frequency. n


Open looppole

Closed looppole

Root Locus Closed-loop response

(log scale)

Figure 8.33: Root locus and Bode plot for a 1st order classic PLL.

Figure 8.33 shows the Root Locus and Bode plot for the 1st order PLL. Ascan be seen the bandwidth of the loop is set by the open loop gain Kv and theDC gain by the inverse of the VCO gain. Due to the presence of the implicitintegrator the PLL is a natural low pass filter.

As mentioned previously the 1st order loop is never used because of thepropagation of the high frequency terms around the loop. Most practical PLLsare 2nd order loops that employ a 1st order filter in the feedback path – i.e.F (s) is a 1st order filter using implemented with a resistor and capacitor on thecase of integrated circuit PLLs. Therefore we can write the filter as:

F (s) =

(1

1 + sω1

)(8.57)

which allows the overall transfer function of the PLL to be now written as followwhen we substitute into (8.55):

Vo(s)

ωi(s)=

1

Ko

(1

1 + sKv

+ s2

ω1Kv

)(8.58)

The Root Locus and Bode plot for this transfer function appears in Figure 8.34.Clearly the roots of the transfer function are:

s = −ω1

2

(1±

√1− 4Kv

ω1

)(8.59)

Equation (8.58) can also be written in the classic 2nd order form as fol-lows. This allows the easy identification of resonant frequency, resonant naturalfrequency and damping coefficient parameters. A brief review of 2nd orderequations in Appendix A is recommended for the reader who has forgotten thedetails of this. Equation (8.58) can now be written as:

Vo(s)

ωi(s)=

1

Ko

(1

s2

ω2n

+ 2ζωns+ 1

)(8.60)


(log scale)

Root Locus Bode Plot

Figure 8.34: Root locus and Bode plot for the 2nd order PLL.

where:

ωn =√Kvω1 (8.61)

ζ =1

2

√ω1

Kv(8.62)

Figure 8.34 shows the root locus and Bode plot for the 2nd order PLL. Ascan be seen as Kv increases the poles of the system become resonant in nature.This can be seen in the Bode plot, with the resonant peak in the frequencyresponse at around Kv rad/sec.

The loop bandwidth is primarily determined by Kv. To tune the loop Kv

is chosen for the bandwidth required, and then ω1 is chosen as low as possiblewithout causing unacceptable resonant behaviour in the loop. One good com-promise is to chose the pole positions to be at the Butterworth filter positionswhich is a maximally flat response. This means that the poles at at an angle of45 with respect to the real axis in the Root Locus. Mathematically this meansthat:

ζ =1√2

(8.63)

and we can therefore write:1√2

=1

2

√ω1

Kv(8.64)

which means that:ω1 = 2Kv (8.65)

Remark 8.57 This last expression means that the filter pole and the overallloop gain (and therefore loop bandwidth) are not independent. Furthermore (al-though we have not shown it) the lock range is also dependent on Kv. Thereforeone cannot can have a wide lock range, for example, and at the same time havegood noise rejection. n

This situation can be improved by the introduction of a zero into filter F (s).The if the zero is positioned correctly with respect to the pole of the filter, then


Loop gain with loop filter and zero (log scale)

1

Phase

Crossoverfrequency

Improvedphasemargin

Figure 8.35: Open loop Bode plots for a 2nd order PLL with zero added.

sufficient phase margin can be achieved in the closed loop Bode plot to allowthe filter bandwidth to be reduced (i.e. a low cut-off frequency for the feedback)independently of the lock range.

The effect of adding a zero to the filter can be seen in the open loop frequencyresponse of the PLL in Figure 8.35. As can be seen, at the unity gain point thephase of open loop phase is approximately < 180 as compared to 180 in thecase of the simple 1st order filter. This means that the phase margin has beenimproved considerably, and the resonant peaking that could occur in the 2ndorder PLL case can be more easily handled.

Figure 8.36 shows the closed loop magnitude frequency response of the PLLwith the zero added into the filter. Notice that there is another degree offreedom with the loop since the frequency response of the loop is determined bythe interaction of three parameters – Kv, ω1 and ω2. Therefore the lock range,which is directly related to the loop gain, can be determined independently ofthe closed loop bandwidth.

8.2.4.2 Brief Review of Synchronisation Techniques for Power Sys-tems

The previous section presented an overview of the operation of the traditionalPLL and various issues associated with the analysis and design of the loop forparticular performance. In this section we shall build on this by giving anoverview of how techniques related to the PLL are used for grid synchronisationin general.


40db/decade

Figure 8.36: Closed loop magnitude response of a 2nd order PLL with zeroadded.

Remark 8.58 Grid synchronisation is required not only in photovoltaic systemsthat are interfacing to the grid, but to any system that needs to synchronise.These techniques there have widespread use in power system control in general.n

The use of the PLL in power system applications leads to some issues that donot arise in communications applications. Consider (8.47) for the traditionalPLL, which I have rewritten here for convenience:

x(t) =UY

2[sin((ωi + ωo)t+ φi + φo)) + sin((ωi − ωo)t+ (φi − φo))] (8.66)

In communications applications the ωi frequency is usually very large, and ωois small by comparison. Therefore the ωi + ωo frequency (the high frequencyterm) is large compared to ωi − ωo (the low frequency term). Therefore it iseasy to set the bandwidth of the loop filter to get rid of the ωi+ωo term almosttotally without affecting the desired ωi − ωo term. This in turn means that thebandwidth of the loop – i.e. its ability to track transient changes in the inputphase, can be increased without causing any issues with the loop performance.

In power systems applications the situation is slightly different. The phase/fre-quency we are attempting to lock onto is the grid frequency – in Australia 50Hzor 314 rad/sec. Therefore the terms that we have coming out of the phase de-tector section of the loop is, assuming that the loop is in lock for the moment,100Hz (i.e. ωi + ωo) and DC (since in lock and steady state ωi = ωo). Howeverduring the lock phase the ωi − ω0 term will not be zero, and is required to pro-vide the movement towards lock. In order not to attenuate this signal too muchthe bandwidth of the filter cannot be set too low. Consequently some of theundesired 100Hz signal will creep through to the VCO and propagate aroundthe loop.

Remark 8.59 The propagation of the 100Hz signal around the loop in powersystems applications leads to the loop being disrupted. Consequently the analysis


Quadraturesignal

generator

+

+

PI controller

+

+

Quadrature phase detector

cosine

sine

VCO

Figure 8.37: Basic in-quadrature PLL.

of loop performance that appears in most books on PLLs is not applicable topower systems, since in the applications that these books consider the doublefrequency component is a much higher frequency than the loop bandwidth. Inthe power systems situation the effect of the 100Hz ripple getting through thefilter is that the PLL takes a lot longer to lock compared to the time predictedby the theory. n

In order to get better performance from PLLs when used in power systemsapplications, almost always some sort of in-quadrature based PLL is used. Thisapproach allows the analysis that is applied to PLLs in communications to beapplied to power systems PLLs.

Remark 8.60 It is ironic that in the case of PLLs the use of three phase PLLsis simpler than the single phase counterparts. This is mainly due to the fact thatan in-quadrature signal has to be generated somehow from the one input signal.n

The essential idea behind in-quadrature PLLs is that from a single input wave-form an orthogonal waveform is produced (i.e. 90 out of phase with the input).Clearly, if the input waveform in not a pure sinusoidal waveform then this pro-cess has to be applied to the various harmonic components as well.

Remark 8.61 The production of the in-quadrature component produces a twophase system, and consequently its properties are the same as a three phasesystem, since any three phase system can be converted into an equivalent twophase system. n

Now for a little more detail of what is behind in-quadrature processing for PLLs.The input signal, which we shall assume for the moment that the input signal isxin(t) = Xin sin(ωt + φ). This signal is input to the quadrature generator thatproduces an output signal xq(t) = −Xin cos(ωt + φ). These two signals are inturn multiplied by the feedback signals, which due to the operation of the PLLare 90 out of phase with the two input signals. Finally the two resultant signalsfrom this multiplication are added together and effectively form the output ofthe phase detector. Figure 8.37 shows the basic structure of this type of PLL.

In order to understand the advantage of this approach to the PLL a littlemathematics is required. If we consider what is happening at the phase detector


multiplier we can write the following expressions:

εpd = X[sin(ωt+ φ) cos(ω′t+ φ′)− cos(ωt+ φ) sin(ω′t+ φ′)] (8.67)= X[sin(ωt+ φ− (ω′t+ φ′)] (8.68)= X[sin((ω − ω′)t+ (φ− φ′))] (8.69)

Clearly if the loop is close to lock then ω−ω′ is small and therefore the φ termsand the ω terms can be rolled into one to give the following expression:

εpd = X sin(ωt+ φ− (ω′t+ φ′)) (8.70)∴ εpd = X sin(θ − θ′) (8.71)

where θ = ωt+ φ and θ′ = ω′t+ φ′.

Remark 8.62 One can see that the main advantage of the in-quadrature ap-proach is that there is no longer an ω + ω′ term appearing out of the phasedetector. Therefore the signal emanating from the phase detector does not re-quired the same degree of filtering. In the case of a power system synchronisationPLL where this double frequency component was disrupting the loop performancefrom the ideal behaviour, the use of the quadrature PLL means that the transientperformance of the loop will now conform to the theory. n

One can see from Figure 8.37 that the output of the phase detector is now fedinto an PI controller. The use of the PI controller here will ensure that the phasedetector error term εpd will be forced to zero when in lock, which in turn meansthat the θ − θ′ = 0 in (8.71). Therefore the PLL has locked onto the phase ofthe signal with zero phase error, and the PLL is also giving the frequency of theinput signal, and the two quadrature components.

Remark 8.63 The main issue with the in-quadrature approach when there isa single phase input signal is the production of the quadrature component ofthe signal. This is especially a problem when there are harmonics present inthe input waveform. We will briefly consider in the following paragraphs sometechniques to do this. n

We can test the above algorithm by setting up a simple simulation. In this casethe simulation has been carried out using the public domain dynamic systemsimulation and matrix computation system called Scilab/Xcos (available forWindows, Linux and Mac OSX from http://www.scilab.org). You can downloadthis system and load up the file for this simulation if you want to experiment.It will be made available on the Blackboard system. Figure 8.38 shows the Xcosmodel for the in-quadrature PLL used for the simulation. The performance ofthis PLL is shown in Figures 8.39, 8.40 and 8.41. In this simulation the inputfrequency and the centre frequency are equal to 2π×50 radians/sec at t = 0. Att = 1 sec the frequency becomes 2π×51 radians/sec. Figure 8.39 shows the inputwaveform and the fed back sine waveform (both normalised to unity amplitude).The part of the response shown is around the area where the input frequencyundergoes the step change. One can see that there is virtually no differencebetween the two waveforms – they are sitting on top of each other. This can beseen from Figure 8.40 which is the error between the two normalised waveforms(i.e. both the input waveform and the output waveform have an amplitude of


Figure 8.38: Xcos simulation model of the basic in-quadrature PLL.

1). Therefore the maximum error due to phase error is 5% in instantaneousamplitude. One can also see that the within about 200 msec this has convergedback close to zero. The final figure, Figure 8.41 shows the output of the PIcontroller used in the PLL. The integrator in this controller essentially storesthe frequency difference between the input and the output frequency. As can beseen from the Figure then difference becomes 2π at t = 1.0 secs. This differenceis then added to the centre frequency to give the estimated input frequency.Once can see that the transient performance of this is quite good, with thecorrect input frequency being identified in approximately 20 to 30 msec.

Remark 8.64 The transient response of the PLL can be improved by raisingthe feedback gain, but this also lets more noise into the loop. It is the inevitabletrade-off between bandwidth and noise rejection. n

The quadrature signal generator (Figure 8.38) is developed as follows. Thestep change generator in the diagram is the desired frequency (it is a step changegenerator to allow transient changes in frequency to be input for testing pur-poses). The frequency ω is passed into an integrator:

θ =

∫ t

0

ω dt (8.72)

This θ term is in turn passed to a A × sin function and the output is A sinωtas required. In order to generate the quadrature waveform this wave form ispassed through an integrator. The output is:∫ t

0

A sinωt dt = −Aω

(cosωt− 1) = −Aω

cosωt+A

ω(8.73)

Therefore in order to get −A cosωt we need to multiply the above expressionby ω and subtract off A.

Remark 8.65 In practice one cannot use this technique to generate the quadra-ture waveform – why is this the case?

Answer: one would have to know the amplitude and radian frequency of thewaveform. Since we do not control the input waveform we have no idea whatthese quantities are. n


Figure 8.39: Xcos simulation result – input waveform and feedback sine wave-form.

Figure 8.40: Xcos simulation result – the error between the input waveform andthe sine feedback waveform.


Figure 8.41: Xcos simulation result – the output of the PI controller which indi-cates the difference between the input frequency and the loop centre frequency.

The quadrature signal generator is simple to do in the case of the simulationsince one can artificially create the waveforms. However, in the case of trueinput waveforms, which may contain harmonics, this task is not quite as simple.For example if the waveform was of the form:

x(t) = A1 sinω1t+A2 sinω2t (8.74)

then it is not known what the amplitudes are (i.e. we do not know A1 and A2)and we have an estimate of, say, ω1 only. The particular harmonic frequencymay not be known. Therefore if the integration approach is taken to generatethe quadrature component we have:∫ t

0

x(t) dt = −A1

ω1cosω1t−

A2

ω2cosω2t+

A1

ω1+A2

ω2(8.75)

Remark 8.66 One can see from this expression that one would have to be ableto pull the harmonic components apart to apply the correct to the amplitudesand to subtract off the offsets (if they are known). n

Remark 8.67 One can also see from (8.75) that the correct phase relationshipis maintained between the harmonics – for example, the A2 sinω2t term and the−A2

ω2cosω2t have the correct in-quadrature relationship. Therefore the integra-

tion does preserve this if one is attempting to get the PLL to synchronise to theω2 frequency. n

One can make a clear connection between the single phase in-quadrature signalprocessing an dq or space vector processing that we are familiar with in variablespeed drives and other three-phase power systems applications. If one considers


Quadraturesignal

generator

PI controller

+

+

Frequency to phase anglegenerator (FPG)

Phase detector (PD)

Figure 8.42: In-quadrature PLL implemented with a Park transformation.

(8.67) one can see that the quadrature outputs of the quadrature generator canbe written as:

vαβ =

[vαvβ

]= X

[sin(ωt+ φ)− cos(ωt+ φ)

](8.76)

Using some definitions from above we can write generate the εpd term out ofthe phase detector as:

vd = vα cos θ′ + vβ sin θ′ (8.77)

We know from the two phase stationary frame to two phase rotating frametransformations present in (B.79) in Section B.3.2 on page B-14 (repeated herefor convenience in slightly different notation):[

vdvq

]=

[cos θ sin θ− sin θ cos θ

] [vαvβ

](8.78)

that the above quadrature signal generation is basically the same as a twostationary frame to rotating frame transformation – i.e. a Park transformation.In Figure 8.37 we are only utilising the vd component in the PLL. This realisationallows use to draw the PLL of Figure 8.37 in a slightly different form as shownin Figure 8.42.

This PLL can also be used for three phase systems. The block diagram forthis situation is shown in Figure 8.43. As can be seen the three phase valuesare fed into a Clark Transformation which essentially outputs the two phasestationary frame values which are equivalent to the quadrature values. Noticein this figure that we have drawn the PLL as a control system, explicitly showingthe feedback processes that form the loop.

Remark 8.68 If the control loop in Figure 8.42 is doing its job correctly thenthe xd signal will be driven to zero (by the action of the PI controller). If oneconsiders the system to be a two phase system with xα and xβ inputs, then thismeans that the θ′ angle will be 90 out of phase with the angle of the xαβ spacevector representation of the in-quadrature stationary frame inputs. n

Remark 8.69 If one looks carefully at Figure 8.42 one can see that it is exactlythe same as the model in Figure 8.38 n

Figure 8.44 shows the space vector representation of the space vector of thequadrature signals relative to the stationary frame αβ axes, and the projection


ParkTransformation

ClarkTransformation

+

-

++

v¤d

vd

vq

!®

μ

v® v¯vavbvc

!¢!

Figure 8.43: The three phase quadrature PLL using a Park Transformation.

of this vector onto the rotating dq axes. In this particular case the x vector isnot aligned with the q axis, so there is a projection onto the positive d axis.It is this value that is multiplied by −1 and then pass it into the PI controllerwhose output becomes the ∆ω value that is added to the centre frequency ofthe PLL. The value of ∆ω in this particular case will be a negative value (sincethe vd value is negated before the PI controller), and this therefore means thatthe rotation speed of the dq frame will be slowed down as it will be effectivelysubtracted from centre frequency. This resultant frequency is then integratedand becomes the θ value that is used to generate the position of the dq axes.Since the frequency of the dq frame is being lowered this means that the angleθ increasing at a slower rate, which in turn means that the angle γ is increasingand the x is moving more in-line with the q axis. Eventually the x vector willbe in-line with the q axis, and then there will be no projection of the vectoronto the d axis. At this point the PLL has locked, and the θ value is at ∠x− π

2radians and ω = ω. Note that the q axis value is clearly |x| at this convergencepoint as well. This situation is shown in Figure 8.45.

The in-quadrature PLL was programmed up in the Python language.3 Thisversion shows how the algorithm may be programmed up, and also has theaddition of generating a fifth harmonic in the input waveforms to see how thePLL copes with this. A listing of the software appears in Appendix G. Thislisting contains more than the code of the two phase PLL. It also contains codefor other variants of PLLs (which are not the current subject of discussion as

3Python is a very powerful freeware object oriented language that is flexible enough to beused to implement websites and coordinate nuclear explosion simulations at Los Almos. It hasa very powerful numeric library that offers matrix manipulation facilities similar Matlab atcompiled speeds. In addition there is a library that mimics the graphics plotting facilities ofMatlab. For Windows the best version of Python(x,y) available at http://www.pythonxy.com.For the MAC the best version if Enthought Python available at http://www.enthought.com.


Figure 8.44: Space vector representation of the convergence process of a ParkTransformation based quadrature PLL.


Figure 8.45: Space vector representation when the Park Transformation quadra-ture based PLL is locked.


4900 5000 5100 5200 5300 5400100

50

0

50

α axis values

Figure 8.46: Two phase PLL implemented in Python showing the estimatedwaveform versus the actual waveform.

well).The test conditions for the following plots are: Amplitude of the input signal

is 100; initial frequency of the input is 50Hz; the sampling frequency is 5kHz;there is a step change in the input frequency from 50Hz to 60 Hz at 5000samples (i.e. 1 sec) into the simulation4. The in-quadrature waveforms aresimply defined as in-quadrature – i..e the simulation does not develop the in-quadrature waveforms from a single phase waveform. Figure 8.46 shows theidentified α axis waveform from the PLL (there is also an amplitude estimatorso that the original waveform can be constructed from an estimated phase andamplitude). The true waveform is shown as a solid line, and the estimatedwaveform as a dashed line. One can see at the point of the step change thatthe true waveform line becomes visible. If one move to the right further in thewaveform, then these two waveforms again merge over the top of one another.Figure 8.47 shows estimated ∆ω centre frequency error that is added to thecentre frequency to generate the actual frequency. One can see that there is veryrapid identification of the new frequency. The correct ∆ω value is 62.8 radians(i.e. 10Hz), and this is the value shown in this plot if a cursor is place on theline to the right of the 5000 sample point.

The power supply is rarely an ideal sinusoid. One interesting question is howdoes this PLL operate under this condition. Figures 8.48 show the same plots asabove, but for the situation where there is a significant 5th harmonic in the input

4This step change in frequency is quite large, and far larger than would be experience inpower systems applications. This change was chosen to demonstrate the tracking capabilityof this PLL.


4500 5000 5500

0

10

20

30

40

50

60

Estimated Frequency Error

Figure 8.47: Two phase PLL implemented in Python showing the estimatefrequency error from the centre frequency of the PLL.

– the amplitude of the 5th harmonic is 30% of the fundamental. As can be seenthere is significant distortion in the estimated waveform, and Figure 8.49 showsthat there are very large oscillations in the estimated frequency error ∆ω. Thefiltering action of the frequency integrator smooths this to some degree, butstill allows significant phase distortion through which would render the PLLunusable in these applications. A low pass filter can be placed in the ∆ω partof the loop, and the resulting ∆ω plot is shown in Figure ??. The gains in thePI feedback also have to be lowered to ensure that the loop is stable, but evenwith this there are substantial oscillations in ∆ω. The lower gains also meanthat the phase convergence is very slow.

Remark 8.70 The upshot of the simulations with the 5th harmonic input in-jection is that the two phase in-quadrature PLL does not work very well. n

The issue of generation of the quadrature signal when the input is a singlephase signal is not simple, especially when harmonics are present. One populartechnique used when the frequency of the input is well known (such as in powersystem applications) is the T

4 transport delay. Clearly this technique is based onthe idea that a delay of T4 where T is the period of the fundamental waveformis effectively a −90 phase shift. The practical implementation of the T

4 delaycan be achieved by a digital shift register where the sampled digital values areshifted on each clocked sample. The length of the shift register is T

4 secs.

Remark 8.71 The T4 phase shift technique will have difficulties when there are

8.3 Wind Turbine Converter Systems 8-73

4800 4900 5000 5100 5200

100

50

0

50

100

α axis values

Figure 8.48: Two phase PLL implemented in Python showing the estimatedwaveform versus the actual waveform when there is a 30% 5th input harmonic.

harmonics in the supply and it the frequency of the supply varies over a widerrange of frequencies. n

STILL HAVE TO ADD MORE HERE ON OTHER TYPES OF SYNCHRO-NISING STRATEGIES.

8.2.5 Islanding Detection Techniques

Yet to be written.

8.3 Wind Turbine Converter Systems

Yet to be written.

8.3.1 Grid Requirements for Wind Turbine Systems

Yet to be written.

8.3.2 Grid Synchronization for Three Phase Systems

Yet to be written


4600 4700 4800 4900 5000 5100 5200

200

100

0

100

200

300

Estimated Frequency Error

Figure 8.49: Two phase PLL implemented in Python showing the estimatefrequency error from the centre frequency of the PLL when there is a 30% 5thinput harmonic.

8.3 Wind Turbine Converter Systems 8-75

0 2000 4000 6000 8000 1000020

0

20

40

60

80

100

120Estimated Frequency Error

Figure 8.50: Two phase PLL implemented in Python showing the estimatefrequency error from the centre frequency of the PLL when there is a 30% 5thinput harmonic and filter.


8.3.3 Brief Overview of Wind Turbine Converter ControlYet to be written.

Part III

Appendices

Appendix A

Review of Second OrderCircuits

This appendix will give a brief review of second order circuits. This is includedas second order series and parallel circuit inevitably come into high speed dig-ital systems due to the presence of inductance and capacitance in the variouscircuits.

A.1 Series RLC Circuits

Consider a circuit of the form shown in Figure A.1. Carrying out standard loopanalysis we can write the following differential equation for this circuit:

Rdi

dt+ L

d2i

dt2+

i

C=dvindt

(A.1)

Taking the Laplace Transform of (A.1) we can write the following transferfunction for the current: transfer function

i(s)

vin(s)=

sC

LCs2 +RCs+ 1(A.2)

and therefore the transfer function for the voltage across the capacitor is:

vo(s)

vin(s)=

1

LCs2 +RCs+ 1(A.3)

One can see that the poles of (A.3) are: poles

s = − R

2L±√

R2

4L2− 1

LC(A.4)

which can be written as:s = −α±

√α2 − ω2

o (A.5)

A-2 Review of Second Order Circuits

i

R

vin

C

L

+

-

vout

Figure A.1: Series RLC circuit

where:

α =R

2L(A.6)

ωo =1√LC

(A.7)

One can get a better impression of the position of the poles if they are plottedon the complex plane. This is shown in Figure A.2. Note that this diagram isonly showing one of the two conjugate poles.

We can define several other terms from this diagram. The natural resonantfrequency , ωd, is the frequency of oscillation of the natural response (i.e. sourcenatural resonant

frequency free response) of the circuit when there is resistance present. This is differentfrom the resonant frequency , ωo, which is the resonant frequency of a losslessresonant frequencyseries RLC circuit.1 Another variable of interest is the damping factor . Thedamping factorformal definitions are:

ωd =√ω2o − α2 (natural resonant frequency) (A.8)

ξ = cos θ =α

ωo(damping factor) (A.9)

From Figure A.2 one can see that if the poles are off the real axis of the com-plex plane then there is a projection of the complex vector onto the imaginaryaxis. This means that there is an oscillatory mode in the response of the circuit.If the angle θ is zero, then the two poles are coincident. This condition corre-sponds to critical damping .2 Because there is not projection onto the imaginarycritical damping

1The resonant frequency is the frequency at which a driven series RLC circuit will exhibitis minimum impedance.

A.1 Series RLC Circuits A-3

wo

wo

a

wd

Im

Re

q

Figure A.2: Series RLC circuit pole positions.

axis there is no oscillatory or over shoot behaviour in the response. From theviewpoint of the equations critical damping corresponds to the condition:

ωd =√ω2o − α2 = 0 (A.10)

Therefore critical damping means that:

α = ωo

R

2L=

1√LC

∴ R = 2

√L

C(A.11)

For the case where:α > ωo (A.12)

we have two real poles generated. One the these poles will move towards theleft on the real axis and the other to the right. The system response is now veryslow, and it is said to be over-damped . There are no oscillations. over damped

Another important property of a series RLC circuit is its impedance. Rear-ranging (A.2) we can write the impedance transfer function:

Z(s) =vo(s)

i(s)=LCs2 +RCs+ 1

Cs(A.13)

If we let s = jω (i.e. the resonant frequency), and substitute this into (A.13)we get:

Z(s) = R+1

jωC− ωL

j

= R+ j

[ω2LC − 1

ωC

](A.14)

2Critical damping gives the fastest response without overshoot.


Clearly the magnitude of this expression has a minimum value when the imag-inary term is zero. Therefore:

ω2LC − 1 = 0⇒ ω =1√LC

= ωo (A.15)

The minimum impedance is R under this condition. As noted earlier, this occursat the resonant frequency (ωo), and not the natural resonant frequency (ωd).

A.1.1 Quality FactorAnother important measure of resonant second order circuits is the quality factor– Q. When a circuit is being driven in resonance this is defined as:

Q , 2πTotal energy stored in the circuitEnergy dissipated per period

(A.16)

In the case of the series RLC circuit consider it to be driven with i(t) =Im cosωot. The expression for the instantaneous energy stored in the inductoris:

eL(t) =1

2Li2 =

1

2LI2

m cos2 ωot (A.17)

Similarly the energy stored in the capacitor can be calculated as follows.We know from the relationship between the current and voltage for a capacitorthat:

v =1

C

∫ t

0

Im cosωot dt (A.18)

∴ v =ImωoC

sinωot (A.19)

We can therefore write:

v2 =I2m

ω2oC

2sin2 ωot (A.20)

Consequently we have:

eC(t) =1

2Cv2 =

1

2

I2m

ω2oC

sin2 ωot =I2mL

2sin2 ωot (A.21)

using (A.15).Therefore the total energy is:

eL(t) + eC(t) =1

2LI2

m(cos2 ωot+ sin2 ωot) =1

2LI2

m (A.22)

which is obviously a constant.The average power dissipation in a resistor with a sinusoidal input is:

PR =1

2I2mR (A.23)

and hence the energy dissipated over a period To is:

PRT =1

2I2mRTo =

1

2foI2mR (A.24)


Using (A.22) and (A.24) in (A.16) one can write:

Q = 2π12LI

2m

12fo

I2mR

= 2πfoL

R

= ωoL

R

∴ Q =1

R

√L

Cusing ωo =

1√LC

(A.25)

If Q = 0.5 then:

R =1

Q

√L

C= 2

√L

C(A.26)

which is the same expression for the resistance when the circuit is criticallydamped. If Q = 1 then we have:

R =

√L

C(A.27)

which is the same expression for the characteristic impedance in transmissionlines. It also means that the energy stored in the circuit is the same as theenergy dissipated per cycle. Therefore the energy that has to be replace percycle is the same as that energy dissipated in the resistor which is the same asthe stored energy.

A.1.2 Time Domain ResponseLet us now consider the time domain solution of (A.3). In this we shall beassuming that for t < 0 then vin(t) = V0, and at t ≥ 0 vin(t) = 0 – i.e. thevoltage drops to zero. Therefore the circuit becomes a source free circuit with aninitial voltage on the capacitor of V0 volts. Therefore we only need to considerthe natural response of the circuit. This situation will also give us a lot ofinformation about the case when there is a positive step in the voltage.

Examination of (A.1) suggests that a possible candidate solution is:

v0(t) = A1es1t +A2e

s2t (A.28)

where:s1,2 = −α± jωd (A.29)

Expanding the exponential terms in this equation we can write:

v0(t) = e−αt [B1 cosωdt+B2 sinωdt] (A.30)

where:

B1 = A1 +A2 (A.31)B2 = j(A1 −A2) (A.32)

Remark A.1 Equation (A.30) is the solution for the underdamped situation inan RLC circuit. Underdamping is characterised by α2 < ω2

0, which means thats1 and s2 in (A.28) are complex terms.


In order that we can determine the B1 and B2 coefficients we apply some bound-ary conditions:

v0(0) = V0 (A.33)dv0(0)

dt= 0 (A.34)

Applying the first of these conditions to (A.30) we can write:

B1 = V0 (A.35)

Taking the derivative of (A.30) we get:

dv0

dt= e−αt [(B2ωd − αB1) cosωdt− (B1ωd + αB2) sinωdt] (A.36)

Applying (A.34) to this expression gives:

αB1 = B2ωd ⇒ B2 =αV0

ωd(A.37)

and hence the voltage equation becomes:

v0(t) = V0e−αt

[cosωdt+

α

ωdsinωdt

](A.38)

and the derivative of this is:

dv0(t)

dt= −V0

[(ωd +

α2

ωd

)sinωdt

](A.39)

From (A.8), (A.7), (A.6) and (A.25) we can derive the following expressions:

ωd =

√1

LC− R2

4L2

=

√1

LC− 1

4LCQ2

=1√LC

√1− 1

4Q2(A.40)

We shall assume that Q > 0.5, which means that the circuit is underdampedand ωd > 0.

If we want to find the point of the first maximum swing in the time response(i.e. the first maximum in the oscillatory response), then we know this mustoccur when ωdt = π. Therefore:

tfm =π

ωd

⇒ tfm =π√LC√

1− 14Q2

(A.41)


We also also write:

v0(tfm) = −V0eαtfm since ωdtfm = π

∴ v0(tfm) = −V0e− R

2L

π√LC√

1− 14Q2

= −V0e

[−π√

4Q2−1

](A.42)

Figure A.3 shows that time plot for a series RLC circuit. In this particularcase the circuit Q is 6.3.

From (A.42) we can drawn the conclusion that:

Vovershoot/Vstep = e

[−π√

4Q2−1

](A.43)

0 0.5 1 1.5 2 2.5 3 3.5 4-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

v t V efm

Q0 0

4 12

( ) = -

-

-

p

eR

Lt-

L

NMO

QP2

tLC

Q

fm=

-

p

11

4 2

Time (secs)t

Vol

tage

vol

tsv

Figure A.3: Time response of a series RLC circuit with Q = 6.3.

A.1.2.1 Forced Response of Series RLC Circuit with Initial InductorCurrent

In this section we shall consider the forced response of the series RLC circuitwhere we have an initial inductor current. The forced response will assumedto be a constant input voltage. More general forcing functions will not beconsidered as they are not required for the material in these notes.

Consider (A.1) which is the general differential equation for the series RLCcircuit. For a constant input voltage the equation becomes:

Rdi

dt+ L

d2i

dt2+

i

C= 0 (A.44)


The natural response for this circuit is of a similar form as that in (A.28) exceptthat the left side of the equation is i(t). As per general theory for the solutionof differential equations, the total solution is the sum of the natural responseand the forced response. Therefore the solution is:

i(t) = A1es1t +A2e

s2t + if (A.45)

where if is the forced response. The forced response in the case of a constantinput voltage is zero as the capacitor is an open circuit as time goes to infinity.Therefore the situation degrades to the simple natural response.

Therefore, assuming the underdamped situation, the solution to the currentequation is of the same form as (A.30) except that it is in terms of current andnot voltage. It can be written as:

i(t) = e−αt(B1 cosωdt+B2 sinωdt) (A.46)

However the initial conditions are now different. We know the following att = 0:

i(0) = B1 = i0 (A.47)

where i0 is the initial inductor current.Taking the derivative of (A.46) we can write (similarly to (A.36)):

di(t)

dt= e−αt [(ωdB2 − αB2) cosωdt− (ωdB1 + αB2) sinωd] (A.48)

The second initial condition is with respect to the derivative of the current. Weknow that:

vL = Ldi

dt(A.49)

therefore at t = 0 we have that:

di(0)

dt=vL(0)

L=Vin − i0R

L(A.50)

since the capacitor is assumed to be uncharged.Clearly at t = 0 the second term of (A.48) is zero, therefore we can write:

ωdB2 − αi0 =Vin − i0R

L(A.51)

∴ B2 =Vin − i0R+ αi0L

ωdL(A.52)

Substituting for B1 and B2 into (A.46) we can write:

i(t) = e−αt[i0 cosωdt+

(Vin − i0R+ αi0L

ωdL

)sinωdt

](A.53)

A.2 Parallel RLC CircuitsThis section carries out a similar analysis for a parallel circuit RLC as wascarried out above for the series RLC circuit. To a large extent the results for

A.2 Parallel RLC Circuits A-9

this circuit configuration are a dual of those above, therefore some of the analysishere will be brief.

The following discussion will be with reference to Figure A.4. If one appliesnodal analysis to this figure one can write the following differential equation forthe circuit:

d2vindt2

+1

RC

dvindt

+vinLC

=1

C

diindt

(A.54)

If we take the Laplace transform of this and rearrange we can get the followingtransfer function: transfer function

iin(s)

vin(s)=C(s2 + 1

RC s+ 1LC )

s(A.55)

vin

iin

R L C

Figure A.4: Parallel RLC circuit.

The impedance transfer function can be simply written from a rearrangement impedance transferfunctionof A.55 as:

Z(s) =vin(s)

iin(s)=

s

C(s2 + 1RC s+ 1

LC )(A.56)

As in the series RLC circuit case we can now find the poles of this transfer polesfunction, which have a similar form to those for the series RLC circuit:

s = −α±√α2 − ω2

o (A.57)

where:

α =1

2RC(A.58)

ωo =1√LC

(A.59)

As with the series RLC circuit we can define:

ωd =√ω2o − α2 (A.60)

Critical damping is defined similarly to that for series RLC circuits in that Critical damping


ωd = 0. This leads to:

α = ωo

∴1

2RC=

1√LC

⇒ R =1

2

√1

LC(A.61)

The impedance of the circuit at resonance, as with the series RLC circuit,is of interest. Substituting s = jω into (A.56) and simplifying and taking themagnitude we can write:

|Z(s)| = ω√ω2

R2 +(

1L − Cω2

) (A.62)

If ω = ωo = 1/√LC then:

|Z(s)| = R (A.63)

which can be shown to be the maximum impedance of the circuit.

A.2.1 Quality Factor

This will not be evaluated in the same detail as was carried out in the series RLCcircuit section since the development is so close. However, the key expressionswill be presented. It is assumed that the input voltage has the form:

vin = Vm cosωot (A.64)

Therefore the current into the inductor is:

i =1

L

∫ t

0

vindτ

=1

L

∫ t

0

Vm cosωotdτ

∴ i =VmLωo

sinωot (A.65)

The energy stored in the inductor is therefore:

eL(t) =1

2Li2

=1

2V 2mC sin2 ωot (A.66)

Similarly the energy stored in the capacitor is:

eC(t) =1

2Cv2

in

=1

2CV 2

m cos2 ωot (A.67)

A.2 Parallel RLC Circuits A-11

The total stored energy is:

eT (t) = eL(t) + eC(t)

=1

2V 2mC(sin2 ωot+ cos2 ωot)

=1

2V 2mC (A.68)

The energy dissipated in the resistor is:

eR(t) = PRTo =V 2mTo2R

=V 2m

2foR(A.69)

Applying the definition of quality factor (A.16) we can write:

Q = 2π12V

2mCV 2m

2foR

= 2πfoRC = ωoRC

= R

√C

L(A.70)

Appendix B

Introduction to Space Vectors

B.1 Introduction

This appendix introduces the concept of space vectors. This introduction iscarried out in a three stage process. Firstly consideration is given to machinewindings to demonstrate that electrical machines can be accurately modeled us-ing sinusoidal functions, even under conditions where there are non-sinusoidalwaveforms present. The sinusoidal assumption is very important in machinemodeling, and is developed because space vectors are developed based on sinu-soidal function variations in machines.

The second part of the appendix uses the sinusoidal assumption to developdq models for electrical machines. Even though dq models were originally devel-oped for electrical machines they find much more general use in power systemsand power electronics where one has three phase supplies. Finally space vec-tor models are developed as an extension of dq modeling, and the connectionsbetween them are shown.

B.2 The Sinusoidal Assumption

One of the main assumptions that is used in the modeling of many types of ACmachines is the sinusoidal assumption. Essentially the assumption is that thewindings in the machine are arranged so that the resultant mmf has a spatiallysinusoidal distribution. A normal AC machine usually has three windings spacedat 120 electrical, each producing a spatially sinusoidal mmf when fed with acurrent. An amazing property of this arrangement is that if it is fed with threetemporal sinusoidal currents, separated temporally by 120, then the resultantmmf is a spatially moving sine wave around the machine (this will be shownmathematically in later sections in this Chapter).

Why is this assumption so important? From a modeling point of view thesinusoidal functions have a rich set of mathematical properties which makethe modeling of machines analytically tractable. One of the key properties ofsinusoidal functions is their connection with vectors, and the consequent abilityto take orthogonal components of them.

In reality the mmf produced by real windings are not pure sinusoids. Mostwindings for real machines are confined to slots in the stator. This leads to an

B-2 Introduction to Space Vectors

mmf that has step changes in it, and consequent higher order spatial harmonics.However, the winding configuration is designed to minimize these harmonics. Aswe shall see below, the significance of these winding harmonics on the perfor-mance of the machine also depends on the harmonics in the flux waveforms thatinteract with the windings.

The sinusoidal assumption is not only applied to the mmf produced by thewindings, but it is also applied to the resultant fluxes produced by the action ofthe mmf on the iron circuit of the machine. In the case of the SYNCREL theiron circuit reluctance varies in a complex fashion due to the rotor saliency. Thismeans that the flux density produced by the mmf is in general not spatially si-nusoidal. However, the harmonics in these waveforms are usually neglected, andonly the fundamental component is considered from an analysis point of view.This may seem to be a gross approximation, but models developed using thisapproach have been shown to give reasonable representations of the behaviourof real machines.

In the remainder of this section we shall look at some of the propertiesof a sinusoidally distributed winding. Specifically, the characteristics of a non-sinusoidal flux density interacting with a sinusoidal winding shall be considered.This is of particular relevance to the SYNCREL and other salient pole machinesas their flux density distributions in general are not sinusoidal.

The remainder of this section discusses the foundations of the sinusoidalassumption, and why it can be used successfully to simplify the modeling ofmachines, with special emphasis on the SYNCREL. Specific issues addressedare:

• Consideration of some of the general properties of sinusoidally distributedwindings (e.g. only link with fields of the same pole number).

• Detailed analysis of the variation of inductance with rotor position for atwo pole axially laminated rotor would be beneficial.

B.2.1 Winding Interaction with Spatial Flux Density Dis-tribution

In this sub-section we shall consider the interaction of a spatially non-sinusoidalflux density distribution with an ideal sinusoidal winding. Such an ideal wind-ing will produce a temporal sinusoidally varying current density around themachine. The following equation can be written for the conductor density as afunction of the angle θp around the periphery of the machine:

n(θp) = na sin θp (B.1)

This waveform has an amplitude of na conductors, and goes positive and neg-ative. How can one have positive and negative numbers of conductors? Thesign convention is based on the direction of the current in the conductor. Thepositive part of this conductor distribution carry currents in one direction, andthe negative part carry the return currents [7].

Given this winding distribution, the mmf spatial distribution readily follows.If the a-phase is carrying ia amps, then the mmf can be calculated by imple-menting Ampere’s Law. This is achieved by carrying out a closed path integral

B.2 The Sinusoidal Assumption B-3

Figure B.1: MMF calculation integration path.

over the full coil span (see Figure B.1 for the path of integration):

FaT (θp) =

∫ θp+π

θp

naia sin θp dθp

= 2naia cos θp

= 2Fa cos θp

∴ Fa(θp) = Fa cos θp where Fa = naia (B.2)

The ‘2’ factor in the front of the right hand side of the above expression isthere because the total mmf is expended across two air gaps, and the Fa(θp)expression represents the mmf expended per air gap.

The total number of coils in the winding is simply the sum of the numberof coils at each θp position. Due to the continuous nature of the proposeddistribution this sum becomes an integral:

Na =

∫ π

0

na sin θp dθp

= 2na (B.3)

Therefore the peak mmf for the winding may be written as:

Fa =Naia

2

Now let us consider some general flux density waveform that varies in thefollowing way spatially with respect to θp around the machine, and also has a


time varying spatial phase angle δ(t):

B(θp) = Bn sinn(θp − δ(t)) (B.4)

This flux waveform is a non-sinusoidal waveform as it contains a number ofharmonics denoted by the integer value of n.

Furthermore assume that the winding is on a machine with the followingphysical dimensions:

l , the length of the machine.

vB , the linear velocity of the B field.

r , the radius of the stator of the machine.

Therefore the B(θp) field phase is changing in the following fashion:

δ(t) =vBt

r(B.5)

This expression implies that the B(θp) field is spatially moving with respect totime.

From basic physics we can say the following – the voltage induced in a lengthof conductor l, moving with a velocity of vB perpendicular to a magnetic fluxdensity of B is:

e = BlvB (B.6)

In the case of a sinusoidally distributed coil the length of conductor for oneside of the coil at some position θp is:

lT = nal sin θp (B.7)

therefore the induced voltage in the conductors at this angular position is:

e(θp) = BvBnal sin θp (B.8)

The flux density at this position at a particular instant of time can be determinedfrom (B.4), and consequently (B.8) becomes:

e(θp) = vBnalBn sin θp sinn(θp − δ(t)) (B.9)

To simplify the following manipulations let Kn , vBnalBn. In order to cal-culate the total voltage produced by these conductors we have to add up thecontributions of all the conductors in the coil. This involves integrating thevoltage at each position θp for the circumference of the machine. Thereforeassuming a single pole pair machine we have:

eT =

∫ 2π

0

Kn sin θp sinn(θp −vBt

r)dθp (B.10)

Using the trigonometric relation sinx sin y = 1/2[sin(x+y)+sin(x−y)] one canwrite:

eT =

∫ 2π

0

Kn

2

[sin

((n+ 1)θp −

nvBt

r

)+ sin

((n− 1)θp −

nvBt

r

)]dθp

(B.11)


For the specific case of n = 1 (i.e. only the fundamental harmonic present)then (B.11) can be integrated and becomes:

eT = K1π sin

(vBt

r

)= K1π sin(ωBt) (B.12)

i.e. the voltage induced by the winding is a temporal sinusoidal voltage (asexpected).

Now consider what happens to the higher order harmonics in the flux densitywaveform. If we carry out the integration of (B.11) for the case of n > 1 wehave:

eT =Kn

2

[− cos

n+ 1

(2π(n+ 1)− nvBt

r

)− cos

n− 1

(2π(n− 1)− nvBt

r

)+

(1

n+ 1+

1

n− 1

)cos

(−nvBtr

)](B.13)

If we consider the various terms in (B.13) using the trigonometric relation:

cos(x− y) = cosx cos y + sinx sin y (B.14)

we get the following:

− cos

n+ 1

(2π(n+ 1)− nvBt

r

)= − 1

n+ 1

[cos 2π(n+ 1) cos

nvBt

r

+ sin 2π(n+ 1) sinnvBt

r

]= − 1

n+ 1cos

nvBt

r(B.15)

and similarly:

− cos

n− 1

(2π(n− 1)− nvBt

r

)= − 1

n− 1cos

nvBt

r(B.16)

Therefore (B.13) can be written as:

eT =Kn

2

[−(

1

n+ 1+

1

n− 1

)cos

nvBt

r+

(1

n+ 1+

1

n− 1

)cos−nvBtr

]= 0; ∀ n > 1 (B.17)

Remark B.1 The implications of the above expression are that the higher orderharmonics in the flux density spatial waveform do not link to the sinusoidallydistributed winding. In other words the pole number of the flux density waveformhas to be the same as that of the winding. This is a very important propertyof sinusoidal windings. One can then consider the flux density harmonics to becontributing to the leakage flux.

Remark B.2 Real machine windings are not exactly sinusoidally distributed asin the ideal case above. Therefore there are spatial harmonics in the windingdistribution itself. Consequently it is possible for higher order harmonics in the


Figure B.2: Dimensions of a single coil.

flux density waveform to link with same pole number harmonic in the windingdistribution, resulting in a harmonic voltage. For example, most winding con-figurations contain a significant third harmonic spatial component, therefore thethird harmonic in the flux density waveform (introduced by saturation effects)can link with the individual windings. Consequently third harmonic voltages canbe seen in the phase voltages.

B.2.2 Winding Interaction with Temporal Flux DensityVariation

In this section we consider a non-sinusoidal, spatially stationary flux densitydistribution which has a sinusoidal temporal variation, interacting with a sinu-soidal winding distribution. For the sake of the following argument consider theflux density to have the following form:

B(θp) = Bn cosnθp (B.18)

Let us firstly consider the n = 1 case. Consider a single coil which has thedimensions shown in Figure B.2. One can calculate the flux linking a coil atany position using the general expression:

φ =

∮B.dS (B.19)

Consider the situation where there is only the fundamental flux density dis-tribution. The above surface integral can be written as follows (using Figure B.2)


for the flux at angle coil position θp1:

φ(θp) = B1r

∫ θp+π

θp

∫ l

0

cos θ dl dθ

= B1r

∫ θp+π

θp

l cos θ dθ

= −2B1rl sin θp (B.20)

The dot product is eliminated in this situation as the flux density is perpendic-ular to the integration surface.

In order to get the voltage induced in the coils at a particular position aroundthe machine the following calculation has to be carried out:

e(θp) = n(θp)dφ(θp)

dt(B.21)

= na sin θpd

dt

(−2B1rl sin θp

)= −2narlB1 sin2 θp

ωcosωt (B.22)

Remark B.3 Equation (B.22) is obtained by realising that we are dealing witha sinusoidal temporal variation of a sinusoidal spatial distribution. Thereforethe amplitude of the flux density is varying with respect to time in a sinusoidalmanner. Therefore:

B1 = B1 sinωt (B.23)

where ω is the frequency of the temporal variation. It is important to realisethat the θp angle in (B.22) is constant with respect to time in this case.

To find the total voltage for the whole winding the individual contributions forthe number of turns at each position θp have to be added:

eT =

∫ π

0

e(θp) dθp

=−2narlB1 cosωt

ω

∫ π

0

sin2 θp dθp

=−narlB1π

ωcosωt (B.24)

i.e. a temporal sinusoidal voltage is produced from the winding as one wouldexpect.

The more interesting case is when the flux density spatial distribution isnon-sinusoidal as in (B.18). In this case the flux for a single coil is:

φ(θp)n = Bnr

∫ θp+π

θp

∫ l

0

cosnθ dl dθ

=Bnrl

n[sinn(θp + π)− sinnθp] (B.25)

1Note that the θp in the following expression is the angle of the most clockwise side of thecoil.


Clearly φ(θp)n = 0 for n even. Therefore the even harmonics do not link to asingle coil.

For the n odd case it can be seen that the expression for the flux becomes:

φ(θp)n =−2Bnrl

nsinnθp (B.26)

To calculate the voltage in a single coil at some position θp we again apply(B.21). Carrying out the differentiation on (B.26) we get:

e(θp)n =−2naBnrl

nωsin θp sinnθp cosωt :n is odd (B.27)

To get the total voltage due to the winding the individual contributions areintegrated as in the previous case:

eT =−2naBnrl cosωt

nω

∫ π

0

sin θp sinnθp dθp (B.28)

It can be shown that∫ π

0sin θp sinnθp dθp = 0, therefore the total voltage due to

the odd harmonics is zero. Therefore, as with the spatially moving flux densitycase, only the component of the flux density that has the same pole number asthe winding links with the winding, even if the harmonics are space stationaryand have a time varying amplitude.

Remark B.4 The main implications of the above analysis is that the flux den-sity component with the same pole number as the winding links with the winding.Therefore, for a pure sinusoidally distributed winding, the harmonics in the fluxdensity only contribute to the leakage flux, and do not have a role in determiningthe performance of the machine. However, in reality a pure sinusoidal windingcannot be produced, and there are spatial harmonics in the winding distribution.Therefore, harmonics in the flux density waveform can link with similar polenumber harmonics in the winding distribution resulting in higher order voltageharmonics being produced in the winding. These harmonics will also have aninfluence on machine performance.

B.3 dq ModelsMost electrical machines with sinusoidally distributed windings are modeledmathematically using a technique called dq modeling. We actually used a re-stricted form of dq modeling in Section C.1, where the dq axes were stronglyassociated with the different permeance axes of the rotor. It is not the purposeof this chapter to give an exhaustive derivation of dq modeling of machines,as this has been done in many machines text books. However, an overview ofthe principles of dq modeling will be presented, and then the dq model for theSYNCREL will be derived.

The fundamental assumption used as the basis of dq modeling is that thewinding distribution in a machine is sinusoidal. In addition a number of othersecondary assumptions are made, which are similar to the assumptions used inSection C.1, namely:

a. The machine does not exhibit stator or rotor slotting effects.

B.3 dq Models B-9

120

Figure B.3: Three phase to two phase transformation.

b. The machine iron is linear material, i.e. there is no saturation effects.

The combined effect of these assumptions is that traditional linear circuit anal-ysis techniques can be used to analyse the electrical circuit of a machine. Thesinusoidal assumption means that various spatial quantities in the machine canbe broken into orthogonal components. It is this that is used to carry out coor-dinate transformations from the three phase axes of a machine to the two phasedq axes.

B.3.1 Stationary Frame Transformations

The general idea of a dq type of transformation can be obtained by consideringthe transformation of the three phase currents to their two phase equivalents.Consider Figure B.3. This shows a conceptual diagram of a three phase ma-chine. The windings represented by the concentrated coils are actually spatiallysinusoidal distributed windings similar to that shown in Figure B.1. The linesthrough the centre of the coils are the axes of the associated winding mmfs, andtherefore can be thought of as a vector that represents the sinusoidal quantities.

B.3.1.1 MMF transformations

Given that the space distribution of the mmfs for windings a, b and c can bemodeled similarly to (B.2) then the following expressions can be written for themmfs:

Fa = Fa cos θp (B.29)

Fb = Fb cos

(θp −

2π

3

)(B.30)

Fc = Fc cos

(θp +

2π

3

)(B.31)


where θp is defined in Figure B.3. The resultant mmf distribution for the threephase machine is:

FT = Fa cos θp + Fb cos

(θp −

2π

3

)+ Fc cos

(θp +

2π

3

)(B.32)

Assuming that the three phase windings have identical turns, and they are beingdriven by three phase currents of the form:

ia = Ipk cosωt (B.33)

ib = Ipk cos

(ωt− 2π

3

)(B.34)

ic = Ipk cos

(ωt+

2π

3

)(B.35)

then (B.32) can be written as:

FT = NIpk

[cosωt cos θp + cos

(ωt− 2π

3

)cos

(θp −

2π

3

)+ cos

(ωt+

2π

3

)cos

(θp +

2π

3

)]=

3

2NIpk cos(ωt− θp) (B.36)

i.e. the resultant mmf has a spatial sinusoidal distribution which is rotatingaround the machine at ωt electrical radians per second.

Remark B.5 Note that this total mmf is expended across two air gaps. There-fore the mmf per air gap is half the value in FT .

If the vectors associated with (B.29), (B.30) and (B.31) are resolved along twoorthogonal axes called the dq axes then the following expressions can be writtenfor the resultant dq axes mmfs:

Fsdq = TFabc (B.37)

i.e.[F sdF sq

]=

[1 − 1

2 − 12

0√

32 −

√3

2

] FaFbFc

(B.38)

It can be shown that F sd + F sq gives the same resultant mmf distributionaround the machine as the original three phase machine. In other words thattransformation has converted the three phase into an equivalent two phase ma-chine with the same mmf distribution.

Addition Add the proof that the DQ axes calculations give the same resultantmmf.

In order to make this transformation invertible the T matrix and Fsdq vector areaugmented as follows: F sd

F sqFγs

=

1 − 12 − 1

2

0√

32 −

√3

21√2

1√2

1√2

FaFbFc

(B.39)

i.e. Fsdqγ = SFabc (B.40)

and Fabc = S−1Fsdqγ (B.41)

B.3 dq Models B-11

where:

S−1 =

23 0

√2

3

− 13

1√3

√2

3

− 13 − 1√

3

√2

3

=2

3

1 0 1√2

− 12

√3

21√2

− 12 −

√3

21√2

i.e. S−1 =

2

3ST (B.42)

The choice of the 1/√

2 augmentation of T was made so that the propertyin (B.42) was obtained. Note that the Fγ term is zero if the three phase mmfscontain no zero sequence components, else this term is not zero. Therefore, fora star connected machine with an isolated neutral Fγ always equals zero, sinceone cannot have zero sequence currents with this configuration.

B.3.1.2 Current Transformations

Given the mmf transformation in the previous section, it is a simple matter toconstruct the transformation for the three phase currents to their equivalent twophase currents. This transformation can be handled in two sensible ways. Thetransformation could be carried out in such a way that the transformed machineproduces the same total power as the original three phase machine. Such trans-formations are called power invariant transformations. Another transformationcan be implemented such that the transformed machine produces 2/3rds thepower of the three phase machine. This is one particular example of a powervariant transformation. Usually the power variant transformation is used, sinceit turns out that in steady state the two phase currents and voltages have ex-actly the same amplitude as the phase voltages and currents of the three phasemachine. If the magnitude of the two phase quantity is taken, and then pro-jected onto the relevant three phase axis, then the instantaneous phase valuecan be found. This transformation is commonly used in the machine modelingliterature because of this property.

Consider the situation where the two phase machine has 2/3rds the resultantmmf compared to the three phase machine. It can be shown that this meansthat the right hand side of (B.40) has to be multiplied by 2/3. Therefore (B.40)and (B.41) can be written as:

Fsdqy =2

3SFabc (B.43)

Fabc =3

2S−1Fsdqγ = STFsdqγ (B.44)

Now consider the mmf expressions expressed in terms of currents and windingturns:

Fsdqγ = N2φisdqγ (B.45)

Fabc = N3φiabc (B.46)


Using (B.43) one can write:

N2φisdqγ =

2

3SN3φiabc (B.47)

where:

N2φ , the number of turns for a windingof the two phase dqγ machine.

N3φ , the number of turns for each windingof the three phase machine.

Since the two phase dqγ machine is an artificial machine of our creation,we are free to choose the number of turns for each of the windings. Clearly ifN2φ = N3φ, i.e. the two phase machine has the same number of turns on itswindings as the three phase machine, and the is relationship has the same formas the mmf relationship. Consequently the isdqγ vector has 2/3rds the magnitudeof the iabc resultant current vector. Therefore the current relationships betweenthe two machines is:

isdqγ =2

3Siabc (B.48)

iabc = ST isdqγ (B.49)

B.3.1.3 Voltage Transformations

Similarly, one can derive the relationship between the three phase and two phasevoltages. Consider the power relationships for the two machines:

P3φ = vTabciabc (B.50)

P2φ = vsT

dqγidqγ (B.51)

We want P2φ = 2/3P3φ. Therefore substituting (B.50) and (B.51) into thisexpression and using (B.48) one can obtain:

vsdqγ =2

3Svabc (B.52)

vabc = STvsdqγ (B.53)

Notice that this expression is in the same form as that for the current. Thereforeit has the same property that the magnitude of the voltage vector is 2/3rds thatof the voltage vector for the three phase machine. If one considers the casewhere the windings are excited by three phase currents of the form in (B.33),(B.34) and (B.35), then it is easy to show that:∣∣isdqγ∣∣ = Ipk (B.54)

i.e. the magnitude of the resultant dqγ vector is equal to the peak current in aphase in steady state. Similarly we can write:∣∣vsdqγ∣∣ = Vpk (B.55)

where Vpk , the peak of three phase sinusoidal voltages supplying the abcwindings. Therefore the use of the 2/3rds power relationship has allowed oneto easily correlate the dqγ voltages and currents to their abc counterparts.

B.3 dq Models B-13

B.3.1.4 Impedance Transformations

Next we need to consider the transformation of the machine parameters be-tween the three phase and two phase machines. Consider the following generalexpressions for the two machines:

vabc = Zabciabc (B.56)vsdqγ = Zsdqγi

sdqγ (B.57)

Using (B.56) together with (B.49) and (B.53) one can write:

vsdqγ =2

3SZabcS

T isdqγ (B.58)

Comparing this expression with (B.57) one can see that:

Zsdqγ =2

3SZabcS

T (B.59)

and Zabc =2

3STZsdqγS (B.60)

These general impedance transformations can be used to generate specifictransformations for the inductances and resistances for a three phase winding.For a three phase winding the impedance matrix can be written as:

Zabc =

Ra + Laap Labp LacpLbap Rb + Lbbp LbcpLcap Lcbp Rc + Lccp

(B.61)

where p , d/dt.By inspection it can be seen that the resistive and inductive transformations

become:

Rsdqγ =

2

3SRabcS

T (B.62)

Rabc =2

3STRs

dqγS (B.63)

Lsdqγ =2

3SLabcS

T (B.64)

Labc =2

3STLsdqγS (B.65)

where:

Rabc =

Ra 0 00 Rb 00 0 Rc

Labc =

Laa Lab LacLba Lbb LbcLca Lcb Lcc


To dqγs To abcFsdqγ = 2

3SFabc Fabc = STFsdqγisdqγ = 2

3Siabc iabc = ST isdqγvsdqγ = 2

3Svabc vabc = STvsdqγΨsdqγ = 2

3SΨabc Ψabc = STΨsdqγ

Lsdqγ = 23SLabcS

T Labc = 23STLsdqγS

Rsdqγ = 2

3SRabcST Rabc = 2

3STRsdqγS

Zsdqγ = 23SZabcS

T Zabc = 23STZsdqγS

Table B.1: Summary of Stationary Frame Transformations

B.3.1.5 Flux Linkage Transformations

Now that we have the inductance and current transformations it is possible todevelop the transformations for the flux linkages. The flux linkage expressionsfor the three and two phase machines are:

Ψabc = Labciabc (B.66)Ψsdqγ = Lsdqγi

sdqγ (B.67)

If (B.64) and (B.48) are substituted into (B.67) then one gets:

Ψsdqγ =

2

3SLabc

2

3STSiabc

=2

3SLabciabc

∴ Ψsdqγ =

2

3SΨabc (B.68)

and Ψabc = STΨsdqγ (B.69)

The stationary frame transformations are summarized in Table B.1.

B.3.2 Rotating Frame TransformationsThe transformation in (B.40) allows the three phase windings to be representedby an equivalent set of two phase windings. These winding are stationary withrespect to the original three phase winding. It is then possible to project thestationary two phase windings onto two phase windings that are at some angleto the stationary winding axes and moving with respect to these axes.

The following discussion is with respect to Figure B.4. This diagram showsa rotating dq axes with respect to the stationary dq axes derived in the previoussection. The angle θsr is defined with reference to the rotating axis as this makesit easier to see the projections of the stationary quantities onto this axis. Usingthe normal convention for angle sign (anti-clockwise is positive angle), one canwrite the following expressions:

F rd1 = F sd cos θsr (B.70)

F rd2 = F sq cos(θsr +π

2) = −F sq sin θsr (B.71)

F rq1 = F sq cos θsr (B.72)

F rq2 = F sd sin θsr (B.73)

B.3 dq Models B-15

Clearly the total mmf on each of the rotating axes is:

F rd = F rd1 + F rd2= F sd cos θsr − F sq sin θsr (B.74)

F rq = F rq1 + F rq2

= F sq cos θsr + F sd sin θsr (B.75)

This expression can be written more succinctly in matrix form:[F rdF rq

]=

[cos θsr − sin θsrsin θsr cos θsr

] [F sdF sq

](B.76)

The zero sequence component can be included by ensuring that it makes nocontribution to the projected vectors as follows: F rd

F rqF rγ

=

cos θsr − sin θsr 0sin θsr cos θsr 0

0 0 1

F sdF sqF sγ

(B.77)

and

F sdF sqF sγ

=

cos θsr sin θsr 0− sin θsr cos θsr 0

0 0 1

F rdF rqF rγ

(B.78)

To make the θ definition consistent with the angle definition used to define theinductance expressions, use θsr = −θrs. Therefore the above can be written as: F rd

F rqF rγ

=

cos θrs sin θrs 0− sin θrs cos θrs 0

0 0 1

F sdF sqF sγ

(B.79)

and

F sdF sqF sγ

=

cos θrs − sin θrs 0sin θrs cos θrs 0

0 0 1

F rdF rqF rγ

(B.80)

These relationships can be written in short form as:

Frdqγ = BFsdqγ (B.81)

Fsdqγ = BTFrdqγ (B.82)

The stationary to rotating frame transformation can be combined with thethree phase to stationary two phase transformation to give the transformationfrom a three phase stationary frame to an arbitrary rotating frame. Clearly thetransformations for the mmf are (using (B.43) and (B.44)):

Frdqγ =2

3CFabc (B.83)

Fabc = CTFrdqγ (B.84)


Figure B.4: Two phase stationary to two phase rotating transformations.

where:

C = BS =

cos θrs cos(θrs − 2π3 ) cos(θrs + 2π

3 )− sin θrs − sin(θrs − 2π

3 ) − sin(θrs + 2π3 )

1√2

1√2

1√2

(B.85)

CT = STBT =

cos θrs − sin θrs1√2

cos(θrs − 2π3 ) − sin(θrs − 2π

3 ) 1√2

cos(θrs + 2π3 ) − sin(θrs + 2π

3 ) 1√2

(B.86)

It can be shown that all the transformations from the abc frame to the dqγrframe have the same form as the stationary frame transformations of Table B.1,except that C and CT are substituted for S and ST respectively, and the su-perscript on the variables becomes r.

From Faraday’s law it is possible to express the voltages in terms of rateof change of flux linkage. In the case of the rotating transformations, this rateof change can be from two causes; (a) the time rate of change of flux linkagecaused by the time rate of change of currents, and (b) the rate of change due tothe relative movement of the frames. The general Faraday relationship is:

vabc = pΨabc (B.87)

and Ψabc = CTΨrdqγ (B.88)

therefore vabc = pCTΨrdqγ (B.89)

As can be seen from (B.85), the C matrix is a time dependent matrix, sinceθrs is changing with respect to time. Therefore expanding (B.89) using the

B.3 dq Models B-17

To dqγr To abcFrdqγ = 2

3CFabc Fabc = CTFrdqγirdqγ = 2

3Ciabc iabc = CT irdqγvrdqγ = 2

3Cvabc vabc = CTvrdqγΨrdqγ = 2

3CΨabc Ψabc = CTΨrdqγ

Lrdqγ = 23CLabcC

T Labc = 23CTLrdqγC

Rrdqγ = 2

3CRabcCT Rabc = 2

3CTRrdqγC

Zrdqγ = 23CZabcC

T Zabc = 23CTZrdqγC

Table B.2: Summary of Rotating Frame Transformations

chain rule one gets:

vabc = pCT Ψrdqγ + CT pΨr

dqγ (B.90)

If one expands (B.90) by taking the appropriate derivatives, and then rearrangesthe result the following expression can be obtained:

vabc = CT

p ψrdψrqψrγ

+ ωrs

−ψrqψrd0

= CTvrdqγ (B.91)

∴ vrdqγ = p

ψrdψrqψrγ

+ ωrs

−ψrqψrd0

(B.92)

As we shall see in the next section, (B.92) is the form of the reluctance machinedq equations.

A summary of the transformations from a stationary frame to a rotatingframe appear in Table B.2.

B.3.3 Example – SYNCREL Linear dq Model

Using the transformations and inductance expressions from the previous sec-tions we are now in the position to form a linear dq model for the three phaseSYNCREL. The transformation process will be carried out in a two stage pro-cess. The first step in process is to convert the three phase model of the machineto the two phase stationary frame model of the machine. Then this model isconverted to a two phase rotating model. The reason for this doing this twostage process is to expose the nature of the two phase stationary frame machine,whereas if a direct transformation to the rotating frame is carried out then thismodel is stepped over. The following discussion is with reference to Figure B.5.This diagram shows a three phase, two pole SYNCREL. The stationary dq frameis aligned with the d-axis along the a-phase mmf axis. The rotating d-axis islocated along the high permeance axis of the rotor. Because the SYNCREL isa synchronous machine, the rotor has to be synchronized with the rotating fieldin steady state. Hence this frame is also synchronized with this field, and isknown as a synchronously rotating reference frame. In this frame it will be seenthat the angle dependence of the inductances disappears, and the currents andvoltages are D.C. values in steady state.


Figure B.5: Conceptual diagram of a three phase SYNCREL.

The most complicated part of the three phase machine to two phase machineconversion is the inductance transformation, so we shall look at this in detail.The inductances for this model were calculated in Section C.1 and appear in(C.56) and (C.57). These inductance expressions have to be transformed usingthe transformations in Table B.1. The inductance matrix in the stationaryframe becomes:

Lsdqγ =3

2

23Ll + L1 + L2 cos 2θpd L2 sin 2θpd 0

L2 sin 2θpd23Ll + L1 − L2 cos 2θpd 0

0 0 23Ll

(B.93)

Equation (B.93) can now be converted to the rotating frame by carrying outthe BLsdqγB

T transformation using the fact that θrs = θpd (i.e. the referenceframe d-axis is aligned with the high permeance axis of the rotor). After consid-erable manipulation one arrives at the following expression for the dq inductancematrix:

Lrdqγ =

Ll + 32 (L1 + L2) 0 0

0 Ll + 32 (L1 − L2) 0

0 0 Ll

(B.94)

If one assumes that the system has not zero sequence currents flowing (i.e.the machine has star connected windings with an open circuit neutral) then thelast column and row can be deleted from the above matrices. Therefore therelevant matrix for the dq inductances is:

Lrdq =

[Ll + 3

2 (L1 + L2) 00 Ll + 3

2 (L1 − L2)

](B.95)

B.3 dq Models B-19

Notice in (B.95) that the θpd dependent inductance values of the originalthree phase model have been converted to time invariant and θpd independentinductances in the dq frame. This results from the fact that the dq referenceframe is tied to the rotor. If one were measuring the inductance whilst fixedto the rotor, the inductance will not change as the rotor is rotated (assuminga non-salient stator). In addition, the transformed windings that are fixedto this frame do not see any movement of the rotor from the moving d-axis,and therefore the mutual inductance term to the orthogonal winding is zero.A consequence of this simplification of the inductances is that the dq framedynamic equations are much simpler than the three phase equations.

In (B.92) we calculated the generic form of the dq dynamic equations takinginto account only the voltage terms due to the flux linkages. If the three phaseconversion process is carried out for the resistance it can be shown that the dqvalues are identical to the three phase values. Therefore, the generic dq equationcan be rewritten in the following form if we include the resistive drop term anduse the fact that the dq inductances are time invariant:

vrdq =

[RR

]irdq +

[LrdLrq

]pirdq + ωpd

[−LrqLrd

]irqd (B.96)

which can be written in scalar form as:

vrd = Rird + Lrddirddt − ωpdL

rqirq

vrq = Rirq + Lrqdirqdt + ωpdL

rdird

(B.97)

where:

Lrd = Ll +3

2(L1 + L2)

Lrq = Ll +3

2(L1 − L2)

Equation (B.97) is shown in diagram form in Figure B.6.It should be noted that the magnitude of the total flux linkage for the SYN-

CREL can be written in terms of the d and q-axis inductances as follows:

ψ =√

(Lrdird)

2 + (Lrqirq)

2 (B.98)

The expression for the torque in a doubly excited system can be shown tobe [28]:

Te =1

2is

2

d

dLsddθpd

+1

2is

2

q

dLsqdθpd

+ isdisq

dLsdqdθpd

(B.99)

where the inductance terms are defined as in (B.93). Note that Lsdq is themutual inductance between the d and q windings. Taking the derivatives inthis expression, and introducing the 3/2 factor to account for three phases, weget the following expression for the torque in terms of the stationary frame dqcurrents:

T e =3

2

[(is

2

q − is2

d )L2 sin 2θpd + 2L2isdisq cos 2θpd

](B.100)

Using the relationship:isdqγ = BT irdqγ (B.101)


R

R

pd qr

qr

L i

pd dr

dr

L i

+

+

-

-

Ldr

Lqr

vdr

vqr

d-axis

q-axis

idr

iqr

Figure B.6: Ideal dq equations.

one can substitute for isd and isq in (B.100) in terms of ird and irq, and obtain:

T e =3

22L2i

rdirq

= (Lrd − Lrq)irdirq (B.102)

All of the analysis thus far has been for a two phase single pole pair ma-chine. A three phase multiple pole machine only requires a slight modificationto the torque expression, with the previously derived torque expression beingmultiplied by the pole pairs of the machine and 3/2:

T e =3

2pp(L

rd − Lrq)irdirq (B.103)

The only other transformation of immediate interest that has not been ex-plicitly carried out is the current transformation. It was eluded to in Sec-tion B.3.1.3 that one property of the rotating transformations was that themagnitude of the current and voltage vectors was equal to that of a single phaseof the three phase machine in steady state. Another property that occurs isthat in steady state ird and irq have D.C. values if the dq-axes are rotating syn-chronously with the rotor. To formally show these properties consider the abcmachine to be driven by currents of the form in (B.132–B.134). These currentsare synchronized to the rotation of the rotor, and consequently so is the resul-tant current vector. Carrying out the transformation from the abc frame to the

B.4 Space Vector Model B-21

dq stationary frame we get:

isdqγ =

Ipk cos(θpd + γ)Ipk sin(θpd + γ)

0

(B.104)

and the further transformation to the dq rotating frame gives:

irdqγ =

Ipk cos γIpk sin γ

0

(B.105)

Notice that if the phase angle γ is zero then the q-axis current is zero, andall the current lies in the d-axis–i.e. along the high permeance axis of the rotor.If the peak value of the abc currents is constant, then in the dq-axes we have aconstant amplitude D.C. value equal to the abc phase amplitude.

B.4 Space Vector Model

An alternative method for modeling machines that has become popular is thespace vector technique. This method of modeling is very similar to the dqmodeling technique, and in fact it is very simple to convert between the twodifferent types of models. This technique has become popular because of thegrowth in vector based control techniques and the fact that machine equationstake a simpler form due to its notation. For example, the electrical dynamicsof an induction machine can represented by two equations (instead of four witha dq model). The form of the equations also evokes a “resultant vector” wayof thinking about the machine’s operation, as opposed to a component vectorapproach with the dq modeling technique. A full discussion of space vectorsapplied to the control of machines can be found in [14]. The application of spacevectors to reluctance machines has not been as pervasive as it has with inductionmachines because the reluctance machine more naturally relates to a componentviewpoint due to the presence of two different permeance axes. However, in somesituations space vectors are a useful tool for viewing the machines operation. Itshould be emphasized that because the reluctance machine does not have anyrotor winding we have no need to develop rotor expressions, as is the case withthe induction machine.

Space vector modeling is based on the concept that the mmf of a three phasemachine can be represented by a resultant vector that has a physical locationin space. This stems from the fact that the individual windings of the phasesare sinusoidally distributed, and the vector for each of the windings can beconsidered to lie on the axis of the phases. It should be noted that the dqmodeling developed in the previous sections used similar assumptions, but themodeling approach was different.


B.4.1 Current Space Vectors

B.4.1.1 Stationary Frame Current Vectors

In a manner similar to (B.32) we can write the following expression for theresultant mmf in a three phase machine:

F sT = N3φ[ia(t)cosθp + ib(t)cos(θp −2π

3) + ic(t)cos(θp −

4π

3)] (B.106)

where θp is the angle from the axis of the a-phase winding as defined previously.The notational simplicity of the space vector formulation is obtained by

introducing complex notation. In the following equations the “ _ ” is used todenote vectors in the complex form. Equation (B.106) can be written as:

F sT = N3φRe[ia(t)e−jθp + ib(t)ej(2π/3−θp) + ic(t)e

j(4π/3−θp)]

=3

2N3φ

2

3Re[ia(t) + aib(t) + a2ic(t)]e

−jθp (B.107)

where a = ej2π/3, and is a vector of unit length lying spatially along the axis ofthe b-phase. Similarly a2 = ej4π/3, and lies along the c-phase axis. Notice thatthis complex notation implicitly means that we have a set of pseudo “dq” axes,which now correspond to the real and imaginary axes.

If (B.107) is broken apart and the current section extracted, and then thereal and complex components are collected together we can write:

is =2

3[ia(t) + aib(t) + a2ic(t)]

= |is| ejαs (B.108)

Figure B.7 shows pictorially what this expression means. The |is| vector isthe magnitude of the resultant current vector. Notice that the direction of thisvector is spatially the same direction as the original mmf vector (since mmf andcurrent are related by a scalar). The αs angle is the angle of this vector withrespect to the reference a-phase axis. If one were to add together the ia, ib,and ic current vectors graphically on this diagram, the resultant current vectorwould have the angle αs but be 3/2 times the magnitude. The 2/3rd termwas introduced into (B.107), and then carried into (B.108), since the resultantcurrent vector has the property that the vector can be directly projected backonto the three phase axes. It should be noted that implicit in this projection isthat there are not zero sequence currents flowing (i.e. ia + ib + ic = 0). It canalso be shown that under this restriction these projections can be representedby the following relationships:

<(is) = ia (B.109)

<(a2is) = ib (B.110)<(ais) = ic (B.111)

In the particular case where the currents are of the form (B.33–B.35) then


Figure B.7: Resolving the current space vector onto the abc axes.

the space vector can be written as follows:

is =2

3Ipk[cosωt+ (cos

2π

3+ j sin

2π

3) cos(ωt− 2π

3)

+ (cos4π

3+ j sin

4π

3) cos(ωt+

2π

3)]

=2

3Ipk[cosωt− 1

2(−1

2cosωt+

√3

2sinωt)

+ j

√3

2(−1

2cosωt+

√3

2sinωt)− 1

2(−1

2cosωt−

√3

2sinωt)

− j√

3

2(−1

2cosωt−

√3

2sinωt)

= Ipk(cosωt+ j sinωt)

∴ is = Ipkejωt (B.112)

Therefore the resultant current vector has a constant magnitude and the angleαs is changing at the constant rate of ω, i.e. the vector is rotating around themachine at a constant angular frequency.

The space vector representation can be simply related back to the dq repre-sentation. From (B.48) it can be seen that:

isd =2

3

[ia −

1

2ib −

1

2ic

](B.113)

isq =1√3

[ib − ic] (B.114)


Figure B.8: Relationship between the dq-axes and current space vectors.

If one takes the real and imaginary components of (B.108) then one can writethe following:

<(is) = <[

2

3(ia + aib + a2ic)

]= <

[2

3(ia + (cos

2π

3+ j sin

2π

3)ib + (cos

4π

3+ j sin

4π

3)ic)

]=

2

3

[ia −

1

2ib −

1

2ic

]= isd (B.115)

Similarly:

=(is) =1√3

[ib − ic] = isq (B.116)

These projections can be seen in Figure B.8. Note that the dq projections arenot as restrictive as the projections onto the abc axes. For example, if thereare zero sequence currents then (B.115) does not equal (B.109). Zero sequencecurrents require the presence of an additional space vector equation, as wasthe case with the dq equations. However, the discussion in this book shall befocussed on balanced (and usually star connected) machines that do not havezero sequence current components.

B.4.1.2 Rotating Frame Current Vectors

Similar space vector expressions can be derived for frames that are not stationaryto the rotor. Consider the situation shown in Figure B.9. Here we have theoriginal is vector as in Figure B.8, as well as the same vector projected ontoanother frame which is possibly rotating.


Figure B.9: Space vector rotating frame transformations.

The current vector can be written with reference to the rotating frame as:

ir = |ir| ejγ

= |ir| ej(αs−θrs)

Now is = |is| ejαs = |ir| ej(θrs+γ) (as |is| = |ir| )= |ir| ejγejθrs

∴ is = irejθrs = ire

−jθsr and

∴ ir = ise−jθrs = ise

jθsr (B.117)

The sign of the angle in (B.117) is dependent on the reference axis for the an-gle difference between the two reference frames. The normal convention adoptedis that the old frame is taken as the reference, therefore the sign convention is:

xnew = xolde−jθnew−old (B.118)

where:

θnew−old , the angle between the new and old axeswith reference to the old axis.

Therefore in (B.117) θrs is the the angle of the rotating reference frame with re-spect to the stationary frame, and θsr is the stationary reference frame measuredwith reference to the rotating reference frame.

The relationships in (B.117) are general and can be applied to all spacevector axis transformations.

B.4.2 Flux Linkage Space VectorThe total flux linking the phases in a three phase machine are:

ψa = Laaia + Labib + Lacic (B.119)ψb = Lbbib + Lbaia + Lbcic (B.120)ψc = Lccic + Lcaia + Lcbib (B.121)


Define the flux linkage space vector as follows:

ψs

=2

3(ψa + aψb + a2ψc) (B.122)

The justification for the definition of the space flux vector is that the funda-mental of the flux linkage to a single phase varies as a sinusoidal function of thecurrent angle to the axis of any particular phase. Therefore the flux linkage hassimilar spatial sinusoidal properties to the mmf of the machine, and the sametechniques can therefore be applied.

Substituting (B.119–B.121) into (B.122)and assuming that

Lab = Lba

Lac = Lca

Lbc = Lcb

one obtains:

ψs

=2

3

[ 1

2

[(2Laa − Lab − Lac) ia + (2Lab − Lbb − Lbc) ib · · ·

+ (2Lac − Lcc − Lbc) ic]· · ·

+ j

√3

2

[(Lbb − Lbc)ib + (Lab − Lac)ia + (Lbc − Lcc)ic

]](B.123)

This expression for a cylindrical rotor machine (i.e. the self inductances areequal, and the mutual inductances are equal) can be simplified greatly. For thereluctance machine the expression is much more complicated. Substituting theinductance expressions (C.56) and (C.57) into (B.123), and after considerablemanipulation one obtains the following expression for the flux space vector in astationary reference frame:

ψs

= (L1 + L2 cos 2θpd)ia + (−L1

2+ L2 cos 2(θpd −

π

3))ib · · ·

+ (−L1

2+ L2 cos 2(θpd +

π

3))ic · · ·

+ j1√3

[(√

3L2 sin 2θpd)ia + (3

2L1 − L2(

3

2cos 2θpd +

√3

2sin 2θpd))ib · · ·

+ (−3

2L1 + L2(

3

2cos 2θpd −

√3

2sin 2θpd))ic

](B.124)

The validity of this expression can be checked as follows. If (B.124) is calculatedfor θpd = 0 and ia = Ipk, ib = −Ipk/2, ic = −Ipk/2, (i.e. the mmf vector liescoincident with the a-phase) then the real part of the inductance is 3/2(L1 +L2)as expected from the dq analysis. A similar result can be found for the imaginarycomponent for θpd = 90, ia = 0, ib =

√3/2Ipk, ic = −

√3/2Ipk (in this case the

mmf is at 90 and the rotor d-axis is also in this position).If the currents are in the form of (B.132–B.134) then (B.124) can be simpli-


fied to the following expression:

ψs

∣∣∣3φ currents

=3

2Ipk

[(L1 cos(θpd + γ) + L2 cos (θpd − γ)) · · · (B.125)

+ j (L1 sin(θpd + γ) + L2 sin(θpd − γ))]

=3

2Ipk

[L1e

j(θpd+γ) + L2ej(θpd−γ)

](B.126)

This special case for the currents has been chosen because it is the form of thecurrents that are applied to a vector controlled machine. It can be seen that theresultant current is synchronized to the rotor position such that the resultantcurrent vector has an angle of γ radians with the rotor high permeance axis (seeFigure B.9). Notice that because the current amplitude only appears as Ipk in(B.126), as opposed to 3/2Ipk, which is the value of the three phase currentvector. The 3/2 that does appear in (B.126) is due to the inductance part ofthe expression. Therefore the magnitude of the flux linkage is 2/3rds of the fluxlinkage for the three phase machine, as was indicated from the definition of theflux linkage expression (B.122).

B.4.3 Voltage Space VectorIn a manner analogous to the definitions of the current and flux space vectorsone can define the voltage space vector:

vs =2

3(va + avb + a2vc) (B.127)

where va,vb,vc are the individual phase voltages.The concept of the voltage space vector is quite abstract. However, its

existence can be justified from the vectors already defined. The voltage ina machine is made up of two components; the resistive drop, and the inducedvoltage from changing flux linkages. We have already defined the current vector,and the resistive drop is simply this vector multiplied by the resistance (which isa scalar). The flux linkages have also been defined as a vector, and taking theirderivative in vector sense also results a vector. Therefore both components ofthe voltage are vectors, and consequently the voltage can be considered to be avector. It is easy to demonstrate that if one takes components of a voltage vectorfor a set of three phase windings one does get the individual abc componentsof the voltages. Note that this process requires that there are no zero sequencevoltages present.

B.4.4 Example – SYNCREL Space Vector ModelWe have assembled enough of the space vector model machinery to constructthe space vector electrical model for the SYNCREL (Synchronous ReluctanceMachine). This machine has been chosen because it is very simple, in fact aboutas simple a model as one can get for a machine. The simplicity results from thespace vector notation. A SYNCREL has only one set of three phase windingson the stator, therefore the expression for the stator voltage in space vectornotation using stationary frame variables is:

vs = Ris +dψ

s

dt(B.128)


It is a straight forward process to verify this expression from the definitionsalready presented for the various space vectors.

Evaluation of the voltage from (B.128) is complex due to the nature of theflux linkage term in a stationary reference frame. A great simplification canbe achieved by converting this expression into a rotating frame synchronizedwith the rotor (as was done with the dq equations). Applying (B.118) to thevoltage, current and flux linkage vectors, one can write the following relationshipbetween the stationary and rotating reference frame vectors:

vs = vrejθpd

is = irejθpd

ψs

= ψrejθpd

(B.129)

Substituting (B.129) into (B.128) gives:

vrejθpd = Rire

jθpd +d

dt

(ψrejθpd

)= Rire

jθpd +dψ

r

dtejθpd + ψ

rejθpdj

dθpddt

∴ vr = Rir +dψ

r

dt+ jωpdψr (B.130)

where ωpd =dθpddt

, rotor angular velocity

θpd , angle from stationary to rotating frame (B.131)

Assuming that the currents being applied to the machine are of the form:

ia = Ipk cos(θpd + γ) (B.132)

ib = Ipk cos(θpd + γ − 2π

3) (B.133)

ic = Ipk cos(θpd + γ +2π

3) (B.134)

then it is not difficult to show that:

is = Ipkej(θpd+γ) (B.135)

Therefore the rotating frame current space vector is, using (B.117):

ir = Ipkejγ (B.136)

Applying a similar transformation to (B.126), one obtains:

ψr

=3

2Ipk[(L1 + L2) cos γ + j(L1 − L2) sin γ]

=3

2Ipk[L1e

jγ + L2e−jγ] (B.137)

B.4.5 Space Vector Power ExpressionNow that we have the space vector representations for the dynamic equationswe are in a position to calculate the input stator power for the machine in


terms of space vectors. Assuming that there are no zero sequence componentsthe following expression can be written for the instantaneous real three phasepower of the machine:

P3φ = vaia + vbib + vcic

= <(vs)<(is) + <(a2vs)<(a2is) + <(avs)<(ais) (B.138)

This equation can also be written in a more compact form:

P3φ =3

2< (vsi

∗s) (B.139)

where the “∗” means complex conjugate. Because the space vectors are closelyrelated to the time domain phasors in steady state the similarity of this expres-sion with the time domain complex power expression should not be surprising.This expression can be confirmed by the following expansion:

< (vsi∗s) = <

((2

3

)2 (va + avb + a2vc

) (ia + a∗ib + a2∗ic

))

= <((2

3

)2 ( 3

2vaia +

3

2vbib +

3

2vcic · · ·

− j√

3

2((ic − ib)va + (ia − ic)vb + (ib − ia)vc)

))=

2

3(vaia + vbib + vcic) (B.140)

As can be seen from (B.140) the space vector representation of the machine isabsorbing 2/3rds the power of the three phase machine. Hence the space vectortransformations we have developed are power variant transformations, as wasthe case for the dq transformations.

B.4.6 Space Vector Expression for SYNCREL Torque

The classic way of calculating the power or torque produced by an electricalmachine is to write the equation for the energy balance in the machine. Thefollowing discussion is based on that in [28]. The expressions developed are forelectrical to mechanical energy conversion. Mechanical to electrical conversionis the dual of this, and will not be discussed separately. The energy balanceequation is based on the conservation of energy principle – i.e. the input energymust be balanced by the losses (both electrical and mechanical), any energytransiently stored in the system (both mechanical and electrical), and the outputenergy in the form of mechanical work. Therefore the energy balance can bewritten as:[

Electricalenergy input

]=

[Electricallosses

]+

[Stored energy

in fields

]+

[Mechanical

energy

](B.141)

In symbol form this may be written as:

Ee = Ele + Efe + Eme (B.142)


The mechanical energy component may not appear as mechanical work, butsome of it may be stored in forms such as kinetic energy and various forms ofpotential energy. Therefore the actual output mechanical energy is:

Emo = Eme − Elm − Esm (B.143)

where:

Elm , the mechanical losses

Esm , the stored mechanical energy

Therefore (B.142) may be written as:

Ee = Ele + Elm︸︷︷︸Losses

+Efe + Esm︸︷︷︸Stored

+Emo (B.144)

The power expression developed above can be used as a means to calculatethe torque produced by the machine. A general expression for torque is:

T =P

ω(B.145)

where T , the mechanical shaft torque, and P , the mechanical shaft power,and ω , the shaft angular velocity. This expression can be used to develop theelectro-magnetic torque for the space vector model of the machine by utilizingthe energy balance expressed in (B.142). If one can identify the loss and fieldstorage terms then they can be subtracted from the total input energy to givethe mechanical output energy. This can then be substituted into (B.145) to givethe electromagnetic torque.

Remark B.6 Note that (B.145) has been defined in terms of the mechanicaloutput shaft quantities. However, in transient situations the mechanical torqueand the electro-magnetic torque are not equal, since some of the electro-magnetictorque is absorbed in accelerating the self inertia of the rotor itself. However,the expression is still valid if all the quantities are defined at the point of theair gap of the machine – i.e. in terms of the electro-magnetic torque and theelectro-magnetic power. This is the approach taken in this analysis.

Consider the expression (B.128). The power expression for the machine can bewritten using the relationship (B.139) as follows:

P3φ =3

2< (vsi

∗s) =

3

2<[(Risi

∗s +

dψs

dti∗s

)](B.146)

Clearly the Risi∗s term is related to the power losses in the machine, therefore

thedψ

s

dt i∗s term must be related to stored field energy and mechanical output

power. Considering the last term for the special case of currents in the form(B.132–B.134), with Ipk constant with respect to time, and using (B.126) we


can write:

dψs

dt=

d

dt

(3

2Ipk

[L1e


])= jω

(3

2Ipk

[L1e


])= jωpdψs (B.147)

where ωpd =dθpddt

Therefore the power expression under this steady state condition becomes:

P3φ =3

2<[(Risi

∗s + jωpdψsi

∗s

)](B.148)

Clearly there is only one term related to the rotational power and that isjωpdψsi

∗s. Expanding this using i∗s = Ipke

−j(θpd+γ) and (B.126) one gets:

P3φ =3

2<[

3

2jωpdI

2pk

(L1 + L2e

−j2γ)]=

9

4ωpdI

2pkL2 sin 2γ (B.149)

∴ T e =9

4I2pkL2 sin 2γ (B.150)

If we remove the restriction that Ipk has to be constant, then we would endup with Ldi/dt type terms in (B.147). These terms are not related to ωpd inany way, and result in change of stored field energy terms in (B.146). Therefore(B.149) is valid for the transient condition as well as for steady state.

The same expression can be obtained if the torque is calculated using therotating reference frame expression of (B.130). In this case the rotational powerterm is even more easily identified. Consider the power expression in this frame:

P3φ =3

2<(jωpdψri

∗r

)=

3

2<(jωpd

3

2Ipk[L1e

jγ + L2e−jγ] Ipke−jγ)

=9

4I2pk<

(jωpdL1 + jωpdL2e

−j2γ)=

9

4ωpdI

2pkL2 sin 2γ (B.151)

as found in the stationary frame case. Therefore the power and torque producedis reference frame independent (as one should expect).

Remark B.7 Note that (B.149) is converted to (B.150) by dividing by ωpd.However, ωpd is in electrical radians/sec, therefore this will only give the correctexpression if the machine is a two pole machine (one pole pair). To makethe expression appropriate for any number of poles, equation (B.150) must bemultiplied by the number of pole pairs.


B.4.7 Relationship Between Space Vectors and dq ModelsClearly the space vector model and the dq model of a machine are very closelyrelated. The Real and Imaginary axes of the space vector model can be con-sidered to be the same as the dq axes. Therefore, by taking the componentsof the space vectors (i.e. taking the Re and Im parts) onto these axes one canobtain the dq representation of the variable or equation. For example, considerthe (B.126) representation for the flux linkage. Taking the < and = parts weobtain:

<(ψs


)=

3

2Ipk[L1 cos(θpd + γ) + L2 cos(θpd − γ)] (B.152)

=(ψs


)=

3

2Ipk[L1 sin(θpd + γ) + L2 sin(θpd − γ)] (B.153)

Calculating the flux linkage using (B.93) and (B.104) one gets the following:[ψsdψsq

]=

3

2Ipk

[L1 cos(θpd + γ) + L2 (cos 2θpd cos(θpd + γ) + sin 2θpd sin(θpd + γ))L1 sin(θpd + γ) + L2 (sin 2θpd cos(θpd + γ)− cos 2θpd sin(θpd + γ))

](B.154)

Since:

cos 2θpd cos(θpd + γ) + sin 2θpd sin(θpd + γ) = cos(θpd − γ)

sin 2θpd cos(θpd + γ)− cos 2θpd sin(θpd + γ) = sin(θpd − γ)

then the space vector and dq expressions are equivalent. This equivalence ismore easily verified if the rotating versions of the two models are compared.Consider (B.137). If Re and Im parts are taken we have:

<(ψr


)=

3

2Ipk [(L1 + L2) cos γ] = Ldid (B.155)

=(ψr


)=

3

2Ipk [(L1 − L2) sin γ] = Lqiq (B.156)

since we know that Ld = 3/2(L1 + L2) and Lq = 3/2(L1 − L2), and id =Ipk cos γ, iq = Ipk sin γ from the dq model theory.

Finally it can be shown that the space vector and dq model theory give thesame torque expressions. Consider the following relationships:

I2pk sin 2γ = 2I2

pk cos γ sin γ

= 2idiq (B.157)

2L2 =2

3

(3

2(L1 + L2)− 3

2(L1 − L2)

)=

2

3(Ld − Lq) (B.158)

Substituting these into (B.150) gives the normal dq torque expression (B.102).

Appendix C

Calculation of Inductances fora Synchronous ReluctanceMachine

C.1 Calculation of InductancesOne of the fundamental parameters of any machine model is the inductance ofthe armature windings of the machine under all operating conditions. Later inthis chapter we shall that the variation of inductances with respect to the me-chanical position of the rotor is directly connected with electromagnetic energyconversion in all machines, and hence with the production of torque. Thereforethe calculation of the SYNCREL inductances is fundamental to understandingthe machines operation.

In the case of the SYNCREL, the armature is on the stator, since the rotordoes not have any windings. We will find that the inductance of a particularwinding varies depending on the position of the rotor in relation to the winding,and the degree of magnetic saturation of the stator and the rotor iron.

This section will determine the self and mutual inductances for the statorwindings of the SYNCREL. The derivation of these inductances will be carriedout in a detailed and formal manner using a traditional approach.

The following standard assumptions are made in the following analysis:

a. The stator windings are sinusoidally distributed. When excited with cur-rent a sinusoidal spatial distribution of mmf is produced.

b. The machine does not exhibit any stator or rotor slotting effects.

c. The machine iron is a linear material, i.e. it is not subject to magnetic sat-uration effects. The permeability of the material is very large in compar-ison to air. Therefore the permeance of the magnetic paths is dominatedby the air gaps.

d. The air gap flux density waveforms can be adequately represented by theirfundamental component.

e. The stator turns are all full pitched (i.e. they cover π electrical radians).

C-2 Calculation of Inductances for a Synchronous Reluctance Machine

Figure C.1: Two pole three phase Syncrel – conceptual diagram

f. There is no leakage flux – i.e. there is perfect coupling between the wind-ings.

Figure C.1 is a conceptual schematic of a two pole, three phase SYNCREL.Note that the rotor shape does not represent a realistic rotor, but is drawn inthis manner to accentuate the variable reluctance in the d and q axes. The axisof the rotor which offers the minimum reluctance to the passage of flux acrossthe air gap from the stator to the rotor is called the d-axis. The maximumreluctance path is denoted as the q-axis. Note that following development willuse the concept of dq axes before the concept has been rigorously developed ina more general framework. This will occur later in section B.3. In the followingdevelopment the dq axes are closely associated with the physical configuration ofthe rotor, therefore the general development can be left to later without havingtoo many problems understanding this material.

A few preliminary conjectures, based on heuristics, can be made about thevariation of the winding inductance with respect to the angular rotor position:

Conjecture C.1 The winding self inductance will be a maximum when the d-axis of the rotor is aligned with the axis of the winding.

Remark C.1 This conjecture concurs with ones intuitive understanding of fluxinteracting with iron. The presence of iron in a coil will result in more flux perunit of current. When the d-axis is aligned with the axis of a coil then therewill be more iron in the flux path for the coil.

Conjecture C.2 The winding self inductance will be a minimum when the q-axis of the rotor is aligned with the axis of the winding.

C.1 Calculation of Inductances C-3

Remark C.2 If there is less iron in the coils flux path then it is harder toproduce flux for a given amount of current in the coil. Clearly if the q-axis isaligned with the axis of the coil then there is a larger air path and less iron forthe flux to travel through.

Conjecture C.3 As the rotor is rotated between these two positions the selfinductance varies. The period of the phase inductance variation is half theperiod of the mmf variation for the phase winding.

Remark C.3 This is fairly obvious since the phase inductance is a maximumwhen a d-axis rotor pole aligns with the phase axis, and this occurs when therotor has rotated through π electrical radians.

Conjecture C.4 There is mutual inductance between the three phase statorwindings that is a function of the rotor position.

Remark C.4 Clearly as the rotor is rotated the amount of iron in the pathsthat would be taken by the mutual flux will vary, and hence the amount of fluxlinking the windings will vary.

A complete analysis of this situation involves computing of all the harmonicsof the flux density waveform and then calculating the total flux linkage withthe winding. One then obtains inductance expressions containing a numberof harmonic terms. The harmonic term amplitudes decrease rapidly with in-creasing harmonic number, allowing the approximation of considering only thefundamental to be made. The constant reluctance path approximation madein the following analysis is essentially the same approximation. If the windingfunction technique is use to calculate the inductances then the harmonic effectsare sometimes more readily included.

C.1.1 Self InductancesFirstly consider the self inductance of the a-phase sinusoidally distributed wind-ing. A useful technique to calculate inductances in situations like this is toconsider that the stator mmf can be broken into two sinusoidally distributedcomponents which can be considered to be acting along the d-axis and the q-axis of the rotor.(this is possible because of the assumed sinusoidal nature ofthe mmf, which implicitly allows components to be taken). Let us consider afew simple cases of the application of this concept. Figure C.1 can be used asan aid to visualise the situation. If, for example. the rotor d-axis is aligned withthe axis of the a-phase winding then the total a-phase mmf acts on the d-axispermeance, and there is no component acting on the q-axis permeance. Sincethe stator mmf is spatially sinusoidally distributed, then this means that theair gap flux density waveform would be sinusoidally distributed. Similarly if therotor q-axis is aligned with the a-phase axis, then the total a-phase mmf actson the q-axis permeance. Between these two rotor positions the permeance seenby the winding is, in general, a complex function of the rotor angular position.Consequently, the air gap flux density distribution is also a complex function ofthe rotor angle.

The sinusoidally distributed mmf on the stator of the machine can be brokeninto two sinusoidal components which are centred on the d and q-axes respec-tively, regardless of the position of the rotor. These component mmfs are then


acting on the d and q-axis permeances, Pd and Pq. Since these permeances areconstant, this is equivalent to saying that the component mmfs are acting on twoconstant air gaps, gd and gq, for the d and q-axes [28]. Therefore the resultantcomponent air gap flux densities should be spatially sinusoidal, and consequentlythe resultant total air gap flux density should also be sinusoidal. This contra-dicts the statements made in the previous paragraph about the complex natureof the air gap flux density. However, the fundamental of the actual air gap fluxdensity is, in practice, very close to that obtained using this approximation, andmeasured inductances for real machines are in reasonable agreement with thecalculated values based on the approximation. The reason for this is that sinu-soidally distributed windings will only link to the components on a flux densitywaveform that have the same pole number as the winding, as was previouslyshown in Section B.2. Therefore, for an ideal sinusoidally distributed windingonly the fundamental component of the flux density can link to the winding,and consequently harmonic flux densities only contribute to leakages.

Remark C.5 An ideal sinusoidally distributed winding cannot be constructed –all true windings have winding space harmonics. These winding harmonics cantherefore link to harmonic flux densities of the same poll number. This can leadto the generation of harmonic voltages, and more complex inductance variationswith rotor position.

Addition Could add a section here examining the assumption that the d andq-axes air gaps can be modeled as constant air gaps. Could consider anideal 2 pole axially laminated machine, looking at the effective air gapseen by the mmf in both the axes.

The following is with reference to Figure C.2, which is a laid out diagram ofFigure C.1. This diagram shows the two fictitious air gaps, with the componentmmfs acting on the d and q-axes respectively. The resultant air gap flux densitydistributions are shown for the two axis waveforms. Notice that the resultantair gap flux density waveform is distorted away from the d-axis of the rotor bythe q-axis flux waveform, the degree of distortion being related to the differencebetween the air gap lengths and the mmf applied in the axes.

In order to calculate the self inductance of the a-phase winding the totalself flux linkage must be calculated for the winding. This self flux linkage hasseparate components contributed by both the d and q-axis fluxes.

Using the approach in [28] we calculate the flux due to one of the componentmmfs acting on one of the air gaps by proceeding in the following manner:

a. Calculate the flux in an incremental area at some angular position in themachine accounting for the spatial distribution of the mmf.

b. One then integrates up these incremental fluxes for a total span of a singlecoil. This gives the total flux linking one coil.

c. Calculate the flux linking all the coils that have their axes at some angularposition around the machine. This is achieved by multiplying the valueobtained in point b by the number of turns that lie in the same positionas the single coil.

d. Finally integrate up the previous value over the coil span accounting forthe change in the number of turns with angular spatial variation.


Figure C.2: Developed diagram of a Syncrel.

e. Once the flux linkage for each air gap is found then the total flux linkageto the a-phase is found by adding together the linkages due to the d andq axes.

Consider the d-axis, as shown in Figure C.3. The expression for the flux overa 180 electrical span of the d-axis mmf can be found as follows. Consider theincremental permeance over an angle of dβ:

dPd =µodA

gd(C.1)


Figure C.3: d axis developed diagram for Syncrel

where:

dA , the incremental area.= lmr dβ

β , machine periphery angle relative to the d axis.

lm , the length of the machine.

r , the radius of the machine at the centre of the air gap.

µo , the permeability of free space.

Therefore the incremental flux can be written as:

dφd = dPd

(Fd cosβ

)=Fdµolmr

gdcosβ dβ (C.2)

where Fd cosβ is the d-axis component mmf.To find the total flux linking a single coil whose most clockwise coil side starts

at α radians relative to the d-axis position, we integrate the d-axis incremental


fluxes dφd for the dA elements using the following integration:

φd =

∫ α+π

α

dφd

=

∫ α+π

α

[Fdµolmr

gdcosβ

]dβ

=−2Fdµolmr

gdsinα (C.3)

where:

Fd = Fa cos θpd the component mmf at θpd, and (C.4)

Fa , the peak mmf of the a-phase.

θpd , the angle of the d-axis around the machine periphery (elec-rad) (C.5)

Remark C.6 Note that the above definition of the flux linkage per turn impliesthat the normal vector for the coil area is at the angle α+π/2 radians. Realisingthis is important in getting the correct sign for the total flux linkage of the coil.

Clearly the maximum flux of 2Fdµolmr/gd is obtained when the coil side α =−π/2 – this means that the coil axis is a 0 radians and hence aligns with thecomponent mmf axis. Equation (C.3) can be written in terms of the total d-axispermeance by utilising the following expression:

Pd =

∫ π2

−π2

dPd

=

∫ π2

−π2

µolmr

gddβ

=µolmrπ

gd(C.6)

therefore (C.3) can be written as:

φd(α) =−2FdPd

πsinα (C.7)

If a coil side starts at some angle α with respect to the d-axis then the coilaxis is at α+ π/2. Define:

αa , angle of the coil axis relative to the d-axis

and hence:αa = α+

π

2(C.8)

and consequently:α = αa −

π

2(C.9)

Substituting this into (C.7) we can write the flux for a single turn whose axis isat αa with respect to the d-axis as:

φd(αa) =−2FdPd

πsin(αa −

π

2)

=2FdPdπ

cosαa (C.10)


This expression can be further manipulated so that the flux is a function of theangle of the d-axis and the coil axis with respect to the axis of the a-phase. Let:

θa , the angle of the coil axis with respect to the a-phase

therefore:αa = θa − θpd (C.11)

Substituting this into (C.10) we can write the following:

φd(θa, θpd) =2FdPdπ

cos(θa − θpd) (C.12)

α+ β = sin ρ (C.13)

We are now in a position to calculate the flux linkage to the turns of a-phaseat some particular coil axis angle θa for some constant d-axis. The number ofturns that have their coil axis at angle θa can be deduced from the turns densityfunction (B.1) as:

nta(θa) = na cos θa (C.14)

Remark C.7 Clearly nta(θa) can be negative. The concept of a negative num-ber of turns/radian at a particular coil axis angle is related to the concept of anegative number of conductors around the periphery of the machine (the signin this case arising from the direction of current in the conductors at thatpoint).The turns density function expressed in θa is essentially the mmf/am-pere for the winding at a particular position. This is also known as a windingfunction. Therefore the negative sign indicates that the flux produced is in theopposite direction across the air gap (i.e. from the stator to the rotor insteadof from the rotor to the stator).

Therefore the total flux linkage for the number of turns at θa is:

ψd(θa) =2FdPdna

πcos θa cos(θa − θpd) (C.15)

We are now in the position to calculate the total flux linkage of the d-axisflux to the a-phase by integrating the flux linkage ψd(θa) at each position θa forthe coil span of the winding. Therefore the total flux linkage is:

ψad(θpd) =2FdPdna

π

∫ γ+π

γ

cos θa cos(θa − θpd)dθa (C.16)

Carrying out this integration and simplifying the result we obtain:

ψad(θpd) = FdPdna cos θpd (C.17)

In a similar fashion, the flux linkage of the q-axis flux with the a-phase canbe found. The procedure is identical to the above so it will not be presentedin detail. Instead we will simply state the results of the intermediate steps andthen present the final flux linkage result.


The incremental permeance for the q-axis is:

dPq =µolmr dβ

gq(C.18)

and therefore the total permeance of over a coil span is:

Pq =

∫ π

0

dPq

=µolmrπ

gq(C.19)

The q-axis is at an angle of π/2 radians with respect to the d-axis. Thereforethe variation of the q-axis mmf is:

Fq = Fq cos(β − π

2) (C.20)

Therefore the q-axis incremental flux linkage is:

dφq = dPq Fq cos(β − π

2) (C.21)

Since cos(β − π2 ) = sinβ, and substituting for dPq in (C.21) gives:

dφq =µoFqlmr

gqsinβ dβ =

FqPqπ

sinβ dβ (C.22)

Consequently the expression for the flux linkage for a single coil can be writtenas:

φq(α) =

∫ α+π

α

dφq

=FqPqπ

∫ α+π

α

sinβ dβ

=2FqPqπ

cosα (C.23)

where α , an angle relative to the d-axis.Carrying out the angle conversion to the coil axes relative to the a-phase as

was done in the d-axis case we can write:

φq(θa) = −2FqPqπ

sin(θa − θpd) (C.24)

The total flux linkage of the q-axis flux to the a-phase can therefore bewritten as:

ψaq(θpd) =

∫ γ+π

γ

nta(θa)φq(θa) dθa

=−2FqPqna

π

∫ γ+π

γ

cos θa sin(θa − θpd) dθa

∴ ψaq(θpd) = −FqPqna sin θpd (C.25)


In the above expressions the peak values of the d and q-axes mmfs are foundby taking components of the a-phase mmf onto the d and q-axes respectivelyas follows:

Fd = Fa cos(−θpd) = Fa cos θpd (C.26)

Fq = Fa sin(−θpd) = −Fa sin θpd (C.27)

where Fa , the peak of the a-phase mmf = naia (from (B.2)). Note that thenegative sign in front of the θpd terms results from the fact that the angle ismeasured relative to the d-axis, and not the a-phase axis,since we are projectingthe a-phase mmf onto the d and q axes.

The total flux linkage to the a-phase can now be calculated by using super-position and adding the components linking to it from the d and q-axes. Using(C.17) and (C.25) we get:

ψaa(θd) = ψad(θd) + ψaq(θd)

= naFa(Pd cos2 θpd + Pq sin2 θpd)

= n2aia(Pd cos2 θpd + Pq sin2 θpd)

=n2aia2

[(Pd + Pq) + (Pd − Pq) cos 2θpd] (C.28)

The rotor self inductance can therefore be calculated as a function of thed-axis position as:

Laa =ψaaia

= L1 + L2 cos 2θpd (C.29)

where:

L1 =N2

8(Pd + Pq)

L2 =N2

8(Pd − Pq)

N , total number of turns in sinusoidal winding= 2na

Figure C.4 shows a plot of (C.29). Notice that the inductance varies as afunction of cos 2θpd with a constant offset as mentioned in conjecture C.3.

The self inductances for the other two phases can be found similarly as:

Lbb = L1 + L2 cos 2

(θpd −

2π

3

)(C.30)

Lcc = L1 + L2 cos 2

(θpd +

2π

3

)(C.31)

Addition Perhaps a remark about the fact that this analysis gives accurate in-ductance results since only the fundamental components of the flux densitydistribution link to the sinusoidal winding, as proved in a previous section.


Figure C.4: ‘a’ phase inductance plot.

C.1.2 Mutual InductancesIn addition to the self inductance of the winding there is also mutual inductancebetween the a, b, and c-phases. These inductances are also a function of theposition of the rotor, since its position clearly changes the reluctance of the fluxpaths between the windings. The process of calculating the general expressionsfor these inductances is very similar to that for the self inductances. We shallwork out in detail the mutual inductance between two windings and then simplystate the relationships between the other windings.

Let us consider the mutual inductance between the a-phase and the b-phase.The spatial sequence of the phases is as shown in Figure B.5. The windingconductor density distribution for the b-phase is:

nb(θp) = nb sin(θp −2π

3) (C.32)

Therefore the number of coils with their axes at some angle θa with respect tothe a-phase (i.e. the winding function) is:

ntb(θ) = nb cos(θa −2π

3) (C.33)

As with the self inductance we shall work out the flux linkage for the d andq axes separately, and then use superposition to calculate the total flux linkage.We can write the expression for the flux linkage for a single turn using theexpression (C.10) calculated for the self inductance case:

φd(αa) =2FdPdπ

cosαa (C.34)


Again we can say:αa = θa − θpd (C.35)

allowing us to again write the flux expression as:

φd(θa, θpd) =2FdPdπ

cos(θa − θpd) (C.36)

We can now write the flux expression for the coils that have their axis at θa as:

ψd(θa, θpd) =2FdPdnb

πcos(θa −

2π

3) cos(θa − θpd) (C.37)

Finally we now find the total linkage of the d -axis flux by integrating over a coilspan of the b-phase:

ψdba =2FdPdnb

π

∫ γ+π

γ

cos(θa −2π

3) cos(θa − θpd)dθa (C.38)

After considerable manipulation this expression can be written as:

ψdba = FdPdnb cos(θpd −2π

3) (C.39)

Using (C.26) the expression becomes:

ψdba = FaPdnb cos θpd cos(θpd −2π

3) (C.40)

Now let us consider the q-axis contribution to the b-phase flux. Using (C.10)we can again write an expression for the q-axis flux linking a single turn centredat the angle αaq relative to the q-axis:

φq(αaq) =2FqPqπ

cosαaq (C.41)

The αaq angle con be converted to angle relative to the a-phase:

θa = θpd + αaq +π

2(C.42)

and therefore:αaq = θa − (θpd +

π

2) (C.43)

Hence φq can be written as:

φq(θa, θpd) =2FqPqπ

cos(θa − θpd −π

2) (C.44)

=2FqPqπ

sin(θa − θpd) (C.45)

Now using the winding function we can write:

ψq(θa, θpd) =2FqPqnb

πcos(θa −

2π

3) sin(θa − θpd) (C.46)


Integrating over the coil span:

ψqba =2FqPqnb

π

∫ γ+π

γ

cos(θa −2π

3) sin(θa − θpd)dθa (C.47)

After considerable manipulation we arrive at the expression for the fluxlinkage from the q-axis to the b-phase:

ψqba = FqPqnb cos(θpd −π

6) (C.48)

Using (C.27) this expression can be written as:

ψqba = −FaPqnb sin θpd cos(θpd −π

6) (C.49)

We are now in a position to calculate the total mutual flux linkage to theb-phase from the a-phase as follows:

ψba = ψdba + ψqba

= Fanb[Pd cos θpd cos(θpd −2π

3)− Pq sin θpd cos(θpd −

π

6)]

= Fanb

Pd

[−1

4(1 + cos 2θpd) +

√3

4sin 2θpd

]+

Pq

[√3

4sin 2θpd +

1

4(1− cos 2θpd)

](C.50)

After manipulation we get the following expression for this mutual inductance:

ψba =nanbia

2

[−(Pd + Pq)

2+ (Pd − Pq) cos(2θpd −

2π

3)

](C.51)

For a balanced machine na = nb, therefore the term in front of this expressionis n2

aia/2. Therefore this expression is the same as that for the self inductancesand hence we can write the mutual inductance in the same form as that for theself inductances:

ψba =N2ia

8

[−(Pd + Pq)

2+ (Pd − Pq) cos(2θpd −

2π

3)

](C.52)

Dividing (C.52) by ia gives the inductance expression:

Lba = Lab = −L1

2+ L2 cos 2(θpd −

π

3) (C.53)

where L1 and L2 are as defined in (C.29).By a similar process it can be shown that the other mutual inductances are:

Lca = Lac = −L1

2+ L2 cos 2(θpd +

π

3) (C.54)

Lcb = Lbc = −L1

2+ L2 cos 2θpd (C.55)


C.1.3 SummaryAssuming that the mmf for each phase varies sinusoidally around the machine,and that the resultant mmf in the machine acts on two different air gaps for thelow and high permeance axes, then the self and mutual inductances of a phasewinding vary as follows with θpd (the angle of the d-axis with the a-phase). Inthe above derivations we did not take into account the leakage inductance termin each of the self inductances. If we assume that the leakage does not changewith rotor position (which may not be a valid assumption) then the leakage canbe included by the addition of the term Ll as shown below:

Self Inductances

Laa = Ll + L1 + L2 cos 2θpdLbb = Ll + L1 + L2 cos 2

(θpd − 2π

3

)Lcc = Ll + L1 + L2 cos 2

(θpd + 2π

3

) (C.56)

Mutual Inductances

Lba = Lab = −L1

2 + L2 cos 2(θpd − π3 )

Lcb = Lbc = −L1

2 + L2 cos 2θpdLca = Lac = −L1

2 + L2 cos 2(θpd + π3 )

(C.57)

where:

L1 =N2

8(Pd + Pq)

L2 =N2

8(Pd − Pq)

N , total number of turns in sinusoidal winding= 2na

Ll , the leakage inductance of each phase

Appendix D

Introduction to InstantaneousImaginary Power

D.1 IntroductionIt is difficult to gain a satisfying physical understanding of the concept of in-stantaneous imaginary power. In this appendix we shall discuss several ways ofinterpreting instantaneous imaginary power.

D.1.1 Single Phase Reactive PowerLet us begin with single phase power expressions. The difficulties in interpretingthe instantaneous imaginary power begin with the interpretation of reactivepower in sinusoidal steady state systems. We will find that single phase reactivepower is not the same as the instantaneous three phase imaginary power.

Consider the following time domain expressions for current and voltage flow-ing into some arbitrary network:

v = V cosωt

i = I cos(ωt+ θ)

Using the definition of instantaneous power we can write:

P = vi

= [V cosωt][I cos(ωt+ θ)]

=V I cos θ

2[1 + cos 2ωt]− V I sin θ cosωt sinωt (D.1)

Using the trig relation:

cosωt sinωt =1

2sin 2ωt (D.2)

we can modify the last term of (D.1) so that the expression becomes:

P =V I cos θ

2︸︷︷︸Average Real power

+V I

2cos(2ωt+ θ)︸︷︷︸

Oscillatory component

(D.3)

D-2 Introduction to Instantaneous Imaginary Power

r

V

r

I

Real

Imag

α

β

θ

I cosθ

I sin θ

Q VI= sin θ

P VI= cosθ

Figure D.1: Phasor relationship for complex power.

The oscillatory power component represents the power flowing into and out ofthe storage element of the particular circuit.1 The average real power componentessentially causes an offset in this oscillation component so that there is anaverage value of power over a complete cycle.

The other way of representing the power expression for sinusoidal steadystate systems is in the form of the complex power:

~S = ~I ~V∗ (D.4)

where ‘∗’ represents the complex conjugate, and the −→x means that x is a phasor.Let us assume that:

~I = Iejα (D.5)~V = Vejβ (D.6)

where I and V represent the current and voltage RMS values.Substituting (D.5) and (D.6) into (D.4) we can write:

~S = VI cos θ + jVI sin θ (D.7)

where θ = α− β.2Equation (D.7) is broken up into two components:

P = VI cos θ (D.8)

Q = VI sin θ (D.9)

One can see the vector relationship of these components in Figure D.1.

1As we shall later this component consists of two different parts, one belonging to the realpower and the other to the imaginary power.

2The angle θ is the angle from the reference voltage vector to the current vector.

D.1 Introduction D-3

The correspondence between (D.8) and the average real power componentof (D.3) is easy to see. However, the correspondence between (D.9) and theoscillatory power part of (6.35) is not immediately obvious. Clearly Q is thecomponent of current that is orthogonal (in a temporal sense) to the voltage,multiplied by that voltage. This correspondence is more easily seen by manip-ulating (6.32) into the form:

P =V I cos θ

2+V I cos θ

2cos 2ωt︸︷︷︸

Real power component

− V I sin θ

2sin 2ωt︸︷︷︸

Reactive power component

(D.10)

where V and I are the peak values of the voltage and current.We can see from this expression that the real power actually oscillates (with

the oscillation being unipolar), and has an average value of (V I/2) cos θ. Thereactive power component on the other hand does not have an offset term andits average value is zero. The amplitude of this term is equal to the Q term inthe complex power expression.

Remark D.1 The concept of reactive power for single phase systems is basedon sinusoidal steady state conditions. The Q value defined in (D.9) is in termsof RMS values of time phasor quantities. If one is to consider instantaneousreactive power then it is the second part of (D.10), which is a sinusoidallyvarying quantity.

Therefore, it is not possible to have a constant value of instantaneous imag-inary power in a single phase system, but only a value related to the peak of asinusoidal waveform. n

Remark D.2 Because the reactive power component of (D.10) is a symmetricbipolar waveform its integral represents energy that is following into a circuitin one half of the cycle, and then back out again in the other half. This couldbe the energy, for example, that is being stored and returned from capacitive orinductive components of the circuit. It can be seen from the expressions derivedthe value of the reactive power ((V I/2) sin θ) is independent of the frequency ofthe supply. n

D.1.2 Three Phase Instantaneous Imaginary Power

We shall gradually approach the concept of instantaneous imaginary power byfirstly considering the sinusoidal steady state power expressions. Let us assumethat the phase currents and voltages to the star connected system are:3

va = V cosωtvb = V cos(ωt+ 2π

3 )vc = V cos(ωt− 2π

3 )ia = I cos(ωt+ θ)ib = I cos(ωt+ 2π

3 + θ)ic = I cos(ωt− 2π

3 + θ)

(D.11)

3The star connection means that there are no zero sequence currents flowing.


These voltages and currents can be multiplied together to give the three phasepower expression:

P = vaia + vbib + vcic

=3V I cos θ

2+V I cos θ

2(cos 2ωt+ cos(2ωt− 2π

3) + cos(2ωt+

2π

3))

− V I sin θ

2(sin 2ωt+ sin(2ωt− 2π

3) + sin(2ωt+

2π

3)) (D.12)

Terms two and three in (D.12) are zero because the cosine and sine terms eachadd to be zero. Therefore the power expression becomes:

P =3V I cos θ

2(D.13)

which is simply three times the average power in (D.10) (as one would expect).The question that naturally arises from the above analysis is where do the termsfor the instantaneous imaginary power exist in these expressions?

Let us consider the last part of (D.12). Rewriting this term one can see that:

− V I sin θ

2sin 2ωt =

V I sin θ

2

[sin(2ωt− 2π

3) + sin(2ωt+

2π

3)

](D.14)

which means that the reactive power in one phase is being absorbed by twoother phases. Therefore the reactive power is cycling around between the threephases, and hence is not seen on the external three phase power (although thereis obviously still the single phase reactive power there in each of the individualphases).

One can understand what is happening here by a change in the representationof the currents and voltages. Let us convert the time domain quantities of (D.11)into space vectors:4

v = |v | ejωt (D.15)

i = |i| ej(ωt+θ) (D.16)

The complex power expression can now be written in terms of the space vectorsdefined above:5

S =3

2i v∗ (D.17)

Substituting for v and i into (D.17) and simplifying we get:

s =3

2(iv cos θ + jiv sin θ) (D.18)

The real power and imaginary power components can readily be seen from(D.18):

p =3

2|i| |v | cos θ (D.19)

q =3

2|i| |v | sin θ (D.20)

4The conversion to space vectors is not an obvious step since we are dealing with powersystem values of current and voltage that may not be associated with an electrical machinewith a sinusoidally distributed winding.

5Note that this space vector definition is defined in this way to conform with the Akagi[29] definition of power.


Remark D.3 The q term in (D.20) is obviously three times the reactive termin (D.10). n

Remark D.4 In this derivation of the real and reactive powers we have usedspace vectors. This has an important implication – the concept of the reactivepower has been generalised because there is no requirement on space vectors thatthey represent sinusoidally varying quantities.6 In the phasor representation thevectors (by definition) represent temporal sinusoidal quantities.

The non-sinusoidal character of space vectors means that the Q term is ameasure of the degree of orthogonality of the current vector with respect to thevoltage space vector. It should be noted that in the case of sinusoidal steady statewaveforms the space vector representation corresponds to the traditional phasorcomplex power as derived in (D.8) and (D.9). n

Using the space vector representation we can define all the expressions thatappear in [29]. Consider Figure D.2. This figure shows the voltage and currentspace vectors at a specific instant of time. The current vector can be resolvedinto a component that lies along the voltage space vector (ip), and an orthogonalcomponent (iq). The real power in the system is:

p = |v |∣∣ip∣∣ = v ip (D.21)

and the imaginary power is:

q = |v |∣∣iq∣∣ = v iq (D.22)

Remark D.5 The definition of q in (D.22) gives one a physical picture of themain components of the imaginary power. As can be seen from this diagram theq value is a measure of the length of the current vector orthogonal to the voltagevector.

If the space vector diagram is for an electrical machine (such as an in-duction machine) then the iq current is essentially the flux producing vectorof the machine. The flux vector of the machine would be coincident with iq.The voltage vector is always at π/2 rad from this vector if the vectors are ro-tating in space and its magnitude is related to that of the flux vector – i.e.|v | = ω |λ| = ω

∣∣ 32Lmiq

∣∣ where Lm is the magnetising inductance of the ma-chine. Therefore, in the particular situation of an electrical machine the q valueis directly related to the energy storage in the magnetic fields of the machine:

q = |v |∣∣iq∣∣

= ω

∣∣∣∣32Lmiq∣∣∣∣ ∣∣iq∣∣

= ω3

2Lmi

2q

= 3ω

[1

2Lmi

2q

](D.23)

The 32Lmi

2q term is the classic energy stored in an inductor term. Therefore,

in the case of an electrical machine the q is related directly to the rate at which6It should be noted that we are assuming in this presentation that there are no zero

sequence currents flowing – i.e. ia + ib + ic = 0.


α

β

θ

α - axis

β - axis

i

v

ip

iq

iα i pα

iβ

i pβ

i qα

i qβ

vα

vβ

Figure D.2: Space vector diagram.

energy is being transferred between the three phase inductances (since Lm ≈ Ls,the self inductance of a phase)

In the case of a power electronic system there may not be an identifiableinductive or capacitive element that is causing the phase difference between thevoltage and the current. In this case it is a little more difficult to gain a physicalunderstanding of what the imaginary power actually relates to. n

Remark D.6 Examination of Figure D.2 shows that i space vector and the“phase” and “orthogonal” components of the current vector can be resolved ontothe stationary αβ axes. Notice that both iα and iβ can be considered to becomposed of two components. For example, iα = iαp+iαq. The iαp component isthe real power component of the iα current, and iαq component is the imaginarycurrent component of iα. Similar observations can be made for the iβ current.These same current components were identified in [29]. n

As we noted above in the case of an inductive load the Q can be seen to cor-respond to the energy stored in the fields of the inductors. However, as notedby Akagi [29], one can generate q using just power electronic switches. Oneimmediately asks the question “where does the energy go in this case?”. If therewas an energy storage component in the power electronic system then the en-ergy could be stored there, but in the compensator application described in [29]there is no energy storage element.

This dilemma can be explained by considering Figure D.2. Let us assumethat the system is being driven by a two phase source (which is equivalent to athree phase source via the three to two phase transformations) From the figurewe can write:

vαiα = eα(iαp + iαq)

= eαiαp︸︷︷︸Real power component

+ eαiαq︸︷︷︸Imaginary power component

(D.24)


and similarly for the β axis:

vβiβ = vβ(iβp + iβq)

= vβiβp︸︷︷︸Real power component

+ vβiβq︸︷︷︸Imaginary power component

(D.25)

Remark D.7 From (D.24) and (D.25) one can see that each phase is carryingpower components that are related to the real power and the imaginary power.n

Let us now relate the iαq and iβq currents to the iq current. Using trigonometryand Figure D.2 we can write:

iαq =∣∣iq∣∣ cos(β +

π

2) = −iq sinβ (D.26)

vα = |v | cosβ (D.27)

iβq =∣∣iq∣∣ sin(β +

π

2) = iq cosβ (D.28)

vβ = |v | sinβ (D.29)

Therefore the power associated with the αβ current components of iq canbe written as:

vαiαq = −viq cosβ sinβ = −viq2

sin 2β (D.30)

vβiβq = viq cosβ sinβ =viq2

sin 2β (D.31)

Therefore one can see under all conditions (i.e. steady state and instanta-neously) that:

vαiαq + vβiβq = −viq2

sin 2β +viq2

sin 2β = 0 (D.32)

In other words the so-called imaginary power components always cancel. If theiq is being produced by a power electronic device, then the energy associatedwith this power is simply being transferred from one of the sources to the othervia the power electronics. Therefore, the sources themselves are effectively theenergy storage device (as compared to the magnetic field in the machine case).

Clearly the above observation means that:

P = vαiα + vβiβ = vαiαp + vβiβp (D.33)

Finally we shall consider the q term as defined in ?? and show that it is thesame as the expressions defined using the space vector approach pursued above.Rewriting the Akagi definition for convenience:

q = vαiβ − vβiα (D.34)

From Figure D.2 we can see that:

iαp =∣∣ip∣∣ cosβ (D.35)

iβp =∣∣ip∣∣ sinβ (D.36)


and these, together with previous current definitions, allows use to write (D.34)as follows:

q = vαiβp + vαiβq − vβiαp − vβiαq= (|v | cosβ)(

∣∣ip∣∣ sinβ) + (|v | cosβ)(∣∣iq∣∣ cosβ)−

(|v | sinβ)(∣∣ip∣∣ cosβ)− (|v | sinβ)(−

∣∣iq∣∣ sinβ)

= |v |∣∣iq∣∣ (D.37)

Remark D.8 Equation (D.37) is the same as (D.22), validating that the twoaxis representation of q is equivalent to the space vector representation. n

Appendix E

Introductory Exercise usingSaber Simulator

E.1 IntroductionSaberr1 is a software simulation program. Its main attribute is that it allowsthe simulation of mixed mode systems – i.e. one can have continuous timeanalogue circuitry, digital circuits, continuous and discrete time transfer func-tions, magnetic systems (such as electrical machines and magnetic actuators),mechanical systems, and hydraulic systems all in the same simulation. This isunusual since most simulation packages cannot readily handle this mix of sys-tems. They tend to be more specialised – i.e. only for electronic circuits, onlyfor power systems, digital simulation packages etc.

Simulation packages are very useful for the simulation of electronic systems,since the models of electronic components behave nearly the same as the actualcomponent. In some circumstances simulation is almost mandatory, since apoor design can result in immediate catastrophic failure of the real circuit. Anexample where this is often true is in the area of power electronics.

The Saber simulator consists of four major components:

• SaberSketch: This provides a means to graphically enter a schematic tobe simulated.

• SaberGuide: To some degree this component is hidden, since it providesthe connection between SaberSketch and the Saber Simulator.

• Simulator: This module is the actual simulation engine. It is activatedvia SaberGuide.

• SaberScope: This is the back end post-processing section of the Sabersystem. SaberScope allows the user to process the files produce by theSaber simulator and produce new files of results, but more importantly itallows the user to generate graphs of the results.

In this introductory exercise we shall be using the Saber simulator for circuitsimulation. The circuit to be simulated is a very simple one, but it is able

1Saber is a registered trademark for Avant!

E-2 Introductory Exercise using Saber Simulator

vS

vd

vL

vR

L

R

i

Saber ground

node

Figure E.1: Simple single phase, half wave rectifier, with an LR load.

to demonstrate many of the features of the software. In order to minimisethe simulation times we shall be using idealised components from the Saberparts library. If one wanted to work out the power dissipation in semiconductorcomponents then the more realistic real component libraries would have to beused, but use of these makes the simulation times considerably longer.

The circuit to be simulated is shown in Figure E.1. It is a simple singlephase half wave rectifier circuit. The only complication is that it has a loadthat includes inductance.

E.2 Circuit Schematic Capture

The first step in the circuit simulation process is to capture the circuit schematic.This is achieved by using the SaberSketch section of the Saber suite. Figure E.2shows the initial screen that appears when SaberSketch is invoked (via the Startmenu).2

The sequence of steps to follow to set-up a design are as follows.

Create the design: This is achieved by selecting the File→New→Design pull-

2The drawing area is shown in white in this figure. This has been done to prevent tonerwastage when this document is printed.

E.2 Circuit Schematic Capture E-3

Partsmenu

Zoomingcontrols

Gridcontrol

Select todraw a line

Invoke SaberGuide

Figure E.2: Initial screen upon invoking SaberSketch.

down menu. If we wanted to open an existing design then one would useOpen→Design, and then navigate to the desired file. Often if SaberSketchstarts it will load the last design file automatically.

Place parts on the schematic: The next step is to place the desired componentson the blank schematic. The is achieved using the Parts Gallery button.When clicked-on this opens up another window which allows one to selectthe parts folder to be used. The folder that you will use for this exercise isthe Analogy Parts Library. If one double-left-clicks on this then the contentsof the Available Categories window will change to a selection of componentcategories. One can select a category, eventually ending up with a listingof individual parts in the Available Parts list scroll window. An exampleof this window is shown in Figure E.3, which shows the content of theInductors & Coupling component category.

To place a component in the schematic one selects a particular componentfrom the Available Parts window and then click-on Place. The componentwill then appear in the middle of the schematic window. An alternativeis to left-click-on the part and then go the to schematic window and clickthe middle mouse button (if there is one).3

One can also access the Parts Gallery via using the right mouse buttonselecting Get Parts→Parts Gallery, or from the Schematics main menu.

3Only works if a mouse driver that recognises the middle mouse button is installed.


Figure E.3: An example of a parts gallery screen.

As a specific example, if we want to place a diode on the schematicthen one navigates to the Analogy Parts Library→Electronic→SemiconductorDevices→Diodes category. From the Available Parts window select theDiode, Ideal (PWL) component and then press Place. If you look at theschematic you will find a green diode in the middle of it. The green colourindicates that the component is selected. If a component is selected thenit can be dragged around the schematic to position it where one likes bymoving the cursor pointer over it (the component then changes to red),pressing the left mouse button, and then dragging to the desired location.

Set a parts properties: Once a part is on the schematic then its properties canbe set. This is carried out by double-left-clicking on the part (one canalso get the properties of the part by right clicking and then selecting theSymbol Properties on the drop-down menu). One can also obtain help ona part by selecting the Help drop-down menu from the properties screen.The Help explains the meaning and range of values for all the propertieslisted for the part.

The properties window contains three columns – Property Name, PropertyValue and a set of round buttons on the right that denote the visibility ofthe property on the schematic. The latter two of these can be altered bythe user. The Property Value fields can contain undef, or *req*. The undeffield usually means means that the value is undefined, but the part willexecute correctly with some underlying default value. However, in manycases this does not make sense. For example the resistor component hasundef for its value, and clearly one would wish to set the value of a resistorin a particular circuit. If an undef value has to be defined the simulator

E.2 Circuit Schematic Capture E-5

will let you know when you try to run the simulation. The *req* fieldmeans that there are no default values defined, and it is mandatory todefine a value. The values of the components can be entered in two mainnumber formats. Saber uses a set of multiplier factors which are shownin Table E.1. One can of course use whole numbers, and also scientificnotation if desired – e.g. 25e-4 for 0.0025.

It should be noted that the ref property name contains a unique name forthe part on the schematic. Sometimes if a part is copied on the schematicthis name is not changed appropriately (this appears to be a bug in thesoftware). Therefore one gets duplicate part references, and consequentlythe simulation fails. One has to manually change the ref name if thisoccurs.4

The visibility field allows one to nominate whether the property value (thevisibility button is half on), or the property name and property value (thevisibility full on), are to be displayed on the schematic. If the button is“off” then nothing about that property is displayed on the schematic.

In a manner similar to the placement of the diode all the other componentsare placed on the schematic. The wires that join the components are drawnby moving the cursor over one of the component node points. The cursorwill change to a cross-hair and pressing and holding the left mouse buttonwill allow a wire to be drawn. There is a grid that wires and componentslie on, which makes drawing the lines very simple. If for some reason thecursor does not change (for examples one is drawing a line not connected toa component, then the wire drawing tool can be selected (see Figure E.2).A wire which does not terminate on a component node can be terminatedby double-left-clicking at the point where one wishes to stop the wire.

Place a Saber ground node: A schematic must contain a ground referencedesignator for the simulator to be able to function. This symbol is calledGround (Saber Node 0) in the parts library. This ground symbol can belocated in a number of places in the parts library tree. The ground isconnected to the point in the schematic from which all the voltages in thedesign will be measured.

Wires: We have already mentioned how to draw wires on the schematic. Onecan also select a wire and delete it by pressing delete on the keyboard, orright clicking and selecting Delete Wire on the drop-down menu. One canalso alter the properties of a wire by right-clicking on the selected wireand selecting Attributes... on the drop-down menu (see Figure E.4 for anexample of the Attributes... window). For example, one can change thename of a wire in the Name field in the window, and then select whetherthis name should be displayed on the schematic (which is often very handyfor documentation reasons).

4A part can be copied by selecting the component and then moving the cursor to theplace where one wishes to have the duplicate component, and then clicking the middle mousebutton.


Name Scientific Notation Saber shortcutfemto 10−15 fpico 10−12 pnano 10−9 nmicro 10−6 umilli 10−3 mkilo 103 kmega 106 meg

Table E.1: Number magnitude specifiers in Saber

Repeat the above steps until the complete circuit shown in Figure E.1 hasbeen drawn. At this point we are now ready to start the simulation phase ofthe exercise.

E.3 Executing the Transient Analysis

In order to carry out the simulation of a design one now has to invoke thesimulator. This is achieved by pressing the SaberGuide button (see Figure E.2).One then gets the screen shown in Figure E.5. Note the new toolbar at the topof the screen. This toolbar allows one to control the Saber simulator from theSaberSketch window.

The main tool used in SaberGuide is the DC/Transient button shown inFigure E.5. If one clicks on this button then the window shown in Figure E.6appears. The parameters circled should be filled out so that the end time andtime step of the simulation are set-up, and the simulator will automatically openSaberScope upon the completion of the simulation.

One can see that there are a number of other tabs on the window. In moresophisticated simulations some of these may have to be used. The only otherone that we shall look at in this simulation is the Input Output tab, which isshown in Figure E.7. The circled quantities have been altered from the defaultvalues. These alterations cause to simulator to save all the signals in the design,and all types of variables (across variables (i.e. voltages) and through variables(i.e. currents)).

Remark E.1 One can also select specific signals for the simulator to save. Thisis essential in large simulations otherwise the output files produced by the simu-lator are huge. The signals can be selected using the Browse Design... selectionfrom the Input Output→Signal List→Select sub-menu. Note that the simulatorhas to be running to carry out this function, therefore it is necessary to start asimulation and stop it (using the Stop button), and then reenter this menu tocarry out this function.

Once all this information has been filled out then one simply clicks OK atthe bottom of the window and the simulation will begin. It firstly netlists thedesign, and if this is successfully completed it will work out the dc starting

E.4 Plotting and Processing Results E-7

Figure E.4: The wire attributes window.

condition, and then finally start the transient analysis. A rotating icon in thetop right corner of the Saber window indicates that the simulator is running.When it finishes, which is very fast in the case of this simulation, the simulatorwill automatically open up SaberScope to allow the results of the simulation tobe post-processed.

E.4 Plotting and Processing Results

If SaberScope has not been set to automatically open then it can be openedmanually via the Results→View Plotfiles in Scope... menu item.

If SaberScope opens automatically it loads the plot file just generated by thesimulator (because of the setting made in the DC/Transient screen), and thendisplays the plot file opened in the Signal Manager window, and the signals inthis plot file in a second window named after the plot file. The SaberScopeopening window is shown in Figure E.8.

Notice in the Diode_LR_cct.tr signal window that some of the signals have a“+” next to them. This means that if one double-left-clicks on them then anothermore detailed signal list will expand from this root. One can then select one ofthese signals to plot, and then left-click the Plot button. Figure E.9 shows theinductor component expanded, and the i(m) signal plotted.

Remark E.2 From Figure E.9 one can see the advantage of naming signals


DC and transient

analysis button

Figure E.5: An example of SaberSketch with the Saber guide toolbar activated.

with meaningful names, as opposed to the default names given to the signals bySaber. The default names in the signal list window do not make much sense.When one is scanning through the signal list for complex designs, it is mucheasier to find the signals/components of interest if the names make sense.

If one wishes to plot a number of variables, then left-click the desired sig-nals holding down the Ctrl key on the keyboard, and then left-click Plot. Theselected signals will all be plotted on separate axes. One can also superimposeseveral plots on the one set of axes. This can be achieved in two different ways,dependent on whether one has already plotted the signals on separate axes. Ifone wishes to plot two signals on the same axis then select one of the signalsand plot it, and then select the other, and go the the plot window and press thecentre mouse button over the graph upon which one wishes the second signalto be plotted.

The other way of plotting two or more signals on the same axis, is to firstlyplot the signals on separate axes, and then use the Stack Region feature. Thisis activate by selecting one of the signals to be “stacked” on the same axis (thisis achieved by placing the mouse cursor over the signal name to the right ofthe plot – the plot will go red, and then left-click), and then right-click and gothe drop-down sub-menu Stack Region. At the bottom of this flyout one cansee a number of Analog signals listed (the number dependent on the numberof signals plotted on the graph window), with Analog 0 being the one at the


Changed fields

Figure E.6: An example dc/transient simulation set-up window.

bottom of the graph window. Select the analog signal number that correspondsto the axis that one wishes to plot onto.

If one plots a signal and wants to delete it, then select the signal in the graphwindow, and then right click to get the drop-down menu and select the DeleteSignal option.

E.4.1 Manipulating ResultsOne of the very powerful features of the SaberScope system is its ability toperform calculations on the results of the simulation, and also to take accuratemeasurements on the waveforms produced.

Let us firstly consider the calculation capability. The waveform calculatorallows one to subtract, add, multiply, divide, and perform a number of othermanipulations on signals. The calculator is activated by pushing the “Calcula-


Changed

variables

Figure E.7: The input-output table of the dc/transient analysis window.

tor” button at the bottom of the screen. The signals that one wishes to carryout the calculations on are selected by left-clicking them in the signal window,and then middle clicking in the area just below the toolbar in the calculator.The signal name should appear in this window and the scrolling window imme-diately below it. The calculator works using reverse polish notation (like a HPcalculator), therefore before selecting an operation we need to select the twosignals to operate on.

In the example shown in Figure E.10, we have selected the inductor voltage(vl) and current (i), and then selected the multiply function of the calculator (*)– i.e. we are working out the instantaneous power flow into the inductor. Theresult then appears in the top window of the calculator. We can then plot thisresult by left clicking the small graph icon at the extreme left of the calculatortoolbar.


Figure E.8: The initial SaberScope window.

In order to look at a waveform in more detail one can expand the horizontalor vertical axis by simply selecting the axis by left-clicking, and then holdingdown the button to extend a yellow bar along the region of the axis that onewishes to expand. One can do this more precisely by right-clicking on the axisof interest and then using the drop-down menu to carry out a more precisenumerical expansion of the axis (or alternatively go back to the original axisscaling).

In addition to expanding the axes using the mouse cursor, one can alsozoom in on the waveforms by simply clicking the mouse over the section of thewaveform of interest, and then dragging out a square marque over the area.This area will then be zoomed on the plot.

All plotted curves have properties that can be altered. This is achieved byselecting the plot of interest, and then right-clicking and selecting Attributes....The contents of the resultant window are self explanatory.

The other major facility that is of use for processing plots is the measurementtool. This is activate by left clicking the “Caliper” button at the bottom of theSaberScope screen. This tool allows one to measure the precise absolute values ofthe quantities on the screen, rise time of steps etc. There are too many featuresto document here, so it is suggested that you have a look at the features, andtry them to see what happens.

E.4.2 Fourier Analysis

The Fourier Analysis facility allows one to get frequency response plots for dataproduced by the simulator. A Fourier Analysis can only be performed after thesimulator has run, and therefore falls into the post-processing category.

In order to perform a Fourier Analysis one must firstly return to the Saber-


Figure E.9: A signal plotted in SaberScope.

Guide window (don’t close the SaberScope window, simply iconise it to keepit out of the way). The following steps are carried out to perform a FourierAnalysis on a periodic waveform.

a. Select the Analyses→Fourier→Fourier... menu.

b. The left window in Figure E.11 will show up. I have filled in some valuesfor this window. The Fundamental Frequency of the output waveforms isknown as it was set by the frequency of the sine wave source in the circuit.The 80 millisecond time next to the Period End dialogue indicates that weare to analyse the period of the output ending at 80 milliseconds. Finallythe Number of Harmonics stipulates the maximum number of harmonicsthat that analysis will calculate.

c. Another tab in the Fourier window is the Input Output tab. Its contentsappear as the right window in Figure E.11. In this case I have set theSignal List to be /... which means all signals, and the Include Signal Typesis set to all, meaning that through and across variables are to be included.

d. Finally we left click OK or Apply and the Fourier analysis is carried outon the signals selected.

Remark E.3 If one is analysing a non-periodic waveform or a pulse then theFast Fourier Transform option should be used.

In order to plot the results of the Fourier analysis go back to SaberScopeand via the Signal Manager window open a file dialogue. One should see a newfile with a fou.ai_pl extension. Click on this file and click on Open. Another

E.5 A Practice Exercise E-13

Figure E.10: An example of a waveform calculation in SaberScope.

signal list box should open with the signals listed for which frequency data isavailable. These signals can then be plotted in a fashion similar to the timedomain signals.

E.5 A Practice ExerciseIn order to test your understanding of the above concepts it is suggested thatyou carry out the following on the circuit of Figure E.1. I suggest that you don’tblindly carry out the simulation, but try and understand what you are seeing inthe results. For a simple circuit, it has surprising results, and you might learnsomething!

a. Execute the simulation and plot graphs of vs, vR, vL and i.

b. Measure the average and rms load current from the plots.

c. Measure the average voltage across the inductor, and try and explain theresult.

d. Measure the voltage across the diode. What is the maximum reversevoltage it is subject to?

e. Plot graphs of the power dissipated in the load and the energy stored inthe inductor. Measure the average power dissipation.

f. Measure the ac source power, and compare this value with the value dis-sipated in the load resistor. Why is there a discrepancy?


Figure E.11: Fourier analysis dialogues in Saber.

g. Perform a frequency analysis of the rectifier output voltage and current.Why is the spectrum of the current different from that of the voltage?

h. Replace the load resistor with a 300 volt dc source. Plot vS , i and vL. Notethat current only flows for part of the half cycle of the voltage supply. Notewhere the peak current occurs.

i. Measure the average and rms values of the load current and voltage. Alsomeasure the average power transferred to the load. Note that the averageload power is now the product of the average current and average loadvoltage.

j. Perform a frequency analysis of the load current and voltage, and comparethe results with the resistive load case.

If the above exercise is carried out successfully then you should have a goodpreliminary working knowledge of the operation of the Saber simulation system.There are many other aspects of the system that we have not considered – youwill need to know these for more sophisticated simulations.

AcknowledgmentThis tutorial is partially based on a Saber tutorial written by Dr. B.J. Cook ofthe Department of Electrical and Computer Engineering, University of Newcas-tle, Australia.

F-2 PV Related Information

Appendix F

PV Related Information

F.1 SunnyBoy Transformerless PV Inverter

SUNNY BOY 3000TL / 4000TL / 5000TL

SB 3000TL-20 / SB 4000TL-20 / SB 5000TL-20

High Yields• Maximum efficiency of 97 %• Multi-String technology*• Transformerless, with H5 topology• Shade management with OptiTrac Global Peak

Simple• Easily accessible connection area• Cable connection without tools• DC plug system SUNCLIX

Communicative• Bluetooth technology as standard• Multilingual graphic display• Multi-function relay as standard

Safe• Integrated ESS DC switch- disconnector

SUNNY BOY 3000TL / 4000TL / 5000TL Perfection Plus. Usability. The transformerless Sunny Boy generationMore communicative, easier to use and more efficient than ever: this Sunny Boy is setting new standards in inverter technology. A modern graphic display, readout of daily values even after sunset, simplified installation concept and wireless communication via Bluetooth: The new Sunny Boys fulfill every wish. With the new OptiTrac Global Peak shade management and an optimal efficiency of 97 %, the inverters ensure optimum solar yield. As transformerless, multi-string devices, the Sunny Boy 4000TL and 5000TL provide maximum flexibility for plant design, and are the first choice for demanding generator designs.

*Sunny Boy 4000TL / 5000TL

F.1 SunnyBoy Transformerless PV Inverter F-3

SMA Solar Technology AGwww.SMA-Solar.com

Accessories

RS485 interface DM-485CB-10

Technical dataSunny Boy3000TL

Sunny Boy4000TL

Sunny Boy4000TL/V

Sunny Boy5000TL

Input (DC)Max. DC power (@ cos ϕ =1) 3200 W 4200 W 4200 W 5300 WMax. DC voltage 550 V 550 V 550 V 550 VMPP voltage range 188 V ‒ 440 V 175 V ‒ 440 V 175 V ‒ 440 V 175 V ‒ 440 VDC nominal voltage 400 V 400 V 400 V 400 VMin. DC voltage / start voltage 125 V / 150 V 125 V / 150 V 125 V / 150 V 125 V / 150 VMax. input current / per string 17 A / 17 A 2 x 15 A / 15 A 2 x 15 A / 15 A 2 x 15 A / 15 ANumber of MPP trackers / strings per MPP tracker 1 / 2 2 / A: 2, B: 2 2 / A: 2, B: 2 2 / A: 2, B: 2Output (AC)AC nominal power (@ 230 V, 50 Hz) 3000 W 4000 W 3680 W 4600 WMax. AC apparent power 3000 VA 4000 VA 4000 VA 5000 VANominal AC voltage; range 220, 230, 240 V;

180 ‒ 280 V220, 230, 240 V; 180 ‒ 280 V

220, 230, 240 V; 180 ‒ 280 V

220, 230, 240 V; 180 ‒ 280 V

AC grid frequency; range 50, 60 Hz; ± 5 Hz 50, 60 Hz; ± 5 Hz 50, 60 Hz; ± 5 Hz 50, 60 Hz; ± 5 HzMax. output current 16 A 22 A 22 A 22 APower factor (cos ϕ) 1 1 1 1Phase conductors / connection phases 1 / 1 1 / 1 1 / 1 1 / 1EfficiencyMax. efficiency / Euro-eta 97.0 % / 96.3 % 97.0 % / 96.4 % 97.0 % / 96.4 % 97.0 % / 96.5 %Protection devicesDC reverse-polarity protection ESS switch-disconnector AC short circuit protection Ground fault monitoring Grid monitoring (SMA Grid Guard) Galvanically isolated / all-pole sensitive fault current monitoring unit / / / /

Protection class / overvoltage category I / III I / III I / III I / IIIGeneral dataDimensions (W / H / D) in mm 470 / 445 / 180 470 / 445 / 180 470 / 445 / 180 470 / 445 / 180Weight 22 kg 25 kg 25 kg 25 kgOperating temperature range ‒25 °C … +60 °C ‒25 °C … +60 °C ‒25 °C … +60 °C ‒25 °C … +60 °CNoise emission (typical) ≤ 25 dB(A) ≤ 29 dB(A) ≤ 29 dB(A) ≤ 29 dB(A)Internal consumption: (night) < 0.5 W < 0.5 W < 0.5 W < 0.5 WTopology transformerless transformerless transformerless transformerlessCooling concept Convection OptiCool OptiCool OptiCoolElectronics protection rating / connection area (as per IEC 60529) IP65 / IP54 IP65 / IP54 IP65 / IP54 IP65 / IP54

Climatic category (per IEC 60721-3-4) 4K4H 4K4H 4K4H 4K4HFeaturesDC connection: SUNCLIX AC connection: screw terminal / plug connector / spring-type terminal // // // //

Display: text line / graphic / / / /Interfaces: RS485 / Bluetooth / / / /Warranty: 5 / 10 / 15 / 20 / 25 years //// //// //// ////Certificates and permits (more available on request) CE, VDE 0126-1-1, DK 5940, RD 1663, G83/1-1, PPC, AS4777, EN 50438*, C10/C11, PPDS* Does not apply to all national deviations of EN 50438 Standard features Optional features not availableData at nominal conditions Type designation SB 3000TL-20 SB 4000TL-20 SB 4000TL-20/V 0159 SB 5000TL-20

SB5000TL-DEN102030 SMA and Grid Guard are registered trademarks of SMA Solar Technology AG. Bluetooth® is a registered trademark owned by Bluetooth SIG, Inc. SUNCLIX is a registered trademark owned by PHOENIX CONTACT GmbH & Co. KG. Text and illustrations reflect the current state of the technology at the time of publication. Technical modifications reserved. No liability for printing errors. Printed on chlorine-free paper.


F.2 Tianwei PV Array Datasheet

F.2 Tianwei PV Array Datasheet F-5


F.3 Australian Standards for PV Inverter Con-nections

F.3.1 AS4777.2-2005: Grid connection of energy systemsvia inverters Part 2: Inverter Requirements

3 AS 4777.2—2005

CONTENTS

Page

1 SCOPE........................................................................................................................ 4

2 NORMATIVE REFERENCES ................................................................................... 4

3 DEFINITIONS............................................................................................................ 5

4 INVERTER REQUIREMENTS.................................................................................. 5

APPENDICES A POWER FACTOR TEST ............................................................................................ 9

B HARMONIC CURRENT LIMIT TEST .................................................................... 10 C TRANSIENT VOLTAGE LIMIT TEST.................................................................... 12

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011

F.3 Australian Standards for PV Inverter Connections F-7

AS 4777.2—2005 4

! Standards Australia www.standards.com.au

STANDARDS AUSTRALIA

Australian Standard

Grid connection of energy systems via inverters

Part 2: Inverter requirements

1 SCOPE

This Standard specifies the requirements for inverters, with ratings up to 10 kVA for single-phase units or up to 30 kVA for three-phase units, for the injection of electric power

through an electrical installation to the electricity distribution network.

NOTES:

1 Although this Standard does not apply to larger systems, similar principles can be used for the design of such systems.

2 Although this Standard is written on the basis that the renewable energy is from a d.c. source (e.g. photovoltaic array), this Standard may be used for systems where the energy is from a variable a.c. source (e.g. wind turbine or micro-hydro system) by appropriate changes to the tests.

3 This Standard does not include EMC requirements. These are mandated by the Australian Communications Authority (ACA). Users attention is drawn to Australian Communication Authority’s document ‘Electromagnetic Compatibility—Information for suppliers of electrical

and electronic products in Australia and New Zealand’ for guidance.

2 NORMATIVE REFERENCES

The following normative documents contain provisions which, through reference in this text, constitute provisions of this Standard.

AS 4777 Grid connection of energy systems via inverters 4777.3 Part 3: Grid protection requirements

60038 Standard voltages

AS/NZS 3100 Approval and test specification—General requirements for electrical equipment

60950 Information technology equipment—Safety 60950.1 Part 1: General requirements

61000 Electromagnetic compatibility (EMC)

61000.3.3 Part 3.3: Limits—Limitation of voltage fluctuations and flicker in publiclow-voltage supply systems, for equipment with rated current less thanor equal to 16 A per phase and not subject to conditional connection

61000.3.5 Part 3.5: Limits—Limitation of voltage fluctuations and flicker in low-voltage power supply systems for equipment with rated current greater than 16 A

IEC 60255 Electrical relays 60255-5 Part 5: Insulation coordination for measuring relays and protection

equipment—Requirements and tests

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


5 AS 4777.2—2005

www.standards.com.au ! Standards Australia

ACA Electromagnetic Compatibility—Information for suppliers of electrical and electronic products in Australia and New Zealand

3 DEFINITIONS

For the purpose of this Standard, the following definitions apply.

3.1 Electricity distribution network

The portion of an electrical system that is operated by an electrical distributor.

3.2 Grid

An alternative term for an electricity distribution network.

3.3 Grid protection device

A device complying with the requirements of AS 4777.3.

3.4 Inverter

A device that uses semiconductor devices to transfer power between a d.c. source or load

and an a.c. source or load.

NOTE: This Standard is written on the basis that the renewable energy is from a d.c. source (e.g. photovoltaic array), but the energy may be from a variable a.c. source (e.g. wind turbine or micro-hydro system) and hence, for the purposes of this Standard, a.c. to a.c. converters that use semiconductor devices are considered to be inverters, as the requirements in this Standard are applicable to such systems.

3.5 Inverter energy system

A system comprising one or more inverters together with one or more energy sources

(which may include batteries for energy storage), controls and one or more grid protection devices.

3.6 Islanding

Any situation where the electrical supply from an electricity distribution network is disrupted and one or more inverters maintains any form of electrical supply, be it stable or not, to any section of that electricity distribution network.

3.7 Nominal grid voltage

The definitions of AS 60038 shall apply.

3.8 Ripple control

A means of one-way communication based on transmitting electrical signals over an electricity distribution network.

3.9 Uninterruptible power supply (UPS) system

A power system comprising inverters, switches, control circuitry and a means of energy storage (e.g. batteries) for maintaining continuity of electrical supply to a load in the case of a disruption of power supply from an electricity distribution network.

4 INVERTER REQUIREMENTS

4.1 General

The inverter shall comply with the appropriate electrical safety requirements of AS/NZS 3100.

NOTE: AS/NZS 3100 allows that if an individual Standard dealing with specific features of the design, construction and testing of any particular class or type of equipment is issued, it supersedes the general requirements of AS/NZS 3100 that are specifically dealt with in that individual Standard.

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


AS 4777.2—2005 6


4.2 Compatibility with electrical installation

The inverter shall have a.c voltage and frequency ratings compatible with AS 60038.

NOTE: The nominal voltage at the point of supply is 230 V a.c. single phase line-to-neutral and 400 V a.c. three phase line-to-line with a tolerance of +10% -6% and a frequency of 50 Hz.

4.3 Power flow direction

Power flow between the energy source and the grid may be in either direction.

4.4 Power factor

The power factor of the inverter, considered as a load from the perspective of the grid, shall be in the range from 0.8 leading to 0.95 lagging for all output from 20% to 100% of rated output. These limits shall not apply if the inverter is approved by the relevant electricity

distributor to control power factor outside this range for the purpose of providing voltage support.

Compliance shall be determined by type testing in accordance with the power factor test

described in Appendix A.

NOTE: Lagging power factor is defined to be when reactive power flows from the grid to the inverter; that is, when the inverter acts as an inductive load from the perspective of the grid.

4.5 Harmonic currents

The harmonic currents of the inverter shall not exceed the limits specified in Tables 1 and 2

and the total harmonic distortion (THD) (to the 50th harmonic) shall be less than 5%. Compliance shall be determined by type testing in accordance with the harmonic current limit test specified in Appendix B.

NOTE: The inverter should not significantly radiate or sink frequencies used for ripple control by the local electrical distributor. The distributor should be consulted to determine which frequencies are used.

TABLE 1

ODD HARMONIC CURRENT LIMITS

Odd harmonic order number Limit for each individual odd harmonic

based on percentage of fundamental

3, 5, 7 and 9 4%

11, 13 and 15 2%

17, 19 and 21 1.5%

23, 25, 27, 29, 31 and 33 0.6%

TABLE 2

EVEN HARMONIC CURRENT LIMITS

Even harmonic order number Limit for each individual even harmonic

based on percentage of fundamental

2, 4, 6 and 8 1%

10 – 32 0.5%

NOTE: The harmonic limits in Tables 1 and 2 are based on those in IEEE 929-2000 IEEE Recommended Practice for

Utility Interface of Photovoltaic (PV) Systems.

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


7 AS 4777.2—2005


4.6 Voltage fluctuations and flicker

The inverter shall conform to the voltage fluctuation and flicker limits as per

AS/NZS 61000.3.3 for equipment rated less than or equal to 16 A per phase and AS/NZS 61000.3.5 for equipment rated greater than 16 A per phase. Compliance shall be determined by type testing in accordance with the appropriate Standard.

4.7 Impulse protection

The inverter shall withstand a standard lightning impulse of 0.5 J, 5 kV with a 1.2/50 waveform. Compliance shall be determined by type testing in accordance with the

impulse voltage withstand test of IEC 60255-5.

4.8 Transient voltage limits

When type tested in accordance with the transient voltage limit test described in

Appendix C, the voltage-duration curve derived from measurements taken at the a.c. terminals of the inverter shall not exceed the limits listed in Table 3.

NOTE: The voltage-duration limits listed in Table 3 are graphically illustrated in Figure 1.

TABLE 3

TRANSIENT VOLTAGE LIMITS

Instantaneous voltage Duration

Line-to-neutral Line-to-line

Seconds Volts Volts

0.000 2 910 1 580

0.000 6 710 1 240

0.002 580 1 010

0.006 470 810

0.02 420 720

0.06 390 670

0.2 390 670

0.6 390 670

4.9 Direct current injection

In the case of a single-phase inverter, the d.c. output current of the inverter at the a.c. terminals shall not exceed 0.5% of its rated output current or 5 mA, whichever is the greater.

In the case of a three-phase inverter, the d.c. output current of the inverter at the a.c. terminals, measured between any two phases or between any phase and neutral, shall not exceed 0.5% of its rated per-phase output current or 5 mA, whichever is the greater.

If the inverter does not incorporate a mains frequency isolating transformer, it shall be type tested to ensure the d.c. output current at the a.c. terminals of the inverter is below the above limits at all power levels.

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


AS 4777.2—2005 8


FIGURE 1 VOLTAGE-DURATION CURVE OF TRANSIENT VOLTAGE LIMITS

4.10 Data logging and communications devices

Any electronic data logging or communications equipment incorporated in the inverter should comply with the appropriate requirements of AS/NZS 60950.1. Particular attention

is drawn to requirements for electrical insulation and creepage and clearance distances.

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


9 AS 4777.2—2005


APPENDIX A

POWER FACTOR TEST

(Normative)

A1 TEST SPECIFICATIONS

The power factor test shall be carried out as follows:

(a) The inverter shall be connected into a test circuit similar to that shown in Figure A1. The grid voltage shall equal the nominal voltage to within 5%.

(b) The d.c. supply shall be varied until the a.c. output of the inverter, measured in

volt-amperes, equals (20 ±5)% of its rated output.

(c) The power factor of the inverter output shall be measured.

(d) Steps (b) and (c) shall be repeated with the inverter operating at (30 ±5)%, (40 ±5)%,

(50 ±5)%, (60 ±5)%, (70 ±5)%, (80 ±5)%, (90 ±5)% and (100 ±5)% of its rated output, measured in volt-amperes.

When subjected to the test described above, the power factor shall comply with the limits

specified in Clause 4.4.

NOTE: This test circuit applies to a single-phase system. To test a three-phase system, an equivalent three-

phase circuit is required.

FIGURE A1 CIRCUIT FOR POWER FACTOR TEST

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


AS 4777.2—2005 10


APPENDIX B

HARMONIC CURRENT LIMIT TEST

(Normative)

B1 TEST SPECIFICATIONS

The harmonic current limit test shall be carried out as follows:

(a) The inverter shall be connected into a test circuit similar to that shown in Figure B1.

(b) The d.c. supply shall be varied until the a.c. output of the inverter, measured in volt-amperes, lies in the range (100 ±5)% of its rated output.

(c) The harmonic current content of the inverter output shall be measured.



FIGURE B1 CIRCUIT FOR HARMONIC CURRENT LIMIT TEST OF A

SINGLE-PHASE SYSTEM.

B2 HARMONIC CURRENT LIMITS

When the inverter is subjected to the test described in Clause B1 above, the harmonic

currents of the inverter shall not exceed the limits specified in Table 1 and Table 2.

B3 SUPPLY SOURCE DURING HARMONIC TESTS

While the harmonic current measurements are being made, the test voltage at the a.c. terminals of the inverter shall meet the following requirements:

(a) The test voltage shall be maintained at the nominal voltage ±5% at the discretion of the testing authority.

(b) The test frequency shall be maintained at (50 ±1)Hz.

(c) In the case of a three-phase supply, the angle between the fundamental voltages of each pair of phases shall be maintained at (120 ±1.5)°.

(d) The harmonic ratios of the test voltage shall not exceed the limits listed in Table B1.

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


11 AS 4777.2—2005


TABLE B1

HARMONIC LIMITS OF TEST VOLTAGE

Harmonic order number Limit based on percentage of fundamental

3 0.9%

5 0.4%

7 0.3%

9 0.2%

even harmonics 2–10 0.2%

11– 50 0.1%

Total harmonic distortion (to the 50th harmonic) 5%

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


AS 4777.2—2005 12


APPENDIX C

TRANSIENT VOLTAGE LIMIT TEST

(Normative)

C1 GENERAL

To prevent damage to electrical equipment connected to the same circuit as the inverter,

disconnection of the inverter from the electricity distribution network shall not result in transient overvoltages beyond the limits specified in Table 3.

C2 TEST SPECIFICATIONS

The transient voltage limit test shall be carried out as follows:

(a) The inverter shall be placed in a test circuit similar to that shown in Figure C1.

(b) The voltage at the a.c. terminals of the inverter before the switch is opened, shall be maintained at the nominal voltage ±5% at the discretion of the testing authority.

(c) The d.c. supply shall be varied until the a.c. output of the inverter, measured in volt-amperes, equals (10 ±5)% of its rated output.

(d) The switch S shall be opened.

(e) The voltage across the a.c. terminals of the inverter shall be recorded at a sample frequency of at least 10 kHz. If the inverter has multiple sets of a.c. terminals, only the a.c. terminals used to connect the inverter to the test circuit (grid connection)

shall be monitored.

(f) Steps (b) to (e) shall be repeated with the inverter operating at (50 ±5)% and (100 ±5)% of its rated output, measured in volt-amperes.

C = 100µF R = 560 k"



FIGURE C1 CIRCUIT FOR TRANSIENT VOLTAGE LIMIT TEST

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


13 AS 4777.2—2005


C3 TRANSIENT VOLTAGE LIMITS

When subjected to the test described in Clause C2, the voltage-duration curve derived from

the sampled a.c. voltage at the inverter terminals shall not exceed the limits specified in Table 3.

NOTE: A voltage-duration curve is calculated using the sampled instantaneous voltage over the complete trip time of the inverter. For each voltage (maximum voltage step 10 V), the number of samples greater than that voltage are counted. This number is then multiplied by the sample interval to derive a duration for that voltage. The voltage-duration curve is the locus of all points derived from this process. The inverter is deemed to comply with the transient voltage limit test if the derived voltage-duration curve lies beneath the appropriate curve of Figure 1 at all points.

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


F.3.2 AS4777.3-2005 Grid connection of energy systemsvia inverters Part 3: Grid protection requirements

3 AS 4777.3—2005

CONTENTS

Page

1 SCOPE........................................................................................................................ 4

2 NORMATIVE REFERENCES ................................................................................... 4

3 DEFINITIONS............................................................................................................ 5

4 GENERAL AND SAFETY REQUIREMENTS.......................................................... 6

5 GRID PROTECTION REQUIREMENTS .................................................................. 6

APPENDICES A LIMITS FOR SUSTAINED OPERATION.................................................................. 9 B GRID PROTECTION DEVICE TESTS .................................................................... 10

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


AS 4777.3—2005 4


STANDARDS AUSTRALIA

Australian Standard

Grid connection of energy systems via inverters

Part 3: Grid protection requirements

1 SCOPE

This Standard specifies the requirements for grid protection devices intended to be used in inverter energy systems, with ratings up to 10 kVA for single-phase units, or up to 30 kVA for three-phase units, and for the injection of electric power through an electrical installation to the electricity distribution network.

NOTES:

1 Although this Standard does not apply to larger systems, similar principles can be used for the grid protection of such systems.

2 These devices do not replace devices used for protection and/or isolation as required in AS/NZS 3000.

3 Although this Standard is written on the basis that the renewable energy is from a d.c. source (e.g. photovoltaic array), this Standard may be used for systems where the energy is from a variable a.c. source (e.g. wind turbine or micro-hydro system) by appropriate changes to the tests.

4 This Standard does not include EMC requirements. These requirements are mandated by the Australian Communications Authority (ACA). Users attention is drawn to Australian Communications Authority’s document ‘Electromagnetic Compatibility—Information for

suppliers of electrical and electronic products in Australia and New Zealand’ for guidance.

2 NORMATIVE REFERENCES

The following normative documents contain provisions which, through reference in this text, constitute provisions of this Standard.

AS 60038 Standard voltages

AS/NZS 3000 Electrical Installations (known as the Australian/New Zealand Wiring Rules)

3100 Approval and test specification—General requirements for electrical equipment

60950 Information technology equipment—Safety 60950.1 Part 1: General requirements

61000 Electromagnetic compatibility (EMC) 61000.3.3 Part 3.3: Limits—Limitation of voltage fluctuations and flicker in public

low-voltage supply systems, for equipment with rated current less than or equal to 16 A per phase and not subject to conditional connection

61000.3.5 Part 3.5: Limits—Limitation of voltage fluctuations and flicker in low-voltage power supply systems for equipment with rated currentgreater than 16 A

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


5 AS 4777.3—2005


IEC 60255 Electrical relays 60255-5 Part 5: Insulation coordination for measuring relays and protection

equipment—Requirements and tests

ACA Electromagnetic Compatibility—Information for suppliers of electrical and electronic products in Australia and New Zealand

3 DEFINITIONS

For the purpose of this Standard, the following definitions apply.

3.1 Active anti-islanding protection

A method of preventing islanding by actively varying the output of the inverter energy system.

3.2 Electricity distribution network

The portion of an electrical system that is operated by an electrical distributor.

3.3 Grid

An alternative term for an electricity distribution network.

3.4 Inverter

A device that uses semiconductor devices to transfer power between a d.c. source or load and an a.c. source or load.

NOTE: This Standard is written on the basis that the renewable energy is from a d.c. source (e.g. photovoltaic array), but the energy may be from a variable a.c. source (e.g. wind turbine or micro-hydro system) and hence, for the purposes of this Standard, a.c. to a.c. converters that use semiconductor devices are also considered to be inverters, as the requirements in this Standard are applicable to such systems.

3.5 Inverter energy system

A system comprising one or more inverters together with one or more energy sources (which may include batteries for energy storage), controls and one or more grid protection devices.

3.6 Islanding

Any situation where the electrical supply from an electricity distribution network is disrupted and one or more inverters maintains any form of electrical supply, be it stable or not, to any section of that electricity distribution network.

3.7 Nominal grid voltage

The definition of AS 60038 shall apply.

3.8 Passive anti-islanding protection

A method of preventing islanding based on monitoring the electricity distribution network.

3.9 Electromechanical switch

An electrical switch in which the OFF state results in the physical separation of conductors (e.g. a mechanical relay). This DOES NOT include transistors or similar semiconductor devices.

3.10 Uninterruptible power supply (UPS) system

A power system comprising inverters, switches, control circuitry and a means of energy storage (e.g. batteries) for maintaining continuity of electrical supply to a load in the case of a disruption of power supply from an electricity distribution network. Ac

cess

ed b

y UN

IVER

SITY

OF

NEW

CAST

LE o

n 21

Apr

201

1


AS 4777.3—2005 6


4 GENERAL AND SAFETY REQUIREMENTS

4.1 General

Grid protection of the inverter energy system shall be provided by a grid protection device. This does not preclude the grid protection device being integral to the inverter, nor a single grid protection device being used to protect an inverter energy system comprising multiple inverters.

Compliance with this Standard shall be determined by type testing the grid protection device on its own and, if necessary, in combination with an inverter. Compliance of this combination shall be conditional on their being used together in the same manner in which they have been type tested. Compliance of one combination of inverter and grid protection device does not preclude compliance of either device as part of a different combination.

4.2 Electrical safety

The grid protection device shall comply with appropriate electrical safety requirements of AS/NZS 3100.

NOTE: AS/NZS 3100 allows that if an individual Standard dealing with specific features of the design, construction and testing of any particular class or type of equipment is issued, it shall supersede the general requirements of AS/NZS 3100 that are specifically dealt with in that individual Standard.

4.3 Connection to low-voltage distribution network

The grid protection device shall be compatible with the low-voltage distribution network.

NOTE: The nominal voltage is 230 V a.c. single phase line-to-neutral and 400 V a.c. three phase line-to-line with a tolerance of +10% -6% at a frequency of 50 Hz.

4.4 Voltage flicker

The grid protection device shall conform to the voltage flicker limits specified in AS/NZS 61000.3.3 for equipment rated less than or equal to 16 A (a.c. current) or AS/NZS 61000.3.5 for equipment rated at greater than 16A (a.c. current). Compliance shall be determined by type testing in accordance with the appropriate Standard.

4.5 Impulse protection

The grid protection device shall withstand a standard lightning impulse of 0.5 J, 5 kV with a 1.2/50 waveform. Compliance shall be determined by type testing in accordance with the impulse voltage withstand test of IEC 60255-5.

4.6 Data logging and communications devices

Any electronic data logging or communications equipment incorporated in the inverter should comply with the appropriate requirements of AS/NZS 60950.1. Particular attention is drawn to requirements for electrical insulation and creepage and clearance distances.

5 GRID PROTECTION REQUIREMENTS

5.1 General

The grid protection device shall operate—

(a) if supply from the grid is disrupted; or

(b) when the grid goes outside preset parameters (e.g. under/over voltage, under/over frequency); or

(c) to prevent islanding.

Specific requirements are contained in Clauses 5.2 to 5.5.

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


7 AS 4777.3—2005


5.2 Disconnection device

The grid protection device shall incorporate a disconnection device which shall prevent power (both a.c. and d.c.) from the inverter energy system entering the grid when the disconnection device operates.

NOTE: The disconnection device need not disconnect sensing circuits.

The disconnection device shall incorporate an electromechanical switch if—

(a) there is no galvanic isolation between the energy source(s) and the grid; or

(b) the inverter system continues to provide electrical power to any portion of the electrical installation (i.e. it operates as an uninterruptible power supply (UPS) system) in the event of the disruption of the grid supply.

NOTES:

1 Galvanic isolation can be achieved by using either a two winding high-frequency transformer or a two winding mains frequency transformer.

2 Galvanic isolation is not required on sensing circuits.

Any disconnection device intended for use with a UPS system shall only break the active conductor(s).

The disconnection device may incorporate semiconductor devices if galvanic isolation exists between the energy source(s) and the grid and the system does not operate as an uninterruptible power supply system.

5.3 Voltage and frequency limits (passive anti-islanding protection)

The grid protection device shall incorporate passive anti-island protection in the form of under- and over-voltage and under- and over-frequency protection. If the voltage goes outside the range Vmin to Vmax or its frequency goes outside the range fmin to fmax, the disconnection device (see Clause 5.2) shall operate within 2 s, where—

(a) Vmin shall lie in the range 200-230 V for a single-phase system or 350-400 V for a three-phase system;

(b) Vmax shall lie in the range 230-270 V for a single-phase system or 400-470 V for a three-phase system;

(c) fmin shall lie in the range 45-50 Hz; and

(d) fmax shall lie in the range 50-55 Hz.

The limits Vmax, Vmin, fmax and fmin may be either preset or programmable. The values Vmax, Vmin, fmax and fmin may be negotiated with the relevant electricity distributor. The settings of the grid protection device shall not exceed the capability of the inverter.

5.4 Limits for sustained operation

The introduction of limits for sustained operation is under consideration.

NOTE: See Appendix A for further information about the proposal.

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


AS 4777.3—2005 8


5.5 Active anti-islanding protection

The grid protection device shall incorporate at least one method of active anti-islanding protection. Examples of such methods include shifting the frequency of the inverter away from nominal conditions in the absence of a reference frequency (frequency shift), allowing the frequency of the inverter to be inherently unstable in the absence of a reference frequency (frequency instability), periodically varying the output power of the inverter (power variation) and monitoring for sudden changes in the impedance of the grid by periodically injecting a current pulse (current injection).

NOTE: Active anti-islanding protection is required in addition to the passive anti-islanding protection described in Clause 5.3 above to prevent the situation where islanding may occur because multiple inverters provide a frequency and voltage reference for one another.

The active anti-islanding protection system shall operate the disconnection device (see Clause 5.2) within 2 s of disruption to the power supply from the grid.

5.6 Reconnection procedure

Only after all the following conditions have been met shall the disconnection device operate to reconnect the inverter to the electricity distribution network–

(a) the voltage of the electricity distribution network has been maintained within the range Vmin–Vmax for at least 1 m, where Vmin and Vmax are as defined in Clause 5.3; and

(b) the frequency of the electricity distribution network has been maintained within the range fmin–fmax for at least 1 m, where fmin and fmax are as defined in Clause 5.3; and

(c) the inverter energy system and the electricity distribution network are synchronized and in-phase with each other.

5.7 Security of protection settings

The internal settings of the grid protection device shall be secured against inadvertent or unauthorized tampering. Changes to the internal settings shall require use of a tool and special instructions not provided to unauthorized personnel.

NOTE: Special interface devices and passwords are regarded as tools.

5.8 Compliance with grid protection requirements

Compliance with the anti-islanding protection requirements shall be determined by type testing in accordance with the anti-islanding protection tests described in Appendix B.

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


9 AS 4777.3—2005


APPENDIX A

LIMITS FOR SUSTAINED OPERATION

(Informative)

It is considered that equipment intended for operation at nominal voltages of 230 V (single-phase) or 400 V (three-phase) can endure operation near 200 V and 270 V (single-phase) and 350 V and 470 V (three-phase) but this equipment should not be expected to operate for extended periods at these extreme voltages.

Consideration is being given to introducing graded trip requirements whereby operation at, or near, extreme voltages is permitted for limited periods with the permitted duration reducing as the operating voltage nears the limit. Thus if the grid voltage moves towards a limit value (per Clause 5.3), disconnection could be required if the voltage stays near the limit for an extended duration (even if it never passes the limit).

Users of this Standard are requested to consider this Proposal and Committee EL-042, Renewable Energy Power Systems and Equipment would welcome comments on this proposal.

Comments should be forwarded to— Projects Manager Committee EL-042 Standards Australia GPO Box 5420 SYDNEY NSW 2001

or by e-mail to [email protected] with the first line stating: ‘For Projects Manager EL-042’

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


AS 4777.3—2005 10


APPENDIX B

GRID PROTECTION DEVICE TESTS

(Normative)

B1 GENERAL

To protect the electricity distribution network from islanding, the inverter shall disconnect from the electricity distribution network whenever the supply from the electricity distribution network is disrupted.

Anti-islanding protection shall be assessed by means of the following tests.

B2 UNDER-AND OVER-VOLTAGE TRIP SETTINGS AND RECONNECTION

TEST

B2.1 Tests

The under- and over-voltage trip settings and reconnection test shall be carried out as follows:

(a) The inverter and grid protection device shall be connected into a test circuit similar to that shown in Figure B1.

(b) The under-voltage trip setting of the grid protection device shall be set to its minimum value, or 200 V, whichever is the greater.

(c) The variable a.c. supply shall be set so that the voltage at the a.c terminals of the device under test equals the nominal grid voltage and its frequency equals (50 ±0.2) Hz, and the input supply shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (50 ±5)% of its rated output or 1 kVA, whichever is the lesser.

(d) The variable a.c. supply shall be slowly adjusted to decrease the voltage at the a.c. terminals of the device under test until the device under test disconnects from the variable a.c. supply. The a.c. voltage at which disconnection occurs shall be recorded.

(e) The variable a.c. supply shall be adjusted to return the voltage at the a.c. terminals of the device under test to the nominal grid voltage. The time taken for the device under test to reconnect to the variable a.c. supply shall be recorded.

(f) The output voltage of the variable a.c. supply shall be set to a voltage equal to the under-voltage trip setting, as recorded at step (d), plus 2 V. The voltage shall then be decreased as rapidly as possible but at a rate less than any dV/dt protection incorporated in the device under test. The time interval between the voltage passing through the voltage measured at step (d) and the device under test disconnecting from the variable a.c. supply shall be recorded.

(g) The over-voltage trip setting of the grid protection device shall be set to its maximum value, or 270 V, whichever is the lesser.

(h) The conditions of step (c) shall be re-established.

(i) The voltage of the variable a.c. supply shall be adjusted slowly to increase the voltage at the a.c. terminals of the device under test until the device under test disconnects from the variable a.c. supply. The a.c. voltage at which disconnection occurs shall be recorded.

(j) Step (e) shall be repeated.

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


11 AS 4777.3—2005


(k) The output voltage of the variable a.c. supply shall be set to a voltage equal to the over-voltage trip setting, as recorded at step (i), less 2 V. The voltage shall then be increased as rapidly as possible but at a rate less than any dV/dt protection incorporated in the device under test. The time interval between the voltage passing through the voltage measured at step (i) and the device under test disconnecting from the variable a.c. supply shall be recorded.

B2.2 Criteria for acceptance

When subjected to the tests described in Paragraph B2.1, the voltage recorded at step (d) shall equal the under-voltage set point ±5 V, the voltage recorded at step (i) shall equal the over-voltage set point ±5 V, the disconnection times recorded at steps (f) and (k) shall each be less than or equal to 2 s and the reconnection times recorded at steps (e) and (j) shall each be 1 min or greater.

NOTE: The above test circuit applies to a single-phase system. To test a three-phase system, an equivalent

three-phase circuit is required.

FIGURE B1 TEST CIRCUIT FOR UNDER- AND OVER-VOLTAGE AND UNDER- AND OVER-FREQUENCY TRIP SETTINGS AND RECONNECTION TESTS

B3 UNDER- AND OVER-FREQUENCY TRIP SETTINGS AND RECONNECTION

TEST

B3.1 Tests

The under- and over-frequency trip settings and reconnection test shall be carried out as follows:

(a) The inverter and grid protection device shall be connected into a test circuit similar to that shown in Figure B1.

(b) The under-frequency trip setting of the grid protection device shall be set to its minimum value, or 45 Hz, whichever is the greater.

(c) The variable a.c. supply shall be set so that the voltage at the a.c terminals of the device under test equals the nominal grid voltage and its frequency equals (50 ±0.2) Hz, and the input supply shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (50 ±5)% of its rated output power or 1 kVA, whichever is the lesser.

(d) The frequency of the variable a.c. supply shall be adjusted slowly to decrease the frequency at the a.c. terminals of the device under test until the device under test disconnects from the variable a.c. supply. The frequency at which disconnection occurs shall be recorded. Ac

cess

ed b

y UN

IVER

SITY

OF

NEW

CAST

LE o

n 21

Apr

201

1


AS 4777.3—2005 12


(e) The frequency of the variable a.c. supply shall be adjusted to return the frequency at the a.c. terminals of the device under test to (50 ±0.2) Hz. The time taken for the device under test to reconnect to the variable a.c. supply shall be recorded.

(f) The output frequency of the variable a.c. supply shall be set to a frequency equal to the under-frequency trip setting, as recorded at step (d), plus 0.1 Hz. The frequency shall then be decreased as rapidly as possible but at a rate less than any df/dt protection incorporated in the device under test. The time interval between the frequency passing through the frequency measured at step (d) and the device under test disconnecting from the variable a.c. supply shall be recorded.

(g) The over-frequency trip setting of the grid protection device shall be set to its maximum value, or 55 Hz, whichever is the lesser.

(h) The conditions of step (c) shall be re-established.

(i) The frequency of the variable a.c. supply shall be adjusted slowly to increase the frequency at the a.c. terminals of the device under test until the device under test disconnects from the variable a.c. supply. The frequency at which disconnection occurs shall be recorded.

(j) Step (e) shall be repeated.

(k) The output frequency of the variable a.c. supply shall be set to a frequency equal to the over-frequency trip setting, as recorded at step (i), less 0.1 Hz. The frequency shall then be increased as rapidly as possible but at a rate less than any df/dt protection incorporated in the device under test. The time interval between the frequency passing through the frequency measured at step (i) and the device under test disconnecting from the variable a.c. supply shall be recorded.

B3.2 Criteria for acceptance

When subjected to the test described above, the frequency recorded at step (d) shall equal the under-frequency set point ±0.1 Hz, the frequency recorded at step (i) shall equal the over-frequency set point ±0.1 Hz and the disconnection times recorded at steps (f) and (k) shall each be less than or equal to 2 s and the reconnection times recorded at steps (e) and (j) shall each be 1 min or greater.

B4 GRID TRIP TEST

B4.1 General

For the grid trip test, the inverter and grid protection device shall be connected into a test circuit similar to that of Figure B2. The test shall be carried out using three different load conditions—

(a) light electronic load;

(b) load match; and

(c) load match plus 10%.

For load condition (a), a test load circuit similar to that shown in Figure B3 shall be used. This consists of a full-wave rectifying bridge connected to a 100 µF capacitive element and a 560 k! resistive element in parallel. For load conditions (b) and (c), a test load circuit similar to that of Figure B4 shall be used. This consists of resistive, inductive and capacitive loads in parallel. In both cases, the inductive load shall be chosen such that it draws 100 VAR from the grid and the capacitive load shall be chosen such that it supplies 100 VAR to the grid. For load condition (b), the resistive load shall be chosen such that it draws a load equal to the real power output of the inverter. For load condition (c), the resistive load shall be chosen such that it draws a load that exceeds the real power output of the inverter by 10%. Ac

cess

ed b

y UN

IVER

SITY

OF

NEW

CAST

LE o

n 21

Apr

201

1


13 AS 4777.3—2005


Values for L and C can be calculated using the following formulae:

f

VL

1002

2

!"

=

Vf

C2

2

100

!"

=

where

V = grid voltage

f = grid frequency

C = capacitance

L = inductance

NOTE: This test circuit applies to a single-phase system. To test a three-phase-system, an equivalent

three-phase circuit is required.

FIGURE B2 CIRCUIT FOR GRID TRIP TEST

C=100µF

R=560 k"

NOTE: This load applies to a single-phase system. To test a three-phase system, an equivalent three-phase

load is required.

FIGURE B3 TEST LOAD FOR GRID TRIP TEST UNDER LOAD CONDITION (A)

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


AS 4777.3—2005 14


B4.2 Grid trip test under load condition (a)

The grid trip test under load condition (a) shall be carried out as follows:

(a) The inverter and grid protection device shall be connected into a test circuit similar to that shown in Figure B2 with a load similar to that shown in Figure B3. The grid voltage shall equal the nominal grid voltage ±5%.

(b) The input supply to the device under test shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (10 ±5)% of its rated output.

(c) The switch S shall be opened and the time for the device under test to disconnect from the test circuit shall be recorded.

(d) Switch S shall be closed and the input supply to the device under test shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (50 ±5)% of its rated output.

(e) Step (c) shall be repeated.

(f) Switch S shall be closed and the input supply to the device under test shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (100 ±5)% of its rated output.

(g) Step (c) shall be repeated.

When subjected to the above test, all three disconnection times shall be less than 2 s.

NOTES:

1 This load applies to a single-phase system. To test a three-phase system, an equivalent three-phase load is

required.

2 The C and L form a resonant load where the reactive power of each component is approximately equal to

100 VAR, i.e. L = C = 100 VAR.

3 Cv

and Lv are the components used in steps B 4.3 (d) and B 4.4 (d) and are not part of the resonant loads.

FIGURE B4 TEST LOAD FOR GRID TRIP TEST UNDER LOAD CONDITIONS (B) AND (C).

B4.3 Grid trip test under load condition (b)

The grid trip test under load condition (b) shall be carried out as follows:

(a) The inverter and grid protection device shall be connected into a test circuit similar to that of Figure B2 with a test load similar to that shown in Figure B4. The resistive load shall be chosen to draw a load approximately equal to the real power output of the device under test required in each of the following three power level tests. The inductive load shall be chosen such that it draws approximately 100 VAR from the grid. The capacitive load shall be chosen such that it supplies approximately 100 VAR to the grid. The grid voltage shall equal the nominal grid voltage ±5%.

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


15 AS 4777.3—2005


(b) The input supply to the device under test, measured in volt-amperes, shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (10 ±5)% of its rated output.

(c) The resistive load (R) shall be increased or decreased until the real power consumption of the test load matches the real power output of the inverter to within ±5%.

(d) Either the inductive or capacitive load shall be adjusted until the reactive power consumption of the test load matches the reactive power output of the device under test (QLoad + QTestload = QInverter output) to ±5%.

NOTE: The purpose of the procedure up to this point is to bring the 50 Hz components of power at the utility disconnection switch to zero. System harmonic voltages will result in harmonic currents in the test circuit. The harmonic currents will typically make it very difficult to make the measurement of power or current flow at the disconnection switch equal to zero.

(e) The switch S shall be opened and the time for the device under test to disconnect from the test circuit shall be recorded.

(f) The switch S shall be closed and the input supply to the device under test shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (50 ±5)% of its rated output.

(g) Steps (c) to (e) shall be repeated.

(h) The switch S shall be closed and the input supply to the device under test shall be varied until the a.c. output power of the device under test, measured in volt-amperes, equals (100 ±5)% of its rated output.

(i) Steps (c) to (e) shall be repeated.


B4.4 Grid trip test under load condition (c)

The grid trip test under load condition (c) shall be carried out as follows:

(a) The inverter and grid protection device shall be connected into a test circuit similar to that shown in Figure B2 with a test load similar to that shown in Figure B4. The resistive load shall be chosen such that is draws a load 1.1 times the real power output of the device under test required in each of the following three power level tests. The inductive load shall be chosen such that it draws approximately 100 VAR from the grid. The capacitive load shall be chosen such that it supplies approximately 100 VAR to the grid. The grid voltage shall equal the nominal grid voltage ±5%.

(b) The input supply to the device under test shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (10 ±5)% of its rated output.

(c) The resistive load (R) shall be increased or decreased until the real power consumption of the test load matches 110% of the real power output of the device under test (i.e. overloads the device under test by 10%) to ±5%.

(d) Either the inductive or capacitive load shall be varied until the reactive power consumption of the test load matches the reactive power output of the device under test to ±5%.

NOTE: The purpose of the procedure up to this point is to bring the 50 Hz components of power at the utility disconnection switch to zero. System harmonic voltages will result in harmonic currents in the test circuit. The harmonic currents will typically make it very difficult to make the measurement of reactive power at the disconnection switch equal to zero.

Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011


AS 4777.3—2005 16


(e) The switch S shall be opened and the time for the device under test to disconnect from the test circuit shall be recorded.

(f) The switch S shall be closed and the input supply to the device under test shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (50 ±5)% of its rated output.

(g) Steps (c) to (e) shall be repeated.

(h) The switch S shall be closed and the input supply to the device under test shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (100 ±5)% of its rated output.

(i) Steps (c) to (e) shall be repeated.


Acce

ssed

by

UNIV

ERSI

TY O

F NE

WCA

STLE

on

21 A

pr 2

011

Appendix G

Python Listing for Two PhasePLL

#===============================================================================## $Id : elec3250_notes . l y x 513 2012−04−29 14:27:06Z reb538 $## $Revision : 513 $## Two Phase PLL Program .## DESCRIPTION#"""This program has been developed from the program that was wri t ten for theAUPEC 2009 paper . I t was used because i t contains most of the necessaryc l a s s e s to e a s i l y implement the two phase PLL. I have l e f t o f l o t of the otherin f ra s t ruc tu r e in the program (most of which i s commented out or not used )j u s t in case I want to deve lop the sof tware fur ther .

The program simply implements the bas ic two phase PLL and demonstrates how i tworks . The waveforms being input to the PLL can be from a two phase source , ora l t e r n a t i v e l y from a s in g l e phase source with in−quadrature waveformgeneration . The in−quadrature generat ion i s not a simple task to ge t r i g h te i t h e r ."""## Written by : Robert Betz# Created on : June 13 , 2011# Last modified on : $Date : 2011−06−29 17:45:43 +1000 (Wed, 29 Jun 2011) $# Last modified by : $Author : reb538 $###===============================================================================

from __future__ import pr int_funct ionfrom pylab import ∗import os

# The fo l l ow ing cond i t iona l import i s to a l low t h i s code to work co r r e c t l y on# both Windows machines and UNIX machines such as Macs of Linux machines .i f os . name == ’ nt ’ :

# The machine i s a Windows machine so import a plat form s p e c i f i c module#import msvcrtopSys = ’Windows ’

e l i f os . name == ’ pos ix ’ :# A posix system .#import s e l e c topSys = ’UNIX ’

G-2 Python Listing for Two Phase PLL

# EXECUTION SWITCHES## Variable to ind ica te tha t synchronous demodulation i s to occur .#SYNC_DEMOD = True

# Add the f o l lwo ing to keep the matp l o t l i b windows a l i v e in the debugger .## See added l i n e s as bottom of the program as we l l .#from Tkinter import Tkw = Tk( )w. withdraw ( )

#==============================================================================## CONSTANTS##==============================================================================

## INITIALISE THE MAIN VARIABLES OF THE SIMULATION# −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

# Form up the three phase waveforms .## Fi r s t l y the amplitudes of the waveforms .## FundamentalX1 = 100.0

# Harmonic amplitude#XH = 30.0

# Fundamental FrequenciesFREQ = 50.0 # This i s the i n i t i a l frequencyFREQ_ALTERED = 60.0 # This i s the changed frequency

# The boolean below contro l s the inc lus ion of harmonic po lu t ion into the# waveforms#HARMONIC_POLUTION = False

# The par t i cu l a r harmonic −− j u s t and in teger number .#HARMONIC_NUM = 5.0

# Set up the sampling frequency in Hertz .#SAMPLING_FREQ = 5000.0

## NOW DEFINE THE PI CONSTANTS FOR feedback in the PLL##Kpf = 1 .0Kif = 1 .0

# Amplitude LPF co e f f i c i e n t s ) .

G-3

# The RECURSIVE_COEFFICIENT_F must be < 1 , and the smal ler i t i s the# higher the bandwidth of the low pass f i l t e r . Note tha t t h i s f i l t e r i s only# 1 s t order .#RECURSIVE_COEFFICIENT_F = 0.992NONRECURSIVE_COEFFICIENT_F = 1.0 − RECURSIVE_COEFFICIENT_F

# The recurs i ve c o e f f i c en t for the low pass f i l t e r used in the PLL loop −−# f i l t e r s the output of the PI con t r o l l e r pr ior to adding to the centre frequency# and in t eg ra t i on .## The non−recurs i ve c o e f f i c en t i s formed by 1.0 − the recurs i ve c o e f f i c i e n t .# Set t h i s va lue to zero i f you do not want a low pass f i l t e r in the# frequency feedback of the SynchronousTwoPhasePLL c l a s s .#FREQ_LPF_RECU_COEFF = 0.0

#===============================================================================## SOME USEFUL LAMBDA FUNCTIONS##===============================================================================

# Scalar rec tangu lar to polar conversion#r e c t2Po la r = lambda x : ( abs (x ) , arctan2 (x . imag , x . r e a l ) )

# Polar to rectangu lar . The input i s a tup l e as produced by rect2Polar of the# form ( abs ( x ) , angle of x )#polar2Rect = lambda x : x [ 0 ] ∗ e ∗∗(x [ 1 ] ∗ 1 .0 j )

# Park transformation . The thetaNew2Old value i s the angle between the new axes and# the old axes .#parkXform = lambda x , thetaNew2Old : x ∗ e∗∗(−thetaNew2Old ∗ 1 .0 j )

# Clark Transformation (power var iant form ) . This accepts three input# var i a b l e s and converts them to two phase va lues in a s ta t ionary re ference# frame .#clarkXform = lambda xa , xb , xc : ( 2 .0 / 3 .0 ∗ ( xa − 0 .5 ∗ xb −0.5 ∗ xc ) +

((1 / sq r t ( 3 . 0 ) ∗ ( xb − xc ) ) ∗ 1 .0 j ) )

# Inverse Clark transform , Returns the three phase va lues as a tup l e .#invClarkXform = lambda x : ( x . r ea l , (−0.5 ∗ x . r e a l + sq r t ( 3 . 0 ) / 2 .0 ∗ x . imag ) ,\

(−0.5 ∗ x . r e a l − sq r t ( 3 . 0 ) / 2 .0 ∗ x . imag ) )

# Allows wrapping of an input va r i a b l e with a range of \pm \pi or 0 to 2\ pi# so that i t w i l l be in the range of \pm\pi#wrapScalar = lambda x : ( fmod (x , ( 2 ∗ pi ) ) − 2 .0 ∗ pi )\

i f ( x > pi ) else ( ( fmod (x , (2 ∗ pi ) ) + 2 ∗ pi ) i f ( x < −pi ) else x )

# Create an array form of the wrapping rout ine .#wrapArray = frompyfunc ( wrapScalar , 1 , 1)

#===============================================================================## Class dec lara t ions##===============================================================================


#===============================================================================## Class dec lara t ions##===============================================================================

class I n t e g r a t o r :""">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

INPUTS:

integratorGain −− the gain of the in t eg ra tor . This value has to be thed i g i t a l gain value .

in teg In i tVa lue −− the i n i t i a l va lue of the in t eg ra tor ( Defaul t = 0.0)

integLimits −− a tup l e containing the ( lower l imi t , upper l im i t ) ofthe in t eg ra tor . ( d e f au l t i s (0 .0 , 0 .0) which i s in t e rpre t ed as unl imited ) .

wrapping −− True means tha t the i n t e g r a l va lue w i l l be wrapped to tha t thevalue l i e s between \pm \pi , False means tha t no wrapping occurs .This i s app l i ed be fore the in t eg ra tor l im i t s .DEFAULT: False

<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

This i s a simple c a l l tha t implements a d i g i t a l in t eg ra tor . I t has beenimplemented as a c l a s s because a c l a s s re ta ins i t s past va lues andthere fore one does not have to worry about t h i s i s sue in the code .

"""def __init__( s e l f , integratorGain , i n t e g In i tVa lu e = 0 . 0 , \

in t egL imi t s = (0 . 0 , 0 . 0 ) , wrapping = False ) :s e l f . kiGain = integra torGa ins e l f . integValue = in t eg In i tVa lu es e l f . integLowerLimit = in t egL imi t s [ 0 ]s e l f . integUpperLimit = in t egL imi t s [ 1 ]s e l f . l imitReached = Falses e l f . wrapping = wrapping

# Allows wrapping of an input va r i a b l e with a range of \pm \pi or 0 to 2\ pi# so that i t w i l l be in the range of \pm\pi#s e l f . wrapScalar = lambda x : ( fmod (x , ( 2 ∗ pi ) ) − 2 .0 ∗ pi )\


#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−def i n t e g r a t o r ( s e l f , inputValue ) :

"""

INPUTS:

inputValue − input to be in tegra ted

OUTPUTS:

( integValue , l imitReached ) −− the output of the integrator , and aboolean ind i ca t ing tha t one of the in t eg ra tor l im i t s has been reached .

"""s e l f . integValue += s e l f . kiGain ∗ inputValue

i f s e l f . wrapping == True :s e l f . integValue = s e l f . wrapScalar ( s e l f . integValue )

s e l f . l imitReached = False

i f s e l f . integLowerLimit != 0 .0 or s e l f . integUpperLimit != 0 .0 :i f s e l f . integValue > s e l f . integUpperLimit :

s e l f . integValue = s e l f . integUpperLimits e l f . l imitReached = True

e l i f s e l f . integValue < s e l f . integLowerLimit :

G-5

s e l f . integValue = s e l f . integLowerLimits e l f . l imitReached = True

return ( s e l f . integValue , s e l f . l imitReached )

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .class Pi :

""">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

In i t i a l i s a t i o n :

kpGain −− Kp proport iona l gain

kiGain −− Ki in t e g r a l gain −− the d i g i t a l gain value .

in i t In tegVa lue −− i n i t i a l in t eg ra tor value ( d e f au l t s e t to 0.0)

integLimits −− a tup l e containing the ( negat ive l imi t , p o s i t i v e l im i t ) ofthe in t eg ra tor . ( d e f au l t i s (0 .0 , 0 .0) which i s in t e rpre t ed as unl imited .

Returns :

( piOutput , iPart , l imitReached ) −− Tuple containing the output of theaddi t ion of the P and I parts , the i n t e g r a l output part , and a booleanind i ca t ing i f the in t eg ra tor l im i t has been reached .<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

This c l a s s implements the PI part of a PI con t r o l l e r . The in t eg ra tor hasl im i t s to the value tha t i t w i l l i n t e g ra t e to . The l im i t s do not have to besymmetrical about zero .

"""def __init__( s e l f , kpGain , kiGain , i n i t I n t e gVa lu e = 0 . 0 , i n t egL imi t s = (0 . 0 , 0 . 0 ) ) :

s e l f . kpGain = kpGains e l f . kiGain = kiGains e l f . intValue = in i t I n t egVa lu es e l f . in tegNegat iveL imit = in t egL imi t s [ 0 ]s e l f . i n t e gPo s i t i v eL im i t = in t egL imi t s [ 1 ]s e l f . l imitReached = Falses e l f . outputValue = in i t I n t egVa lu es e l f . i n t e g r a t o r = In t e g r a t o r ( s e l f . kiGain , in i t In t egVa lue , i n t egL imi t s )

#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−def pi ( s e l f , inputValue ) :

returnTuple = s e l f . i n t e g r a t o r . i n t e g r a t o r ( inputValue )s e l f . intValue = returnTuple [ 0 ]s e l f . l imitReached = returnTuple [ 1 ]

s e l f . outputValue = s e l f . intValue + s e l f . kpGain ∗ inputValue

# Now make sure tha t the output i s l imi t ed as we l l . Note tha t t h i s can# occur even though the in t eg ra tor i t s e l f in not in l im i t .#i f s e l f . in tegNegat iveL imit != 0 .0 or s e l f . i n t e gPo s i t i v eL im i t != 0 .0 :

i f s e l f . outputValue > s e l f . i n t e gPo s i t i v eL im i t :s e l f . outputValue = s e l f . i n t e gPo s i t i v eL im i t

e l i f s e l f . outputValue < s e l f . in tegNegat iveL imit :s e l f . outputValue = s e l f . in tegNegat iveL imit

return ( s e l f . outputValue , s e l f . intValue , s e l f . l imitReached )

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

class Lpf1stOrder :""">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>In i t i a l i s a t i o n :


( recurs iveCoef f , nonrecursiveCoef f ) −− t up l e containing the recurs i ve andnon recurs i ve c o e f f i c i e n t s .

<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

Returns :

The f i l t e r value of the input quant i ty .

"""def __init__( s e l f , f i l t e r C o e f f s ) :

s e l f . f i l t e r C o e f f s = f i l t e r C o e f f ss e l f . pastOutputs = 0

#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−def l p f ( s e l f , inputQuantity ) :

"""Inputs :

inputQuantity −− rea l or complex number the i s the input to thef i l t e r .

Returns :

The f i l t e r e d input value .

"""s e l f . pastOutputs = s e l f . f i l t e r C o e f f s [ 0 ] ∗ s e l f . pastOutputs + \

s e l f . f i l t e r C o e f f s [ 1 ] ∗ inputQuantity

return s e l f . pastOutputs

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .class SinglePhaseEPLL :

""">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

INITIALISATION INPUTS:

ampFil terCoeffs −− ( recurs i ve co e f f i c i en t , non−recurs i ve c o e f f i c i e n t ) forthe amplitude low pass f i l t e r .

phaseFi l t e rCoe f f s −− ( recurs i ve co e f f i c i en t , non−recurs i ve c o e f f i c i e n t )for the phase feedback low pass f i l t e r .

piGains −− ( kp gain , k i gain ) for the PI feedback con t r o l l e r

ampIntegGain −− continuous time gain of the in t eg ra tor using in theamplitude est imation sec t ion of the con t r o l l e r .

vcoCentreFreq −− centre frequency of the VCO express ion in Hertz .

samplesPerCentreFreqPeriod −− number of samples in one cyc l e of a waveformwith the period corresponding to the vcoCentreFreq .

p i In tegra torLimi t s −− ( lower in t eg ra tor l imi t , upper in t eg ra tor l im i t ) .The lower and upper l im i t s of the in t eg ra tor . Defaul t i s (0 .0 , 0 .0) whichmeans tha t there are no in t eg ra tor l im i t s .

estAmpPhase −− ( est imated i n i t i a l amplitude , est imated i n i t i a l phase ) .tup l e containing va lues of the i n i t i a l est imated amplitude and phase ofthe waveform . The de f au l t va lue i s (0 .0 , 0 . 0 ) .

<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

DESCRIPTION

This c l a s s d i g i t a l l y implements the Enhance Phase Locked Loop as proposedby Karimi−Ghartemani . This var iant of the EPLL contains two lp f , onefeed ing data into the PI block , and the other in the path of the i n t e g r a lva lue in the amplitude est imation part of the EPLL."""

G-7

def __init__( s e l f , ampFi l terCoef f s , pha s eF i l t e rCoe f f s , piGains , ampIntegGain ,vcoCentreFreq , samplesPerCentreFreqPeriod ,p i I n t e g r a t o rL im i t s = (0 . 0 , 0 . 0 ) , estAmpPhase = (0 . 0 , 0 . 0 ) ) :

# Create the low pass f i l t e r s for the amplitude and phase feedback paths .#s e l f . ampLpf = Lpf1stOrder ( ampFi l t e rCoe f f s )s e l f . phaseLpf = Lpf1stOrder ( pha s eF i l t e rCoe f f s )

# The amplitude feedback gain i s in an analogue form . For the d i g i t a l# vers ion of the in t eg ra tor to have the same e f f e c t i v e gain have to# mul t ip ly the gain by the time in t e r v a l between the samples .#s e l f . ampIntegGain = ampIntegGain ∗ 1 .0 / ( vcoCentreFreq ∗ samplesPerCentreFreqPeriod )

# Gain of the pure in t eg ra tor to generate the phase from the frequency error and the# centre frequency .#s e l f . phaseFeedbackIntegGain = 1 .0 / ( vcoCentreFreq ∗ samplesPerCentreFreqPeriod )

# Now f i n a l l y s ca l e the pi i n t e g r a l gain and save the proport iona l gain .#s e l f . p i IntegGain = piGains [ 1 ] ∗ 1 .0 / ( vcoCentreFreq ∗ samplesPerCentreFreqPeriod )s e l f . piPropGain = piGains [ 0 ]

# Now create the PI part of the con t r o l l e r . Note tha t under t h i s i n s t an t i a t i on# i t has been created with no in t e g r a l l im i t s .#s e l f . piFreqFdbk = Pi ( s e l f . piPropGain , s e l f . p i IntegGain )

# Now form the amplitude in t eg ra tor#s e l f . ampInteg = In t eg r a t o r ( s e l f . ampIntegGain , i n t egL imi t s = p i I n t e g r a t o rL im i t s )

# Form the angular frequency in t eg ra tor#s e l f . phaseInteg = In t e g r a t o r ( s e l f . phaseFeedbackIntegGain , \

0 . 0 , ( 0 . 0 , 0 . 0 ) , wrapping = True )

# Now def ine some var i a b l e s used in the sof tware .#s e l f . waveformErr = 0 .0s e l f . estPhase = estAmpPhase [ 1 ]s e l f . estAmp = estAmpPhase [ 0 ]s e l f . s inePh i = s in ( s e l f . estPhase )s e l f . cosPhi = cos ( s e l f . estPhase )s e l f . estWaveform = s e l f . estAmp ∗ s e l f . cosPhis e l f . vcoCentreOmega = 2 .0 ∗ pi ∗ vcoCentreFreqs e l f . f r e qCo r r e c t i on = 0 .0

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .def eP l l ( s e l f , i nputS igna l ) :

""">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>INPUTS:

inputSigna l −− the current sample of the waveform being processed .

OUTPUTS:

( estPhase , estAmp , estwaveform , waveformErr ) −− a tup l e containing theva lues ind ica ted .

<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

This i s the ac tua l EPLL code i t s e l f . This implements the Karimi−Ghartemanialgori thm with the addi t ion of low pass f i l t e r s and po s s i b l e l im i t s onthe frequency PI in t eg ra tor ( depending on the i n i t i a l i s a t i o n of thec l a s s ) .

The code i s d iv ided into three sec t ions −− the phase de tec tor sect ion ,


which inc ludes the amplitude estimation , the PI frequency error and lowpass f i l t e r sect ion , and f i n a l l y the vo l t age con t ro l l e d o s c i l l a t o r sec t ion .I w i l l attempt the c l e a r l y i d en t i f y these as the code i s developed . Notetha t these sec t ion names fo l l ow those used in the o r i g i na l Karimi−Ghartemanipapers wri t ten on t h i s ."""# This i s the code for the phase de tec tor and amplitude est imation sec t ion# of the system .#s e l f . waveformErr = inputS igna l − s e l f . estWaveform

inputToIntegrator = s e l f . waveformErr ∗ s e l f . cosPhi

( s e l f . estAmp , l imitReached ) = s e l f . ampInteg . i n t e g r a t o r ( inputToIntegrator )

i f l imitReached :print ( " In t e g r a t o r l im i t reached in EPLL Amplitude i n t e g r a t o r " )

# Fi l t e r the amplitude est imate#s e l f . estAmp = s e l f . ampLpf . l p f ( s e l f . estAmp)

# Now form the new est imate of the output waveform for t h i s i t e r a t i on of# the algorithm .#s e l f . estWaveform = s e l f . estAmp ∗ s e l f . cosPhi

# Now feed the error into the PI con t r o l l e r and VCO#inputToPi = s e l f . waveformErr ∗ s e l f . s inePh i

( inputToVco , s e l f . f r eqCor r ec t i on , l imitReached ) = \s e l f . piFreqFdbk . p i ( s e l f . phaseLpf . l p f ( inputToPi ) )

i f l imitReached :print ( "Limit reached in the EPLL phase feedback i n t e g r a t o r " )

# (inputToVco , freqCorrect ion , l imitReached ) = s e l f . piFreqFdbk . pi ( inputToPi )

# Now feed through to the VCO#( s e l f . estPhase , l imitReached ) = s e l f . phaseInteg . i n t e g r a t o r ( inputToVco + s e l f . vcoCentreOmega )

i f l imitReached :print ( "Limit reached in the EPLL VCO in t e g r a t o r " )

s e l f . s inePh i = s in ( s e l f . estPhase )s e l f . cosPhi = cos ( s e l f . estPhase )

return ( s e l f . estPhase , s e l f . estAmp , s e l f . estWaveform , s e l f . waveformErr )

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .class TwoPhasePLL :

""">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>Class i n i t i a l i s a t i o n :

f bF i l t e rCoe f f s −− t up l e containing the two feedback f i l t e r c o e f f i c i en t s ,with the order in the tup l e being ( recurs i ve co e f f i c i en t , non−recurs i vec o e f f i c i e n t ) .

piGains −− t up l e containing the two PI con t r o l l e r gains , with the order inthe tup l e being ( propor t iona l gains , i n t e g r a l gain ) .

fundamentalFreq −− the est imated FUNDAMENTAL frequency . Frequency i sexpressed in Hz . NOTE THAT THIS IS THE FUNDAMENTAL FREQUENCY, AND IFHARMONCS ARE BEING CONSIDERED THEN SEE BELOW FOR OTHER PARAMETER.

samplesPerFundCycle −− the number of samples per cyc l e of the est imatedfundamental frequency .

G-9

harmonicNumberToLockTo −− the harmonic of the fundamental to lock to . Thisharmonic number i s used to determine the centre frequency of the VCO.DEFAULT VALUE IS 1 ( the fundamental ) .

Returns :

tup l e − ( est imated input phase ( radians ) , frequency correc t ion (Hz))

<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

This c l a s s implements a bas ic two phase phase locked loop (PLL) . Theoutput of the PLL i s the phase angle of the input and the frequency errorterm fed around the PLL to correc t for errors in the phase . This phaselocked loop i s implemented in a d i g i t a l form so that the phase de tec tor i sa "pure" phase de tec tor −− i . e . i t does ∗NOT∗ use a mu l t i p l i e r and f i l t e rto de t ec t the phase error , but ins tead uses true phase d i f f e r ence . Thisapproach means tha t 2∗ pi wrap around must be appropriate handled .

The use of the true phase error approach means tha t in p r inc i p l e therewould not be ac components f lowing through the feedback path of the PLL.However , there w i l l be phase noise in t h i s path , and for t h i s reason a LPFi s a l so in the phase error feedback .

The other i n t e r e s t i n g part of the PLL i s tha t i t incorporates a PIcon t r o l l e r in the phase feedback path . This means tha t the phase lockedloop i s capable of l ock ing onto the phase of the input waveform with azero phase error .

The centre frequency passed into the c l a s s i s the fundamental frequency ofthe system . However , the PLL may be used to ex t rac t harmonic f r requenc ie s ofthe fundamental , and there fore the harmonic number i s passed in .

The methods ins ide t h i s c l a s s are designed to be ca l l e d from a loop . Thisi s because the PLLs are used in a feedback s t ruc ture tha t requ i res theinput of knowledge from other PLLs .

Usage :To use the c l a s s c a l l the method p l l in s ide a loop . The va lues passed arethe instantaneous va lues of a two phase var iab le , passed in as a complexnumber .

"""

#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

def __init__( s e l f , f bF i l t e rCo e f f s , piGains , fundamentalFreq , samplesPerFundCycle ,harmonicNumberToLockTo = 1) :

s e l f . f bF i l t e rC o e f f s = f bF i l t e rC o e f f ss e l f . piGains = piGainss e l f . fundamentalFreq = fundamentalFreqs e l f . fundamentalOmega = 2 .0 ∗ pi ∗ fundamentalFreqs e l f . in tegratorGa inFactor = 1 .0 / ( s e l f . fundamentalFreq ∗ samplesPerFundCycle )s e l f . p i In teg ra to rGa in = s e l f . piGains [ 1 ] ∗ s e l f . in tegratorGa inFactors e l f . omegaCorrection = 0 .0s e l f . e s tS igna lPhase = 0 .0s e l f . f i l t e r edFeedback = 0 .0s e l f . p i I n t eg ra lVa lue = 0 .0s e l f . p i In teg ra lVa luePrev = 0 .0s e l f . phaseError = 0 .0s e l f . pha s eF i l t e r = Lpf1stOrder ( f bF i l t e rC o e f f s )s e l f . harmonicNumber = harmonicNumberToLockTos e l f . piReturn = 0 .0

# Now ca l cu l a t e the centre frequency of the VCO. Note tha t the PLL i s# being used to ex t rac t phase of a two phase representa t ion of a se t# of three phase waveforms . Therefore we need to consider the f a c t tha t# higher order harmonics of the fundamental may cons t i t u t e a negat ive# sequence −− i . e . the space vector ro ta t e s in the oppos i te d i r ec t i on# as compared to the fundamental .## The algoirthm to ca l cu l a t e the phase sequence i s based on# ca l cu l a t i n g the e f f e c t i v e phase of the harmonic waveform for each of# the phase back at the zero angle . For example , for the 5 th harmonic


# there i s 72degs for a complete period (on the o r i g i na l the ta ax i s# for the fundamental ) . The ’a ’ phase 5 th harmonic s t a r t s as zero# degrees at the zero degrees on the fundamental the ta ax i s . The ’ b ’# phase harmonic s t a r t s at an o f f s e t zero degrees at 120 degrees on# the fundamental the ta ax i s . Since a period of the 5 th harmonic i s 72# degs , then there are 1 2/3 rds periods of the 5 th harmonic in 120# degs of the fundamental . Therefore i f one s l i d e s back the waveform# of the 5 th harmonic tha t s t a r t s at the ’ b ’ phase ( i . e . 120 degs )# then there w i l l be 1 2/3 rds cyc l e s to get back to zero degrees . The# 2/3 rds part of t h i s i s the important part , in tha t i t means tha t# t h i s ’ b ’ phase harmonic looks l i k e a waveform that i s s h i f t e d by 120# degs . S imi lar l y the ’ c ’ phase o f f s e t 5 th harmonic w i l l have 3 1/3rd# cyc l e s of the 5 th harmonic to get back to zero degrees . The net# r e s u l t i s tha t the apparent phase sequence of the 5 th harmonic i s# the reverse of the fundamental .## I f a s imi lar s t ra t egy i s app l i ed to the 7 th harmonic , then we have 2# 1/3 cyc l e s per 120 degs . The 1/3rd remainder part means tha t the ’ b ’# phase a l i gned vers ion w i l l be in the same phase r e l a t i on sh i p as the# normal po s i t i v e phase sequence .## The genera l ru l e there fo re i s tha t i f remainder (120/( degs for# harmonic cyc l e )) = 1/3rd then phase sequence i s pos i t i v e , e l s e i f# 2/3 rds then negat ive .## There are i s sue s with doing the comparisions with t h i s due to the# inaccurate representa t ion of numbers in computers .#

i f round (modf (120 .0 / (360 .0 / s e l f . harmonicNumber ) ) [ 0 ] ) == 1.0 :# The phase sequence i s negat ive#s e l f . centreOmega = − s e l f . harmonicNumber ∗ s e l f . fundamentalOmega

else :# Phase sequence po s i t i v e#s e l f . centreOmega = s e l f . harmonicNumber ∗ s e l f . fundamentalOmega

# A couple of u t i l i t y rout ines tha t are used . They are carr ied here so tha t# the c l a s s i s s e l f contained .



# Scalar rec tangu lar to polar conversion#s e l f . r e c t2Po la r = lambda x : ( abs (x ) , arctan2 ( imag (x ) , r e a l ( x ) ) )

# Ins tan t i a t e a PI c l a s s#s e l f . p i = Pi ( s e l f . piGains [ 0 ] , s e l f . p i In teg ra to rGa in )

# Ins tan t i a t e the frequency to phase in t eg ra tor#s e l f . f r e q I n t e g r a t o r = In t e g r a t o r ( s e l f . integratorGainFactor , \

0 . 0 , ( 0 . 0 , 0 . 0 ) , wrapping = True )

#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

def p l l ( s e l f , i nputS igna l ) :

"""The PLL code .

Inputs :inputSigna l − a complex number ( two phase ) representa t ion ofthe s i gna l .

Returns : ( s i gna l phase , centre frequency error )

G-11

"""

s e l f . phaseError = s e l f . wrapScalar ( s e l f . r e c t2Po la r ( inputS igna l ) [ 1 ] \− s e l f . e s tS igna lPhase )

## Now low pass f i l t e r the phase error## HAVE COMMENTED OUT THE FILTER FOR THE MOMENT. ADDED LINE BELOW TO# COPY THE VALUES IN THE s e l f . f i l t e redFeedback# s e l f . f i l t e r edFeedback = s e l f . phaseFi l t e r . l p f ( s e l f . phaseError )s e l f . f i l t e r edFeedback = s e l f . phaseError

# Apply a PI con t r o l l e r to t h i s f i l t e r e d error

s e l f . piReturn = s e l f . p i . p i ( s e l f . f i l t e r edFeedback )s e l f . e s tS igna lPhase = s e l f . f r e q I n t e g r a t o r . i n t e g r a t o r ( s e l f . piReturn [ 0 ]

+ s e l f . centreOmega ) [ 0 ]

return ( s e l f . e s tS igna lPhase , s e l f . piReturn [ 1 ] / ( 2 . 0 ∗ pi ) )

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .class SynchronousAmplitudeExtraction :

"""I n i t i a l i s a t i o n :

ampFil terCoeffs => ( recurs i ve coe f f , non−recurs i ve coe f f ) : A tup l econtaining the f i l t e r c o e f f i c i e n t s for the 1 s t order low pass f i l t e r usedto f i l t e r the output of the synchronous demodulation .

Descript ion :

This c l a s s e x t rac t s the amplitude of a two phase quant i ty using asynchronous frame conversion and f i l t e r i n g technique . The main method ofthe c l a s s i s " fi l teredAmp ". The complex value to be f i l t e r e d and the angleof the synchronous frame are passed into the rout ine . I t i s designed to beca l l e d on each pass through a process ing loop , each time passing in acomplex number tha t represents a two phase s ta t ionary frame representa t ionof a three phase value . The value i s then converted to a synchronouslyro ta t ing frame , and then the DC component i s f i l t e r e d out .

"""def __init__( s e l f , ampFi l t e rCoe f f s ) :

s e l f . ampFi l t e rCoe f f s = ampFi l t e rCoe f f s# Create the low pass f i l t e r to be used .s e l f . ampFilter = Lpf1stOrder ( ampFi l t e rCoe f f s )

#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−def f i l teredAmp ( s e l f , twoPhaseValue , thetaFrameAngle ) :

"""Input :A complex number represent ing a s ta t ionary frame two phase value .

thetaFrameAngle − angle between the new and the o ld frame .

Returns :

Tuple −− ( f i l t e r complex dq value , f i l t e r e d amplitude )

"""# Convert the two phase value from the s ta t ionary frame to the# the ta angle frame .#syncFrameValue = parkXform ( twoPhaseValue , thetaFrameAngle )

# Now f i l t e r the value .#f i l t e redComplexValue = s e l f . ampFilter . l p f ( syncFrameValue )


return ( f i l teredComplexValue , abs ( f i l t e redComplexValue ) )

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .class AkagiFeedForward :

"""

INITIALISATION

Tuple −− ( recurs i ve coe f f , non−recurs i ve coe f f ) . This tup l e contains thec o e f f i c i e n t s for the low pass f i l t e r e d used in the feedforward demodulation .This c o e f f i c i e n t s are for a simple low pass 1 s t order f i l t e r tha t i s meantto f i l t e r out the DC component of the waveform .

DESCRIPTION

This c l a s s implements a synchronously ro ta t ing frame f i l t e r for a par t i cu l a rharmonic . This technique for harmonic ex t rac t ion i s commonly used , and hasbeen used e x t en s i v e l y by Akagi for h i s ac t i v e f i l t e r s . Hence the name of thec l a s s .

Refer to the methods of the c l a s s to see what they do .

"""def __init__( s e l f , l p F i l t e rC o e f f s ) :

# Create an instance of the SynchronousAmplitudeExtraction c l a s s .#s e l f . dq5thHarmonic = SynchronousAmplitudeExtraction ( l pF i l t e rC o e f f s )s e l f . dqWaveform = ze ro s ( numPoints , complex )s e l f . i = 0 .0

#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−def __rotatingDqComponents ( s e l f , alphaBetaComponents , frameAngle ) :

"""

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

PARAMETERS

alphaBetaComponents −− complex number representa t ion the two phases ta t ionary frame components of a harmonic r ich waveform .

frameAngle −− a rea l number represent ing the angle of the ro ta t ingframe r e l a t i v e to the s ta t ionary frame in radians .

RETURNS

Complex number represent ing the dq components of the harmonic in thealpha + jbe ta components tha t are synchronised with the ro ta t ion of theframe .

"""return s e l f . dq5thHarmonic . f i l teredAmp ( alphaBetaComponents , frameAngle )

#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−def harmonicComponent ( s e l f , alphaBetaComponents , frameAngle ) :

"""PARAMETERS

alphaBetaComponents −− complex number alpha + ( beta j ) whichrepresents the two phase s ta t ionary frame components of a harmonic r ichwaveform .

frameAngle −− a rea l number represent ing the angle of the ro ta t ingframe r e l a t i v e to the s ta t ionary frame in radians .

RETURNS

G-13

Complex number represent ing dq component sample of the harmonicwaveform whose frequency corresponds to the rate of change of theframeAngle .

"""s e l f . dqWaveform [ s e l f . i ] = s e l f . __rotatingDqComponents ( alphaBetaComponents ,

frameAngle ) [ 0 ]

# Now convert the value back to a s ta t ionary frame and return#temp = parkXform ( s e l f . dqWaveform [ s e l f . i ] , −frameAngle )s e l f . i += 1return temp

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .class SynchronousTwoPhasePLL :

"""

INITIALISATION

Ki −− the i n t e g r a l gain of the feedback PI −− the analogue value .

Kp −− the propor t iona l gain of the feedback PI

fundamentalFreq −− the est imated FUNDAMENTAL frequency . Frequency i sexpressed in Hz . NOTE THAT THIS IS THE FUNDAMENTAL FREQUENCY, AND IFHARMONCS ARE BEING CONSIDERED THEN SEE BELOW FOR OTHER PARAMETER.

samplesPerFundCycle −− the number of samples per cyc l e of the est imatedfundamental frequency .

f reqLpfCoef f −− a tup l e containing the recurs i ve and non−recurs i ve c o e f f i c i e n t sfor the low pass f i l t e r on the frequency error term .DEFAULT = (0.0 , 1 .0) => f i l t e r not ac t i v e

harmonicNumberToLockTo −− the harmonic of the fundamental to lock to . Thisharmonic number i s used to determine the centre frequency of the VCO.DEFAULT VALUE IS 1 ( the fundamental ) .

i n i t i a lPhase −− an est imate of the i n i t i a l phase of the d ax i s .DEFAULT VALUE i s 0 .0 .

DESCRIPTION

This c l a s s implements a c l a s s i c a l three phase synchronous PLL. The PLL i sb a s i c a l l y the one pub l i shed in a paper by Kaura and Blasko in 1997.

"""def __init__( s e l f , Ki , Kp, fundamentalFreq , samplesPerFundCycle ,

f r eqLp fCoe f f = ( 0 . 0 , 1 . 0 ) , harmonicNumberToLockTo = 1 ,i n i t i a l Ph a s e = 0 . 0 ) :

s e l f . fundamentalFreq = fundamentalFreqs e l f . harmonicNumber = harmonicNumberToLockTo

# Calcu late the centre frequency in rads/ sec#s e l f . fundamentalOmega = 2 .0 ∗ pi ∗ s e l f . fundamentalFreq

# Now ca l cu l a t e the centre frequency of the VCO. Note tha t the PLL i s# being used to ex t rac t phase of a two phase representa t ion of a se t# of three phase waveforms . Therefore we need to consider the f a c t tha t# higher order harmonics of the fundamental may cons t i t u t e a negat ive# sequence −− i . e . the space vector ro ta t e s in the oppos i te d i r ec t i on# as compared to the fundamental .


## The algori thm to ca l cu l a t e the phase sequence i s based on# ca l cu l a t i n g the e f f e c t i v e phase of the harmonic waveform for each of# the phase back at the zero angle . For example , for the 5 th harmonic# there i s 72degs for a complete period (on the o r i g i na l the ta ax i s# for the fundamental ) . The ’a ’ phase 5 th harmonic s t a r t s as zero# degrees at the zero degrees on the fundamental the ta ax i s . The ’ b ’# phase harmonic s t a r t s at an o f f s e t zero degrees at 120 degrees on# the fundamental the ta ax i s . Since a period of the 5 th harmonic i s 72# degs , then there are 1 2/3 rds periods of the 5 th harmonic in 120# degs of the fundamental . Therefore i f one s l i d e s back the waveform# of the 5 th harmonic tha t s t a r t s at the ’ b ’ phase ( i . e . 120 degs )# then there w i l l be 1 2/3 rds cyc l e s to get back to zero degrees . The# 2/3 rds part of t h i s i s the important part , in tha t i t means tha t# t h i s ’ b ’ phase harmonic looks l i k e a waveform that i s s h i f t e d by 120# degs . S imi lar l y the ’ c ’ phase o f f s e t 5 th harmonic w i l l have 3 1/3rd# cyc l e s of the 5 th harmonic to get back to zero degrees . The net# r e s u l t i s tha t the apparent phase sequence of the 5 th harmonic i s# the reverse of the fundamental .## I f a s imi lar s t ra t egy i s app l i ed to the 7 th harmonic , then we have 2# 1/3 cyc l e s per 120 degs . The 1/3rd remainder part means tha t the ’ b ’# phase a l i gned vers ion w i l l be in the same phase r e l a t i on sh i p as the# normal po s i t i v e phase sequence .## The genera l ru l e there fo re i s tha t i f remainder (120/( degs for# harmonic cyc l e )) = 1/3rd then phase sequence i s pos i t i v e , e l s e i f# 2/3 rds then negat ive .## There are i s sue s with doing the comparisions with t h i s due to the# inaccurate representa t ion of numbers in computers .#

i f round (modf (120 .0 / (360 .0 / s e l f . harmonicNumber ) ) [ 0 ] ) == 1.0 :# The phase sequence i s negat ive#s e l f . centreOmega = − s e l f . harmonicNumber ∗ s e l f . fundamentalOmega

else :# Phase sequence po s i t i v e#s e l f . centreOmega = s e l f . harmonicNumber ∗ s e l f . fundamentalOmega

# A couple of u t i l i t y rout ines tha t are used . They are carr ied here so tha t# the c l a s s i s s e l f contained .



# Scalar rec tangu lar to polar conversion#s e l f . r e c t2Po la r = lambda x : ( abs (x ) , arctan2 (x . imag , x . r e a l ) )

# Polar to rectangu lar . the input i s a tup l e as produced by rect2Polar of the# form ( abs ( x ) , angle of x )#s e l f . po lar2Rect = lambda x : x [ 0 ] ∗ e ∗∗(x [ 1 ] ∗ 1 .0 j )

# Park transformation . The thetaNew2Old value i s the angle between the new axes and# the old axes .#s e l f . parkXform = lambda x , thetaNew2Old : x ∗ e∗∗(−thetaNew2Old ∗ 1 .0 j )

# Clark Transformation (power var iant form ) . This accepts three input# var i a b l e s and converts them to two phase va lues in a s ta t ionary re ference# frame .#s e l f . clarkXform = lambda xa , xb , xc : ( 2 .0 / 3 .0 ∗ ( xa − 0 .5 ∗ xb −0.5\

∗ xc ) + ((1 / sq r t ( 3 . 0 ) ∗ ( xb − xc ) ) ∗ 1 .0 j ) )

# Inverse Clark transform , Returns the three phase va lues as a tup l e .

G-15

#s e l f . invClarkXform = lambda x : ( x . r ea l , (−0.5 ∗ x . r e a l + sq r t ( 3 . 0 ) / 2 .0 ∗ x . imag ) ,\

(−0.5 ∗ x . r e a l − s q r t ( 3 . 0 ) / 2 .0 ∗ x . imag ) )

# Create an instance of the PI con t r o l l e r used in the feedback path#s e l f . fdBackPi = Pi (Kp, Ki / ( s e l f . fundamentalFreq ∗ samplesPerFundCycle ) )

# Create an instance of a s i n g l e po le low pass f i l t e r to be used to# f i l t e r o s c i l l a t i o n s out of the frequency .#

s e l f . freqLPF = Lpf1stOrder ( f r eqLp fCoe f f )

# Create an instance of the frequency in t eg ra tor#s e l f . f r e q I n t e g = In t e g r a t o r ( 1 . 0 / ( s e l f . fundamentalFreq ∗ samplesPerFundCycle ) ,\

i n i t i a lPha s e , ( 0 . 0 , 0 . 0 ) , wrapping = True )

# Use to s tore the phase of the input .#s e l f . phase = i n i t i a l Ph a s e

# Used to s tore the frequency error#s e l f . f r eqEr r = 0 .0

# The frequency est imate#s e l f . f r eqEs t = 0 .0

#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−def p l l ( s e l f , ∗ args ) :

"""

This method implements to core of the three phase synchronous PLL. There ference value for the d ax i s i s f i x ed at zero ( by the feedback ) ,which means tha t the ac tua l phase angle of the waveform i s 90 degreesfrom th i s −− i e . the q ax i s a l i gn s with the synchronous frame .

Inputs : Two phase s ta t ionary frame quant i ty in a tup l e as xd and xq , ORthree phase quant i ty in a tup l e as xa , xb , xc

Returns : Tuple containing :− [ 0 ] three phase quan t i t i e s as a tup l e −− xa , xb , xc ;− [ 1 ] phase : the phase of the space vector ;− [ 2 ] two phase synchronous frame value as a complex value ;

NB: The phase va lues are normalised −− peak value i s 1 .0 .− [ 3 ] the est imated frequency error between the centre frequency and

the ac tua l frequency

"""

i f l en ( args ) == 2 :twoPhaseValues = args [ 0 ] + args [ 1 ] ∗ 1 . 0 j

else :# Fi r s t l y convert to a two phase rectangu lar form using the Clark# transformation#twoPhaseValues = s e l f . clarkXform ( args [ 0 ] , a rgs [ 1 ] , a rgs [ 2 ] )

# Now carry out the park transformation to the est imated the ta ax i s .#syncTwoPhaseValue = s e l f . parkXform ( twoPhaseValues , s e l f . phase )

# Get the d ax i s component as the feedback value#fdbckErr = −syncTwoPhaseValue . r e a l

# Feed the error into the PI con t r o l l e r and then f i l t e r i t .#s e l f . f r eqEr r = s e l f . freqLPF . l p f ( s e l f . fdBackPi . p i ( fdbckErr ) [ 0 ] )


# Now add the centre frequency ( a l so known as the feedforward component )#s e l f . f r eqEs t = s e l f . f r eqEr r + s e l f . centreOmega

# Now in t eg ra t e the frequency est imate to ge t the est imated phase . Note# that t h i s in t eg ra tor w i l l a l so carry out −pi < Theta <= pi wrapping .#s e l f . phase = s e l f . f r e q I n t e g . i n t e g r a t o r ( s e l f . f r eqEs t ) [ 0 ]

# Now convert the two phase va r i a b l e s from the synchronous frame back# to a three phase s ta t ionary frame .#twoPhaseValues = s e l f . parkXform ( syncTwoPhaseValue , − s e l f . phase )threePhaseValues = s e l f . invClarkXform ( twoPhaseValues )

return ( threePhaseValues , s e l f . phase , syncTwoPhaseValue , s e l f . f r eqEr r )

#@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@## MAIN PROGRAM START##@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

i f __name__ == ’__main__ ’ :

#===========================================================================## Derived Variable De f in i t i ons##===========================================================================

omega = 2 .0 ∗ pi ∗ FREQ # Fundamental angular frequency of the supplyfund_cycles = 100 .0 # Number of cyc l e s of frequency for s imulat ion to run

# Set up for 5kHz sampling −− i . e . 100 samples per 2 ∗ pi radians of the 50Hz# waveform .#samplesPerCycle = SAMPLING_FREQ / FREQ # Samples per cyc l e of FREQ Hz waveformdeltaT = 1.0 / (FREQ ∗ samplesPerCycle ) # time seperaton of samplesdeltaTheta = 2 ∗ pi / samplesPerCycle # separat ion of samples at 50Hz

# Now we want to s imulat ion a change in the frequency of the input waveform# at about the halfway point through the array . This change in frequency# i s simulated in t h i s program by e f f e c t i v e l y changing the de l t a the ta of# the the ta array . This can be achieved by using a sca l ing fac tor to# mul t ip l e a subse t of the array by the fac tor . This f ac tor i s represented# as a r e l a t i v e value of the o r i g i na l de l taTheta value .#re lat iveFreqChange = FREQ_ALTERED / FREQ

deltaThetaAltered = 2 ∗ pi ∗ re lat iveFreqChange / samplesPerCycle

# Separation of samples in radians for the nominal frequency of 50Hz with# 100 samples per period of the waveform . Note tha t the i n i t i a l array i s# for the i n i t i a l frequency FREQ and only for ha l f the t o t a l number of cyc l e s .# A second array i s formed at the new a l t e r ed frequency − FREQ_ALTERED, and# th i s array i s then appended to the f i r s t one to form the complete the ta# array#thetaFreq = [ x ∗ deltaTheta for x in range ( i n t ( fund_cycles / 2 ∗ samplesPerCycle ) ) ]

# The fo l l ow ing l i s t formation i s a l i t t l e t r i c k y to ensure tha t there i s a# correc t t r ans i t i on from the i n i t i a l frequency waveform to the new frequency# waveform .#thetaFreqAltered = [ x ∗ de l taThetaAltered + thetaFreq [ l en ( thetaFreq ) − 1 ] for x in

range (1 , i n t ( fund_cycles / 2 ∗ samplesPerCycle ) − 1 , 1 ) ]thetaFreq . extend ( thetaFreqAltered )

G-17

theta = array ( thetaFreq )

# Have to change the type s ince the r e s u l t o f the wrapArray i s of dtype# ob j ec t which cannot be used in the s ine and cosine funct ions tha t f o l l ow .#theta = wrapArray ( fmod ( theta , 2 ∗ pi ) ) . astype ( f l o a t )

# Get the dimensions of the array so tha t the data s torage can be def ined# and loop var i ab l e def ined .#numPoints = theta . shape [ 0 ]

## Note tha t the waveforms below are as generated in the book# "Grid Converters for Photovo l ta ic and Wind Power Systems" by# Teodorescu , Liserre and Rodriguez .## The waveforms below are assuming tha t we have the quadrature waveforms .# However in the case of a s i n g l e phase system , the v_beta waveform would# be generated by an in−quadrature waveform generator . There would normally# be a t rans i en t assoc ia ted with the generation of t h i s waveform .#i f not HARMONIC_POLUTION :

v_alpha = X1 ∗ s i n ( theta )v_beta = −X1 ∗ cos ( theta )

else :# Harmonic po lu t ionv_alpha = X1 ∗ s i n ( theta ) + XH ∗ s i n (HARMONIC_NUM ∗ theta )v_beta = −(X1 ∗ cos ( theta ) + XH ∗ cos (HARMONIC_NUM ∗ theta ) )

stationaryFrameComplexValue = v_alpha + v_beta ∗1 .0 j

# ∗∗∗∗ DATA STORAGE ARRAYS ∗∗∗∗## Now se t up some storage arrays for various parameters tha t are ca l cu l a t ed# and may need to be subsequent ly p l o t t e d .#feedback_f = ze ro s ( numPoints )phase_err_f = ze ro s ( numPoints )est_fundamental_phase = ze ro s ( numPoints )

int_feedback_f = ze ro s ( numPoints )pi_output_f = ze ro s ( numPoints )int_pi_f = ze ro s ( numPoints )

realImagComponents = ze ro s ( numPoints , complex )estTheta = ze ro s ( numPoints )estFreqErr = ze ro s ( numPoints )estSpaceVectorPhase = ze ro s ( numPoints )amplReturnValue = ze ro s ( numPoints , tup l e )

# Low pass f i l t e r c o e f f i c i e n t s for the l p f used in the two phase PLL.#f r e qLp fCoe f f s = (FREQ_LPF_RECU_COEFF, 1 .0 − FREQ_LPF_RECU_COEFF)

## ∗∗∗∗ CLASS INSTANTIATIONS ∗∗∗∗### NB: Note tha t we are cheat ing a l i t t l e here in tha t we are i n i t i a l i s i n g# th i s c l a s s with knowledge of the waveforms −− t h i s i s in the form of the# i n i t i a l phase .#inquadPl l = SynchronousTwoPhasePLL ( Kif , Kpf , FREQ, samplesPerCycle ,

f r eqLp fCoe f f s , i n i t i a l Ph a s e = −pi )

# Create the synchronous amplitude ex t rac t ion c l a s s . This i s not part of the# c l a s s i c two phase p l l s t ra tegy , but i s there so tha t the est imated# or i g i na l waveform can be reconstructed for comparison .#inquadAmp = SynchronousAmplitudeExtraction ( (RECURSIVE_COEFFICIENT_F,

NONRECURSIVE_COEFFICIENT_F))


## ∗∗∗∗ MAIN LOOP ∗∗∗∗#for i in range ( numPoints − 1) :

# Execute the PLL code .#pl lReturnValue = inquadPl l . p l l ( v_alpha [ i ] , v_beta [ i ] )

# Now carry out the amplitude ex t rac t ion so tha t the est imated waveform# can be p l o t t e d .#amplReturnValue [ i +1] = inquadAmp . f i l teredAmp ( stationaryFrameComplexValue [ i ] ,

p l lReturnValue [ 1 ] )

# The amplitude returned from the above method should be equal to the# q ax i s value from the inquadPl l . p l l method when everyth ing s e t t l e s# down .

# The value of the the ta angle returned from inquadPl l . p l l should be# the angle of the d ax i s once the system has converged proper ly .# Therefore the correc t angle for the phase of space vector i t s e l f# should be 90 degrees fur ther than t h i s .#estTheta [ i +1] = pl lReturnValue [ 1 ] + pi / 2 .0

# Estimated frequency error#estFreqErr [ i +1] = pl lReturnValue [ 3 ]

# Save the est imated phase of the space vector#estSpaceVectorPhase [ i +1] = pl lReturnValue [ 1 ]

# Now convert the space vector in a s ta t ionary frame back to the two# phase component va lues . This i s achieved by r e a l i s i n g the tha t# est_theta value (which was derivd from the fram angle ) i s the angle# of the space vector . The rea l and imaginary components are the# sine and cosine est imated components .#realImagComponents [ i +1] = polar2Rect ( ( amplReturnValue [ i +1 ] [ 1 ] , estTheta [ i +1]))

# ∗∗∗∗ PLOT RESULTS ∗∗∗∗#f i g u r e ( )p l o t ( v_alpha , ’k− ’ )g r id (True )hold (True )p l o t ( r e a l ( realImagComponents ) , ’ k−− ’ )t i t l e ( r "$\ alpha$ ax i s va lue s " )

f i g u r e ( )p l o t ( v_beta , ’ k− ’ )g r id (True )hold (True )p l o t ( imag ( realImagComponents ) , ’ k−− ’ )t i t l e ( r "$\beta$ ax i s va lues " )

f i g u r e ( )p l o t ( estFreqErr , ’ k− ’ )g r id (True )t i t l e ( "Estimated Frequency Error " )

# Now generate the angle of the q ax i s of the re ference frame . Note tha t the# type has to be changed because the r e s u l t o f the un iversa l array funct ion# i s of type dtype and not f l o a t .#thetaPlot = wrapArray ( fmod ( theta + pi , 2 ∗ pi ) ) . astype ( f l o a t )

f i g u r e ( )p l o t ( estSpaceVectorPhase , ’ k−− ’ )g r id (True )

G-19

hold (True )p l o t ( thetaPlot , ’ k− ’ )t i t l e ( "Real and Estimated Space Vector Phase" )

# The fo l l ow ing l i n e s are in the code t e f f e c t i v e l y pause the simulat ion# but at the same time keep the matp l o t l i b windows ac t i v e so tha t they can# be in terac ted with by the user in terms of expanding etc to look at the# de t a i l .## The user can h i t any key to cause the program to e x i t .#i f opSys == ’Windows ’ :

print ( "Hit any key to stop " )while not msvcrt . kbhit ( ) :

w. update ( )e l i f opSys == ’UNIX ’ :

keyHit = Falseprint ( "Hit any key to stop " )while not keyHit :

i , o , e = s e l e c t . s e l e c t ( [ sys . s td in ] , [ ] , [ ] , 0 . 0 )i f i == [ ] :

w. update ( )else :

keyHit = True

c l o s e ( ’ a l l ’ )

Bibliography

[1] D. Grahame Holmes and Thomas A. Lipo. Pulse Width Modulation forPower Converters - Principles and Practice. Wiley Interscience, 2003.ISBN 0-471-20814-0. 1.3.2.2

[2] Ned Mohan, Tore M. Undeland, and William P. Robbins. Power Electronics– Converters, Applications and Design. John Wiley and Sons, 3rd edition,2003. ISBN: (USA) 0-471-22693-9, (WIE) 0-471-42908-2. (document), 2.2,2.4.10, 2.4.10.1, 2.37, 2.4.10.1, 2.4.10.2, 2.4.10.3, 2.42, 2.44, 2.71, 2.4.11,2.4.12, 2.4.12, 2.4.12, 2.53, 3.2.1.1.2, 3.3, 3.3.3.1, 3.3.3.3, 5.1, 5.2.1, 6.2.1.1,6.5.1, 7.1, 7.2, 7.2.1.1

[3] Muhammad H. Rashid. Power Electronics – Circuits, Devices and Appli-cations. Prentice-Hall, 2nd edition, 1993. ISBN: 0-13-334483-5. 2.2, 5.1

[4] Abraham I. Pressman. Switching Power Supply Design. McGraw Hill, 2ndedition, 1998. ISBN: 0070522367. 2.2, 2.4.10, 2.4.11, 3.3, 4.3

[5] Ron Lenk. Practical Design of Power Supplies. IEEE Press/McGraw-Hill,1998. ISBN:0-7803-3458-2 or 0-07-134324-5. 2.2, 2.4.11, 3.3, 3.3, 3.3.1,3.3.1, 4.1, 4.2.1.8, 4.3, 4.3, 4.3.5.2, 14, 4.46, 4.3.5.3

[6] Texas Instruments. Modelling, analysis and compensation of the current-mode converter. Available from www.ti.com, Application Note U 97. 3.3.3.3

[7] Gordon R. Slemon. Electric Machines and Drives. Addison-Wesley, 1992.ISBN: 0-201-57885-9. 4.3.3.3.2, 4.3.3.3.2, B.2.1

[8] Ferroxcube. Ferroxcube Data Manual. Available: http://www.ferroxcube.-com. (document), 4.3.5, 4.16, 4.17, 4.3.5.1, 4.3.5.1.5, 4.18, 4.19, 4.3.5.2,4.20, 4.21

[9] Ferroxcube. Ferroxcube Selection Guide. Available: http://www.-ferroxcube.com. (document), 4.3.5, 4.15, 4.3.5

[10] V. Gourishanker. Electro-mechanical Energy Conversion. InternationalTextbooks in Electrical Engineering. International Textbook Company,1965. 9

[11] Thomas H. Barton. Rectifiers, Cycloconverters and AC Controllers. OxfordUniversity Press, 1994. 5.1

[12] W. Shepherd and L.N. Hulley. Power Electronics and Motor Control. Cam-bridge University Press, 1987. 5.1

G-22 BIBLIOGRAPHY

[13] Erwin Kreyszig. Advanced Engineering Mathematics. John Wiley and Sons,1972. 6.2.1

[14] Peter Vas. Vector Control of AC Machines. Number 22 in Monographs inElectrical and Electronic Engineering. Oxford University Press, New York,1990. ISBN 0-19-859370-8. 7.2.1.1, 7.4.3.2, B.4

[15] R.E. Betz and B.J. Cook. A digital current controller for three phase voltagesource inverters. Technical Report EE9702, School of Electrical Engineeringand Computer Science, University of Newcastle, Australia, 1997. Availableat: http://www.eecs.newcastle.edu.au/users/staff/reb. 7.2.1.1, 7.2.1.1

[16] P.W. Wheeler, J. Rodriguez, J.C. Clare, L. Empringham, and A. Wein-stein. Matrix converters: a technology review. Industrial Electronics, IEEETransactions on, 49(2):276–288, Apr 2002. (document), 7.4.3.1, 7.4.3.1,7.16, 7.38, 7.4.4.2, 7.4.4.3

[17] A. Alesina and M. Venturini. Solid-state power conversion: A fourier anal-ysis approach to generalized transformer synthesis. Circuits and Systems,IEEE Transactions on, 28(4):319–330, Apr 1981. 7.1, 7.4.3.1, 7.4.3.1, 7.26,7.27

[18] A. Alesina and M.G.B. Venturini. Analysis and design of optimum-amplitude nine-switch direct ac-ac converters. Power Electronics, IEEETransactions on, 4(1):101–112, Jan 1989. 7.26

[19] D. Casadei, G. Serra, A. Tani, and L. Zarri. Matrix converter modulationstrategies: a new general approach based on space-vector representation ofthe switch state. Industrial Electronics, IEEE Transactions on, 49(2):370–381, Apr 2002. 7.4.3.2

[20] D. Casadei, G. Serra, and A. Tani. Reduction of the input current harmoniccontent in matrix converters under input/output unbalance. IndustrialElectronics, IEEE Transactions on, 45(3):401–411, Jun 1998. 7.4.3.2

[21] Remus Teodorescu, Marco Liserre, and Pedro Rodriguez. Grid Con-verters for Photovoltaic and Wind Power Systems. Wiley, 2011. ISBN9780470057513. (document), 8.1, 8.1, 8.2.1.3, 8.2.2.1, 8.29, 8.2.2.5, 8.2.3,8.2.3.1, 8.4, 8.2.3.2

[22] Martina Calais, Andrew Ruscoe, and Michael Dymond. Transformerless pvinverter issues revisited ? are australian standards adequate? In Solar09,the 47th ANZSES Annual Conference, Townsville, Queensland, Sept-Oct2009. ANZSES. 8.2.1

[23] Ben G. Streetman. Solid State Electronic Devices 2nd Edition. Prentice-Hall, 1980. 8.2.1.2

[24] T. Kerekes, R. Teodorescu, P. RodrÌ andguez, G. VÂ· andzquez, and E. Ald-abas. A new high-efficiency single-phase transformerless pv inverter topol-ogy. Industrial Electronics, IEEE Transactions on, 58(1):184 –191, jan.2011. (document), 8.2.1.3, 8.8

BIBLIOGRAPHY G-23

[25] J.M. Carrasco, L.G. Franquelo, J.T. Bialasiewicz, E. Galvan, R.C.P.Guisado, Ma.A.M. Prats, J.I. Leon, and N. Moreno-Alfonso. Power-electronic systems for the grid integration of renewable energy sources:A survey. Industrial Electronics, IEEE Transactions on, 53(4):1002 –1016,june 2006. (document), 8.9, 8.10, 8.2.1.3, 8.11

[26] R.S. Lai and K.D.T. Ngo. A pwm method for reduction of switching lossin a full-bridge inverter. In Applied Power Electronics Conference andExposition, 1994. APEC ’94. Conference Proceedings 1994., Ninth Annual,pages 122 –127 vol.1, feb 1994. 8.2.1.3

[27] Paul R. Gray and Robert G. Meyer. Analysis and Design of Analog Inte-grated Circuits. John Wiley and Sons, 1977. 8.2.4.1

[28] D. O’Kelly and S. Simmons. Introduction to Generalized Electrical MachineTheory. McGraw Hill, England, 1968. B.3.3, B.4.6, C.1.1, C.1.1

[29] Hirofumi Akagi, Yoshihira Kanazawa, and Akira Nabae. Instantaneousreactive power compensators comprising switching devices without en-ergy storage components. IEEE Transaction on Industry Applications,20(3):625–630, May/June 1984. 5, D.1.2, D.6, D.1.2

power electronics notes betz

Documents