power and a new class of future fpga architectures sinan kaptanoglu actel, fellow

Power and a New Class of Future FPGA Architectures

Sinan KaptanogluActel, Fellow

12/12/2007, IC-FPT, Kitakyushu, Japan

Sinan Kaptanoglu, Actel Corp. 2

A Rough Outline

A historical look at FPGAs A new market driver? Future Technologies Future Design Methods Future Architectures



A Historical Look at FPGAs



Infancy (1985-1990)

FPGAs were invented in the 1985-1987 time frame.● Other programmable logic (PALs and PLDs) predate

FPGAs by several years. Infancy period is marked by:

● Immature architectures and SW.● Too small, too slow, and too expensive for anything

other than glue logic.



Childhood (1990-1994)

Very exciting and inventive years.● Many startups, many new architectures.● PLDs grew into CPLDs and temporarily challenged

the FPGAs.● FPGAs grew bigger, faster and cheaper.● Software became much better.● Synthesis replaced schematic capture.



But…

By and large, FPGAs were still limited to doing glue logic.● For most applications, FPGAs were still not big

enough, fast enough, or easy enough to design with. The IC industry was driven by the PCs, in which

FPGAs played no role at all. In 1993, it looked like the entrenched ASICs

would not budge at all.



Then something new came…

Something that profoundly changed the FPGA landscape.● It was NOT a fantastic new FPGA architecture…● It was NOT a great and totally unexpected

breakthrough in technology.



It was a new market for FPGAs

“The Internet Age” had begun.● The rapidly growing datacom/telecom markets

valued design flexibility and quick time-to-market more than cost or performance.

● Suddenly, everybody needed bigger and faster routers and base infrastructure.

● Development cycles for datacom were shrunk to mere months.

● The volumes were low (not in millions).



Datacom/telecom and FPGAs

FPGAs and datacom/telecom ideally suited each other, and they mutually drove each other’s boom:● FPGAs provided the needed flexibility and made

new datacom/telecom products possible in short development cycles.

● Datacom/telecom rapidly increased the FPGA revenues, starting a boom.

● New applications ignited a rapid increase in the density and performance of FPGAs.



The young adult years (1995-2001)

The datacom/telecom markets grew very rapidly, and their share of the programmable market grew with it.● Communication’s share was less than 10% in 1994.● It peaked out at 58% by 2000.

New architectures were developed and refined to better serve this market.● FPGA vendors had a great ally: Moore’s law and the ever

shrinking process technology! This allowed FPGAs to keep up with the needs of datacom by

doubling the density every two years. FPGAs became the next generation process drivers in the

process foundries.



Changing landscape…

Many startups died in this period. FPGAs which were not targeted to datacom fell

behind in revenue:● Anti-fuses were not reprogrammable and not well

suited to datacom. This pushed Actel into other less lucrative markets.

● Altera was flying high early, but it was in trouble by late 1990s, because CPLDs could not keep up with the increasing density of the FPGAs and the needs of the newer datacom applications.



Then came the bust in 2001…

The communications industry felt the bust harder than any other sector.

Countless datacom/telecom start-ups went out of business.● Demand for new datacom/telecom equipment nose-

dived.● In parallel, FPGA revenues declined 40% within a

single year. And the middle ages started.



In the middle ages…

Xilinx kept designing FPGAs for the datacom/telecom market first and foremost.● Virtex was followed by: Virtex-2,4,5…

But they also developed lower cost derivatives for other markets.

● Revenues declined initially, but they gradually recovered.

● An era of slower growth began.



In the middle ages… Altera made a successful transition from CPLDs

to FPGAs starting with Stratix and its derivatives.● Ironically, Stratix was aimed at the data-com market

of the boom years. Other markets were addressed with derivative lower cost

products.

● Like Xilinx’s, Altera’s revenues also declined initially, but gradually recovered.



In the middle ages… Actel successfully transitioned itself from making

only anti-fuse FPGAs to flash based reprogrammable FPGAs.● These new devices were aimed at the low cost

markets as well as markets that put a premium on design security.

● Revenues declined initially, but recovered quickly.



Middle ages (2002-2008) FPGAs have settled down to a pattern of healthy but

slower growth, with small ups and downs.● Market leading FPGAs continue being designed for datacom,

but their low cost derivatives target all other markets combined.

FPGAs no longer appear to be a very vibrant industry with a lot of rapid innovation.● That’s the price one pays for maturity?● Take comfort: the ASICs are worse off.

Dataquest estimates that ASICs shrunk by 4% in 2007.



Which future awaits FPGAs?

More of the same FPGAs?● Similar architectures for everybody?● Less innovation, more marketing?

Good continued growth, but at a slower pace…

OR Another boom: but what might start it? If history repeats, it will be a rapidly growing

new market for FPGAs!



A new market driver?



A new rapidly growing market

We are witnessing a dramatic increase in portable devices.● These are usually battery operated.

Not a temporary blip:● More new devices and types of devices are coming

to market continuously.● Expected to accelerate in the 2010s.



Spectrum of portable devices

Vo

lum

e

Consumer

Industrial, Medical

Military, Automotive

Features



Portable market predictions

Gartner-Dataquest predicts 1.6B smart phones by 2010.

Juniper Research predicts 56M high end MP3 players by 2010.

Industrial/Medical/Automotive sectors are growing more rapidly than any other FPGA market.● Portable devices within these sectors are growing

the fastest.



Gartner-Dataquest estimates

2002 Market - $2.3B 2010 Market - $6.8B

New adopters are mostly from the consumer and the industrial sectors

Data Proc8.2%

Industrial24.2%

Consumer14.6%

Mil/Aero9.3%

Auto6.2%

Comm37.4%

Mil/Aero6.9%

Consumer7.6%

Industrial15.3%

Data Proc15.7%

Comm53.8%

Auto0.6%



What’s the big deal about the portable market?

Possibly there is no big deal:● Perhaps these are just yet another type of devices

which may use FPGAs sometimes.● But we could have said the same thing about the

datacom market back in 1993. What similarities are there between the datacom

market in 1993 and the portable device market in 2007?



Similarities are…

In 1993, datacom had very short design cycles and preferred FPGAs.● But it could not use FPGAs frequently because the FPGAs

often failed to meet minimum performance and density requirements.

In 2007, portable device market has short design cycles and prefer FPGAs. ● But it cannot use FPGAs frequently because the FPGAs often

fail to meet the minimum static power requirements.



This market is different…

Because:● Most portables are battery powered.● Portable devices spend most of their time awake,

idle, but doing very little. Varies from 50% to 99.99% of the life. This requires very low static power usage.

Compare that to datacom:● An FPGA in a router is active all the time.● Idle is for repairs and updates only.● A good FPGA for datacom is unlikely to be well

suited for portables and vice versa.



Don’t the low-cost derivatives address this market?

The low cost derivatives of market leading FPGAs indeed save area and power both.

But the static power of these devices are still two to three orders of magnitude too large for most battery powered applications.



The minimum requirements:

The FPGAs for portable devices need a very low power “Idle” state.● Measured in tens of W.

Idle state does not mean “switched off” or even deep “stand-by”:● Idle means very light activity.● Idle means that all FPGA flip-flops retain their state

without being saved to and restored from a memory.● Switching from idle to active must be very quick in a

few clock cycles, not thousands.



Can this be done?



An optimist’s view…

If we design new FPGA architectures custom tailored for the unique needs of the Portable device market, we give ourselves the best chance to witness a second boom in FPGAs.● These new FPGAs will not replace today’s products.

They will co-exist with them to serve different markets.



A pessimist’s view…

Most ICs don’t experience any boom. FPGAs were lucky to have had one!

We are unlikely to meet the idle power requirements of the portable market very soon. Therefore:● Accept maturity, and be happy with the slower but

steady growth.



OK, let’s be optimists for a while…

How do we design FPGAs for the portable market?



First learn from ASICs…

Use all the circuit and process tricks that the low-power ASICs have employed:● For the lowest leakage power, start by using a

designated “low power” process from your favorite FAB.

● Use high-k dielectrics for the gate, if available.



Learn from ASICs:

Use a multiple-VT process.

● Use highest VT devices wherever you can without

adversely affecting performance.● For example, all configuration bits in an SRAM based

FPGA should be built out of highest VT transistors.



More tricks from ASICs…

Consider using a multi-Vdd

process.

● There has been a wealth of research on multi-VT and

multi-Vdd

circuit design for power reduction in ASICs.

● If a multi-Vdd

process is not available, consider using

a reduced Vdd

operation.

Consider using long-channel devices. Consider power gating.



More tricks from ASICs…

Consider using a triple-oxide-process, if available:● Good for gate leakage.● Extra mask, extra cost.

If available, use a triple-well process to take advantage of well biasing.● Again good for leakage, but costly.



And yet more…

If you are really desperate, as a last resort, consider stacked gates.● Very costly (in area) for incommensurate returns in

leakage reduction.



And then, get help from SW…

Use all power-driven synthesis, tech-mapping, and place & route.

● If you used well-biasing, or multiple VT, or multiple

Vdd

, let place & route arrange it as best as it can (in

different parts of the FPGA) for the best power. At the end, do power based bit-mask selection for

configuration bits.



When you have adopted most of these tricks from ASICs…

You have far exceeded the level of “low power” derivatives of the current popular FPGA architectures.● You have definitely improved static power, but not

sufficiently.● You kept the changes to a minimum so that you can

amortize the development effort for the original architectures.



This is good, but not enough…

We need to explore fancier process technologies, circuit design methods and FPGA architectures.● The new FPGAs must be fully custom tailored for the

portable market. Even if that means they will not be very good for datacom

applications.



Promising technologies for FPGAs specifically targeted to portable devices



The trend is not good…

CMOS process and portable devices seem to be heading in opposite directions.

The transistor leakage has increased with every CMOS shrink to date.● For source-drain and gate leakage both.

As we move down the silicon dimensions the leakage will only get worse.● It’s just physics.● Using the exact same type of materials, a shrink

will leak more than the previous generation, unless the voltage is scaled.



Vdd

is not scaling!

Most 130nm low-power CMOS processes use 1.2V core operation.

So do most 90nm and 65nm low-power CMOS processes.

Most 45nm low-power processes will use 1.0V, or 0.9V at best.● Even those which use high-k dielectric materials.



This is not very likely to change

Vdd

will not scale very much in order to maintain

a modest performance and in order to keep the gate leakage under control.● With or without high-k materials.

But the source-drain leakage will keep increasing from each process node to the next.



Future technologies

Three examples of promising technologies for future FPGAs for the portable device market



Here is an incomplete list…

In increasing order of maturity:1) SOIAS (Silicon-on-Insulator-with-an-Active-

Substrate) technology.

2) Very high-k gate-oxide technology, with very small gate leakage.

3) Embedded flash-switch technology.

It is possible to combine any two or even all three.



SIOAS technology



SOIAS based architectures

Let’s start first with the basic SOI:

Insulator (Si02)

n+ p- n+

Metal-1 bulk-SiO2 Metal-1

gate (poly/metal)

gate oxide



SOIAS adds a back-substrate From Yang et al. (1995, IEEE-IEDM)

Insulator (Si02)

n+ p- n+

Metal-1 bulk-SiO2 Metal-1

gate (poly/metal)

gate oxide

Insulator (Si02)

p+ i-poly



Fine-grain dynamic back-gate biasing

Fine grain back-bias:● In space and time both.● We can back bias individual logic modules, FFs or

individual routing buffers.● Change biasing frequently.● Order of magnitude reduction in static power

compared to low-power bulk-CMOS. Need a highly sophisticated power driven

synthesis, place and route.● Even ASICs can’t do this very well yet.



SOI uses less dynamic power

Dynamic power is lower for any SOI due to lower gate and junction capacitances.

Many standard cell designs claim 50% dynamic power reduction compared to bulk CMOS (SOITECH claim.)



Very high-k gate oxides



Very high-k dielectric gate oxides

Literature is full of promising new gate insulators.● Penryn is shipping with hafnium oxide.● Other’s examples will follow suit soon.● Feasibility is proven, but reaching maturity will take

time. These materials will allow us to play a one-time

game with VT and V

dd.



Ready for the next shrink?

Suppose you are at a process node X, with operating voltage V, threshold voltage T, and gate oxide thickness G.

Ideal shrink is at sX, sV, sT, and sG, where s is the shrink factor.● Often s = sqrt(0.5) = 0.7.

All’s good here, except performance, which is roughly proportional to (V-T)2, which now becomes s2*(V-T)2 for the shrink.● Your new performance is only s2 that of the old one,

which is unacceptable.



Restoring the performance…

To counter, you go with sX, pV, qT, and pO, with q < s < p < 1

Now the speed of the shrink will go like (pV – qT)2.● Choose (pV – qT) >= (V – T).● For example V = 1.2, T = 0.4, p = 0.83, q = 0.5, and

V-T = 0.8 before and after. But now your source-drain leakage is

unacceptably bad!



Now fight the leakage…

If you don’t have very high-k gate oxide, you are out of luck. You have to live with the worsened leakage.

With a high-k gate oxide however, you can do sX, V, T, rO, where r < 1.

Now the performance is even better than before, and the leakage (both kinds) are no worse than before.



Reduce source-drain

leakage

Increase V

T

Reduce Idsat

Reduce speed

Starting from low VT and high source-drain

leakage…

Increase gate

leakage

Increase V

dd

Increase Idsat

Increase speed

Decrease gate

leakage

Use High-k

dielectric



Flash-switch technology



Flash-switch technology

The most mature technology today for low static power.

Not the same as flash-memory-on-the-side (FMOS) which loads SRAM configuration bits in the FPGA.● FMOS approach may make a good FPGA, but not a

good low-power FPGA.● Most Lattice products and MAX-2 from Altera has

FMOS.



Actel’s combined flash cell

Flash Cell

NOR-Flash memory-

bit

Flash-switch



Actel’s flash cell

Very low leakage: Each switch leaks only a few pico-amps!

This technology combines the flash memory bit and the flash-switch to a single very low leakage cell.● This cell is used directly in the signal path, not for

controlling SRAM bits.● The technology is ideal for configuration, but the

leakage of the CMOS logic and routing buffers still needs to be dealt with.



Not just some futuristic technology

It is shipping today in IGLOO™. Actel IGLOOTM is the lowest power family of

reprogrammable FPGAs in the market. Depending on the expected idle time, it can

extend the battery life by more than a factor of 10 compared to any other FPGA in the market!



Igloo has the lowest static power.

● Its leakage in “flash-freeze”

state is 300 to 1000 times

better!

Igloo advantage comes from flash switches in signal path!

Static power comparison

mW

atts

0.12 mW

40 mW

60 mW

150 mW

0

20

40

60

80

100

120

140

160

Igloo Competitor "A" Competitor "B" Competitor "C"



Battery life comparison at 95% idle

95% idle, 5% at 100MHz, Smart-phone application

0 500 1000 1500 2000 2500 3000 3500 4000 4500

Igloo

anti-fuse fpga

low power CPLD

low cost SRAMfpga

low cost Flash-SRAM hybrid

Hours of Battery life



Are we already there then?

We are indeed very close, IGLOO™ is a great product for portable devices.● But we can do even better. A future FPGA using an

order of magnitude less “idle” power than IGLOO™ is possible.



A promising circuit design technique

On-chip low-swing differential signaling



Low-swing differential signaling

Lowest dynamic and static power!● But costly in silicon area!

One needs sense-amps at every input of the logic modules and FFs.

● Also costly in development effort. Immunity to noise and immunity to SEU is

unproven.



Low-swing differential signaling

Hybrids are possible:● Some regular routing resources, plus some (mostly)

differential signal routing resources. Let a smart place and route make the right choices for the

power and performance.

● Can also be combined with SOIAS and flash-cell technologies.



Examples of promising architectural changes



Overall architecture optimization

Current FPGAs are architected to minimize [(Area)a * (Delay)d].● The exponents a and d vary by a factor of two: 0.7 <

a, d < 1.5.

Instead, we need to minimize: [(Area)a * (Delay)d / (Battery-life)b]

● With 0.7 < a, d < 1.0 < b <= 2



Current architectures are very heavily DSP-oriented

Market leading low cost FPGAs come with many hard multipliers.

This makes good sense in many markets but not for portable devices:● Very few portable apps will benefit from a hundred

18X18 multipliers on FPGA.● For most portable applications just a few multipliers

are enough.



Ratio of used routing buffers FPGAs use unidirectional buffers nowadays. For a typical design, more than half of these

remain unused after place and route.● They contribute to leakage in “Idle”.

It is possible to redesign the interconnect architecture such that only 20% of the buffers remain unused for typical designs.● Then the total number of buffers can be reduced,

with a corresponding decrease in leakage.

A hand-waving explanation



Ratio of used routing buffers Doing this without increasing the mux area very

much and without reducing routability is the key!● Different interconnect topology is needed!● Changes are not simple.● There is a performance penalty, but it could be kept

well below 10%.



Ratio of used carry chains

In a typical design 70% to 90% of all ripple carry chains are unused!● Carry chain drivers are large by necessity, and they

leak a lot.● The carry chain can be redesigned to reduce the

leakage by up to 50%. Performance loss can be kept in single digits.

● Overall impact on total leakage is not that big, but every little bit helps.



Dual port RAMs

Dual port RAMs are popular.● Especially useful to build FIFOs.● For the argument here “dual port” and “two port”

amount to the same thing. However, the dual port RAMs are used as single

port RAMs more than 90% of the time.● Except in datacom applications!



Dual port RAMs

A dual port RAM used in single port mode has half of its outputs tied OFF.● These will leak in the unused state.

Dual port RAM cells have two or more additional transistors, which increase leakage.

For FPGAs for portable devices, it is better to provide mostly single port RAMs, and some dual port RAMs.● Significant help with leakage.



IO leakage…

Unused IO drivers do not leak much because of the thicker gate oxide.

But there is a huge amount of other circuitry in front of the pad drivers.● These leak a lot more, especially because the FPGA

IOs are designed to support many different IO standards.

By circuit redesign and by supporting fewer IO standards the leakage can be reduced significantly.



Don’t forget the peripherals…

One rarely worries about PLLs, crystal oscillators, other clock generators, voltage pumps, etc...● They don’t contribute much to the dynamic power,

but they are a major component of the “idle” static power.

These mostly analog blocks should be redesigned for FPGAs serving portable applications with much reduced idle power consumption.



Now tackle dynamic power



Next tackle the dynamic power:

Even though not as critical as static idle power, dynamic power is still very important for battery operated apps.

We can improve dynamic power by doing similar things as ASICs.● All changes combined, we can improve it up to a

factor of two or so.● Unlike the static power, there is no way to improve it

by several orders of magnitude. The only way to improve it by an order of magnitude is by

low-swing differential signaling.



FPGA specific optimizations…

For dynamic power, FPGA specific optimization involves primarily IOs and clock networks.● Other parts of FPGAs are optimized similarly to

ASICs. IOs use 30% to 50% of dynamic power.

● For IOs, the most effective strategy is integration: Low voltage (1.2V) IOs are preferred.



Clock architectures will change

In current architectures 20% to 50% of the core power is burned by clocks!● This is 3 to 10 times larger than ASICs.

This is a relic of the mid-1990s design:● FPGAs come with 6 to 24 global distribution

networks, because this was the only reliable way of distributing low-skew signals on FPGAs in 1990s.



It even affected FPGA synthesis…

FPGA synthesis generates (relatively) few clocks, with many clock enables.● This is a very nice and clean methodology.● Very friendly for synchronous design.● But it wastes power!

We need FPGAs that can support many (hundreds) small clocks.● No support for explicit ENA on flip-flops.● That’s what ASICs have been doing!



Clocks will make the switch first

It may take a long time for the first FPGA using all low-swing differential signaling to come to market.● Way before then, however, we will have FPGAs that

use differential signaling in global clock networks.● It’s the lowest hanging fruit.



Summary



The second FPGA boom may be on its way… The rapidly growing portable device market is

the best candidate that may start the second FPGA boom.

But the FPGAs must meet the static power requirements of this market.● We can do this by designing new FPGAs specifically

for portable devices, rather than trying to retrofit old ones.

● The old FPGAs will not go away, they continue to serve markets which do not care very much about battery life.

Thank you!

power and a new class of future fpga architectures sinan kaptanoglu actel, fellow

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