power analysis of wep encryption
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Power Analysis of WEP Encryption. Jack Kang Benjamin Lee CS252 Final Project Fall 2003. Outline. Background and Motivation Objective Theory Experimental Methodology Experimental Results Conclusions Future Work & Directions Questions. Background and Motivation (1/4). - PowerPoint PPT PresentationTRANSCRIPT
Power Analysis of WEP Encryption
Jack KangBenjamin LeeCS252 Final ProjectFall 2003
Outline
Background and Motivation Objective Theory Experimental Methodology Experimental Results Conclusions Future Work & Directions Questions
Background and Motivation (1/4)
The Digital Divide Gap between the digitally empowered and digitally
poor, between developing and developed nations Can information and communication technologies
(ICT) close the gap? There are social AND economic reasons to solve
this problem
Background and Motivation (2/4)
Problems More talk than action Financial sustainability Coordination of activities Scope E-governance
Bottom of The Pyramid (BOP) Prahad argues that it is profitable to serve the poor Multinational Corporations have financial incentive to step in
Background and Motivation (3/4)
Prahalad, C.K. and Hammon, Allen, Serving the World's Poor, Profitably, Harvard Business Review, 9/2002.
Background and Motivation (4/4)
So what about the technical problems? Low-cost Low-power Intermittent Connectivity User Interfaces for populations with multiple
languages and low levels of literacy Shared accesses as a possibly dominant use
mode Limited skilled workforce for maintenance
Objective
Evaluate high-level software optimizations and low-level hardware configurations for reducing power dissipation applied to WEP encryption
Provide a framework for further study in wireless communication infrastructure for developing regions
Theory – Loop Unrolling
A compiler technique that extends the size of loop bodies by replicating the body n times
The loop exit condition is then adjusted accordingly
Why is power saved? More efficient front end – less branches means the
fetch unit is able to fetch large blocks without being interrupted by control decisions
Less branches in the code means reduced power dissipation of the branch prediction hardware
Theory – Cache Optimizations
Choices in associativity and block sizes will affect the miss rate of the cache.
Power can be saved if we can reduce the miss rate.
No need to go off chip Better performance means we may be able to
lower the clock frequency (and thus voltage levels) and still meet minimum performance needs
Experimental Methodology
Software WEP encryption Software is cheaper (low-cost) Easier to upgrade (limited maintenance)
SimpleScalar Simulates hardware and software configurations
Wattch Provides power estimation
Wired Equivalent Privacy (1/3)
Overview 802.11 wireless standard Provides wireless network with security equivalent
to wired network Confidentiality Access Control Data Integrity
Wired Equivalent Privacy (2/3) Encryption
Hirani, Sohail A. Energy Consumption of Encryption Schemes in Wireless Devices. Master’s Thesis. University of Pittsburgh, April 2003.
Wired Equivalent Privacy (3/3) Decryption
Hirani, Sohail A. Energy Consumption of Encryption Schemes in Wireless Devices. Master’s Thesis. University of Pittsburgh, April 2003.
SimpleScalar (1/2)
Baseline Simulation - Microprocessor In-order issue No branch prediction Minimal number of functional units
Integer ALU Floating Point ALU Integer Multiplier/Divider Floating Point Multiplier/Divider
SimpleScalar (2/2)
Baseline Simulation – Memory L1 Instruction Cache
16-KB cache 32-byte blocks Full associativity
L1 Data Cache 16-KB cache 32-byte blocks 4-way associativity
Unified L2 Cache 18-KB cache 32-byte blocks 4-way associativity
Wattch (1/2)
Overview Framework for analyzing and optimizing
microprocessor power dissipation at the architectural level
Wattch v1.02 SimpleScalar Interface Simulated PISA instruction set Built on Pentium 4/x86 platform
Wattch (2/2)
Conditional Clocking Styles NCC – No conditional clocking CC1 – Simple conditional clocking
Zero power dissipation with zero accesses CC2 – Aggressive conditional clocking (ideal)
Linear power dissipation with fractional accesses CC3 – Aggressive conditional clocking (non-ideal)
15% power dissipation with zero accesses
Experimental Results (1/3)
Cache Associativity (2/3)
Cache Associativity (3/3)
Conclusions
Significant power savings from software and hardware optimizations
Loop Unrolling Max = 17% reduction Median = 15.9% reduction Mean = 15.9% reduction
Cache Associativity Max = 12.5% reduction Median = 4% reduction Mean = 5% reduction
Future Work & Directions Study combined effects of optimizations
Apply these optimizations for new microprocessor configurations
Apply these optimizations to a larger test suite
References David Brooks, Vivek Tiwari, and Margaret Martonosi, Wattch: A Framework
for Architectural-Level Power Analysis and Optimizations, 27th International Symposium on Computer Architecture (ISCA), June 2000.
Doug Burger and Todd M. Austin, The SimpleScalar Tool set, Version 2.0, Computer Architecture News, pages 13-25, June 1997.
Sohail Hirani, Energy Consumption of Encryption Schemes in Wireless Devices, Master’s Dissertation, University of Pittsburgh, 2003.
Kenneth Keniston, Grassroots ICT projects in India: Some Preliminary Hypotheses, ASCI Journal of Management 31(1&2), 2002.
C.K. Prahalad and Allen Hammon, Serving the World's Poor, Profitably, Harvard Business Review, September 2002.
C.K. Prahalad and Stuart L. Hart, The Fortune at the Bottom of the Pyramid, strategy+business, issue 26, 2002.
SimpleScalar toolset. http://www.simplescalar.com Wattch toolset. http://www.ee.princeton.edu/~dbrooks/wattch-form.html
Questions
Any Questions?