portable stimulus power domain verification case study ...€¦ · many customers, 8 major. proven...

The Leader in Portable Stimulus

Portable Stimulus Power Domain Verification Case Study

Verification Futures 2018

Today’s Disjointed, Low-Level Verification Process

© Breker Verification Systems, Inc. All rights reserved. 2 Breker Systems Confidential

Silicon

Limited connection to

verification tests,

complex device visibility

SoC

Difficult HW/SW syncing,

corner case coverage,

debug visibility

UVM

Complex sequence

synchronization, laborious

test authoring

PSS Concept: Verification Search Engine

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Describe intent

Set constraints

Example: Airline Flight Booking

Tool synthesizes all the options

Example Scenario: Texting a Camera Image


Bus IF

Display Processor

Bus IF

Bus IF

Touchpad

Bus IF

Camera

Bus IF

Bus IF WiFi Modem

Bu

s IF

CPU

CPU CPU

Flash

Bus IF

GPS

Bu

s IF

Bluetooth

Bu

s IF

NFC

Bu

s IF

Bu

s IF B

us IF

Power

Bus IF

DMA

LTE Modem

CDMA Modem

CPU

DRAM

Audio Codec

Bus IF

camera_c

capture ↓

photo touchpad_c

enter ↓

message

cpu_c

comp_msg ↓

bPkt_p

datStr

bPkt_p

datStr

lte_c

lte_vip : extvip_c

receive ↑

tx ↑

lte_p

packet

cdma_c

cdma_vip : extvip_c

receive ↑

tx ↑

cdma_p

packet

screen_p

screen

✖

Courtesy: Accellera PSSS Tutorial

What Does a Real Graph Look Like?


Example: ARMv8 System Scenario Model

Yellow Octagons are hierarchical modules that can be expanded

Purple Diamonds are select goals (randomized decision points)

Blue rectangles are sequence goals

expanded module boundary

The Accellera Portable Stimulus Standard (PSS)


Breker Founder and Leading Contributor with C++ Donation

Proposed Portable Stimulus Specification (Courtesy: Accellera Systems Initiative)

Accellera Sponsored Portable Stimulus Working Group

Breker fully supports PSS/DSL and PSS/C++

plus a Native C++ option

Breker Systems Confidential


Breker: Enabling Your Verification GPS

Scenario test-case synthesis for all stages of the verification process from a single, comprehensible, executable intent specification

» Executable Intent Specification driven verification Leveraging enhanced Portable Stimulus for easily authored Graph-based, Portable, Sharable (GPS) scenario models

» Intelligent Testbench test synthesis AI-driven functional test synthesis generating optimized test cases for rapid corner-case bug detection

» Practical Deployment models Eliminating UVM & SoC headaches by layering test-case content into existing verification flows


Breker PSS Applied to UVM

Automatic synthesis of multi-threaded sequences from easily authored scenario

Synthesis of scoreboard, coverage models in existing UVM environment

Top-down, abstract random constraints for simplified test configuration


Agent Agent Agent VIP

Scenario Model

SD

Sys

DC

PP

Cam

TrekUVM

Scoreboard

Coverage Model

DUT

Synthesis

Synthesis

Top Down Constraint


SoC Verification Engineer Persona

Simplified, HW/SW synchronized, randomized abstract tests, manipulating system resources

Stress tests (e.g. coherency) to find corner case issues for emulation and simulation

Easy debug visualization of system level test progress, with back door “trickboxing,” memory management, HSI

© Breker Verification

Systems, Inc. All rights reserved.

9

Tr ekSoC

Cache-Coherent Switching Fabric

CPU CPU CPU CPU

L1 L1 L1 L1

L2

CPU CPU CPU CPU

L1 L1 L1 L1

L2

…

L3 Cache / Snoop Filter

Memory Controller

Memory Controller

Offload

Compiler

test.c test.c test.c

TrekBox

test.c test.c test.tbx

PCIE Ethernet

PCIE VIP

Ethernet VIP

Scenario Model

Qualification: Complex SW-driven cases, hard corner case scenarios

Power Domain Breker PSS Verification Example

© Breker Verification Systems, Inc. All rights reserved. . Breker Systems Confidential 10

Fabric

Main Memory Sub-system

ARM M7 Sub-system

Block 1 Block 2 Block 3

Data Processing Path

ARM M7 sub-system with various peripherals that access data in a specific sequence

Multiple power domains must be exercised as devices operates

Blocks pre-verified so UVM scoreboards, UVCs exist

Traditional verification with combination of SW C tests, transactions to manipulate power domains randomly are complex making it hard to discover problem corner cases

Power Domain State Machine Scenario


Power domain switching state machine provides operational detail

Scenario can be coded that may be layered into functional verification graph

PD

Reset

Cold Boot

Scan

Sniff

Sniff Exit

Deep Sleep

Deep Sleep Exit

Sleep

Sleep Exit

Sleep Warm Boot

Idle / Processing / Communication

Power Domain Switch Testbench


Fabric

Main Memory Sub-system

ARM M7 Sub-system

Block 1 Block 2 Block 3

UVM Scoreboard

UVc

Design Under Test

Scenario Model

Tr ekSoC

Compiler

test.c test.c test.c

TrekBox

Test.tbx

Testbench: existing UVM components incl. scoreboard and processor C tests

Graph-based scenario model loaded into TrekSoC produces synchronized sequences and C tests

Single scenario model generates complete set of synchronized tests

Power Domain PSS Graphed Scenario


Device reset, cold boot process, basic system checks

Warm boot cycle, with memory content loss. The test process, using C tests in memory, allow for this

Functional operation commences: chains of producer/consumer scenarios cycled

At various intervals, power domain reset executed, randomly interrupting processing. After a warm boot cycle device expected to resume cycling transparently

Synchronization between the C-tests on the processor and the transactions must be maintained, even as the memory is reset

Synchronized test sets


Multi-threaded tests layered into testbench to drive processor, transactions, etc., that provide functional tests together with power domain cycling

Single scenario produces 1000s tests using high level randomization to exercise broad range of corner cases

Test scenario took 1 week to design, instead of 2-3 months normally

Portable Stimulus Leadership on Real Projects


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China

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Breker India

Global, Leading Customer Portfolio


Breker: Your Verification GPS


Practical applications of PSS to solve difficult UVM and SoC verification challenges, with effective, unique deployment models

Portable Stimulus leader. Leveraging enhanced standard as executable intent specification across verification process. Your verification GPS

Many customers, 8 major. Proven on leading edge projects with significant schedule impact. Works with, agnostic across, standard environments

For more Information:

www.brekersystems.com


portable stimulus power domain verification case study ...€¦ · many customers, 8 major. proven...

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