PNV @ Lyonimec for WP3

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Cells structures and process flows

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1. Epifree

2. PolySi

3. Epifoils

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Material

EpifreeMicron-thin mono c-Si on foreign substrate

Formation of macropores

Annealing at high temperature

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A simple solar-cell process

1. Film formation by annealing

2. (Surface passivation)

3. Aluminium deposition: rear-contact

4. Bonding and detachment: anodic bonding

5. Heterojunction emitter formation:

i/n+ a-Si and Indium Tin Oxide deposition

6. Ti/Pd/Ag top contacts evaporation

7. Si etching for cell definition

Fragile material!

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EpifreeHeterojunction cell

Substrate

Alc-Si / p-type

i/n+ a-Si / ITOAg

ITO - 75 nmn+ a-Si - 12 nm

i a-Si - 12 nm

p c-Si - 1.1 µm

p++ c-Si - 25 nm

Emitter:

Base:

BSF:

5 cm x 5 cm glass substrate

1 cm x 1 cm cell

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Substrate

Thin film c-Si solar cell

~ 100 nm

Substrate

Seed layer formation(crystalline)

Substrate

Non-Si substrate

Epitaxial growth

Substrate

3-10 µm

PolySiThin-film c-Si layers on non-Si substrates

(here) By: Al induced crystallisation

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PolySiHeterojunction cell

ITO - 75 nmn+ a-Si - 12 nm

i a-Si - 12 nm

p c-Si - 3 µm

p+ c-Si - 500 nmp++ c-Si - 250 nm

Emitter:

Base:

5 cm x 5 cm

alumina substrate

1.1 cm x 1.1 cm cell

aluminaFOx - 100 nm Rear:

Ag

Substrate

p++ c-Sic-Si

a-Si/ITOAl

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PolySi on alumina substrateCross section view

FOxSi seed for epi (actual layer is thicker)

Alumina

1 µm

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Roughness of poly

1 µm 2 µm

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10© IMEC 2013/ CONFIDENTIAL

Epi on porous Si for transfer to glass

VALERIE.DEPAUW@IMEC.BE

epitaxial n-type base

(in-situ)

epi p emitter

parent substrate

epi p+

Low-porosity layer

Separation layer(high porosity layer)

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Epifoils – Final targetInterdigitated back-contacts, epi rear-emitt er

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silicone

Ti/Al

EPI c-Si: n

SiNx ARC

EPI c-Si: n+

EPI c-Si: p+

a-Si: iSiOx

a-Si: n+

glass

SiO2

Ti/Al

Front-side: High temperature processes

Rear-side: Low temperature processes

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Epifoils – Current workTwo-side contacted cell - easier

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Front-side: High temperature processes= our IBC 23% cells

silicone

EPI c-Si: n

SiNx ARC

DIFFUSED c-Si: n+

EPI c-Si: p+

glass

SiO2

Metal

Metal (Al or Ti)

a-Si: iSiOx

Rear-side: • a-Si passivation of emitter• PECVD SiO2 reflector• Metal contact

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n base

Current epifoils: another (textured) view

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p+ emitter passivation

passivationARC

Now:Random pyramids

Future:Nanopatterning!

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1st Cell results

1 µm epifreeTrends

3.5 µm polySi

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Cell results: 1 µm c-Si

Texturing Jsc (mA/cm2)

Voc(mV)

η(%)

No 12.6 471 4.3

NIL 15.3 435 4.8

• 22% increase in current

• Voc decreased due to passivation and plasma damage

• Increased efficiency

The nanopattern was integrated

successfullyC. Trompoukis et al., Appl. Phys. Lett. 101, 103901 (2012)

Non optimized pattern

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PNV final aim: 30

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Trends – 4 runs statistics

RUN Jsc Voc FF Eta4 13.3 325 57 2.454 NIL 14.8 260 66 2.543 14.1 282 56 2.23 NIL 14.5 247 64 2.32 12.5 281 60 2.12 NIL 16.2 246 59 2.31 7.4 489 56 2.01 NIL 12.3 492 67 4.1

Increase in current due to better light trapping Decrease in voltage due to plasma damage Overall increase in efficiency

Same trends for all 4 runs so far when adding nanopattern

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Cell results: 3-5 um polySi

Texturing Jsc (mA/cm2)

Voc(mV)

η(%)

No 18.1 411 4.5

NIL 21.0 406 5.1

• 15% increase in current

• Voc reduced

• Increased efficiency

Glass

1 μm c-Si (p-type)Al

Ag i/n+ a-Si / ITOAl

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PNV final aim: >30

nanophotonics for ultra-thin crystalline silicon photovoltaics

project 309127

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Epifree

ITO

Silicon

Al contact

Substrate

a-Si

Cell techno: Substrate + mesa + no optical spacer on the back, Si on Al directly. Heteroj.Ref: what exists (PiPV Valerie)During the project: optimise structure, supertrate, spacer...

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PolySi

Alumina (granular, looks like white paint, 1mm thick) + a flowable oxide (Fox)

Or Si\SiO2

3 μm c-Si (p-type)

Al

Ti\Pd\Ag

i/n+ a-Si (10+10nm)/ ITO (75nm?)

Al

Interdigitated (every ~500microns)200nm c-Si (p++type)

Techno: substrate is Alumina+ Fox or Si/SiO2 + Poly (high and low dopings) + HeteroJRef: CSG, see paper attached.During the project: probably no structure change.

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n-type Si

p+

+n

SiO2

Silicone~70nm PECVD SiNx~10nm thermal oxideFSF

Emitter~120nm thermal oxideMEtal

BSF i/n+ a-SiMEtal

Epifoils: goal, ibc like

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n-type Si

Front: FSF diffused on n-type epilayer, random pyramids covered with ~10nm thermal oxide, ~70nm PECVD SiNxcontactsSilicone

Rear side: a-Si passivation with oxide reflector and contacts through holes.Al (either Pfeiffer or Leybold), or Ti/Al (Pfeiffer)

Epifoils: presently

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PNV @ LyonLPICM for WP3

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Outline

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1. Epifree

2. PolySi

3. Epifoils

4. PECVD epitaxy

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Process Flow and cell architecture

• PECVD epitaxy

• Stress induced lift off

• Final stack

(i)+(p) or (n) aSi:H

Epi-Si (~ 3µm)

(i)+(n) or (p) aSi:H

Metal mirror

Glass

(i)+(p) or (n) aSi:H

Epi-Si (~ 3µm)

(p) Or (n) Epi-Si

Metal mirror

Glass

a) Metal evap. on epi-si

b) Glued to transfer substrate

c) Mechanical and thermal stress (~ 400-500°C)

- HF or in situ c-Si (100) wafer surface cleaning- SiH4/H2 PECVD epitaxy 175°C

C-Si wafer

Epi-SiFragile interface

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Material Characterization

FWHM 5,3 cm-1 by Raman for 2,5 µm ELO layer

RMS ~ 1,1 nm

1,1 nm RMS roughness for6 µm ELO Si 6µm epi-Si

(i)aSi:H/(n)aSi:H

Kapton

• Low roughness and good crystal quality is kept through the lift off process

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Electrical properties under study

First life time confirms material quality

Effective life time by Time Resolved Microwave Conductivity

Setup

epi-Si (~3,2µm)

N+ asi:H

Kapton tape

Few tens of µs decay time

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Transferred epi-PECVD diode: preliminary results

ITO

(i)aSi:H/(n+)a-Si:H

2,5 µm (i)epi-Si

Al

PDMS/Glass• Jo ~ 1e-9 mA/cm2

• n ~ 4

0,03 cm2