plug and play guidelines legacy

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Legacy Plug and PlayGuidelines

A Technical Reference for LegacyPCs and Peripherals for the

Microsoft Windows Family ofOperating Systems

ersion !"# $ May !%& !'''

Legacy Plug and Play Guidelines 1997-1999 Intel Corporation and Microsoft Corporation. All rights reser ed.

(ntel Corporation and Microsoft Corporation


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The information contained in this document represents the current view of Intel Corporationand Microsoft Corporation on the issues discussed as of the date of publication. Because

Intel and Microsoft must respond to changing mar et conditions! it should not beinterpreted to be a commitment on the part of Intel and Microsoft! and Intel and Microsoftcannot guarantee the accuracy of any information presented. This document is forinformational purposes only. I"T#L $"% MIC&'(')T M$*# "' +$&&$"TI#(!#,P(( '& IMPLI#%! I" T-I( %'C M#"T.

Intel Corporation and Microsoft Corporation may have patents or pending patentapplications! trademar s! copyrights! or other intellectual property rights covering sub/ectmatter in this document. The furnishing of this document does not give you any license tothese patents! trademar s! copyrights! or other intellectual property rights.

Intel and Microsoft do not ma e any representation or warranty regarding specifications inthis document or any product or item developed based on these specifications. Intel andMicrosoft disclaim all e0press and implied warranties! including but not limited to theimplied warranties of merchantability! fitness for a particular purpose! and freedom from

infringement. +ithout limiting the generality of the foregoing! Intel and Microsoft do notma e any warranty of any ind that any item developed based on these specifications! orany portion of a specification! will not infringe any copyright! patent! trade secret! or otherintellectual property right of any person or entity in any country. It is your responsibility tosee licenses for such intellectual property rights where appropriate. Intel and Microsoftshall not be liable for any damages arising out of or in connection with the use of thesespecifications! including liability for lost profit! business interruption! or any other damageswhatsoever.

$ctive,! Bac 'ffice! %irect(how! %irect,! Microsoft! M(1%'(! "et(how! +in23!+indows! +indows "T! and the +indows logo are either registered trademar s ortrademar s of Microsoft Corporation in the nited (tates and4or other countries.

Intel and Pentium are registered trademar s! and Intel567! MM,! and ,eon are trademar sof Intel Corporation.

'ther product and company names herein may be the trademar s of their respectiveowners.

8 9::;


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Contents

Welcome 5-ow to se This Guide...................................................................................................7Conventions sed in This Guide....................................................................................7&eferences and &esources...............................................................................................;

Chapter 1 9Basic Legacy Plug and Play 9

Legacy Plug and Play (pecifications..............................................................................:ni=ue Plug and Play %evice I%s.................................................................................9>

'ption &'M Guidelines...............................................................................................99?P"P@ Aendor Codes and Compatible I%s..................................................................99I4' %ecoding ................................................................................................................99

Chapter 2 12ISA Plug and Play 12

(ystem &e=uirements for Plug and Play I($ ..............................................................93Plug and Play I($ %evice &e=uirements.....................................................................92

Plug and Play I($ (tandards for %evices...............................................................92'ption &'Ms for I($ Boot %evices.......................................................................92I4' %ecoding for I($ %evice..................................................................................95I($ I& (haring.....................................................................................................95%eterministic Aalues for nimplemented &egisters..............................................95Correct Identifiers for I($ %evices.........................................................................95BI'( &eporting or (erial I% for (ystem Board %evices........................................9P"P (uffi0es and Compatible %evice I%s..............................................................9'ption &'Ms for Boot %evices..............................................................................97

Chapter 3 1Legacy (erial Port ........................................................................................................9;Legacy Parallel Port .....................................................................................................96

#PP (upport and &estricted I4' addresses.............................................................96Compatibility! "ibble Mode! and #CP Protocols ..................................................9:I### 9365 Port Connector (pecifications..............................................................9:Plug and Play %evice I%s for I### 9365 Peripherals ...........................................9:Compatible I% *ey for Parallel %evice I%.............................................................3>

Legacy Mouse Port and %evices...................................................................................3>Legacy *eyboard Port and %evices..............................................................................39Legacy )%C...................................................................................................................39

Appendi! A 22I"#$ %&A$ and I'( Port Addresses 22

)i0ed Interrupts.............................................................................................................33Legacy %M$ $ssignments...........................................................................................33Legacy I4' $ddress $ssignments.................................................................................32

Appendi! B 25%e)ice Identi*iers 25

Plug and Play Aendor and %evice I%s.........................................................................3Generic +indows %evice I%s.......................................................................................37

Interrupt Controllers................................................................................................3;



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Timers......................................................................................................................3;%M$........................................................................................................................3;

*eyboards................................................................................................................3;Parallel %evices.......................................................................................................36(erial %evices..........................................................................................................36%is Controllers......................................................................................................3:%isplay $dapters.....................................................................................................3:Peripheral Buses......................................................................................................2>&eal1Time Cloc ! BI'(! and (ystem Board %evices.............................................2>PCMCI$ Controller Chip (ets...............................................................................29Mouse.......................................................................................................................29

"etwor $dapters....................................................................................................22(ound! Aideo Capture! and Multimedia.................................................................2;Modems...................................................................................................................26

+lossary 39Inde! ,5Plug and Play re-uirements 1. ,/Plug and Play$ 10 ,/re-uirements$ 19 ,/ISA de)ice re-uirements$ 12 1/ ,I 120,$ 19 2. ,parallel ports and de)ices$ 19 2. ,



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This guide is for engineers who build personal computers! e0pansion cards! and peripheral devices that will be used with the Microsoft D +indows D 231bit operatingsystems and that incorporate legacy components. The specific focus of this guide is Plugand Play configuration of resources for the following system componentsE

Industry (tandard $rchitecture FI($ bus and devices (erial ports and devices I### 93651based parallel ports and devices *eyboard and mouse ports and devices

Important In general! it is strongly recommended that system designers implementPlug and Play for +indows 3>>> and +indows :6 based on the re=uirementsdefined in Advanced Configuration and Power Interface Specification, Version1.0 or later F$CPI 9.> ! plus the driver guidelines defined in the Microsoft+indows 3>>> %river %evelopment *it F%%* .

In addition! designers are strongly encouraged to see legacy1free alternatives forsystem design! avoiding the I($ bus because of the throughput bottlenec s andresource limitations of I($ design.

-owever! it is recogniHed that to meet some customer re=uirements! systemmanufacturers must provide some systems that support the legacy I($ bus. Thegoal of this document is to provide guidelines for legacy hardware design that willresult in the optimal user e0perience when the hardware is used with the +indowsfamily of operating systems.

This guide is a supplement to the legacy Plug and Play specifications Favailable athttpE44www.microsoft.com4hwdev4respec4pnpspecs.htm ! and the driver implementationguidelines defined in the Microsoft +indows : %%*. $ll material in this guide has

previously appeared in the following documentsE

PC 97 Hardware Design uide FMicrosoft Press D! 9::; I(B" 91 ;329126919 PC 9! S"ste# Design uide FMicrosoft Press! 9::; I(B" 91 ;3291;971; PC 99 S"ste# Design uide FMicrosoft Press! 9::6 I(B" >1;2 71> 9619

1997-1999 Intel Corporation and Microsoft Corporation. All rights reser ed.

+elcome


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Chapter ! Welcome %

-ow to se This GuideThis guide is divided into several chapters! with appendi0es that list detailedsettings.

Chapter Contents

Chapter 9! ?Basic Legacy Plugand Play@

%efines basic specifications and guidelines forimplementing legacy Plug and Play.

Chapter 3! ?I($ Plug and Play@ Provides specific guidelines for implementing Plug andPlay I($! for the computer system and for individualdevices.

Chapter 2! ?I4' Ports and%evices@

Provides Plug and Play guidelines for legacy serial and parallel ports and for legacy mouse and eyboardconnectors.

$ppendi0 $! ?I& ! %M$! andI4' Port $ddresses@ I& ! %M$! and I4' Port $ddresses

$ppendi0 B! ?%eviceIdentifiers@

Lists compatible I%s for legacy and I($ devices.

Glossary %efines technical terms and acronyms related tohardware and the +indows operating systems.

This guide is co1authored by Intel Corporation and Microsoft Corporation.

$dditional information about hardware design is available from Intel Corporation athttpE44developer.intel.com.

$dditional information about hardware design is available from the Microsoft web

sites at httpE44www.microsoft.com4hwdev4.

Conventions sed in This GuideThe following conventional terms are used throughout this guide.

Add on de)ices%evices that are traditionally added to the base server system to increasefunctionality! such as audio! networ ing! graphics! and so on. $dd1on devicesfall into two categoriesE devices built onto the system board set and devices one0pansion cards added to the system through a system1board connector such asPeripheral Component Interconnect FPCI .

Intel Architecture

&efers to computers based on 751bit and 231bit microprocessors that use theIntel $rchitecture instruction set! such as Intel D Pentium D! Intel Pentium withMM, technology! Pentium Pro! Pentium II! Pentium II ,eon ! orcompatible processors. MM, technology refers to IntelJs media1enhancementtechnology that includes new instructions added to the Intel $rchitectureinstruction set.

Legacy&efers to any feature in the system based on older technology for which



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Chapter ! Welcome *

compatibility continues to be maintained in other system components.

System de)ices$lso on$%oard devices. &efers to devices on the system board set such asinterrupt controllers! eyboard controller! real1time cloc ! direct memory accessF%M$ page registers! %M$ controllers! memory controllers! floppy discontroller F)%C ! $T1$ttachment F$T$ ports! serial and parallel ports! PCI

bridges! and so on. In todayJs servers! these devices are typically integrated withthe supporting chip set.

Windo4s&efers to the Microsoft +indows : or +indows :6 operating systems!including any add1on capabilities and any later versions of the operating system.

Windo4s 2...&efers to the Microsoft +indows 3>>> operating system! including any add1oncapabilities and any later versions of the operating system.

)or a list of acronyms and definitions of technical terms! see the Glossary later inthis guide.

&eferences and &esourcesThe following represents some of the information resources! services! and toolsavailable to help build hardware optimiHed to meet the re=uirements defined in thisguide. This section also lists technical references for the specifications cited in thisguide.

In*ormation "esources

Intel developer informationhttpE44developer.intel.com

Microsoft hardware developer information httpE44www.microsoft.com4hwdev4

Microsoft %eveloper "etwor FM(%" Professional (ubscriptionPhoneE F6>> ; :1 5;5'utside "orth $mericaE F 9> 3; 1>;72)a0E F 9> 3; 1>;73httpE44msdn.microsoft.com4

echnical "e*erences

Advanced Configuration and Power Interface Specification, Version 1.0httpE44www.teleport.com4Kacpi4

I&' Persona( S"ste#)* Co##on Interfaces, Part "o. (65)1:6>: I&' Persona( S"ste#)* 'ouse +ec nica( -eference, Part "o. (76,1333:

International Business Machines CorporationIBM Customer Publications (upportE F6>> 6;:13;'r contact an IBM sales representative



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Chapter ! Welcome +

Microsoft Platform (%*! +indows : %%*! and +indows 3>>> %%* Provided through M(%" Professional subscription

httpE44msdn.microsoft.com4subscriptions4Microsoft +indows -ardware Compatibility List F-CL

httpE44www.microsoft.com4hwtest4hcl4

Plug and Play specificationshttpE44www.microsoft.com4hwdev4respec4pnpspecs.htm



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This chapter defines the basic specifications and implementation guidelines forlegacy Plug and Play.

)or information about Plug and Play drivers support under +indows : ! see the+indows : %%*. Plug and Play for A0% drivers under +indows :6 should alsofollow the guidelines defined in the +indows : %%*.

)or information about Plug and Play support under +indows 3>>>! see the+indows 3>>> %%*.

Legacy Plug and Play (pecifications#ach bus and device provided in the computer system must meet the current Plugand Play specifications related to its class! including re=uirements clarifications

published for some Plug and Play specifications. )or $CPI1based systems! buses

and devices must also meet the re=uirements defined in (ection 7 of the AdvancedConfiguration and Power Interface Specification, -evision 1.0 . This specificationdefines the re=uirements for automatic device configuration! resource allocation!and dynamic disable capabilities.

The following shows current version numbers for all legacy Plug and PlayspecificationsE

P(ug and P(a" &I S Specification Version 1.0a

Important This specification applies only for non1$CPI1based systems.$CPI1based systems must follow the re=uirements defined in $CPI 9.>.

P(ug and P(a" / terna( C ' Device Specification, Version 1.0

P(ug and P(a" Industr" Standard Arc itecture ISA2 Specification,Version 1.0a

C(arification to P(ug and P(a" ISA Specification, Version 1.0a P(ug and P(a" Para((e( Port Device Specification, Version 1.0% P(ug and P(a" S#a(( Co#puter S"ste# Interface Specification, Version 1.0


Basic Legacy Plug and Play


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Chapter ! Welcome !#

6ote (tandard system devices are e0cluded from this re=uirement. The system canreserve static resources for devices such as programmable interrupt controllers

FPICs 9 and 3! 63 513 timer! 6>53 eyboard controller! real1time cloc ! %M$ page registers! %M$ controllers 9 and 3! and math coprocessor. )or systems basedon Intel $rchitecture compatible processors! these fi0ed resources are located at I4'addresses under 9>>h and can also include a "onmas able Interrupt F"MI .

$ll system1board devices must use I($1compatible addresses. This includesdevices with I4' port addresses within the reserved range >h0))h. )orinformation about legacy system I4' addresses! see $ppendi0 $! ?I& ! %M$! andI4' Port $ddresses.@

ni=ue Plug and Play %evice I%s

#ach device connected to an e0pansion bus must be able to supply its ownuni=ue I%. The following are the specific re=uirements for Plug and Playdevice I%sE

#ach separate function or device on the system board must be separatelyenumerated therefore! each must provide a device I% in the manner re=uired inthe current Plug and Play specification for the bus it uses.

If a device on an e0pansion card is enumerated by the BI'(! it must havea uni=ue I% and its own resources according to the current device I%re=uirements for the bus to which the card is connected. This includes devicesthat are separately enumerated on multifunction cards or multifunction chips.

In addition! if an '#M uses a proprietary mechanism to assign asset or serial

numbers to hardware! this information must be available to the operating systemusing +indows hardware instrumentation technology! as defined in the 3etwor4

PC S"ste# Design uide(ines, Version 1.0% or later .

The following are e0ceptions to the re=uirement for a uni=ue Plug and Play I%E

Legacy devices attached to the I($ bus on the system board do not have uni=uePlug and Play I%s for e0ample! serial ports! parallel ports! or Personal(ystem43 FP(43 compatible port devices. The method for device identificationis defined in the P(ug and P(a" ISA Specification, Version 1.0a, and the$CPI 9.> specification .

(ome multifunction devices! such as (uper I4'! might include devices that donot have uni=ue Plug and Play I%s or uni=ue PCI subsystem I%s! but that aresupported by drivers provided with the +indows operating system.

$ device such as a multifunction PCI device that supports a number offunctions but uses only a single set of relocatable resources does not have to

provide separate I%s for each function included on the device.



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Chapter ! Welcome !!

'ption &'M GuidelinesThese guidelines apply for devices that use option &'M on systems based on Intel$rchitecture processors! whether the device is present on the system board or

provided through an e0pansion card.

'ption &'Ms are usually located on cards used as system boot devices. %uring the boot process! option &'Ms initialiHe the boot devices! which provide the primaryinput! primary output! and Initial Program Load FIPL device to boot the system.-owever! Plug and Play option &'Ms can be used to supply the Plug and Playe0pansion header to devices other than boot devices! enabling them to initialiHe

both devices when the system boots.

?P"P@ Aendor Codes and Compatible I%s$ll legacy devices not enumerated by the system1board interface must not use theacronym for Plug and Play! ?P"P@ in their vendor and device codes. The P"Pvendor code is reserved for Microsoft and for vendors whose hardware isspecifically assigned a particular I%. 'ther hardware can use a P"P code onlywhen defining a deviceJs Compatible I% FCI% and only after first indicating thedeviceJs -ardware I% in the Plug and Play header.

se of CI%s are recommended for devices that use device drivers provided with the+indows operating system! such as a (tandard PC C'M Port FP"P> >> .

)or information about using P"P CI%s! see $ppendi0 B! ?%evice Identifiers.@ Toobtain a uni=ue P"P vendor I%! complete the form provided athttpE44www.microsoft.com4hwdev4pnpid.htm.

I4' %ecoding#ach device must support a uni=ue I4' port address in the 971bit address range.This re=uirement means that! at a minimum! the upper address lines F$9>1bit address range.

%evices that use less than 971bit I4' decode create conflicts that cannot be resolved by a Plug and Play operating system. Phantom Falias addressing is not supported by the +indows operating system and cannot be used to meet this re=uirement.

"otice that this re=uirement does not apply for the three I($ auto1configurationregisters used during device enumeration and configuration. The $%%((!+&IT# %$T$! and $% %$T$ registers will continue to use 931bit decodingas described in the ISA P(ug and P(a" Specification, Version 1.0a.



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This chapter summariHes Plug and Play re=uirements for any I($ legacyimplementations.

In addition to I($ e0pansion cards! the following are also I($ devicesE

6>53 and similar controllers! ports! eyboards! and mice %irect memory access F%M$ controllers and slaves )loppy dis controllers F)%Cs Interrupt controllers Legacy parallel and serial ports Math coprocessors Programmable interrupt timers FPITs

AG$ controllers

-owever! any such devices located at I4' addresses below 9>>h can use fi0edresources and are e0empt from Plug and Play re=uirements for uni=ue I%s! fle0ibleresource configuration! and dynamic disable capabilities.

)or details about the interrupt re=uest FI& settings! %M$ address! and I4' portaddresses for specific devices! see $ppendi0 $! ?I& ! %M$! and I4' Port$ddresses.@

(ystem &e=uirements for Plug and Play I($This section summariHes the basic re=uirements for a PC system that includes theI($ bus.

If I($ support is included in a system! the manufacturer must implement thestandards described in the following Plug and Play specificationsE

P(ug and P(a" ISA Specification, Version 1.0a P(ug and P(a" &I S Specification, Version 1.0a


I($ Plug and Play


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Chapter ! Welcome !,

C(arifications to t e P(ug and P(a" &I S Specification, Version 1.0a .

The Plug and Play specifications are available from the web site athttpE44www.microsoft.com4hwdev4respec4pnpspecs.htm.

$dditional I($ clarifications and white papers related to I($ Plug and Play underthe Microsoft +indows operating system are available from the web site athttpE44www.microsoft.com4hwdev4legacy4.

6ote (tandard system devices are e0cluded from this re=uirement. The system canreserve static resources for devices such as interrupt controllers 9 and 3! 63 513timer! 6>53 eyboard controller! real1time cloc ! %M$ page registers! %M$controllers 9 and 3! and math coprocessor Fif present . )or a system based on Intel$rchitecture! these fi0ed resources are located at I4' addresses below 9>>- andcan also include an "MI mas .

Plug and Play I($ %evice &e=uirementsThis section includes additional re=uirements for I($ cards! including re=uirementsfor design implementations that appear only as recommendations in the I($specification! to ensure that such cards will perform correctly under +indows.

The information in this section is provided for manufacturers of I($ devices whowant to ensure that their devices are completely compatible with Plug and Playoperating systems.

)or more details! see the Plug and Play I($ (pecification! version 9.>a.

Plug and Play I($ (tandards for %evices$ny card or bus that implements Plug and Play I($ must fully implement thestandards defined in the P(ug and P(a" ISA Specification, Version 1.0a. Thisspecification also defines the re=uirements for a uni=ue I% for each I($ device. Theuni=ue I% is used to identify the device for Plug and Play configuration.

'ption &'Ms for I($ Boot %evices'ption &'Ms must be used only on cards that contain boot devices.

Cards with option &'Ms must not hoo the primary boot interrupts FInt :h! Int 9>h!Int 92h! Int 96h! and Int 9:h until the system calls the boot connection vector in theselected option &'M e0pansion header.

)or cards with option &'Ms! the default configuration must be able to be disabledafter the card has been isolated.



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Chapter ! Welcome !-

I4' %ecoding for I($ %evice

This circuit can be simple enough to limit I4' addresses to the >h to 2))h range! orit can be fle0ible enough to use the upper address regions.

The device must meet the guidelines for 971bit I4' decoding defined in Chapter 9!?Basic Legacy Plug and Play!@ in this guide.

I($ I& (haringnder +indows : 4:6 Fbut not +indows "TD 5.> or +indows 3>>> ! an I($

device and its driver can support I& sharing if resource re=uirementscannot be met. This capability applies only for devices of the same class! not acrossdevice classes.

To share I& s! the following re=uirements must be metE

The I& line must be pulled high by the system board. The I& line must never be driven high by the devices. To signal an interrupt! devices must pull the I& line low for a minimum of

9>> nanoseconds and then release it. The interrupt is signaled by the risingedge that occurs as a result of the pull1up on the I& line.

The drivers for all devices connected to the I& line must correctly support theinterrupt1sharing services of the virtual programmable interrupt controllerdevice FApic% . This means that after dispatching an interrupt from Apic%! thedrivers must respond to Apic% and correctly indicate whether they actually

processed an interrupt for their devices. Apic% will ensure that all devices with

pending interrupts have been serviced before returning from the interrupt. I& sharing support implemented in the device driver for servicing interrupts.

%eterministic Aalues for nimplemented &egisters$ny unimplemented registers in the range >>h when they are read.

Correct Identifiers for I($ %evicesIn the Plug and Play I($ specification! it is re=uired that a Plug and Play card have

bothE $n industry1uni=ue Aendor I% Fac=uired by completing the form provided at

httpE44www.microsoft.com4hwdev4pnpid.htm $ company1uni=ue Product I% Fassigned by the manufacturer



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Chapter ! Welcome !.

The specification re=uires that this Product I% be uni=ue among all Plug and PlayI($ cards manufactured by that company.

This means each product Ffor e0ample! fa0 card! display adapter! sound adapter!and so on and every model Ffor e0ample! 95.5 fa0! 36.6 fa0! and so on from thesame manufacturer must have different product identifiers.

This is a re=uirement because it allows the operating system to isolate and identifythese different cards. The user must never have a Plug and Play card that cannot beidentified because it cannot be distinguished from other models of cards from thesame manufacturer. The use of a uni=ue Product I% does not solve the problemsthat occur when a user installs two of the same cards in a PC system.

In those cases! the user might install a Plug and Play card but will not receiveindication that it was installed and the card will not wor . )or this purpose! the Plugand Play I($ specification defines a uni=ue serial1number field that can be added tothe Aendor and Product I%s to ma e the card completely uni=ue. $ board1uni=uenumber in the serial1number field is re=uired for I($ devices included on a system.

BI'( &eporting or (erial I% for (ystem Board%evices

$ peripheral I($ device implemented on the system board can use a fi0ed (erial I%Fwhich is not uni=ue if the device is reported through the BI'(.

If the system board device participates in the Plug and Play I($ isolation schemeFrather than being reported through the BI'( ! then it must meet the samere=uirements for a uni=ue (erial I% as for an add1on card.

"otice that it is possible that an add1on card containing an I($ chip might be addedto a PC system that contains the same chip on the system board. In such a case! theadd1on device will be found only if it has a different (erial I%.

P"P (uffi0es and Compatible %evice I%s%evice I%s that use the three1character P"P suffi0 are allowed only in theCompatible %evice I% field and cannot be used as %evice I% or Logical %evice I%fields. The e0ception would be the device to which the P"P1based I% wasoriginally assigned.

&esource data describe what resources must be available for each logical device onthe card Ffor e0ample! number of available I& numbers! address ranges ofmemory! and so on . &esource data can be stored in the same nonvolatile storagedevice Fsuch as a serial &'M that contains the serial identifier. The resource datain the nonvolatile storage device must be se=uentially loaded into the resource dataregister F>5h .

The content of the nonvolatile storage device must be programmed with theinformation the system needs to interpret which resources the card re=uires. The



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Chapter ! Welcome !%

structure of the data contained in the storage device is variable! depending on whatresources are needed.

The resource data for a Plug and Play I($ card can be read while the card is in theConfig state. This card can enter the Config state either after it has been isolatedduring the isolation se=uence or whenever it receives a +a e FCard (elect "umberNC("O software command in which the C(" matches the C(" assigned to thecard. 'nly one card at a time can be in the Config state.

'ption &'Ms for Boot %evicesPlug and Play I($ e0pansion cards that contain boot devices re=uire some specialconsiderations to properly boot the system. The system must implement support forPlug and Play I($ boot devices and option &'Ms as described in the Plug and PlayBI'( specification.

The types of devices re=uired for the boot process include the primary input deviceFusually a eyboard ! the primary output device Fusually a display adapter andmonitor ! and any IPL devices.

$ny Plug and Play I($ e0pansion card that provides a boot function must be activewhen the system powers up. This gives non1Plug and Play systems the means forusing Plug and Play I($ devices during a legacy boot process.

In this case! a non1Plug and Play system BI'( will not perform the isolationse=uence but will instead perform a &'M scan to detect the presence of a bootdevice. $fter the &'M scan detects the presence of an option &'M on the bootdevice! the system &'M will /ump to the option &'M to initialiHe the device. ThePlug and Play option &'M on the card will detect that the system BI'( is not Plugand Play1compatible and will respond accordingly.

$lthough an initial set of static resources must be provided during this legacy boot!the Plug and Play I($ card must be capable of changing these resources using thestandard Plug and Play I($ isolation and configuration process.

$s re=uired in the Plug and Play I($ specification! resource usage of a card isalways reflected in the cardJs configuration registers. This information allows+indows to easily determine the default settings of a Plug and Play boot device.The default settings can then be overridden by the operating system with fullcooperation of the device driver.



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!*

C - $ P T # & 2

This chapter presents guidelines for legacy I4' ports and devices! including serialand parallel ports.

Legacy (erial PortThis section defines re=uirements for legacy serial ports.

$ 97 >$ buffered niversal $synchronous &eceiver4Transmitter F $&Tor e=uivalent buffered legacy serial port is the standard implementation. )oracceptable performance under +indows! the device must be able to support 99 .3*

baud.

$ legacy serial port must provide fle0ible resource configuration and completedynamic disable capabilities as defined in the P(ug and P(a" / terna( C '

Device Specification, Version 1.0.

These are the recommended resource settings for legacy serial devicesE

)our I4' locations for each port! where the standard I($ I4' addresses are2)6h! 3)6h! 2#6h! 3#6h. sing the standard addresses ensures the properfunctioning of software that directly addresses these locations.

Two I& signals! where the standard is programmable interrupt controller1 based FPIC1based I& 2 and I& 5. sing the standard I& signals ensuresthe proper functioning of software written for systems that use standardI& signals.

Two I& s are re=uired for each port. If two serial ports are implemented in thesystem! the I& s can be assigned as followsE

)or serial port $E PIC1based I& 5 and I& 99 )or serial port BE PIC1based I& 2 and I& 9>

$n infrared FI& adapter port might replace a serial port in a system. In such a case!the I& port should use the resource configuration that would otherwise be assignedto the second serial port.

"otice that I& sharing can be implemented under +indows if the minimumresource re=uirement cannot be met.

Important Conflict resolution for legacy serial port must ensure the availability ofat least one serial port. In the event of an irreconcilable conflict with other serial

ports on the system! a legacy serial port must be capable of being disabled by Plugand Play software. This allows at least one of the two conflicting serial ports tooperate correctly.



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Chapter ! Welcome !+

Legacy Parallel PortThis section presents guidelines for legacy parallel ports.

$ legacy parallel port must provide fle0ible resource configuration followingthe P(ug and P(a" Para((e( Port Device Specification, Version 1.0%. &esourcere=uirements must be met for each device of this type on the system. There=uirements cannot be split between two ports on the system.

)or legacy parallel devices! the following are the minimum resource re=uirementsfor each parallel port on the systemE

&e=uiredE (upport I($ I4' addresses of 2;6h and 3;6h! plus 2BC or avendor1assigned I4' address. sing these standard I4' addresses ensures

proper functioning of software written for operating systems that directlyaddress these locations.

&ecommendedE Map the base I4' address to four additional locations. &e=uiredE (upport PIC1based I& and I& ;. sing these standard I& s

ensures proper functioning of software written for operating systems that usestandard I& signals.

&ecommendedE (upport five additional I& signals. &e=uiredE (upport two uni=ue %M$ channel selections if the parallel port

design supports bloc data transfers to memory using %M$ controllers. "otice also that the %M$ function will not wor on a parallel port withoutan I& because the end of a %M$ transfer is signaled by an interrupt.

To ensure Plug and Play support for resolution of resource conflicts! a full listof options for all possible configuration combinations must be enumerated!includingE

'ptions for both e0tended capabilities port F#CP mode! which re=uires an I4'address! an I& ! and a %M$ selection! and standard LPT mode! whichre=uires only an I4' address.

'ptions that specify only the I4' address! allowing +indows to assign the I&and %M$ channel.

'n Intel $rchitecture systems! the operating system considers the parallel port baseaddress F4 stored in the first BI'( %ata $rea FB%$ locations to be LPT9. Theaddress stored in the second location is LPT3! and so on. 'n &I(C1based systems!

the information is in the $&C tree. 'n all $CPI1based systems! the information isobtained through the $CPI tree.

#PP (upport and &estricted I4' addresses(ome enhanced parallel port F#PP implementations re=uire eight contiguousI4' ports. If #PP support is implemented! the hardware cannot use the I($



19/48

Chapter ! Welcome !'

I4' address 2BCh as a base I4' address because AG$ devices re=uire use of port 2C>h.

Compatibility! "ibble Mode! and #CP Protocols(upport for a parallel port must include! at a minimum! the compatibility1mode andnibble1mode protocols re=uired by the I### 936519::5 specification. This allowsother I### 93651compliant devices to be connected without problems.

The port must also support the #CP protocol as defined by I### 9365 to allowconnections with higher1speed parallel peripherals.

&ecommendedE #nable #CP by default.

I### 9365 Port Connector (pecificationsI### 93651I


20/48

Chapter ! Welcome /#

$ll M$" )$CT & and M'%#L ey values must remain uni=ue for eachmanufacturer. $ll M$" )$CT &! M'%#L! CL$((! and %#(C&IPTI'"

ey values must remain static for a specific unit! where I% values do not change fordifferent hardware configurations. )or e0ample! a user simply adding a memorymodule to a printer should not change the M'%#L ey value reported as part of thedevice I%. -owever! if the user adds memory by installing an upgrade it thatre=uires a different driver or re=uires the e0isting driver to behave differently! thenchanging the M'%#L value is acceptable as part of the upgrade installation

process.

The CL$(( ey describes the type of parallel device. The CL$(( ey can containthe values P&I"T#&! M'%#M! "#T! -%C! PCMCI$! M#%I$! )%C! P'&T(!(C$""#&! or %IGC$M. -%C refers to hard dis controller. M#%I$ refers toany multimedia device. )%C refers to floppy dis controller.

The %#(C&IPTI'" ey is an $(CII string of up to 936 characters that containsa description of the device the manufacturer wants to have presented if a devicedriver is not found for the peripheral.

)or information about how the system determines the correct peripheral devicedriver! see the +indows : %%* and +indows 3>>> %%*.

Compatible I% *ey for Parallel %evice I%The CI% ey in the device identification string can provide a value that e0actlymatches a peripheral name supported by a device driver shipped with +indows.The value must match a value listed in the deviceJs I") file.

Legacy Mouse Port and %evicesThe following re=uirements must be met to ensure that all Plug and Playre=uirements are met and that built1in Microsoft1supplied drivers support the

pointing device. If a P(431style port is used! the following re=uirements must bemetE

Comply in full with re=uirements in Persona( S"ste#)* Specification, by IBM. se an 6>53 chip For e=uivalent to ensure compatibility with +indows. In most

cases! the e0isting 6>53 eyboard port is sufficient the chip initiates a PIC1 based I& 93 interrupt when the pointing device is connected.

(upport PCI1based I& 93 to ensure the proper functioning of software writtenfor legacy systems that use this I& signal.

&eturn e0pected codes! including send I% F>)3h and responseac nowledgement F$C* F>)$h ! plus 91byte I%.



21/48

Chapter ! Welcome /!

Legacy *eyboard Port and %evicesIf a P(431style eyboard port is used! it must meet the following re=uirements!which ensure that all Plug and Play re=uirements are met and that built1inMicrosoft1supplied drivers support this device.

(upport I& 9 on Intel $rchitecture to ensure the proper functioning of softwarewritten for legacy systems! which e0pect to use this I& signal.

Map the I4' address ports to 7>h and 75h. &eturn e0pected scan codes! including send I% F>)3h and response $C*

F>)$h ! plus 31byte I%.

Legacy )%CThe following resource re=uirements must be met for each legacy )%C device onthe systemE

se static I4' addresses 2)3h! 2)5h! and 2) h. $dditional addresses can be provided in the event of conflict

se I& 7 se %M$ Channel 3 if )%C supports bloc data transfers to memory using

%M$ controllers

These resources cannot be shared among devices of the same type.

The )%C must be capable of being configured! relocated! and disabled. )ore0ample! if the legacy )%C is located on the system board and an adapter thatincludes an )%C is added to the system! the system1board )%C must be capable of

being disabled to prevent conflicts with the new adapter.

If the legacy )%C is located on an e0pansion card! the e0pansion card must allowindependent dynamic disabling of the )%C and the hard dis controller. In this case!the adapter will continue to function if the )%C is disabled because of conflicts.



22/48

//

$ P P # " % I , $

This appendi0 lists resource assignments for I& ! %M$! and I4' port addressesused by built1in devices on legacy system boards.

)i0ed InterruptsThe following I& s are used by I($ and system devices and are considered to befi0ed assignments.

i!ed Interrupts

:ard4are I"# %e*ault assignment

I& > (ystem timer

I& 9 *eyboard

I& 3 (econd programmable interrupt controller FPIC cascade

I& 2 C'M 3I& 5 C'M 9

I& (ometimes LPT 3 not considered fi0ed

I& 7 (tandard floppy dis controller F)%C

I& ; LPT 9

I& 6 &eal1time cloc 4CM'(

I& :

I& 9> (ometimes C'M 5 not considered fi0ed

I& 99 (ometimes C'M 2 not considered fi0ed

I& 93 P(431style mouse

I& 92 Coprocessor

I& 95 Primary Integrated %evice #lectronics FI%# controller

I& 9 (econdary I%# controller

Legacy %M$ $ssignments


I& ! %M$! and I4' Port $ddresses


23/48

Chapter ! Welcome /,

The following table lists %M$ channel assignments that are used by legacy devicesand are therefore considered fi0ed.

Legacy %&A Considered i!ed

:ard4are %&A System *unction ;de*ault I($ e0pansion

%M$ 9

%M$ 3 )%C

%M$ 2 #0tended capabilities port F#CP parallel port on LPT 9

%M$ 5 %M$ controller cascading

%M$

%M$ 7

%M$ ;

Legacy I4' $ddress $ssignmentsThe following table lists I4' addresses that are used by legacy devices and aretherefore considered fi0ed.

Legacy System I'(

I'( Address %e*ault system *unction

>>>>>>) (lave %M$

>>9>>96 (ystem

>>>9) (ystem

>>3>>39 Master 63 :>>5>>52! >>56>5B Programmable interrupt timer FPIT 9! PIT 3

>> >> 3 (ystem

>>7> *eyboard4mouse controller

>>79 (ystem control port B

>>75 *eyboard4mouse status

>>;>>;9 "onmas able Interrupt F"MI enable4real1time cloc

>>69>6B %M$ page registers

>>:>>:9 (ystem

>>:3 (ystem control port $

>>:2>:) (ystem Continued2



24/48

Chapter ! Welcome /-

Legacy System I'( continued2

I'( Address %e*ault system *unction

>>$>>$9 (lave interrupt controller

>>C>>%# Master %M$ controller

>>)>>)9 Coprocessor busy clear4reset

>9;>9;; (econdary I%# controller

>9)>9); Primary I%# controller

>3>9 Qoystic interface

>33>33) (ound Blaster

>3;63;$ LPT 3 F,T parallel port 2

>3#63#) $lternate C'M F5

>3)63)) C'M 3

>22>229 MP 15>9

>2;7 I%# Controller

>2;62;$ LPT 9 F,T parallel port 3

>26626B )re=uency modulation F)M synthesis

>2B>2BB M%$! #G$4video graphics array FAG$

>2BC2B# LPT 2 F,T parallel port 9

>2C>2%) #G$4AG$

>2#>2#; PCIC PCMCI$ controllers

>2#62#) $lternate C'M F2

>2)>2); )%C e0cluding >2)7

>2)62)) C'M 9> 25 2; +indows (ound (ystem1compatible

>C)6C)B Peripheral Component Interconnect FPCI ports



25/48

/.

$ P P # " % I , B

This appendi0 lists CI%s for Plug and Play vendor I%s and device I%s.

6ote )or non1BI'( enumerated I($ devices! new vendor I%s must be registered by completing the form provided at httpE44www.microsoft.com4hwdev4pnpid.htm or by sending mail to ihvRmicrosoft.com with ? P6PI% @ in the sub/ect line.

Plug and Play Aendor and %evice I%s$ll non1BI'( enumerated devices must not use ?P"P@ in their vendor anddevice codes. Instead! the vendor must register a three1character vendor code. TheP"P vendor code is reserved for Microsoft and can be used only when defining adeviceJs CI% after indicating the deviceJs -ardware I% in the Plug and Playheader.

se of CI%s is strongly recommended for devices that use inbo0 device drivers!

such as a ?(tandard PC C'M Port@ FP"P> >> .The following e0ample output of a Plug and Play header is provided as a referencefor the Microsoft +indows operating system.

Vendor ID: XXXFFFF

Serial Number: 00000001Checksum (reported): 0x5!N! Version: 1"0Vendor Ver": 10De#ice Description: ID !ortDe#ice ID: XXX0001

Doesn$t Support I%& 'an e CheckinVendor De ined *o ical De#ice Control 'e isters:

NoneCompatible De#ice ID: PNP0600

De#ice Description: ID

Dependent +unction 0Dependent +unction 1

nd o Dependent +unctions


%evice Identifiers


26/48

Chapter ! Welcome /%

+hen the user is installing devices that use this method! a dialog bo0 appears at the beginning of the enumeration se=uence to suggest use of the +indows : 4:6 default

driver. +indows : 4:6 also provides the option of using a manufacturer1supplieddis in case the user wants to choose a manufacturer1supplied driver.

)or multifunction adapters! you should supply an I") file that chooses theappropriate drivers! including default drivers! for all the adapterJs devices. This

prevents additional dialog bo0es from repeatedly re=uesting the default driver ora manufacturerJs dis for the remaining devices on the adapter.

+hen an I") file is used in this manner for default driver selection! it must lin the-ardware I% F,,,>>>> to the appropriate compatible device driver fromthe +indows : 4:6 distribution C% or installation dis s. If this is not done!+indows : 4:6 will continue to =uery the user for either the default driver or a newdriver! thus defeating the purpose of using the I") file in this way.

Generic +indows %evice I%sMany devices! such as the interrupt controller or the eyboard controller! haveno standard #0tended Industry (tandard $rchitecture F#I($ I%. $lso! a set ofcompatible devices! such as video graphics array FAG$ and (uper AG$ F(AG$ !are not actually devices but define a compatibility hardware subset. Set another setof I%s needs to be used to identify buses.

Microsoft has reserved an #I($ prefi0 FP"P to identify various devices that do nothave e0isting #I($ I%s. Microsoft also uses P"P to define compatibility devices.The I%s are defined in the following tables.

%e)ice I% "angesI% range Category

P"P>000 (ystem devices

P"P6000 "ettwor adapters

P"P$000 (mall computer system interface F(C(I ! proprietary C% adapters

P"PB000 (ound! video capture! multimedia

P"PC00000 instead



27/48

Chapter ! Welcome /*

Interrupt Controllers%e)ice I% %escription

P"P>>>> $T interrupt controller

P"P>>>9 #I($ interrupt controller

P"P>>>3 MC$ interrupt controller

P"P>>>2 $dvanced Protocol Interrupt Controller F$PIC

P"P>>>5 Cyri0 (LiC MP interrupt controller

Timers%e)ice I% %escription

P"P>9>> $T timer P"P>9>9 #I($ timer

P"P>9>3 MC$ timer

%M$%e)ice I% %escription

P"P>3>> $T direct memory access F%M$ controller

P"P>3>9 #I($ %M$ controller

P"P>3>3 MC$ %M$ controller

*eyboards %e)ice I% %escriptionP"P>2>> IBM PC4,T eyboard controller F621 ey

P"P>2>9 IBM PC4$T eyboard controller F671 ey

P"P>2>3 IBM PC4,T eyboard controller F651 ey

P"P>2>2 IBM #nhanced F9>949>31 ey! P(43 mouse support

P"P>2>5 'livetti eyboard F621 ey

P"P>2> 'livetti eyboard F9>31 ey

P"P>2>7 'livetti eyboard F671 ey

P"P>2>; Microsoft +indows eyboard

P"P>2>6 General Input %evice #mulation Interface FGI%#I legacy

Continued



28/48

Chapter ! Welcome /+

7ey8oards continued2

%e)ice I% %escription

P"P>2>: 'livetti eyboard F$9>949>31 ey

P"P>2>$ $T T 2>3 eyboard

P"P>2>B &eserved by Microsoft

P"P>23> Qapanese eyboard $>9 F9>71 ey

P"P>239 Qapanese eyboard F9>91 ey

P"P>233 Qapanese $, eyboard

P"P>232 Qapanese eyboard >>34>>2 F9>71 ey

P"P>235 Qapanese eyboard >>9 F9>71 ey

P"P>23 Qapanese Toshiba des top eyboard

P"P>237 Qapanese Toshiba laptop eyboard

P"P>23; Qapanese Toshiba noteboo eyboard

P"P>25> *orean eyboard F651 ey

P"P>259 *orean eyboard F671 ey

P"P>253 *orean enhanced eyboard

P"P>252 *orean enhanced eyboard 9>9b

P"P>252 *orean enhanced eyboard 9>9c

P"P>255 *orean enhanced eyboard 9>2

Parallel %evices%e)ice I% %escription

P"P>5>> (tandard LPT port

P"P>5>9 #0tended capabilities port F#CP printer port

(erial %evices%e)ice I% %escription

P"P> >> (tandard PC C'M port

P"P> >9 97 >$1compatible C'M port

P"P> >3 Multiport serial device Fnon1intelligent 97 >

P"P> 9> Generic Ir%$1compatible device

P"P> 99 Generic Ir%$1compatible device



29/48

Chapter ! Welcome /'

%is Controllers%e)ice I% %escriptionP"P>7>> Generic #(%I4I%#4$T$1compatible hard dis controller

P"P>7>9 Plus -ardcard II

P"P>7>3 Plus -ardcard II,L4#U

P"P>7>2 Generic Integrated %evice #lectronics FI%# supporting %evice Bayspecifications

P"P>;>> PC standard floppy dis controller F)%C

P"P>;>9 (tandard )%C supporting %evice Bay specification

%isplay $dapters%e)ice I% %escription

P"P>:>> AG$ compatible

P"P>:>9 Aideo (even A&$M4A&$M II49>35i

P"P>:>3 6 954$ compatible

P"P>:>2 Trident AG$

P"P>:>5 Cirrus Logic laptop AG$

P"P>:> Cirrus Logic AG$

P"P>:>7 Tseng #T5>>>

P"P>:>; +estern %igital AG$

P"P>:>6 +estern %igital laptop AG$

P"P>:>: (2 Inc. :994:35

P"P>:>$ $TI ltra Pro4Plus FMach 23

P"P>:>B $TI ltra FMach 6

P"P>:>C ,G$ compatible

P"P>:>% $TI AG$ +onder

P"P>:># +eite P:>>> graphics adapter

P"P>:>) 'a Technology AG$

P"P>:9> Compa= Aision

P"P>:99 ,G$43

P"P>:93 Tseng Labs +234+23i4+23p

P"P>:92 (2 Inc. 6>94:364:75

P"P>:95 Cirrus Logic 53:4 525 Fmemory1mapped

Continued



30/48

Chapter ! Welcome ,#

%isplay Adapters continued2


P"P>:9 Compa= $dvanced AG$ F$AG$

P"P>:97 $TI ltra Pro Turbo FMach 75

P"P>:9; &eserved by Microsoft

P"P>:96 Matro0 MG$

P"P>:9: Compa= Aision 3>>>

P"P>:9$ Tseng +936

P"P>:2> Chips Technologies (AG$

P"P>:29 Chips Technologies $ccelerator

P"P>:5> "C& ;;c33e (AG$

P"P>:59 "C& ;;c23blt

P"P>:)) Plug and Play monitors FA#($ display data channel N%%CO

Peripheral Buses%e)ice I% %escription

P"P>$>> I($ bus

P"P>$>9 #I($ bus

P"P>$>3 MC$ bus

P"P>$>2 Peripheral Component Interconnect FPCI bus

P"P>$>5 A#($4AL1bus

P"P>$> Generic $dvanced Configuration and Power Interface F$CPI bus

P"P>$>7 Generic $CPI #0tended I4' F#I' bus

&eal1Time Cloc ! BI'(! and (ystem Board %evices


P"P>6>> $T1style spea er sound

P"P>B>> $T real1time cloc

P"P>C>> Plug and Play BI'( Fonly created by the &''T enumerator

P"P>C>9 (ystem board

P"P>C>3 General I% for reserving resources re=uired by Plug and Play system

board registers Fnot specific to a particular deviceP"P>C>2 Plug and Play BI'( event notification interrupt

Continued



31/48

Chapter ! Welcome ,!

"eal ime Cloc=$ BI(S$ and System Board %e)ices continued2


P"P>C>5 Math co1processor

P"P>C> $dvanced Power Management F$PM BI'( Fversion1independent

P"P>C>7 &eserved for identification of early Plug and Play BI'(implementation

P"P>C>; &eserved for identification of early Plug and Play BI'(implementation

P"P>C>6 $CPI system board hardware

P"P>C>: $CPI embedded controller

P"P>C>$ $CPI control method battery

P"P>C>B $CPI fan

P"P>C>C $CPI power1button deviceP"P>C>% $CPI lid device

P"P>C># $CPI sleep1button device

P"P>C>) PCI interrupt lin device

P"P>C9> $CPI system indicator device

P"P>C99 $CPI thermal Hone

P"P>C93 %evice Bay Controller F%BC

P"P>C92 Plug and Play BI'( Fused when $CPI mode cannot be used

PCMCI$ Controller Chip (ets

%e)ice I% %escriptionP"P>#>> Intel 6327 1compatible PCMCI$ controller

P"P>#>9 Cirrus Logic CL1P%7;3> PCMCI$ controller

P"P>#>3 AL(I AL63C957 PCMCI$ controller

P"P>#>2 Intel 6327 1compatible CardBus controller

Mouse%e)ice I% %escription

P"P>)>> Microsoft bus mouse

P"P>)>9 Microsoft serial mouse

P"P>)>3 Microsoft InPort mouseP"P>)>2 Microsoft P(431style mouse

P"P>)>5 Mouse (ystems mouse

Continued



32/48

Chapter ! Welcome ,/

&ouse continued2


P"P>)> Mouse (ystems 21button mouse FC'M3

P"P>)>7 Genius mouse FC'M9

P"P>)>; Genius mouse FC'M3

P"P>)>6 Logitech serial mouse

P"P>)>: Microsoft BallPoint serial mouse

P"P>)>$ Microsoft Plug and Play mouse

P"P>)>B Microsoft Plug and Play BallPoint mouse

P"P>)>C Microsoft1compatible serial mouse

P"P>)>% Microsoft InPort1compatible mouse

P"P>)># Microsoft1compatible P(431style mouse

P"P>)>) Microsoft (erial BallPoint1compatible mouse

P"P>)9> Te0as Instruments uic Port mouse

P"P>)99 Microsoft1compatible bus mouse

P"P>)93 Logitech P(431style mouse

P"P>)92 9 P(43 port for P(431style mouse

P"P>)95 Microsoft *ids mouse

P"P>)9 Logitech bus mouse

P"P>)97 Logitech (+I)T device

P"P>)9; Logitech1compatible serial mouse

P"P>)96 Logitech1compatible bus mouseP"P>)9: Logitech1compatible P(431style mouse

P"P>)9$ Logitech1compatible (+I)T device

P"P>)9B -P 'mniboo mouse

P"P>)9C Compa= LT# Trac ball P(431style mouse

P"P>)9% Compa= LT# Trac ball serial mouse

P"P>)9# Microsoft *ids Trac ball mouse

P"P>)9) &eserved by Microsoft Input %evice Group

P"P>)3> &eserved by Microsoft Input %evice Group

P"P>)39 &eserved by Microsoft Input %evice Group

P"P>)33 &eserved by Microsoft Input %evice GroupP"P>)32 &eserved by Microsoft Input %evice Group

P"P>))) &eserved by Microsoft (ystems

9 The system BI'( should report the P(43 port! not which type of mouse is connected to that port.



33/48

Chapter ! Welcome ,,

"etwor $dapters%e)ice I% %escription

P"P6>>9 "ovell4$nthem "#23>>

P"P6>>5 Compa= "#23>>

P"P6>>7 Intel #ther#0press423

P"P6>>6 -P #thertwist #I($ L$" $dapter423 F-P3;356$

P"P6>7 ngermann1Bass "I ps or "I ps4#'TP

P"P6>;3 %#C F%#399 #therwor s MC4TP

P"P6>;2 %#C F%#393 #therwor s MC4TP B"C

P"P6>;6 %C$ 9>1MB MC$

P"P6>;5 -P MC L$" $dapter497 TP FPC3;357

P"P6>C: IBM To en &ing

P"P6>C$ IBM To en &ing II

P"P6>CB IBM To en &ing II4(hort

P"P6>CC IBM To en &ing 54971MB

P"P6>%2 "ovell4$nthem "#9>>>

P"P6>%5 "ovell4$nthem "#3>>>

P"P6>% "#9>>> compatible

P"P6>%7 "#3>>> compatible

P"P6>%; "ovell4$nthem "#9 >>T

P"P6>%6 "ovell4$nthem "#39>>

P"P6>%% (MC $&C"#TPC

P"P6>%# (MC $&C"#T PC9>>! PC3>>

P"P6>%) (MC $&C"#T PC99>! PC39>! PC3 >

P"P6>#> (MC $&C"#T PC92>4#

P"P6>#9 (MC $&C"#T PC93>! PC33>! PC37>

P"P6>#3 (MC $&C"#T PC3;>4#

P"P6># (MC $&C"#T PC7>>+! PC7 >+

P"P6>#; %#C %#PC$

P"P6>#6 %#C F%#9>> #ther+or s LC

P"P6>#: %#C F%#3>> #ther+or s Turbo

Continued



34/48

Chapter ! Welcome ,-

"etwor $dapters (continued)%e)ice I% %escription

P"P6>#$ %#C F%#9>9 #ther+or s LC4TP

P"P6>#B %#C F%#3>9 #ther+or s Turbo4TP

P"P6>#C %#C F%#3>3 #ther+or s Turbo4TP B"C

P"P6>#% %#C F%#9>3 #ther+or s LC4TP B"C

P"P6>## %#C ##9>9 Fbuilt1in

P"P6>#) %#Cpc 522 +( Fbuilt1in

P"P6>)9 2Com #therLin Plus

P"P6>)2 2Com #therLin II or IITP F61bit or 971bit

P"P6>)5 2Com To enLin

P"P6>)7 2Com #therLin 97

P"P6>); 2Com #therLin III

P"P6>)6 2Com generic #therLin Plug and Play device

P"P6>)B Thomas1Conrad TC7>5

P"P6>)C Thomas1Conrad TC7>53

P"P6>)% Thomas1Conrad TC7953

P"P6>)# Thomas1Conrad TC795

P"P6>)) Thomas1Conrad TC7353

P"P69>> Thomas1Conrad TC735

P"P69> %C$ 9>1MB

P"P69>7 %C$ 9>1MB )iber 'ptic

P"P69>; %C$ 9>1MB Twisted Pair P"P6992 &acal "I7 9>

P"P699C ngermann1Bass "I pc

P"P693> ngermann1Bass "I pc4#'TP

P"P6932 (MC (tarCard PL ( F+%46>>2(

P"P6935 (MC (tarCard PL ( with on1board hub F+%46>>2(-

P"P693 (MC #therCard PL ( F+%46>>2#

P"P6937 (MC #therCard PL ( with boot &'M soc et F+%46>>2#BT

P"P693; (MC #therCard PL ( with boot &'M soc et F+%46>>2#B

Continued



35/48

Chapter ! Welcome ,.

6et4or= Adapters continued2


P"P6936 (MC #therCard PL ( TP F+%46>>2+T

P"P693$ (MC #therCard PL ( 97 with boot &'M soc et F+%46>92#BT

P"P693% Intel #ther#0press 97 or 97TP

P"P693) Intel To en#0press 9745

P"P692> Intel To en#0press MC$ 9745

P"P6923 Intel #ther#0press 97 FMC$

P"P692; $rtisoft $#19

P"P6926 $rtisoft $#13 or $#12

P"P6959 $mplicard $C 39>4,T

P"P6953 $mplicard $C 39>4$T

P"P695B #vere0 (peedLin 4PC97 F#A3>3;

P"P69 -P PC L$" $dapter46 TP F-P3;35

P"P69 7 -P PC L$" $dapter497 TP F-P3;35;$

P"P69 ; -P PC L$" $dapter46 TL F-P3;3 >

P"P69 6 -P PC L$" $dapter497 TP Plus F-P3;35;B

P"P69 : -P PC L$" $dapter497 TL Plus F-P3;3 3

P"P69 ) "ational (emiconductor #thernode V97$T

P"P697> "ational (emiconductor $T4L$"TIC #thernode 971$T2

P"P697$ "C& To en1&ing 51MB I($

P"P697% "C& To en1&ing 97451MB I($P"P69:9 'licom 9745 To en &ing $dapter

P"P69C2 (MC #therCard PL ( #lite F+%46>>2#P

P"P69C5 (MC #therCard PL ( 9>T F+%46>>2+

P"P69C (MC #therCard PL ( #lite 97 F+%46>92#P

P"P69C7 (MC #therCard PL ( #lite 97T F+%46>92+

P"P69C; (MC #therCard PL ( #lite 97 Combo F+%46>92#+ or 6>92#+C

P"P69C6 (MC #ther#lite ltra 97

P"P69#5 Pure %ata P%I:>3 123 FTo en &ing

P"P69#7 Pure %ata P%I >6W F$rc"et

P"P69#; Pure %ata P%I 97W F$rc"etP"P69#B Proteon To en &ing FP92:>

P"P69#C Proteon To en &ing FP92:3

Continued



36/48

Chapter ! Welcome ,%

6et4or= Adapters (continued)


P"P69#% Proteon I($ To en &ing F925>

P"P69## Proteon I($ To en &ing F9253

P"P69#) Proteon I($ To en &ing F9257

P"P69)> Proteon I($ To en &ing F925;

P"P69)) Cabletron #3>>> (eries %"I

P"P63>> Cabletron #39>> (eries %"I

P"P63>: Uenith %ata (ystems U1"ote

P"P63>$ Uenith %ata (ystems "#3>>>1compatible

P"P6392 ,ircom Poc et #thernet II

P"P6395 ,ircom Poc et #thernet I

P"P639% &adi(ys #,M19>

P"P633; (MC 2>>> (eries

P"P6336 (MC :9C3 controller

P"P6329 $dvanced Micro %evices $M39>>4$M9 >>T

P"P6372 Tulip "CC197

P"P63;; #0os 9>

P"P636$ Intel : 1based #thernet

P"P636B TI3>>>1style To en &ing

P"P636C $M% PC"et )amily cards

P"P636% $M% PC"et23 FAL1bus version

P"P63:5 Ir%$ Infrared "%I( driver FMicrosoft1supplied

P"P63B% IBM PCMCI$1"IC

P"P63C3 ,ircom C#9>

P"P63C2 ,ircom C#M3

P"P6239 %#C #thernet Fall types

P"P6232 (MC #therCard Fall types e0cept 6>924$

P"P6235 $&C"#T1compatible

P"P6237 Thomas Conrad Fall $&C"#T types

P"P623; IBM To en &ing Fall types

P"P626 &emote networ access F&"$ driver

P"P626; &"$ point1to1point protocol FPPP driver P"P6266 &eserved for Microsoft networ ing components

P"P626: Peer IrL$" I& driver FMicrosoft1supplied

P"P62:> Generic networ adapter



37/48

Chapter ! Welcome ,*

SCSI and Proprietary C% "(& Adapters


P"P$>>3 )uture %omain 971;>>9B Trantor 936 (C(I controller

P"P$>9% Trantor T97> (C(I controller

P"P$>9# Trantor T226 Parallel (C(I controller

P"P$>9) Trantor T256 Parallel (C(I controller

P"P$>3> Trantor Media Aision (C(I controller

P"P$>33 $lways I"13>>> (C(I controller

P"P$>3B (ony proprietary C%1&'M controller

P"P$>3% Trantor T92b 61bit (C(I controller

P"P$>3) Trantor T2 6 Parallel (C(I controller

P"P$>2> Mitsumi L 1>> (ingle (peed C%1&'M controller W drive

P"P$>29 Mitsumi ),1>>9 (ingle (peed C%1&'M controller W drive

P"P$>23 Mitsumi ),1>>9 %ouble (peed C%1&'M controller W drive

(ound! Aideo Capture! and Multimedia%e)ice I% %escription

P"PB>>> (ound Blaster 9. sound device

P"PB>>9 (ound Blaster 3.> sound device

P"PB>>3 (ound Blaster Pro sound device

P"PB>>2 (ound Blaster 97 sound device

P"PB>>5 Thunderboard1compatible sound device

P"PB>> $dlib1compatible fre=uency modulation F)M synthesiHer device

P"PB>>7 MP 5>9 compatible

P"PB>>; Microsoft +indows (ound (ystem1compatible sound device

P"PB>>6 Compa= Business $udio

P"PB>>: Plug and Play Microsoft +indows (ound (ystem device

P"PB>>$ MediaAision Pro $udio (pectrumFTrantor (C(I1enabled! Thunder Chip1disabled

P"PB>>B MediaAision Pro $udio 21%

Continued



38/48

Chapter ! Welcome ,+

Sound$ >ideo Capture$ and &ultimedia continued2


P"PB>>C Music uest M ,123M

P"PB>>% MediaAision Pro $udio (pectrum BasicFno Trantor (C(I! Thunder Chip1enabled

P"PB>># MediaAision Pro $udio (pectrumFTrantor (C(I1enabled! Thunder Chip1enabled

P"PB>>) MediaAision QaHH197 chip set F'#M versions

P"PB>9> $uravision A0P >> chip set>> Compa= 955>> modem FTB%

P"PC>>9 Compa= 35>>4:7>> modem FTB%



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,'

(ee also the -ardware Glossary available onhttpE44www.microsoft.com4hwdev4glossary.htm.

Acronyms and A00re)iationsACPI $dvanced Configuration andPower Interface

A6SI $merican "ational (tandards Institute

API application programming interface

APIC $dvanced Programmable InterruptController

A"C $dvanced &I(C Computing

ASCII $merican (tandard Codefor Information Interchange

A IBM registered trademar for PC4$T

A A $T $ttachment

A API $T$ Pac et Interface

B%A BI'( %ata $rea

BI(S basic I4' system

CI% Compatible I%

C&(S complementary metal1o0ide semiconductor

C(& 9. Component 'b/ect Model 3. legacyserial port.

%%7 driver development it

%LL dynamic lin library

%&A direct memory access

CP e0tended capabilities port

I% #nhanced Integrated %evice #lectronics

ISA e0tended I($

PP enhanced parallel port

SC% #0tended (ystem Configuration %ata

C% floppy dis controller

I ( first in4first out

+B gigabyte

:CL -ardware Compatibility List

:C -ardware Compatibility Tests

I% Integrated %evice #lectronics

I Institute of #lectrical and #lectronics#ngineers

I:> independent hardware vendor

I'( input4output

I(C L I4' control

IPL initial program load

I"P I4' re=uest pac et

I"# interrupt re=uest

ISA Industry (tandard $rchitecture

LA6 local area networ

LBA logical bloc addressing

L % light1emitting diode

LP line printer

L?6 logical unit number

&B megabyte&S%6 Microsoft %eveloper "etwor

6&I "onmas able Interrupt

( & original e=uipment manufacturer

PCI Peripheral Component Interconnect

PI( programmed I4'

Plug and Play and Legacy !e ice "upport

1997-199# Intel Corporation and Microsoft Corporation. All rights reser ed.

Glossary


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P(S power1on self1test

PS'2 Personal (ystem43

"A& random access memory

"ISC reduced instruction set computing

"(& read1only memory

rt real time

SCSI small computer system interface

S%7 software developers it

S (mall )orm )actor

SI+ (pecial Interest Group

S>+A (uper AG$

?A" niversal $synchronous&eceiver4Transmitter

?PS uninterruptible power supply

>+A video graphics array

W:#L +indows -ardware uality Laboratory

2ardware 1lossary

AACPI $dvanced Configuration and Power Inter1

face. $ specification that defines a new interface tothe system board that enables the operating systemto implement operating system


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1lossary -!

C(& 9. Component 'b/ect Model the core of'L#. %efines how 'L# ob/ects and their clients

interact within processes or across process boundaries. 3. Legacy serial port.

CP? Central processing unit. $ computational andcontrol unit of a computer the device that interpretsand e0ecutes instructions. By definition! the CPis the chip that functions as the ?brain@ of thecomputer.

4data rate The speed of a data transfer process!normally e0pressed in bits per second or bytes persecond.

%%C %isplay data channel. The Plug and Play baseline for monitors. The communications channel between a monitor and the display adapter to whichit is connected. This channel provides a method forthe monitor to convey its identity to the displayadapter.

de)ice $ny circuit that performs a specific function!such as a parallel port.

de)ice I% $ uni=ue $(CII string for a devicecreated by enumerators to identify a hardware deviceand used to cross1reference data about the devicestored in the registry. %istinguishes each logicaldevice and bus from all others on the system.

%LL %ynamic lin library. $PI routines thatser1mode applications access through ordinary procedure calls. The code for the $PI routine is notincluded in the userJs e0ecutable image. Instead! theoperating system automatically points the e0ecutableimage to the %LL procedures at run time.

%&A %irect memory access. $ method of movingdata from a device to memory For vice versa withoutthe help of the microprocessor. The system boarduses a %M$ controller to handle a fi0ed number ofchannels! each of which can be used by only onedevice at a time.

dri)er *ernel1mode code used either to control or

emulate a hardware device.

5CP #0tended capabilities port. $n asynchronous!

61bit


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1lossary -/

I6I *ile InitialiHation file. Commonly used under+indows 2. and earlier! I"I files have been used

by both the operating system and individual applica1tions to store persistent settings related to an appli1cation! driver! or piece of hardware. In +indows 231

bit operating systems! I"I files are supported for bac ward compatibility! but the registry is the preferred location for storing such settings.

input class The class of filters that provides aninterface for -I% hardware! including (B andlegacy devices! plus proprietary and other -I%hardware! under the +%M -I% architecture.

integrated de)ice $ny device such as a parallel port or graphics adapter that is designed on thesystem board rather than on an e0pansion card.

inter*ace )or parameters on a connection re=uest! aspecific set of methods and properties implementedon a medium that a filter connection uses tocommunicate! such as a specific set of I'CTLs.

I'( Input4output. Two of the three activities thatcharacteriHe a computer Finput! processing! andoutput . &efers to the complementary tas s ofgathering data for the microprocessor to wor withand ma e the results available to the user through adevice such as the display! dis drive! or printer.

I(C L Input4output control. $ custom class ofI&Ps available to ser mode. #ach +%M classdriver has a set of I'CTLs that it uses to communi1cate with applications. The I'CTLs give the classdriver information about intended usage byapplications. The class driver performs all I'CTL

parameter validation.

IPL Initial program load. $ device used by thesystem during the boot process to load an operatingsystem into memory.

I"P I4' re=uest pac et. %ata structures that driversuse to communicate with each other. The basicmethod of communication between ernel1modedevices. $n I&P is a ey data structure for +%M!which features multiple layered drivers. In +%M!every I4' re=uest is represented by an I&P that is

passed from one driver layer to another until there=uest is complete. +hen a driver receives an I&P!it performs the operation the I&P specifies! and theneither passes the I&P bac to the I4' Manager fordisposal or onto an ad/acent driver layer. $n I&P

pac et consists of two partsE a header and the I4'stac locations.

I"# Interrupt re=uest. $ method by which a devicecan re=uest to be serviced by the deviceJs software

driver. The system board uses a PIC to monitor the priority of the re=uests from all devices. +hen are=uest occurs! a microprocessor suspends thecurrent operation and gives control to the devicedriver associated with the interrupt number issued.The lower the number for e0ample! I& 2 thehigher the priority of the interrupt. Many devicesonly support raising re=uests of specific numbers.

ISA Industry (tandard $rchitecture. $n 61bitFand later! a 971bit e0pansion bus that provides a

buffered interface from devices on e0pansion cardsto the internal bus.

6=ernel The core of the layered architecture thatmanages the most basic operations of the operatingsystem! such as sharing the processor betweendifferent bloc s of e0ecuting code! handlinghardware e0ceptions! and other hardware1dependentfunctions.

=ernel mode The processor mode that allows full!unprotected access to the system. $ driver or threadrunning in ernel mode has access to systemmemory and hardware.

=ernel mode dri)er %river for a logical! virtual! or physical devices.

LLA6 Local area networ . $ group of computersand other devices dispersed over a relatively limitedarea and connected by a communications lin thatenables any device to interact with any other deviceon the networ . Co#pare wit +$".

legacy $ny feature in the system based on oldertechnology for which compatibility continues to bemaintained in other system components.

local 8us sually refers to a system bus directlyconnected to the microprocessors on a system board.

sed collo=uially to refer to system board busesthat are located closer to the microprocessor thane0pansion buses Fthat is! with less buffering ! whichare therefore capable of greater throughput.




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Mminidri)er $ hardware1specific %LL that uses aMicrosoft1provided class driver to accomplish mostactions through functions call and provides onlydevice1specific controls.

monolithic dri)er $ driver that has many differentclasses of functionality contained in the same driver.

mother8oard See system board.

multi*unction de)ice $ piece of hardware thatsupports multiple! discrete functions! such as audio!mi0er! and music! on a single adapter.

7ni88le mode $n asynchronous! peripheral1to1hostchannel defined in the I### 936519:55 standard.Provides a channel for the peripheral to send data tothe host! which is commonly used as a means ofidentifying the peripheral.

6&I "onmas able Interrupt. $n interrupt thatcannot be overruled by another service re=uest. $hardware interrupt is called nonmas able if it cannot

be mas ed by the processorJs interrupt enable flag.

O( & 'riginal e=uipment manufacturer. sed

primarily to refer to systems manufacturers.

option "(& 'ptional read1only memory foundon an e0pansion card. 'ption &'Ms usually containadditional firmware re=uired to properly boot the

peripheral connected to the e0pansion card! fore0ample! a hard drive.

PPCI Peripheral Component Interconnect. $ 231bitor 751bit bus designed to be used with devices thathave high bandwidth re=uirements! such as thedisplay subsystem.

planar See system board.

Plug and Play $ design philosophy and set ofspecifications that describe hardware and softwarechanges to the system and its peripherals thatautomatically identify and arbitrate resourcere=uirements among all devices and buses on thesystem. Plug and Play specifies a set of device driverinterface elements that are used in addition to! not in

place of! e0isting driver architectures.

port $ connection or soc et used to connect adevice such as a printer! monitor! or modem tothe computer. Information is sent from the computerto the device through a cable.

port dri)er $ low1level driver that responds to aset of system1defined device control re=uests and

possibly to an additional set of driver1definedFprivate device control re=uests sent down by acorresponding class driver. $ port driver insulatesclass drivers from the specifics of host bus adaptersand synchroniHes operations for all its class drivers.

P(S Power1on self1test. $ procedure of thesystem BI'( that identifies! tests! and configuresthe system in preparation for loading the operatingsystem.

R"A& &andom access memory @(emiconductor1

based memory that can be read and written by themicroprocessor or other hardware devices. &efers tovolatile memory! which can be written as well asread.

registry In +indows 231bit operating systems! thetree1structured hierarchical database where generalsystem hardware and software settings are stored.The registry supersedes the use of separate I"I filesfor all system components and applications that

now how to store values in the registry.

resource 9. $ set from which a subset can beallocated for use by a client! such as memory or bus

bandwidth. This is not the same as resources that areallocated by Plug and Play. 3. $ general term thatrefers to I& signals! %M$ channels! I4' portaddresses! and memory addresses for Plug and Play.

"ISC &educed instruction set computing. $ typeof microprocessor design that focuses on rapid andefficient processing of a relatively small set ofinstructions. &I(C architecture limits the number ofinstructions that are built into the microprocessor!

but optimiHes each so it can be carried out veryrapidly usually within a single cloc cycle.

rt &eal time. In computing! refers to an operatingmode under which data is received and processedthe results are returned instantaneously.




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SSCSI (mall computer system interface.

Pronounced ?scuHHy.@ $n I4' bus designed as amethod for connecting several classes of peripheralsto a host system without re=uiring modifications togeneric hardware and software.

static resources %evice resources! such as I&signals! %M$ channels! I4' port addresses! andmemory addresses! that cannot be configured orrelocated.

S>+A (uper AG$. $ video standard established by A#($ to provide high1resolution color display onIBM1compatible computers.

system 8oard A(so motherboard or planar. The primary circuit board in a system that containsmost of the basic components of the system.

system de)ices %evices on the system board! suchas interrupt controllers! eyboard controller! real1time cloc ! %M$ page registers! %M$ controllers!memory controllers! )%C! $T$ ports! serial and

parallel ports! PCI bridges! and so on. In todayJssystems! these devices are typically integrated inthe supporting chip set.

8?A" niversal $synchronous &eceiver4Transmitter. $ module composed of a circuitthat contains both the receiving and transmittingcircuits re=uired for asynchronous serialcommunication.

?PS ninterruptible power supply. $ deviceconnected between a computer and a power sourcethat ensures that electrical flow to the computer isnot interrupted because of a blac out and! in mostcases! protects the computer against potentiallydamaging events such as power surges and

brownouts.

user mode The nonprivileged processor mode inwhich application code e0ecutes! including protectedsubsystem code in +indows "T 5.> and+indows 3>>>.

user mode dri)ers +in231based multimediadrivers and A%%s for M(1%'(>> %%*.

WW:#L +indows -ardware uality Labs.Provides testing services for hardware and driversfor +indows 231bit operating systems. (eehttpE44www.microsoft.com4hwtest4.

Win32 API $ 231bit application programminginterface for +indows 231bit operating systems thatincludes sophisticated operating system capabilities!security! and $PI routines for +indows1basedapplications.




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971bit I4' decoding! 99! 953#6h and 3)6h! I($ I4' standard address! 9;2#6h and 2)6h! I($ I4' standard address! 9;6>53

chip! 3>Plug and Play re=uirements! 9>

$C* Fac nowledgment codes! 39codes

eyboard ports and peripherals! 39mouse ports and pointing devices! 39

$CPI F$dvanced Configuration and Power Interfacelegacy devices! 9>

parallel port base addresses! 9:addresses

3;6h! 962;6h! 962BC! 962C>h! 9:2)3h! 392)5h! 392) h! 397>h! 3975h! 39I($ I4' standard 9;I($1compatible addresses! 9>

$dvanced &I(C computing F$&C interface! parallel ports! 9:

$(CII values in device I%s! 9:! 3>

asset numbers assigned to hardware! 9>asynchronous receivers F niversal $synchronous

&eceiver4Transmitter ! 9;audio components! device I%s! 2;126automatic configuration. See resource configurationBI'(

device I%s! 2>129I($ devices reported through! 9

parallel port addresses! 9:Plug and Play! 93192BI'( %ata $rea FB%$ ! 9:

boot devices! option &'Ms! 99! 92195! 97 buses

device I%s ! 2>legacy serial port re=uirements! 9;196re=uirements! 9>

C%1&'M devices! proprietary adapter device I%s! 2712;

C(arification to P(ug and P(a" ISA Specification, :CL$(( ey! 3>compatibility mode! 9:Compatible I%

Compatible I% FCI% ey! 3>obtaining vendor codes! 99P"P suffi0! 99! 9 197

conflict resolution. See resource conflictsconnectors

%B3 ! 9:I### 9365! 9:

parallel ports! 9:controllers

dis controllers! 3:interrupt! 9>interrupt! 3;

%B3 connector! 9:%#C $lpha systems! parallel port base addresses! 9:

decoding! 971bit I4'! 99! 95%#(C&IPTI'" ey! 3

plug and play guidelines legacy

Documents