“Planning for Dry Run: material for discussion”

Gianluca Lamanna (CERN)

TDAQ meeting 23.05.2012

When?• The dry run will start the 15 of July:

– All the people involved should be available by this date

– Overlap with the Analysis week– Possible delay in the installation of fibers

& cabling infrastructure• The dry run will finish the 15 of

August:– The subsystems people are kindly

request to be available until August 15– The actual Dry Run will finish with the

begin of the technical Run (October).

2012 layoutNA62 / 2012 Layout

LKrSLM readout + CREAM Prototype ?

MUV 2+3½ Straw

Chamber

CHANTIPrototype

8 LAV, 3 with Readout

CEDAR≈50% equipped

Temp. Beam Pipe

CHODSAC

• CEDAR (no KTAG), CHANTI, LAV, CHOD, LKr, MUV2/3, SAC/IRC; STRAW as “Observer” • Most of the support infrastructure (fibers, network, control room, pc farm room, …) will be ready at the end of June… with some possible delay

What is provided?• Most of the infrastructure up to the readout rack (LTU,

TTCex, clock fiber, switch, choke & error cables, TEL62 server, gigabit fiber to the router, patch panels…)

• Crates, TEL62, TDCB, LAVFEE & Cables will be provided according to your request, but, after test and validation , they are placed under subdetector responsibility (in any case the experts will be around for the whole dry run)

• Cabling from TEL62 to patch panel and switch should be provided by the subdetector (for instance: CCPC ethernet cables, data ethernet cables, Choke/error cables,…)

• Think what you need and ask in case of doubt!

Readout program

TTC clock and trigger

TEL62 r/o fw

TDCB fw

L0TPControl Program

CCPC server

Framework for event display

CDRSub-detector system (FEE, TEL62, Crates, TDCB, cables, …)

Timeline

Setup

Trigger test

SynchronizationPulser test

Control lines test

Trigger primitive test

Infrastructure test

Additional tests

July 15

August 15

Technical run

Lab tests and pre-installation

Setup• Electronics commissioning:

– FEE setup and tests (thresholds, noise, …)– Standalone test:

• Ancillary monitor systems in TEL62• Local sniffer , simplified version of readout program

• Network test– The TEL62 send packets on the network (auto-trigger)

• Clock installation and test• Farm installation and test• LKr

– Test of the SLM readout– The SLMs send packet to the PCFARM

• The TALK board produces and receives triggers (self test)

Electronics# channels (in 2012)

FEE R/O

CEDAR 128 16 (dr) CEDAR board

TDCB+TEL62

CHANTI 46 4 (dr) Chanti board + LAV FEE

TDCB+TEL62

LAV 480 LAV FEE TDCB+TEL62STRAW ~1800 Cover Board

+ SRBTEL62

CHOD 128 LAV FEE TDCB+TEL62LKR ~5000 CPD+SLM PCsMUV2 88 LAV FEE TDCB+TEL62MUV3 <296 CFD+TRAM TDCB+TEL62IRC/SAC 8 LAV FEE TDCB+TEL62

Electronics inventoryDetector LAVFE

ECHANTI 2LAV 15

CHOD 4

MUV2 9

SAC/IRC 1

Detector # ch TDCBCEDAR 128 1CHANTI 46 1LAV 480 9

CHOD 128 2MUV1/2 264(88) 2MUV3 296 3SAC/IRC 4 1

Detector TEL62CEDAR 1CHANTI 1LAV 3

STRAW 1

CHOD 1LKR/L0 3MUV1/2 1MUV3 1SAC/IRC 1

Trigger test• LTUs and TTC

messages test• Trigger transmission:

– The TALK board sends triggers requests

– The TEL62s count the triggers and provide the total number of trigger at the special trigger “End of Burst”

• Test of TALK-TAXI trigger distribution

• LTU test in standalone mode

PP

PP

PP

PP

SL

TTC

TAXI

TALK FPGA

To CPD

to R/O PC

TEL62

Synchronization test• Start of burst & End of

Burst– Test of SOB & EOB signals

transmission to the TEL62– Test of SOB & EOB to

PCFARM• Synchro system test:

– The TALK board sends a special “synchro” trigger

– The TEL62s send a packet with the timestamp

– The offset (theoretically = 0) for each TEL62 is computed

• Measure of the offset of the timestamp distributed to the CPD and the trigger timestamp

L0TP

TTC

TTC

TTC

TEL62

TEL62

TEL62

Fine time synchronization• The fine time synchronization can’t be

done in the Dry Run• Set up everything is needed for the

technical run• Think the strategy for time synchro

procedure and monitoringdet1 det2

FEEFEE

TDC TDC

DT1,0

DT1,1

DT2,0

DT2,1

DTtof

Pulser test• At predefined timestamps the

TDCB will send a pulse on the last TDC-cable pair (problem with MUV3)– The TALK board will ask for this

event 1ms later– Test of reconstruction & event

display– Specific test for sub-detectors

• LKr calibration:– Test of the TALK board LKr

calibration system

PulserTDCB

TTC

Data

TEL62

TALK

Cedar NINO Board

1 ms0xC1A0C1A0

0xC1A0C1A0

time

TEL62 Detector

TALK

Pulse at

Trigger at

Control lines test• Test of choke & error

– TEL62 generate (fake) choke and error– The TALK board stops the triggers, sends

special trigger choke/error on, waits for choke/error off, etc etc

– Test of the LTU counters– Test of the CHEF board– The TEL62 provide a summary of

choke/error in the EOB

Control lines test

Trigger decision test• Test the TALK board capability to generate

trigger decisions:– Fake internal primitives generated by LEMO

signals (problem with MUV3)– Trigger based on real primitives coming through

ethernet– Offline reconstruction of the trigger decision (min

bias)

Additional test• GPU• CDR in critical conditions (buffering,

high bandwidth (<1 Gb/s), …)• Network high rate capability• PC Farm high rate with L1 “fake”

algorithms • Preparation of the procedure for TDC

synchronization during the technical run

• …

Infrastructure test• Network, TTC fibers, Choke&Error

physical structure, Control Program, Readout software, CCPC server, Event display, CDR, …

• Two phases:– Commissioning

• Before the dry run (if it’s possible)– PC Farm, Control Program, CCPC server,…

– Characterization• During the dry run

Common systems people• TEL62, TDCB: Marco, Bruno, Stefano,

Franco, Elena, …• LAV FEE: Mauro R., Francesco G.,…• PC Farm SW & HW: Jonas, Paolo• TTC & LTU: Marian, Roman, Vlado,…• TALK: Riccardo, Gianluca, Dominique• Control Program: Nicolas• Network: Riccardo, Alberto,Gianluca,

…• CDR: ???

Conclusions• The success of most of the tests depends critically on

the TEL62 and TALK FW:– The TEL62 firmware is still in critical condition in some part– In the TALK firmware some (small) part is still missed – Pisa and CERN will work deeply in the next month to guarantee

a minimum set of “features” in both side• Network and PC Farm tests are essential to prepare

data acquisition for the technical run• The commissioning and the test of the whole

electronics chain for every sub-detectors is very important to ensure an effective data taking in the technical run.

• The prototypes of all the ancillary systems (Control program, CCPC server, framework for event display, CDR,…) will be tested during the dry run.