placement by simulated annealing. simulated annealing simulates annealing process for placement ...
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Placement by Simulated Annealing
Simulated Annealing
Simulates annealing process for placement Initial placement
− Random positions
Perturb by block exchanging If Δcost < 0, acceptotherwise, may still accept if const increase is not
too much− Too much increase?− Depends on the algorithm stage
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Search Space
Cost
Avoids getting trapped in local minimum
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Input: set of all cells VOutput: placement P
T = T0 // set initial temperature
P = PLACE(V) // arbitrary initial placementwhile (T > Tmin)
while (!STOP()) // not yet in equilibrium at T new_P = PERTURB(P) Δcost = COST(new_P) – COST(P) if (Δcost < 0) // cost improvement P = new_P // accept new placement else // no cost improvement r = RANDOM(0,1) // random number [0,1) if (r < e -Δcost/T) // probabilistically accept P = new_P T = α ∙ T // reduce T, 0 < α < 1
Simulated Annealing – Algorithm
Temperature Reduction Function
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Tem
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Cost Decrease
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1 51 101 151 201 251 301 351 401
Co
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SA Parameters
• Quality of result depends largely on parameters:
Initial Temperature Final Temperature Stop Criterion Cooling Schedule Move (Perturb) Function Cost Function
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VPR Package
V. Betz and J. Rose, “VPR: A new packing, placement and routing tool for FPGA research,” International Workshop on Field-Programmable Logic and Applications, 1997.
J. Luu, I. Kuon, P. Jamieson, T. Campbell, A. Ye, M. Fang, and J. Rose, “VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling,” in Int’l Symp. on Field-Programmable Gate Arrays, Feb. 2009, pp. 133–142.
VPR 5.0, http://www.eecg.utoronto.ca/vpr. VPR 6.0, Beta Release, May 30, 2011
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Placement can Make A Difference
MCNC Benchmark circuit e64 (contains 230 4-LUT). Placed to a FPGA.
Random InitialPlacement
FinalPlacement
After DetailedRouting
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TimberWolf Package
Based on simulated annealing Handles both placement and routing
• Design styles: gate-array, standard-cell macrocell
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TimberWolf Gate-Array Placement
• State: An assignment of the gates to the gate positions.
• Move Interchange 2 gates, OR Move a gate to a vacant position.
• Cost Function Total wire length estimation Congestion
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Cooling Schedule Initial temperature: 4x106
Final temperature: 1
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0.8
0.8
0.95
IToolswww.internetcad.com
Variable die
33% smaller
Translator, Floorplanner, Standard Cell Placer, Gate Array Placer, Global Router & Detail Router
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TimberWolf for Standard Cell
• Perturbs:MoveSwapMirror around y-axis
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Range LimiterWhat pairs of modules can be
interchanged?• Range Limiter for Move:
At the beginning, (WT, HT) is very large
− big enough to contain the whole chip.
Window size shrinks slowly as the temperature decreases.
− Height and width log(T).
Stage 2: window size is so small− No inter-row module interchanges
are possible.
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TimberWolf for Standard Cell
• Stage 1 (at high temperature): Move cells between different rows as well as
within the same row.Allow overlapping of cells.Minimize the total wire length, cell overlapping,
and differences in row lengths.
• Stage 2 (at low temperature):Remove overlapping from the solution of Stage 1.Exchange adjacent cells.Minimize total wire length.
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Cost Function
),(2 2 jioverlapCostcellsji
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ithDesRowLengithActRowLengCost |)()(|3
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iVweightiyspaniHwieghtixspanCost
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yspan
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• Advantages: Can find global optimum (given sufficient time) Well-suited for detailed placement
• Disadvantages: Very slow To achieve high-quality implementation, laborious parameter tuning
is necessary Randomized, chaotic algorithms - small changes in the input
lead to large changes in the output
• Practical applications of SA: Small placement instances with complicated constraints Detailed placement, where SA can be applied in small windows FPGA layout, where complicated constraints
Simulated Annealing
Tabu Search
From a solution s, find a set of solutions in this neighborhood N(s).
• Tabu List (T): Recently tried movements
− To avoid loop. Select a solution from N(s) – T with minimum cost.
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Probabilistic Congestion Estimation
M. Saeedi, M. Saheb Zamani, A. Jahanian, “Evaluation, prediction and reduction of routing congestion,” Microelectronics Journal, Elsevier, 2007.
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Channelless Standard Cell
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Probabilities
The probability of a v-bend path from bin (i, j) to bin (n,m) to pass through the horizontal/vertical track (x, y).
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Stataistics
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Congestion Estimation
The number of all possible paths from bin (i,j) to bin (n,m) which pass through the horizontal/vertical track in bin (x,y)
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from bin (i,j) to bin (n,m)24
Congestion Map
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