pipecheck hands-on mcm... · 2019. 7. 3. · simplesc: an sc microarchitecture •partially...

PipeCheck Hands-On

Overview▪Will take you through modelling simple uarches in µSpec

▪ simpleSC: An SC microarchitecture

• Partially completed uarch specification in VM, you will fill in remainder

▪ Initially, will look at verifying individual litmus test programs

▪ Later, will look at verifying across all programs (an infinite space!)

The simpleSC Microarchitecture

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 13-stage

in-order

pipelines


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Loads

access

Mem in

Execute

stage


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Stores sent

to Memory

during

Writeback

Stores sent

to Memory

during

Writeback


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Stores sent

to Memory

during

Writeback

Stores sent

to Memory

during

Writeback

1. Start VirtualBox VM

2. Open a Terminal

3. Partially completed SC uarch in/home/check/pipecheck_tutorial/uarches/SC_fillable.uarch

µSpec: A DSL for Specifying Microarchitectures▪ Language has capabilities similar to first-order logic (FOL)

• forall, exists, AND (/\), OR (\/), NOT (~), implication (=>)

• Has a number of built-in predicates which take memory operations as input

− e.g. ProgramOrder i j where i and j are loads/stores

− Other predicates include SamePhysicalAddress, SameData, IsAnyRead, …• See “Check Quick Start” handout for a more extensive list

• Predicates can also reference nodes and edges

− e.g. EdgeExists ((i1, Fetch), (i2, Fetch))

− This predicate is true iff an edge exists between i1 and i2’s Fetch stages

• All µhb edges are transitive (so µSpec is not a subset of FOL)

µSpec: A DSL for Specifying Microarchitectures▪Microarchitecture spec has three components:

• Stage identifier definitions

• Macro definitions (optional)

• Axiom definitions

▪Macros allow:

• decomposition of axioms into smaller parts

• reuse of uspec fragments

▪Axioms are each a partial ordering on the events in an execution

▪ Job of PipeCheck is to ensure that these axioms correctly work together to uphold ISA-level MCM requirements for a litmus test

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writeback

Execute

Fetch

Core 0

Memory Hierarchy

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writeback

Execute

Fetch

Core 0

Stores and loads go through

the pipeline stages in order

Memory Hierarchy

The Instr_Path Axiom

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writeback

Execute

Fetch

Core 0

Stores go through the

pipeline stages and reach

memory in order

Memory Hierarchy

Axiom “Instr_Path":forall microops "i",AddEdges [((i, Fetch), (i, Execute), "path");

((i, Execute), (i, Writeback), "path")].


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writeback

Execute

Fetch

Core 0



memory in order

Memory Hierarchy



Axiom

name


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writeback

Execute

Fetch

Core 0



memory in order

Memory Hierarchy



Microop: A single load/store op.

May correspond to an ISA instr,

or part of an ISA instr.


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writeback

Execute

Fetch

Core 0



memory in order

Memory Hierarchy



For all load/store ops…


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writeback

Execute

Fetch

Core 0



memory in order

Memory Hierarchy



Add edges from Fetch to Execute, and

Execute to Writeback

Specifying µSpec Nodes▪A node represents a particular event in a particular instruction’s

execution

▪ Format for nodes is: (instr, stage/event_name)

▪Thus, (i, Fetch) represents the fetch stage of instruction i…

µhb Graphs for co-mp Using AxiomsEach column represents an instruction flowing

through the pipeline

(i1) (i2)

Fetch

Execute

Writeback

(i3) (i4)

Thread 0 Thread 1

i1: Store [x] 1i2: Store [x] 2

i3: r1 = Load [x]i4: r2 = Load [x]

SC Forbids: r1=2, r2=1, Mem[x] = 2

Edges added according to Instr_Pathaxiom

Initially, Mem[x] = 0

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Fetchi1

Fetchi2

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1All instructions on the

same core go through

Fetch in program

order

Fetchi1

Fetchi2

The PO_Fetch Axiom

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch



Fetch in program order

FetchAxiom "PO_Fetch":forall microops "i1",forall microops "i2",SameCore i1 i2 /\ ProgramOrder i1 i2 =>AddEdge ((i1, Fetch), (i2, Fetch), "PO", "blue").

The PO_Fetch Axiom

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch





Use of predicates to check that instrs are

on the same core and in program order

The PO_Fetch Axiom

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch





Add edge from Fetch stage of earlier

instruction to Fetch stage of later instruction



(i1) (i2)

Fetch

Execute

Writeback

(i3) (i4)

Thread 0 Thread 1







(i1) (i2)

Fetch

Execute

Writeback

(i3) (i4)

Thread 0 Thread 1




Edges Added Using PO_Fetch axiom


Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Executei1

Fetchi1

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Executei1

Fetchi1

Executei2

Fetchi2

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

If two instructions on

the same core go

through Fetch in order,

they will go through

Execute in the same

order

Executei1

Fetchi1

Executei2

Fetchi2

The Execute_Stage_Is_In_order Axiom

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1If two instructions on the


Fetch in order, they will

go through Execute in the

same order

Execute

FetchAxiom "Execute_stage_is_in_order":forall microops "i1",forall microops "i2",SameCore i1 i2 /\EdgeExists ((i1, Fetch), (i2, Fetch), "") =>AddEdge ((i1, Execute), (i2, Execute), "PPO").


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch





same order

Execute


If instructions on same core

go through Fetch in order…


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch





same order

Execute


…then they go through

Execute in the same order.

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Fetchi1

Writebacki1

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Fetchi1

Writebacki1

Fetchi2

Writebacki2

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1


the same core go

through Fetch in order,

they will go through

Writeback in the same

order

Fetchi1

Writebacki1

Fetchi2

Writebacki2

The Writeback_Stage_Is_In_Order Axiom

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch




go through Writeback in

the same order

Fetch

Writeback

Axiom "Writeback_stage_is_in_order":forall microops "i1",forall microops "i2",________ i1 i2 /\EdgeExists ((i1, _____), (i2, _____), "") =>AddEdge ((i1, _________), (i2, _________), "PPO").

If two instructions on the same core go through Fetch in

order, they will go through Writeback in the same order

The Writeback_Stage_Is_In_Order Axiom

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch




go through Writeback in

the same order

Fetch

Writeback

Axiom "Writeback_stage_is_in_order":forall microops "i1",forall microops "i2",________ i1 i2 /\EdgeExists ((i1, _____), (i2, _____), "") =>AddEdge ((i1, _________), (i2, _________), "PPO").

Axiom "Writeback_stage_is_in_order":forall microops "i1",forall microops "i2",SameCore i1 i2 /\EdgeExists ((i1, Fetch), (i2, Fetch), "") =>AddEdge ((i1, Writeback), (i2, Writeback), "PPO").

If two instructions on the same core go through Fetch in

order, they will go through Writeback in the same order



(i1) (i2)

Fetch

Execute

Writeback

(i3) (i4)

Thread 0 Thread 1







(i1) (i2)

Fetch

Execute

Writeback

(i3) (i4)

Thread 0 Thread 1




Edges fromExecute_stage_is

_in_order & Writeback_stage

_is_in_orderaxioms


Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Memory Hierarchy

Writebacki1 Writebacki2

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Memory Hierarchy

All writes to the same address must be

totally ordered at memory.

(coherence order)


Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Memory Hierarchy



(coherence order)


i1: Store y=1 i2: Store y=2

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Memory Hierarchy



(coherence order)



OR

Coherence order:

The WriteSerialization Axiom

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1


the same core go

through Writeback in

order, they must reach

the Memory Hierarchy

in the same order

Writebacki1

Writebacki2

Memory Hierarchy

Axiom "WriteSerialization":forall microops "i1",forall microops "i2",( ~(SameMicroop i1 i2) /\ IsAnyWrite i1/\ IsAnyWrite i2 /\ SamePhysicalAddress i1 i2) =>(EdgeExists ((i1, Writeback), (i2, Writeback)) \/EdgeExists ((i2, Writeback), (i1, Writeback))).


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1


the same core go




in the same order

Writebacki1

Writebacki2

Memory Hierarchy


Two different writes to the

same address


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1


the same core go




in the same order

Writebacki1

Writebacki2

Memory Hierarchy


Either i1 is before i2 in

coherence order, OR vice-versa.

µhb Graphs for co-mp Using Axioms

Thread 0 Thread 1




WriteSerialization axiom


Thread 0 Thread 1





Two solutions;

Each enumerated separately(i1) (i2)

Fetch

Execute

Writeback

(i3) (i4) (i1) (i2)

Fetch

Execute

Writeback

(i3) (i4)


Thread 0 Thread 1





Two solutions;

Each enumerated separately

We will focus on left

graph going forward

(i1) (i2)

Fetch

Execute

Writeback

(i3) (i4) (i1) (i2)

Fetch

Execute

Writeback

(i3) (i4)

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Memory Hierarchy


i1: Store y=1 i2: Store y=2OR

Coherence order:

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Memory Hierarchy



Coherence order:

Test requires

y_final = 2

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Memory Hierarchy

If a litmus test requires that an address has the value

of a certain write at the end of the test, that write must

be the last to reach memory.



Coherence order:

Test requires

y_final = 2

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Memory Hierarchy

If a litmus test requires that an address has the value

of a certain write at the end of the test, that write must

be the last to reach memory.



Coherence order:

Test requires

y_final = 2

Enforced by test

EnforceFinalWrite axiom in the µSpec

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebacki1 Executei2

Memory Hierarchy

Executei1

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebacki1 Executei2

Memory Hierarchy

Executei1

A write must complete

its writeback before

loads/stores on the

same core that are

fetched after the write.

(otherwise the write could

be reordered with later

writes or later reads)

The EnforceWritePPO Axiom

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1


the same core go




in the same order

Writebacki1

Writebacki2

Memory Hierarchy

Axiom "EnforceWritePPO":forall microop "w",forall microop "i",(__________ w /\ ________ w i/\ EdgeExists((w, Fetch), (i, Fetch), "")) =>

AddEdge ((w, _________), (i, _______)).

A write must complete its writeback before execution of

loads/stores on the same core that are fetched after the

write.

The EnforceWritePPO Axiom

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1


the same core go




in the same order

Writebacki1

Writebacki2

Memory Hierarchy

Axiom "EnforceWritePPO":forall microop "w",forall microop "i",(__________ w /\ ________ w i/\ EdgeExists((w, Fetch), (i, Fetch), "")) =>

AddEdge ((w, _________), (i, _______)).

A write must complete its writeback before execution of

loads/stores on the same core that are fetched after the

write.

Axiom "EnforceWritePPO":forall microop "w",forall microop "i",(IsAnyWrite w /\ SameCore w i/\ EdgeExists((w, Fetch), (i, Fetch), "")) =>

AddEdge ((w, Writeback), (i, Execute)).



(i1) (i2)

Fetch

Execute

Writeback

(i3) (i4)

Thread 0 Thread 1







(i1) (i2)

Fetch

Execute

Writeback

(i3) (i4)

Thread 0 Thread 1




Edge added by EnforceWrite

PPO axiom


Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebacki1

Execute

Y = 0

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1If a load reads the initial value

of a memory location, it must

execute before any write to

that location reaches Mem.

Writebacki1

Execute

Y = 0

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch





Writebacki1

i: Load y=0

Execute

Y = 0

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch





Writebacki1

w: Store y=1 i: Load y=0

Execute

Y = 1

The BeforeAllWrites Macro

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch





Writebacki1


Execute

Y = 0Y = 1

DefineMacro "BeforeAllWrites":DataFromInitialStateAtPA i /\forall microop "w", ((IsAnyWrite w /\ SamePhysicalAddress w i/\ ~SameMicroop i w) =>AddEdge ((i, _______), (w, _________))).


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch





Writebacki1


Execute

Y = 0Y = 1


Macro: This is a µSpec fragment

that can be instantiated as part

of a larger axiom


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch





Writebacki1


Execute

Y = 0Y = 1


Check that the load reads

the data from the initial

state of the litmus test


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch





Writebacki1


Execute

Y = 0Y = 1


If a load reads the initial value of a memory location, it

must execute before any write to that addr completes its

writeback.


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch





Writebacki1


Execute

Y = 0Y = 1


DefineMacro "BeforeAllWrites":DataFromInitialStateAtPA i /\forall microop "w", ((IsAnyWrite w /\ SamePhysicalAddress w i/\ ~SameMicroop i w) =>AddEdge ((i, Execute), (w, Writeback))).


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch





Writebacki1


Execute

Y = 0Y = 1


DefineMacro "BeforeAllWrites":DataFromInitialStateAtPA i /\forall microop "w", ((IsAnyWrite w /\ SamePhysicalAddress w i/\ ~SameMicroop i w) =>AddEdge ((i, Execute), (w, Writeback))).

Enforce that the load

executes before all writes

to its address in the test

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Memory Hierarchy

Writebacki1

Execute

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Memory Hierarchy

A load must execute either

before or after any write to its

address completes writeback.

Writebacki1

Execute

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Memory Hierarchy




Writebacki1

w: Store y=val1 i: Load y=val2

Execute

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Memory Hierarchy




Writebacki1


Execute

OR

The Before_Or_After_Every_SameAddrWrite Macro

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Memory Hierarchy



address reaches memory.

Writebacki1


Execute

OR

DefineMacro "Before_Or_After_Every_SameAddrWrite":forall microop "w", ((IsAnyWrite w /\ SamePhysicalAddress w i) =>(AddEdge ((w, Writeback)), (i, Execute)) \/AddEdge ((i, Execute), (w, Writeback)))).

The Before_Or_After_Every_SameAddrWrite Macro

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Memory Hierarchy



address reaches memory.

Writebacki1


Execute

OR

DefineMacro "Before_Or_After_Every_SameAddrWrite":forall microop "w", ((IsAnyWrite w /\ SamePhysicalAddress w i) =>(AddEdge ((w, Writeback)), (i, Execute)) \/AddEdge ((i, Execute), (w, Writeback)))).

Either w completes writeback

before i executes, or vice-versa.

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebackw

Execute

Y = 0

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebackw

Execute

A load must read from the latest write to that address to reach

memory.

Y = 0

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebackw

Execute

Alternatively:

1) The load must execute after the write it reads from

2) No writes to that address between the source write and the read

Y = 0

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebackw

w: St y=1

Execute

Alternatively:



Y = 1

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebackw

w: St y=1 i: Load y=1

Execute

Alternatively:



Y = 1

Finding Axioms

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebackw


Execute

Alternatively:



Y = 2

Writebackw’

w’: St y=2

The No_SameAddrWrites_Btwn_Src_And_Read Macro

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebackw


Execute


memory.

Alternatively:



Y = 0Y = 1Y = 2

Writebackw’

w’: St y=2

DefineMacro "No_SameAddrWrites_Btwn_Src_And_Read":exists microop "w", (IsAnyWrite w /\ ___________________ w i /\ ________ w i/\ AddEdge ((w, Writeback), (i, Execute)) /\~(exists microop "w'",IsAnyWrite w' /\ ___________________ i w’ /\~SameMicroop w w’ /\ EdgesExist [((w, Writeback), (w’, Writeback));

((w’, Writeback), (i, Execute))])).




Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebackw


Execute


memory.

Alternatively:



Y = 0Y = 1Y = 2

Writebackw’

w’: St y=2



DefineMacro "No_SameAddrWrites_Btwn_Src_And_Read":exists microop "w", (IsAnyWrite w /\ SamePhysicalAddress w i /\ SameData w i/\ AddEdge ((w, Writeback), (i, Execute)) /\~(exists microop "w'",IsAnyWrite w' /\ SamePhysicalAddress i w’ /\~SameMicroop w w’ /\ EdgesExist [((w, Writeback), (w’, Writeback));



Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebackw


Execute


memory.

Alternatively:



Y = 0Y = 1Y = 2

Writebackw’

w’: St y=2





Read i executes after its source

write w reaches memory…


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebackw


Execute


memory.

Alternatively:



Y = 0Y = 1Y = 2

Writebackw’

w’: St y=2





…and there are no writes w’ to

that addr between the source

write w and the read i.

Putting the Macros together: the Read_Values axiom

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebackw


Execute


memory.

Alternatively:



Y = 0Y = 1Y = 2

Writebackw’

w’: St y=2

Axiom "Read_Values":forall microops "i",IsAnyRead i =>(ExpandMacro BeforeAllWrites \/(ExpandMacro No_SameAddrWrites_Btwn_Src_And_Read/\ExpandMacro Before_Or_After_Every_SameAddrWrite

)).


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebackw


Execute


memory.

Alternatively:



Y = 0Y = 1Y = 2

Writebackw’

w’: St y=2


)).

For all reads i (same identifier

used in the macros)…


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebackw


Execute


memory.

Alternatively:



Y = 0Y = 1Y = 2

Writebackw’

w’: St y=2


)).

…either the read executes

before all writes (expand

macro defined earlier)…


Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebackw


Execute


memory.

Alternatively:



Y = 0Y = 1Y = 2

Writebackw’

w’: St y=2


)).

…or the read reads from

the latest write to that

address



(i1) (i2)

Fetch

Execute

Writeback

(i3) (i4)

Thread 0 Thread 1







(i1) (i2)

Fetch

Execute

Writeback

(i3) (i4)

Thread 0 Thread 1




• i3 must be sourced from the write i2

• No intervening writes; constraint satisfied




(i1) (i2)

Fetch

Execute

Writeback

(i3) (i4)

Thread 0 Thread 1




• i4 must be sourced from i1

• But i2 intervenes! => Constraint unsatisfiable




(i1) (i2)

Fetch

Execute

Writeback

(i3) (i4)

Thread 0 Thread 1




• i4 must be sourced from i1

• But i2 intervenes! => Constraint unsatisfiable


Cannot find an acyclic graph that satisfies all constraints =>

Forbidden Execution of co-mp is NOT observable on µarch!

Test your completed SC uarch!

Memory Hierarchy

Writeback

Execute

Fetch

Core 0

Writeback

Execute

Fetch

Core 1

Writebackw


Execute


memory.

Alternatively:



Y = 0Y = 1Y = 2

Writebackw’

w’: St y=2

# Assuming you are in ~/pipecheck_tutorial/uarches/$ check -i ../tests/SC_tests/co-mp.test -m SC_fillable.uarch

# If your uarch is valid, the above will create co-mp.pdf in your# current directory (open pdfs from command line with evince)# To run the solution version of the SC uarch on this test:# (Note: this will overwrite the co-mp.pdf in your current folder)$ check -i ../tests/SC_tests/co-mp.test -m SC.uarch –d solutions/

# If you get an error (cannot parse uarch, ps2pdf crashes, etc),# examine your syntax or ask for help.# If the outcome is observable (“BUG”), compare the graphs# generated by the solution uarch to those of your uarch.

# To compare the uarches themselves:$ diff SC_fillable.uarch solutions/SC.uarch

Run the entire suite of SC litmus tests!# Assuming you are in ~/pipecheck_tutorial/uarches/$ run_tests –v 2 -t ../tests/SC_tests/ -m SC_fillable.uarch

# The above will generate *.gv files in ~/pipecheck_tutorial/out/# for all SC tests, and output overall statistics at the end. If # the count for “Buggy” is non-zero, your uarch is faulty. Look for the tests that output “BUG” to find out which tests fail.

# You can use gen_graph to convert gv files into PDFs:$ gen_graph –i <test_gv_file>

# Compare your uarch with the solution SC uarch using diff to find # discrepancies:$ diff SC_fillable.uarch solutions/SC.uarch

PipeCheck Verification Time

0.01

0.1

1

safe

029 ss

lrf

i001 m

prf

i002

rfi0

04sa

fe0

10sa

fe0

30sa

fe0

22iw

p2

8b

test

and

set lb

safe

033

safe

036

safe

004

safe

006

rfi0

07 n5

test

and

set2

iwp

23

b sbsa

fe0

17p

od

wr0

00

amd

5rf

i008

safe

018 wrc

co-m

psa

fe0

02sa

fe0

31sa

fe0

09sa

fe0

05m

p+f

ence

ssa

fe0

20m

p+s

tale

ldrf

i000

safe

007

test

and

set3

safe

003 n

6sa

fe0

14sa

fe0

12rf

i016

rfi0

12sa

fe0

32rw

c-u

nfe

nce

dsa

fe0

11iw

p2

8a

safe

001

safe

026

safe

000 n

8sa

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08sa

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i013

safe

027

rwc-

fen

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rfi0

17 iriw

iwp

24

safe

021

rfi0

14sa

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16 n4

safe

015

safe

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rfi0

18rf

i011

rfi0

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d1

0sa

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i015

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dw

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1sa

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06 n1

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024

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23sa

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i009

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10 n3

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27

n2

Ru

nti

me

(s)

FiveStage (No SB) FiveStage (w/ SB) gem5 O3 OpenSPARC T2

Covered the basics of what PipeCheck can do…

▪But there’s more!

▪PipeCheck can handle heterogeneous pipelines:


▪…and microarchitectural optimizations…

Left: Speculative Load Reordering

Right: Speculative Fence Retirement


▪…and the methodology is extensible to other ordering types, including…

CCICheck: Coherence orderings that affect consistency (with ViCL abstraction)

COATCheck: Addr Translation/Virtual Memory orderings that affect consistency

PipeCheck Summary

▪ Fast, automated per-program verification

▪Check implementation against ISA spec

▪Decompose RTL verification into smaller per-axiom sub-problems

• More on that after the coffee break with RTLCheck!

▪Open-Sourced:

https://github.com/daniellustig/coatcheck

Repo from this tutorial:

https://github.com/ymanerka/pipecheck_tutorial

https://github.com/daniellustig/coatcheck

https://github.com/ymanerka/pipecheck_tutorial

pipecheck hands-on mcm... · 2019. 7. 3. · simplesc: an sc microarchitecture •partially...

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