pic24fj64ga004 family data sheet - microchip technology · an8/rp18/cn10/pma2/rc2 sosci/rp4/cn1/rb4...

PIC24FJ64GA004 FAMILY28/44-Pin General Purpose, 16-Bit Flash Microcontrollers

High-Performance CPU• Modified Harvard Architecture• Up to 16 MIPS Operation @ 32 MHz • 8 MHz Internal Oscillator with 4x PLL Option and

Multiple Divide Options• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier• 32-Bit by 16-Bit Hardware Divider• 16-Bit x 16-Bit Working Register Array• C Compiler Optimized Instruction Set Architecture:

- 76 base instructions- Flexible addressing modes

• Two Address Generation Units (AGUs) for Separate Read and Write Addressing of Data Memory

Special Microcontroller Features• Operating Voltage Range of 2.0V to 3.6V• 5.5V Tolerant Input (digital pins only)• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins• Flash Program Memory:

- 10,000 erase/write- 20-year data retention minimum

• Power Management modes: - Sleep, Idle, Doze and Alternate Clock modes- Operating current: 650 A/MIPS, typical at 2.0V- Sleep current: 150 nA, typical at 2.0V

• Fail-Safe Clock Monitor (FSCM) Operation:- Detects clock failure and switches to on-chip,

low-power RC oscillator • On-Chip, 2.5V Regulator with Tracking mode• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)• Flexible Watchdog Timer (WDT) with On-Chip,

Low-Power RC Oscillator for Reliable Operation• In-Circuit Serial Programming™ (ICSP™) and

In-Circuit Debug (ICD) via 2 Pins• JTAG Boundary Scan Support

Analog Features• 10-Bit, up to 13-Channel Analog-to-Digital Converter:

- 500 ksps conversion rate- Conversion available during Sleep and Idle

• Dual Analog Comparators with Programmable Input/Output Configuration

Peripheral Features• Peripheral Pin Select (PPS):

- Allows independent I/O mapping of many peripherals- Up to 26 available pins (44-pin devices)- Continuous hardware integrity checking and safety

interlocks prevent unintentional configuration changes• 8-Bit Parallel Master/Slave Port (PMP/PSP):

- Up to 16-bit multiplexed addressing, with up to 11 dedicated address pins on 44-pin devices

- Programmable polarity on control lines• Hardware Real-Time Clock/Calendar (RTCC):

- Provides clock, calendar and alarm functions• Programmable Cyclic Redundancy Check (CRC)• Two 3-Wire/4-Wire SPI modules (support 4 Frame

modes) with 8-Level FIFO Buffer• Two I2C™ modules Support Multi-Master/Slave

mode and 7-Bit/10-Bit Addressing• Two UART modules:

- Supports RS-485, RS-232, and LIN/J2602- On-chip hardware encoder/decoder for IrDA®

- Auto-wake-up on Start bit- Auto-Baud Detect- 4-level deep FIFO buffer

• Five 16-Bit Timers/Counters with Programmable Prescaler• Five 16-Bit Capture Inputs• Five 16-Bit Compare/PWM Outputs• Configurable Open-Drain Outputs on Digital I/O Pins• Up to 3 External Interrupt Sources

Device

Pins

Prog

ram

Mem

ory

(byt

es)

SRA

M(b

ytes

)

Remappable Peripherals

I2C

™

10-B

it A

/D(c

h)

Com

para

tors

PMP/

PSP

JTA

G

Rem

appa

ble

Pin

s

Tim

ers

16-

Bit

Cap

ture

Inpu

t

Com

pare

/PW

MO

utpu

t

UA

RT

w/

IrDA

®

SPI

PIC24FJ16GA002 28 16K 4K 16 5 5 5 2 2 2 10 2 Y YPIC24FJ32GA002 28 32K 8K 16 5 5 5 2 2 2 10 2 Y YPIC24FJ48GA002 28 48K 8K 16 5 5 5 2 2 2 10 2 Y YPIC24FJ64GA002 28 64K 8K 16 5 5 5 2 2 2 10 2 Y YPIC24FJ16GA004 44 16K 4K 26 5 5 5 2 2 2 13 2 Y YPIC24FJ32GA004 44 32K 8K 26 5 5 5 2 2 2 13 2 Y YPIC24FJ48GA004 44 48K 8K 26 5 5 5 2 2 2 13 2 Y YPIC24FJ64GA004 44 64K 8K 26 5 5 5 2 2 2 13 2 Y Y

2010-2013 Microchip Technology Inc. DS39881E-page 1

PIC24FJ64GA004 FAMILY

Pin Diagrams

PIC

24FJ

XXG

A00

2

1234567891011121314

2827262524232221201918171615

28-Pin SPDIP, SSOP, SOIC

28-Pin QFN(1)

10 11

23

6

1

18192021

22

12 13 1415

87

1617

232425262728

9

PIC24FJXXGA00254

MCLR

VSS

VDD

AN0/VREF+/CN2/RA0AN1/VREF-/CN3/RA1

PGED1/AN2/C2IN-/RP0/CN4/RB0

SOSCO/T1CK/CN0/PMA1/RA4SOSCI/RP4/PMBE/CN1/RB4

OSCO/CLKO/CN29/PMA0/RA3OSCI/CLKI/CN30/RA2

AN5/C1IN+/SCL2/RP3/CN7/RB3AN4/C1IN-/SDA2/RP2/CN6/RB2

PGEC1/AN3/C2IN+/RP1/CN5/RB1

PGED3/ASDA1/RP5/CN27/PMD7/RB5

VDDVSS

PGEC3/ASCL1/RP6/CN24/PMD6/RB6

DISVREGVCAP/VDDCORE

RP7/INT0/CN23/PMD5/RB7

TDO/SDA1/RP9/CN21/PMD3/RB9TCK/SCL1/RP8/CN22/PMD4/RB8

AN9/RP15/CN11/PMCS1/RB15AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14AN11/RP13/CN13/PMRD/RB13AN12/RP12/CN14/PMD0/RB12

PGED2/TDI/RP10/CN16/PMD2/RB10PGEC2/TMS/RP11/CN15/PMD1/RB11

VSS

PGED1/AN2/C2IN-/RP0/CN4/RB0

OSCO/CLKO/CN29/PMA0/RA3OSCI/CLKI/CN30/RA2

AN5/C1IN+/SCL2/RP3/CN7/RB3AN4/C1IN-/SDA2/RP2/CN6/RB2

PGEC1/AN3/C2IN+/RP1/CN5/RB1

DISVREGVCAP/VDDCORE

TDO/SDA1/RP9/CN21/PMD3/RB9

AN11/RP13/CN13/PMRD/RB13AN12/RP12/CN14/PMD0/RB12

PGED2/TDI/RP10/CN16/PMD2/RB10PGEC2/TMS/RP11/CN15/PMD1/RB11

VDD

PG

EC

3/AS

CL1

/RP6

/CN

24/P

MD

6/R

B6

SO

SCO

/T1C

K/C

N0/

PMA

1/R

A4

SOS

CI/R

P4/P

MB

E/C

N1/

RB

4

RP7

/INT0

/CN

23/P

MD

5/R

B7TC

K/SC

L1/R

P8/C

N22

/PM

D4/

RB

8

PG

ED

3/A

SDA

1/R

P5/C

N27

/PM

D7/

RB

5M

CLR

AN

0/VR

EF+

/CN

2/R

A0

AN

1/VR

EF-

/CN

3/R

A1

VD

DV

SS

AN

9/R

P15/

CN

11/P

MC

S1/R

B15

AN10

/CV R

EF/R

TCC

/RP1

4/C

N12

/PM

WR

/RB1

4

Legend: RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins.Note 1: Back pad on QFN devices should be connected to Vss.

DS39881E-page 2 2010-2013 Microchip Technology Inc.


Pin Diagrams (Continued)

1011

23456

1

18 19 20 21 2212 13 14 15

3887

44 43 42 41 40 3916 17

2930313233

232425262728

36 34359

PIC24FJXXGA004

37

44-Pin QFN(1)

SC

L1/R

P8/C

N22

/PM

D4/

RB

8R

P7/IN

T0/C

N23

/PM

D5/

RB

7PG

EC

3/A

SC

L1/R

P6/C

N24

/PM

D6/

RB

6PG

ED

3/A

SD

A1/

RP5

/CN

27/P

MD

7/R

B5

VDD

TDI/P

MA

9/R

A9

SOS

CO

/T1C

K/C

N0/

RA

4

VSS

RP2

1/C

N26

/PM

A3/

RC

5R

P20/

CN

25/P

MA

4/R

C4

RP1

9/C

N28

/PM

BE/

RC

3AN12/RP12/CN14/PMD0/RB12

PGEC2/RP11/CN15/PMD1/RB11PGED2/RP10/CN16/PMD2/RB10

VCAP/VDDCOREDISVREG

RP25/CN19/PMA6/RC9RP24/CN20/PMA5/RC8RP23/CN17/PMA0/RC7RP22/CN18/PMA1/RC6

SDA1/RP9/CN21/PMD3/RB9

AN11/RP13/CN13/PMRD/RB13 AN4/C1IN-/SDA2/RP2/CN6/RB2AN5/C1IN+/SCL2/RP3/CN7/RB3AN6/RP16/CN8/RC0AN7/RP17/CN9/RC1AN8/RP18/CN10/PMA2/RC2

SOSCI/RP4/CN1/RB4

VDDVSSOSCI/CLKI/CN30/RA2OSCO/CLKO/CN29/RA3TDO/PMA8/RA8

PG

EC

1/A

N3/

C2I

N+/

RP1

/CN

5/R

B1

PG

ED

1/AN

2/C

2IN

-/RP0

/CN

4/R

B0

AN

1/VR

EF-

/CN

3/R

A1

AN0/

V RE

F+/C

N2/

RA

0M

CLR

TMS

/PM

A10

/RA

10

AVD

DAV

SS

AN

9/R

P15/

CN

11/P

MC

S1/R

B15

AN

10/C

V RE

F/R

TCC

/RP1

4/C

N12

/PM

WR

/RB

14TC

K/PM

A7/

RA

7

Legend: RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins.Note 1: Back pad on QFN devices should be connected to Vss.



Pin Diagrams (Continued)

1011

23456

1

18 19 20 21 2212 13 14 15

38

87

44 43 42 41 40 3916 17

2930313233

232425262728

36 3435

9

37

44-Pin TQFP

PIC24FJXXGA004

AN12/RP12/CN14/PMD0/RB12PGEC2/RP11/CN15/PMD1/RB11PGED2/RP10/CN16/PMD2/RB10

VCAP/VDDCOREDISVREG

RP25/CN19/PMA6/RC9RP24/CN20/PMA5/RC8RP23/CN17/PMA0/RC7RP22/CN18/PMA1/RC6

SDA1/RP9/CN21/PMD3/RB9

AN11/RP13/CN13/PMRD/RB13 AN4/C1IN-/SDA2/RP2/CN6/RB2AN5/C1IN+/SCL2/RP3/CN7/RB3AN6/RP16/CN8/RC0AN7/RP17/CN9/RC1AN8/RP18/CN10/PMA2/RC2

SOSCI/RP4/CN1/RB4

VDDVSSOSCI/CLKI/CN30/RA2OSCO/CLKO/CN29/RA3TDO/PMA8/RA8

SC

L1/R

P8/C

N22

/PM

D4/

RB

8R

P7/IN

T0/C

N23

/PM

D5/

RB

7P

GEC

3/R

P6/A

SC

L1/C

N24

/PM

D6/

RB

6P

GED

3/R

P5/A

SD

A1/

CN

27/P

MD

7/R

B5

VD

D

TDI/P

MA

9/R

A9

SO

SCO

/T1C

K/C

N0/

RA

4

VS

SR

P21/

CN

26/P

MA3

/RC

5R

P20/

CN

25/P

MA4

/RC

4R

P19/

CN

28/P

MBE

/RC

3

PG

EC

1/A

N3/

C2I

N+/

RP1

/CN

5/R

B1

PG

ED

1/AN

2/C

2IN

-/RP0

/CN

4/R

B0

AN

1/VR

EF-

/CN

3/R

A1

AN

0/VR

EF+

/CN

2/R

A0

MC

LR

TMS

/PM

A10

/RA

10

AVD

DAV

SS

AN

9/R

P15/

CN

11/P

MC

S1/R

B15

AN

10/C

VRE

F/R

TCC

/RP1

4/C

N12

/PM

WR

/RB

14TC

K/PM

A7/

RA

7

Legend: RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins.



Table of Contents1.0 Device Overview .......................................................................................................................................................................... 72.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 173.0 CPU ........................................................................................................................................................................................... 234.0 Memory Organization ................................................................................................................................................................. 295.0 Flash Program Memory.............................................................................................................................................................. 476.0 Resets ........................................................................................................................................................................................ 537.0 Interrupt Controller ..................................................................................................................................................................... 598.0 Oscillator Configuration .............................................................................................................................................................. 959.0 Power-Saving Features............................................................................................................................................................ 10310.0 I/O Ports ................................................................................................................................................................................... 10511.0 Timer1 ..................................................................................................................................................................................... 12512.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 12713.0 Input Capture............................................................................................................................................................................ 13314.0 Output Compare....................................................................................................................................................................... 13515.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 14116.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 15117.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 15918.0 Parallel Master Port (PMP)....................................................................................................................................................... 16719.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 17720.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 18921.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 19322.0 Comparator Module.................................................................................................................................................................. 20323.0 Comparator Voltage Reference................................................................................................................................................ 20724.0 Special Features ...................................................................................................................................................................... 20925.0 Development Support............................................................................................................................................................... 21926.0 Instruction Set Summary .......................................................................................................................................................... 22327.0 Electrical Characteristics .......................................................................................................................................................... 23128.0 Packaging Information.............................................................................................................................................................. 251Appendix A: Revision History............................................................................................................................................................. 267Appendix B: Additional Guidance for PIC24FJ64GA004 Family Applications ................................................................................... 268Index ................................................................................................................................................................................................. 269The Microchip Web Site ..................................................................................................................................................................... 273Customer Change Notification Service .............................................................................................................................................. 273Customer Support .............................................................................................................................................................................. 273Reader Response .............................................................................................................................................................................. 274Product Identification System ............................................................................................................................................................ 275



TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. Wewelcome your feedback.

Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:• Microchip’s Worldwide Web site; http://www.microchip.com• Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.

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mailto:[email protected]://www.microchip.comhttp://www.microchip.com


1.0 DEVICE OVERVIEWThis document contains device-specific information forthe following devices:

• PIC24FJ16GA002• PIC24FJ32GA002• PIC24FJ48GA002• PIC24FJ64GA002• PIC24FJ16GA004• PIC24FJ32GA004• PIC24FJ48GA004• PIC24FJ64GA004

This family introduces a new line of Microchip devices:a 16-bit microcontroller family with a broad peripheralfeature set and enhanced computational performance.The PIC24FJ64GA004 family offers a new migrationoption for those high-performance applications whichmay be outgrowing their 8-bit platforms, but don’trequire the numerical processing power of a digitalsignal processor.

1.1 Core Features

1.1.1 16-BIT ARCHITECTURECentral to all PIC24F devices is the 16-bit modifiedHarvard architecture, first introduced with Microchip’sdsPIC® Digital Signal Controllers (DSCs). The PIC24FCPU core offers a wide range of enhancements, such as:

• 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces

• Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data)

• A 16-element working register array with built-in software stack support

• A 17 x 17 hardware multiplier with support for integer math

• Hardware support for 32 by 16-bit division• An instruction set that supports multiple

addressing modes and is optimized for high-level languages such as ‘C’

• Operational performance up to 16 MIPS

1.1.2 POWER-SAVING TECHNOLOGYAll of the devices in the PIC24FJ64GA004 familyincorporate a range of features that can significantlyreduce power consumption during operation. Keyitems include:

• On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs.

• Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat.

• Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software.

1.1.3 OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC24FJ64GA004 family offerfive different oscillator options, allowing users a rangeof choices in developing application hardware. Theseinclude:

• Two Crystal modes using crystals or ceramic resonators.

• Two External Clock modes offering the option of a divide-by-2 clock output.

• A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz.

• A Phase Lock Loop (PLL) frequency multiplier, available to the External Oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz.

• A separate internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications.

The internal oscillator block also provides a stablereference source for the Fail-Safe Clock Monitor. Thisoption constantly monitors the main clock sourceagainst a reference signal provided by the internaloscillator and enables the controller to switch to theinternal oscillator, allowing for continued low-speedoperation or a safe application shutdown.



1.1.4 EASY MIGRATIONRegardless of the memory size, all devices share thesame rich set of peripherals, allowing for a smoothmigration path as applications grow and evolve.

The consistent pinout scheme used throughout theentire family also aids in migrating to the next largerdevice. This is true when moving between devices withthe same pin count, or even jumping from 28-pin to44-pin devices.

The PIC24F family is pin-compatible with devices in thedsPIC33 family, and shares some compatibility with thepinout schema for PIC18 and dsPIC30. This extendsthe ability of applications to grow from the relativelysimple, to the powerful and complex, yet still selectinga Microchip device.

1.2 Other Special Features• Communications: The PIC24FJ64GA004 family

incorporates a range of serial communication peripherals to handle a range of application requirements. There are two independent I2C modules that support both Master and Slave modes of operation. Devices also have, through the Peripheral Pin Select (PPS) feature, two independent UARTs with built-in IrDA encoder/decoders and two SPI modules.

• Peripheral Pin Select (PPS): The Peripheral Pin Select feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins.

• Parallel Master/Enhanced Parallel Slave Port: One of the general purpose I/O ports can be reconfigured for enhanced parallel data communi-cations. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 16 external address lines in Master modes.

• Real-Time Clock/Calendar (RTCC): This moduleimplements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application.

• 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds.

1.3 Details on Individual Family Members

Devices in the PIC24FJ64GA004 family are availablein 28-pin and 44-pin packages. The general blockdiagram for all devices is shown in Figure 1-1.

The devices are differentiated from each other in twoways:

1. Flash program memory (64 Kbytes forPIC24FJ64GA devices, 48 Kbytes forPIC24FJ48GA devices, 32 Kbytes forPIC24FJ32GA devices and 16 Kbytes forPIC24FJ16GA devices).

2. Internal SRAM memory (4k for PIC24FJ16GAdevices, 8k for all other devices in the family).

3. Available I/O pins and ports (21 pins on 2 portsfor 28-pin devices and 35 pins on 3 ports for44-pin devices).

All other features for devices in this family are identical.These are summarized in Table 1-1.

A list of the pin features that are available on thePIC24FJ64GA004 family devices, sorted by function, isshown in Table 1-2. Note that this table shows the pinlocation of individual peripheral features and not howthey are multiplexed on the same pin. This informationis provided in the pinout diagrams in the beginning ofthe data sheet. Multiplexed features are sorted by thepriority given to a feature, with the highest priorityperipheral being listed first.



TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ64GA004 FAMILY

Features

16G

A00

2

32G

A00

2

48G

A00

2

64G

A00

2

16G

A00

4

32G

A00

4

48G

A00

4

64G

A00

4

Operating Frequency DC – 32 MHz Program Memory (bytes) 16K 32K 48K 64K 16K 32K 48K 64KProgram Memory (instructions) 5,504 11,008 16,512 22,016 5,504 11,008 16,512 22,016Data Memory (bytes) 4096 8192 4096 8192Interrupt Sources(soft vectors/NMI traps)

43(39/4)

I/O Ports Ports A, B Ports A, B, CTotal I/O Pins 21 35Timers: Total Number (16-bit) 5(1)

32-Bit (from paired 16-bit timers) 2Input Capture Channels 5(1)

Output Compare/PWM Channels 5(1)

Input Change Notification Interrupt 21 30Serial Communications: UART 2(1)

SPI (3-wire/4-wire) 2(1)

I2C™ 2Parallel Communications (PMP/PSP) YesJTAG Boundary Scan Yes10-Bit Analog-to-Digital Module (input channels)

10 13

Analog Comparators 2Remappable Pins 16 26

Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch

(PWRT, OST, PLL Lock) Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations Packages 28-Pin SPDIP/SSOP/SOIC/QFN 44-Pin QFN/TQFP Note 1: Peripherals are accessible through remappable pins.



FIGURE 1-1: PIC24FJ64GA004 FAMILY GENERAL BLOCK DIAGRAM

InstructionDecode &

Control

16

PCH

16

Program Counter

16-Bit ALU

23

24

Data Bus

16

DivideSupport

16

16

16

8

InterruptController

StackControlLogic

RepeatControlLogic

Data Latch

Data RAM

AddressLatch

Address Latch

Program Memory

Data Latch

16

Address Bus

Lite

ral D

ata

23

Control Signals

16

16

16 x 16W Reg Array

Multiplier17x17

OSCI/CLKIOSCO/CLKO

VDD, VSS

TimingGeneration

MCLR

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

BOR and

Precision

ReferenceBand Gap

FRC/LPRCOscillators

RegulatorVoltage

VDDCORE/VCAP

DISVREG

PORTA(1)

PORTC(1)

RA

RC

PORTB

RB

Note 1: Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions.2: BOR and LVD functionality is provided when the on-board voltage regulator is enabled.3: Peripheral I/Os are accessible through remappable pins.

RP(1)

RP

Comparators(3)Timer2/3(3)Timer1 RTCC

IC1-5(3)

10-Bit

PWM/SPI1/2(3) I2C1/2

Timer4/5(3)

PMP/PSP

OC1-5(3) CN1-22(1) UART1/2(3)

LVD(2)

PCL

Inst Latch

Read AGUWrite AGU

PSV & TableData AccessControl Block

Inst Register

EA MUX

A/D



TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS

Function

Pin Number

I/O Input Buffer Description28-PinSPDIP/

SSOP/SOIC

28-PinQFN

44-PinQFN/TQFP

AN0 2 27 19 I ANA A/D Analog Inputs.AN1 3 28 20 I ANAAN2 4 1 21 I ANAAN3 5 2 22 I ANAAN4 6 3 23 I ANAAN5 7 4 24 I ANAAN6 — — 25 I ANAAN7 — — 26 I ANAAN8 — — 27 I ANAAN9 26 23 15 I ANAAN10 25 22 14 I ANAAN11 24 21 11 I ANAAN12 23 20 10 I ANAASCL1 15 12 42 I/O I2C Alternate I2C1 Synchronous Serial Clock Input/Output.(1)

ASDA1 14 11 41 I/O I2C Alternate I2C2 Synchronous Serial Clock Input/Output. (1)

AVDD — — 17 P — Positive Supply for Analog Modules.AVSS — — 16 P — Ground Reference for Analog Modules.C1IN- 6 3 23 I ANA Comparator 1 Negative Input.C1IN+ 7 4 24 I ANA Comparator 1 Positive Input.C2IN- 4 1 21 I ANA Comparator 2 Negative Input.C2IN+ 5 2 22 I ANA Comparator 2 Positive Input.CLKI 9 6 30 I ANA Main Clock Input Connection.CLKO 10 7 31 O — System Clock Output.Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

ANA = Analog level input/output I2C™ = I2C/SMBus input bufferNote 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.



CN0 12 9 34 I ST Interrupt-on-Change Inputs.CN1 11 8 33 I STCN2 2 27 19 I STCN3 3 28 20 I STCN4 4 1 21 I STCN5 5 2 22 I STCN6 6 3 23 I STCN7 7 4 24 I STCN8 — — 25 I STCN9 — — 26 I STCN10 — — 27 I STCN11 26 23 15 I STCN12 25 22 14 I STCN13 24 21 11 I STCN14 23 20 10 I STCN15 22 19 9 I STCN16 21 18 8 I STCN17 — — 3 I STCN18 — — 2 I STCN19 — — 5 I STCN20 — — 4 I STCN21 18 15 1 I STCN22 17 14 44 I STCN23 16 13 43 I STCN24 15 12 42 I STCN25 — — 37 I STCN26 — — 38 I STCN27 14 11 41 I STCN28 — — 36 I STCN29 10 7 31 I STCN30 9 6 30 I STCVREF 25 22 14 O ANA Comparator Voltage Reference Output.DISVREG 19 16 6 I ST Voltage Regulator Disable.INT0 16 13 43 I ST External Interrupt Input.

MCLR 1 26 18 I ST Master Clear (device Reset) Input. This line is brought low to cause a Reset.

TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Function

Pin Number


SSOP/SOIC

28-PinQFN

44-PinQFN/TQFP

Legend: TTL = TTL input buffer ST = Schmitt Trigger input bufferANA = Analog level input/output I2C™ = I2C/SMBus input buffer

Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.



OSCI 9 6 30 I ANA Main Oscillator Input Connection.OSCO 10 7 31 O ANA Main Oscillator Output Connection.PGEC1 5 2 22 I/O ST In-Circuit Debugger/Emulator and ICSP™ Programming

Clock.PGEC2 22 19 9 I/O STPGEC3 14 12 42 I/O STPGED1 4 1 21 I/O ST In-Circuit Debugger/Emulator and ICSP Programming

Data.PGED2 21 18 8 I/O STPGED3 15 11 41 I/O STPMA0 10 7 3 I/O ST/TTL Parallel Master Port Address Bit 0 Input (Buffered Slave

modes) and Output (Master modes).PMA1 12 9 2 I/O ST/TTL Parallel Master Port Address Bit 1 Input (Buffered Slave

modes) and Output (Master modes).PMA2 — — 27 O — Parallel Master Port Address (Demultiplexed Master

modes).PMA3 — — 38 O —PMA4 — — 37 O —PMA5 — — 4 O —PMA6 — — 5 O —PMA7 — — 13 O —PMA8 — — 32 O —PMA9 — — 35 O —PMA10 — — 12 O —PMA11 — — — O —PMA12 — — — O —PMA13 — — — O —PMBE 11 8 36 O — Parallel Master Port Byte Enable Strobe.PMCS1 26 23 15 O — Parallel Master Port Chip Select 1 Strobe/Address Bit 14.PMD0 23 20 10 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or

Address/Data (Multiplexed Master modes).PMD1 22 19 9 I/O ST/TTLPMD2 21 18 8 I/O ST/TTLPMD3 18 15 1 I/O ST/TTLPMD4 17 14 44 I/O ST/TTLPMD5 16 13 43 I/O ST/TTLPMD6 15 12 42 I/O ST/TTLPMD7 14 11 41 I/O ST/TTLPMRD 24 21 11 O — Parallel Master Port Read Strobe.PMWR 25 22 14 O — Parallel Master Port Write Strobe.


Function

Pin Number


SSOP/SOIC

28-PinQFN

44-PinQFN/TQFP





RA0 2 27 19 I/O ST PORTA Digital I/O.RA1 3 28 20 I/O STRA2 9 6 30 I/O STRA3 10 7 31 I/O STRA4 12 9 34 I/O STRA7 — — 13 I/O STRA8 — — 32 I/O STRA9 — — 35 I/O STRA10 — — 12 I/O STRB0 4 1 21 I/O ST PORTB Digital I/O.RB1 5 2 22 I/O STRB2 6 3 23 I/O STRB3 7 4 24 I/O STRB4 11 8 33 I/O STRB5 14 11 41 I/O STRB6 15 12 42 I/O STRB7 16 13 43 I/O STRB8 17 14 44 I/O STRB9 18 15 1 I/O STRB10 21 18 8 I/O STRB11 22 19 9 I/O STRB12 23 20 10 I/O STRB13 24 21 11 I/O STRB14 25 22 14 I/O STRB15 26 23 15 I/O STRC0 — — 25 I/O ST PORTC Digital I/O.RC1 — — 26 I/O STRC2 — — 27 I/O STRC3 — — 36 I/O STRC4 — — 37 I/O STRC5 — — 38 I/O STRC6 — — 2 I/O STRC7 — — 3 I/O STRC8 — — 4 I/O STRC9 — — 5 I/O ST


Function

Pin Number


SSOP/SOIC

28-PinQFN

44-PinQFN/TQFP





RP0 4 1 21 I/O ST Remappable Peripheral.

RP1 5 2 22 I/O STRP2 6 3 23 I/O STRP3 7 4 24 I/O STRP4 11 8 33 I/O STRP5 14 11 41 I/O STRP6 15 12 42 I/O STRP7 16 13 43 I/O STRP8 17 14 44 I/O STRP9 18 15 1 I/O STRP10 21 18 8 I/O STRP11 22 19 9 I/O STRP12 23 20 10 I/O STRP13 24 21 11 I/O STRP14 25 22 14 I/O STRP15 26 23 15 I/O STRP16 — — 25 I/O STRP17 — — 26 I/O STRP18 — — 27 I/O STRP19 — — 36 I/O STRP20 — — 37 I/O STRP21 — — 38 I/O STRP22 — — 2 I/O STRP23 — — 3 I/O STRP24 — — 4 I/O STRP25 — — 5 I/O STRTCC 25 22 14 O — Real-Time Clock Alarm Output.SCL1 17 14 44 I/O I2C I2C1 Synchronous Serial Clock Input/Output.SCL2 7 4 24 I/O I2C I2C2 Synchronous Serial Clock Input/Output. SDA1 18 15 1 I/O I2C I2C1 Data Input/Output.SDA2 6 3 23 I/O I2C I2C2 Data Input/Output.SOSCI 11 8 33 I ANA Secondary Oscillator/Timer1 Clock Input.SOSCO 12 9 34 O ANA Secondary Oscillator/Timer1 Clock Output.


Function

Pin Number


SSOP/SOIC

28-PinQFN

44-PinQFN/TQFP





T1CK 12 9 34 I ST Timer1 Clock.TCK 17 14 13 I ST JTAG Test Clock Input.TDI 21 18 35 I ST JTAG Test Data Input.TDO 18 15 32 O — JTAG Test Data Output.TMS 22 19 12 I ST JTAG Test Mode Select Input.VDD 13, 28 10, 25 28, 40 P — Positive Supply for Peripheral Digital Logic and I/O Pins.VDDCAP 20 17 7 P — External Filter Capacitor Connection (regulator enabled).VDDCORE 20 17 7 P — Positive Supply for Microcontroller Core Logic (regulator

disabled).VREF- 3 28 20 I ANA A/D and Comparator Reference Voltage (low) Input.VREF+ 2 27 19 I ANA A/D and Comparator Reference Voltage (high) Input.VSS 8, 27 5, 24 29, 39 P — Ground Reference for Logic and I/O Pins.


Function

Pin Number


SSOP/SOIC

28-PinQFN

44-PinQFN/TQFP





2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS

2.1 Basic Connection RequirementsGetting started with the PIC24FJ64GA004 family of16-bit microcontrollers requires attention to a minimalset of device pin connections before proceeding withdevelopment.

The following pins must always be connected:

• All VDD and VSS pins (see Section 2.2 “Power Supply Pins”)

• All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”)

• MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”)

• ENVREG/DISVREG and VCAP/VDDCORE pins (PIC24F J devices only)(see Section 2.4 “Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)”)

These pins must also be connected if they are beingused in the end application:

• PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”)

• OSCI and OSCO pins when an external oscillator source is used (see Section 2.6 “External Oscillator Pins”)

Additionally, the following pins may be required:

• VREF+/VREF- pins used when external voltage reference for analog modules is implemented

The minimum mandatory connections are shown inFigure 2-1.

FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS

Note: The AVDD and AVSS pins must always beconnected, regardless of whether any ofthe analog modules are being used.

PIC24FJXXXX

VD

D

VS

S

VDD

VSS

VSS

VDD

AVD

D

AVS

S

VD

D

VS

S

C1

R1

VDD

MCLRVCAP/VDDCORE

R2 (EN/DIS)VREG

(1)

C7

C2(2)

C3(2)

C4(2)C5(2)

C6(2)

Key (all values are recommendations):C1 through C6: 0.1 F, 20V ceramicC7: 10 F, 6.3V or greater, tantalum or ceramicR1: 10 kΩR2: 100Ω to 470ΩNote 1: See Section 2.4 “Voltage Regulator Pins

(ENVREG/DISVREG and VCAP/VDDCORE)” for an explanation of the ENVREG/DISVREG pin connections.

2: The example shown is for a PIC24F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately.

(1)



2.2 Power Supply Pins

2.2.1 DECOUPLING CAPACITORSThe use of decoupling capacitors on every pair ofpower supply pins, such as VDD, VSS, AVDD andAVSS is required.

Consider the following criteria when using decouplingcapacitors:

• Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.

• Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm).

• Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capaci-tor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F).

• Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance.

2.2.2 TANK CAPACITORSOn boards with power traces running longer than sixinches in length, it is suggested to use a tank capacitorfor integrated circuits including microcontrollers tosupply a local power source. The value of the tankcapacitor should be determined based on the traceresistance that connects the power supply source tothe device, and the maximum current drawn by thedevice in the application. In other words, select the tankcapacitor so that it meets the acceptable voltage sag atthe device. Typical values range from 4.7 F to 47 F.

2.3 Master Clear (MCLR) PinThe MCLR pin provides two specific device functions:device Reset, and device programming and debug-ging. If programming and debugging are not requiredin the end application, a direct connection to VDD maybe all that is required. The addition of other com-ponents, to help increase the application’s resistanceto spurious Resets from voltage sags, may bebeneficial. A typical configuration is shown inFigure 2-1. Other circuit designs may be implemented,depending on the application’s requirements.

During programming and debugging, the resistanceand capacitance that can be added to the pin mustbe considered. Device programmers and debuggersdrive the MCLR pin. Consequently, specific voltagelevels (VIH and VIL) and fast signal transitions mustnot be adversely affected. Therefore, specific valuesof R1 and C1 will need to be adjusted based on theapplication and PCB requirements. For example, it isrecommended that the capacitor, C1, be isolatedfrom the MCLR pin during programming and debug-ging operations by using a jumper (Figure 2-2). Thejumper is replaced for normal run-time operations.

Any components associated with the MCLR pinshould be placed within 0.25 inch (6 mm) of the pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS

Note 1: R1 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met.

2: R2 470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electro-static Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met.

C1

R2R1

VDD

MCLR

PIC24FXXXXJP



2.4 Voltage Regulator Pins

(ENVREG/DISVREG and VCAP/VDDCORE)

The on-chip voltage regulator enable/disable pin(ENVREG or DISVREG, depending on the devicefamily) must always be connected directly to either asupply voltage or to ground. The particular connectionis determined by whether or not the regulator is to beused:

• For ENVREG, tie to VDD to enable the regulator, or to ground to disable the regulator

• For DISVREG, tie to ground to enable the regulator or to VDD to disable the regulator

Refer to Section 24.2 “On-Chip Voltage Regulator”for details on connecting and using the on-chipregulator.

When the regulator is enabled, a low-ESR (< 5Ω)capacitor is required on the VCAP/VDDCORE pin tostabilize the voltage regulator output voltage. TheVCAP/VDDCORE pin must not be connected to VDD andmust use a capacitor of 10 µF connected to ground. Thetype can be ceramic or tantalum. Suitable examples ofcapacitors are shown in Table 2-1. Capacitors withequivalent specification can be used.

Designers may use Figure 2-3 to evaluate ESRequivalence of candidate devices.

The placement of this capacitor should be close toVCAP/VDDCORE. It is recommended that the tracelength not exceed 0.25 inch (6 mm). Refer toSection 27.0 “Electrical Characteristics” foradditional information.

When the regulator is disabled, the VCAP/VDDCORE pinmust be tied to a voltage supply at the VDDCORE level.Refer to Section 27.0 “Electrical Characteristics” forinformation on VDD and VDDCORE.

FIGURE 2-3: FREQUENCY vs. ESR PERFORMANCE FOR SUGGESTED VCAP

.

Note: This section applies only to PIC24F Jdevices with an on-chip voltage regulator.

10

1

0.1

0.01

0.0010.01 0.1 1 10 100 1000 10,000

Frequency (MHz)

ESR

()

Note: Typical data measurement at 25°C, 0V DC bias.

TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS

Make Part # Nominal Capacitance Base Tolerance Rated Voltage Temp. Range

TDK C3216X7R1C106K 10 µF ±10% 16V -55 to +125ºCTDK C3216X5R1C106K 10 µF ±10% 16V -55 to +85ºC

Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to +125ºCPanasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to +85ºC

Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to +125ºCMurata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to +85ºC



2.4.1 CONSIDERATIONS FOR CERAMIC

CAPACITORSIn recent years, large value, low-voltage, surface-mountceramic capacitors have become very cost effective insizes up to a few tens of microfarad. The low-ESR, smallphysical size and other properties make ceramiccapacitors very attractive in many types of applications.

Ceramic capacitors are suitable for use with the inter-nal voltage regulator of this microcontroller. However,some care is needed in selecting the capacitor toensure that it maintains sufficient capacitance over theintended operating range of the application.

Typical low-cost, 10 F ceramic capacitors are availablein X5R, X7R and Y5V dielectric ratings (other types arealso available, but are less common). The initial toler-ance specifications for these types of capacitors areoften specified as ±10% to ±20% (X5R and X7R), or-20%/+80% (Y5V). However, the effective capacitancethat these capacitors provide in an application circuit willalso vary based on additional factors, such as theapplied DC bias voltage and the temperature. The totalin-circuit tolerance is, therefore, much wider than theinitial tolerance specification.

The X5R and X7R capacitors typically exhibit satisfac-tory temperature stability (ex: ±15% over a widetemperature range, but consult the manufacturer’s datasheets for exact specifications). However, Y5V capaci-tors typically have extreme temperature tolerancespecifications of +22%/-82%. Due to the extreme tem-perature tolerance, a 10 F nominal rated Y5V typecapacitor may not deliver enough total capacitance tomeet minimum internal voltage regulator stability andtransient response requirements. Therefore, Y5Vcapacitors are not recommended for use with theinternal regulator if the application must operate over awide temperature range.

In addition to temperature tolerance, the effectivecapacitance of large value ceramic capacitors can varysubstantially, based on the amount of DC voltageapplied to the capacitor. This effect can be very signifi-cant, but is often overlooked or is not alwaysdocumented.

Typical DC bias voltage vs. capacitance graph for X7Rtype capacitors is shown in Figure 2-4.

FIGURE 2-4: DC BIAS VOLTAGE vs. CAPACITANCE CHARACTERISTICS

When selecting a ceramic capacitor to be used with theinternal voltage regulator, it is suggested to select ahigh-voltage rating, so that the operating voltage is asmall percentage of the maximum rated capacitor volt-age. For example, choose a ceramic capacitor rated at16V for the 2.5V or 1.8V core voltage. Suggestedcapacitors are shown in Table 2-1.

2.5 ICSP PinsThe PGECx and PGEDx pins are used for In-CircuitSerial Programming (ICSP) and debugging purposes.It is recommended to keep the trace length betweenthe ICSP connector and the ICSP pins on the device asshort as possible. If the ICSP connector is expected toexperience an ESD event, a series resistor is recom-mended, with the value in the range of a few tens ofohms, not to exceed 100Ω.

Pull-up resistors, series diodes and capacitors on thePGECx and PGEDx pins are not recommended as theywill interfere with the programmer/debugger communi-cations to the device. If such discrete components arean application requirement, they should be removedfrom the circuit during programming and debugging.Alternatively, refer to the AC/DC characteristics andtiming requirements information in the respectivedevice Flash programming specification for informationon capacitive loading limits and pin input voltage high(VIH) and input low (VIL) requirements.

For device emulation, ensure that the “CommunicationChannel Select” (i.e., PGECx/PGEDx pins),programmed into the device, matches the physicalconnections for the ICSP to the Microchipdebugger/emulator tool.

For more information on available Microchipdevelopment tools connection requirements, refer toSection 25.0 “Development Support”.

-80

-70

-60

-50

-40

-30

-20

-10

0

10

5 10 11 12 13 14 15 16 17

DC Bias Voltage (VDC)

Cap

acita

nce

Cha

nge

(%)

0 1 2 3 4 6 7 8 9

16V Capacitor

10V Capacitor

6.3V Capacitor



2.6 External Oscillator PinsMany microcontrollers have options for at least twooscillators: a high-frequency primary oscillator and alow-frequency secondary oscillator (refer toSection 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the sameside of the board as the device. Place the oscillatorcircuit close to the respective oscillator pins with nomore than 0.5 inch (12 mm) between the circuitcomponents and the pins. The load capacitors shouldbe placed next to the oscillator itself, on the same sideof the board.

Use a grounded copper pour around the oscillatorcircuit to isolate it from surrounding circuits. Thegrounded copper pour should be routed directly to theMCU ground. Do not run any signal traces or powertraces inside the ground pour. Also, if using a two-sidedboard, avoid any traces on the other side of the boardwhere the crystal is placed.

Layout suggestions are shown in Figure 2-5. In-linepackages may be handled with a single-sided layoutthat completely encompasses the oscillator pins. Withfine-pitch packages, it is not always possible to com-pletely surround the pins and components. A suitablesolution is to tie the broken guard sections to a mirroredground layer. In all cases, the guard trace(s) must bereturned to ground.

In planning the application’s routing and I/O assign-ments, ensure that adjacent port pins, and othersignals in close proximity to the oscillator, are benign(i.e., free of high frequencies, short rise and fall timesand other similar noise).

For additional information and design guidance onoscillator circuits, please refer to these MicrochipApplication Notes, available at the corporate web site(www.microchip.com):

• AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro® Devices”

• AN849, “Basic PICmicro® Oscillator Design”• AN943, “Practical PICmicro® Oscillator Analysis

and Design”• AN949, “Making Your Oscillator Work”

FIGURE 2-5: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT

GND

`

`

`

OSCI

OSCO

SOSCO

SOSC I

Copper Pour Primary OscillatorCrystal

Secondary

Crystal

DEVICE PINS

PrimaryOscillator

C1

C2

Sec Oscillator: C1 Sec Oscillator: C2

(tied to ground)

GND

OSCO

OSCI

Bottom LayerCopper Pour

OscillatorCrystal

Top Layer Copper Pour

C2

C1

DEVICE PINS

(tied to ground)

(tied to ground)

Single-Sided and In-line Layouts:

Fine-Pitch (Dual-Sided) Layouts:

Oscillator



2.7 Configuration of Analog and

Digital Pins During ICSP Operations

If an ICSP compliant emulator is selected as a debug-ger, it automatically initializes all of the A/D input pins(ANx) as “digital” pins. Depending on the particulardevice, this is done by setting all bits in the ADnPCFGregister(s), or clearing all bit in the ANSx registers.

All PIC24F devices will have either one or moreADnPCFG registers or several ANSx registers (one foreach port); no device will have both. Refer toSection 21.0 “10-Bit High-Speed A/D Converter” formore specific information.

The bits in these registers that correspond to the A/Dpins that initialized the emulator must not be changedby the user application firmware; otherwise,communication errors will result between the debuggerand the device.

If your application needs to use certain A/D pins asanalog input pins during the debug session, the userapplication must modify the appropriate bits duringinitialization of the A/D module, as follows:

• For devices with an ADnPCFG register, clear the bits corresponding to the pin(s) to be configured as analog. Do not change any other bits, particu-larly those corresponding to the PGECx/PGEDx pair, at any time.

• For devices with ANSx registers, set the bits corresponding to the pin(s) to be configured as analog. Do not change any other bits, particularly those corresponding to the PGECx/PGEDx pair, at any time.

When a Microchip debugger/emulator is used as aprogrammer, the user application firmware mustcorrectly configure the ADnPCFG or ANSx registers.Automatic initialization of this register is only doneduring debugger operation. Failure to correctlyconfigure the register(s) will result in all A/D pins beingrecognized as analog input pins, resulting in the portvalue being read as a logic ‘0’, which may affect userapplication functionality.

2.8 Unused I/OsUnused I/O pins should be configured as outputs anddriven to a logic low state. Alternatively, connect a 1 kΩto 10 kΩ resistor to VSS on unused pins and drive theoutput to logic low.



3.0 CPU

The PIC24F CPU has a 16-bit (data) modified Harvardarchitecture with an enhanced instruction set and a24-bit instruction word with a variable length opcodefield. The Program Counter (PC) is 23 bits wide andaddresses up to 4M instructions of user programmemory space. A single-cycle instruction prefetchmechanism is used to help maintain throughput and pro-vides predictable execution. All instructions execute in asingle cycle, with the exception of instructions thatchange the program flow, the double-word move(MOV.D) instruction and the table instructions. Over-head-free program loop constructs are supported usingthe REPEAT instructions, which are interruptible at anypoint.

PIC24F devices have sixteen, 16-bit working registersin the programmer’s model. Each of the workingregisters can act as a data, address or address offsetregister. The 16th working register (W15) operates asa Software Stack Pointer for interrupts and calls.

The upper 32 Kbytes of the data space memory mapcan optionally be mapped into program space at any16K word boundary defined by the 8-bit Program SpaceVisibility Page Address (PSVPAG) register. The programto data space mapping feature lets any instructionaccess program space as if it were data space.

The Instruction Set Architecture (ISA) has beensignificantly enhanced beyond that of the PIC18, butmaintains an acceptable level of backward compatibil-ity. All PIC18 instructions and addressing modes aresupported, either directly, or through simple macros.Many of the ISA enhancements have been driven bycompiler efficiency needs.

The core supports Inherent (no operand), Relative,Literal, Memory Direct and three groups of addressingmodes. All modes support Register Direct and variousRegister Indirect modes. Each group offers up to sevenaddressing modes. Instructions are associated withpredefined addressing modes depending upon theirfunctional requirements.

For most instructions, the core is capable of executinga data (or program data) memory read, a working reg-ister (data) read, a data memory write and a program(instruction) memory read per instruction cycle. As aresult, three parameter instructions can be supported,allowing trinary operations (that is, A + B = C) to beexecuted in a single cycle.

A high-speed, 17-bit by 17-bit multiplier has beenincluded to significantly enhance the core arithmeticcapability and throughput. The multiplier supportsSigned, Unsigned and Mixed mode, 16-bit by 16-bit or8-bit by 8-bit, integer multiplication. All multiplyinstructions execute in a single cycle.

The 16-bit ALU has been enhanced with integer divideassist hardware that supports an iterative non-restoringdivide algorithm. It operates in conjunction with theREPEAT instruction looping mechanism and a selectionof iterative divide instructions to support 32-bit (or16-bit), divided by 16-bit, integer signed and unsigneddivision. All divide operations require 19 cycles tocomplete, but are interruptible at any cycle boundary.

The PIC24F has a vectored exception scheme with upto 8 sources of non-maskable traps and up to 118 inter-rupt sources. Each interrupt source can be assigned toone of seven priority levels.

A “block diagram of the CPU is shown in Figure 3-1.

3.1 Programmer’s ModelThe programmer’s model for the PIC24F is shown inFigure 3-2. All registers in the programmer’s model arememory mapped and can be manipulated directly byinstructions. A description of each register is providedin Table 3-1. All registers associated with theprogrammer’s model are memory mapped.

Note: This data sheet summarizes the features ofthis group of PIC24F devices. It is notintended to be a comprehensive referencesource. For more information, refer to the“PIC24F Family Reference Manual”,“CPU” (DS39703).



FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM

InstructionDecode &

Control

16

16-Bit ALU

23

23

24

23

Data Bus

16

DivideSupport

ROM Latch

16

RAGUWAGU

16

16

8

InterruptController

Data Latch

Data RAM

AddressLatch

Control Signalsto Various Blocks

Program Memory

Data Latch

Address Bus

16

Lite

ral D

ata

16 16

HardwareMultiplier

16

To Peripheral Modules

Address Latch

PSV & TableData AccessControl Block

PCHProgram CounterStack

ControlLogic

LoopControlLogic

PCL

Instruction Reg

EA MUX

16 x 16W Register Array



TABLE 3-1: CPU CORE REGISTERS

FIGURE 3-2: PROGRAMMER’S MODEL

Register(s) Name Description

W0 through W15 Working Register ArrayPC 23-Bit Program CounterSR ALU STATUS RegisterSPLIM Stack Pointer Limit Value RegisterTBLPAG Table Memory Page Address RegisterPSVPAG Program Space Visibility Page Address RegisterRCOUNT Repeat Loop Counter RegisterCORCON CPU Control Register

N OV Z C

TBLPAG

22 0

7 0

015

Program Counter

Table Memory Page

ALU STATUS Register (SR)

Working/AddressRegisters

W0 (WREG)

W1

W2

W3

W4

W5

W6

W7

W8

W9

W10

W11

W12

W13

Frame Pointer

Stack Pointer

PSVPAG7 0

Program Space Visibility

RA

0

RCOUNT15 0

Repeat Loop Counter

SPLIM Stack Pointer Limit

SRL

Registers or bits shadowed for PUSH.S and POP.S instructions.

0

0

Page Address Register

15 0CPU Control Register (CORCON)

SRH

W14

W15

DC IPL2 1 0— ——————

IPL3 PSV— — — — — — — — — — — — — —

PC

Divider Working Registers

Multiplier Registers

15 0

Value Register

Address Register

Register



3.2 CPU Control Registers

REGISTER 3-1: SR: ALU STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0— — — — — — — DC

bit 15 bit 8

R/W-0(1) R/W-0(1) R/W-0(1) R-0 R/W-0 R/W-0 R/W-0 R/W-0IPL2(2) IPL1(2) IPL0(2) RA N OV Z C

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-9 Unimplemented: Read as ‘0’bit 8 DC: ALU Half Carry/Borrow bit

1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)of the result occurred

0 = No carry-out from the 4th or 8th low-order bit of the result has occurredbit 7-5 IPL: CPU Interrupt Priority Level Status bits(1,2)

111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled110 = CPU Interrupt Priority Level is 6 (14)101 = CPU Interrupt Priority Level is 5 (13)100 = CPU Interrupt Priority Level is 4 (12)011 = CPU Interrupt Priority Level is 3 (11)010 = CPU Interrupt Priority Level is 2 (10)001 = CPU Interrupt Priority Level is 1 (9)000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit1 = REPEAT loop in progress0 = REPEAT loop not in progress

bit 3 N: ALU Negative bit1 = Result was negative0 = Result was non-negative (zero or positive)

bit 2 OV: ALU Overflow bit1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation0 = No overflow has occurred

bit 1 Z: ALU Zero bit1 = An operation which effects the Z bit has set it at some time in the past0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result)

bit 0 C: ALU Carry/Borrow bit1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurred

Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1) = 1.2: The IPL Status bits are concatenated with the IPL3 bit (CORCON) to form the CPU Interrupt Priority

Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.



3.3 Arithmetic Logic Unit (ALU)The PIC24F ALU is 16 bits wide, and is capable of addi-tion, subtraction, bit shifts and logic operations. Unlessotherwise mentioned, arithmetic operations are 2’scomplement in nature. Depending on the operation, theALU may affect the values of the Carry (C), Zero (Z),Negative (N), Overflow (OV) and Digit Carry (DC)Status bits in the SR register. The C and DC Status bitsoperate as Borrow and Digit Borrow bits, respectively,for subtraction operations.

The ALU can perform 8-bit or 16-bit operations,depending on the mode of the instruction that is used.Data for the ALU operation can come from the Wregister array, or data memory, depending on theaddressing mode of the instruction. Likewise, outputdata from the ALU can be written to the W register arrayor a data memory location.

The PIC24F CPU incorporates hardware support forboth multiplication and division. This includes adedicated hardware multiplier and support hardwarefor 16-bit divisor division.

3.3.1 MULTIPLIERThe ALU contains a high-speed, 17-bit x 17-bitmultiplier. It supports unsigned, signed or mixed signoperation in several multiplication modes:

1. 16-bit x 16-bit signed2. 16-bit x 16-bit unsigned3. 16-bit signed x 5-bit (literal) unsigned4. 16-bit unsigned x 16-bit unsigned5. 16-bit unsigned x 5-bit (literal) unsigned6. 16-bit unsigned x 16-bit signed7. 8-bit unsigned x 8-bit unsigned

REGISTER 3-2: CORCON: CPU CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0— — — — IPL3(1) PSV — —

bit 7 bit 0

Legend: C = Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-4 Unimplemented: Read as ‘0’bit 3 IPL3: CPU Interrupt Priority Level Status bit(1)

1 = CPU Interrupt Priority Level is greater than 70 = CPU Interrupt Priority Level is 7 or less

bit 2 PSV: Program Space Visibility in Data Space Enable bit1 = Program space is visible in data space0 = Program space is not visible in data space

bit 1-0 Unimplemented: Read as ‘0’

Note 1: User interrupts are disabled when IPL3 = 1.



3.3.2 DIVIDERThe divide block supports 32-bit/16-bit and 16-bit/16-bitsigned and unsigned integer divide operations with thefollowing data sizes:

1. 32-bit signed/16-bit signed divide2. 32-bit unsigned/16-bit unsigned divide3. 16-bit signed/16-bit signed divide4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0and the remainder in W1. Sixteen-bit signed andunsigned DIV instructions can specify any W registerfor both the 16-bit divisor (Wn), and any W register(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.The divide algorithm takes one cycle per bit of divisor,so both 32-bit/16-bit and 16-bit/16-bit instructions takethe same number of cycles to execute.

3.3.3 MULTI-BIT SHIFT SUPPORTThe PIC24F ALU supports both single bit andsingle-cycle, multi-bit arithmetic and logic shifts.Multi-bit shifts are implemented using a shifter block,capable of performing up to a 15-bit arithmetic rightshift, or up to a 15-bit left shift, in a single cycle. Allmulti-bit shift instructions only support Register DirectAddressing for both the operand source and resultdestination.

A full summary of instructions that use the shiftoperation is provided below in Table 3-2.

TABLE 3-2: INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATIONInstruction Description

ASR Arithmetic shift right source register by one or more bits.SL Shift left source register by one or more bits.LSR Logical shift right source register by one or more bits.



4.0 MEMORY ORGANIZATIONAs Harvard architecture devices, PIC24F micro-controllers feature separate program and data memoryspaces and buses. This architecture also allows thedirect access of program memory from the data spaceduring code execution.

4.1 Program Address SpaceThe program address memory space of thePIC24FJ64GA004 family devices is 4M instructions.The space is addressable by a 24-bit value derived

from either the 23-bit Program Counter (PC) during pro-gram execution, or from table operation or data spaceremapping, as described in Section 4.3 “InterfacingProgram and Data Memory Spaces”. User access to the program memory space is restrictedto the lower half of the address range (000000h to7FFFFFh). The exception is the use of TBLRD/TBLWToperations which use TBLPAG to permit access tothe Configuration bits and Device ID sections of theconfiguration memory space.

Memory maps for the PIC24FJ64GA004 family ofdevices are shown in Figure 4-1.

FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES

000000h

0000FEh

000002h

000100h

F8000EhF80010h

FEFFFEh

FFFFFFh

000004h

000200h0001FEh000104h

Reset Address

User FlashProgram Memory(11K instructions)

DEVID (2)

GOTO Instruction

Reserved

Alternate Vector TableReserved

Interrupt Vector Table

PIC24FJ32GA

Con

figur

atio

n M

emor

y Sp

ace

Use

r Mem

ory

Spac

e

Flash Config Words

Note: Memory areas are not shown to scale.

Reset Address

Device Config Registers

DEVID (2)

GOTO Instruction

Reserved



PIC24FJ48GA

FF0000h

F7FFFEhF80000hDevice Config Registers

800000h7FFFFFh

Reserved

Reserved

Flash Config Words

00AC00h00ABFEh

UnimplementedRead ‘0’ Unimplemented

Read ‘0’

Reset Address



DEVID (2)

GOTO Instruction

Reserved



PIC24FJ64GA

Reserved

Flash Config Words

UnimplementedRead ‘0’

Reset Address

DEVID (2)

GOTO Instruction

Reserved



PIC24FJ16GA

Flash Config Words


Reserved

UnimplementedRead ‘0’

005800h0057FEh

002C00h002BFEh

User FlashProgram Memory(5.5K instructions)

008400h0083FEh




4.1.1 PROGRAM MEMORY

ORGANIZATIONThe program memory space is organized inword-addressable blocks. Although it is treated as24 bits wide, it is more appropriate to think of eachaddress of the program memory as a lower and upperword, with the upper byte of the upper word beingunimplemented. The lower word always has an evenaddress, while the upper word has an odd address(Figure 4-2).

Program memory addresses are always word-alignedon the lower word, and addresses are incremented ordecremented by two during code execution. Thisarrangement also provides compatibility with datamemory space addressing and makes it possible toaccess data in the program memory space.

4.1.2 HARD MEMORY VECTORSAll PIC24F devices reserve the addresses between00000h and 000200h for hard-coded program execu-tion vectors. A hardware Reset vector is provided toredirect code execution from the default value of thePC on device Reset to the actual start of code. A GOTOinstruction is programmed by the user at 000000h withthe actual address for the start of code at 000002h.

PIC24F devices also have two Interrupt Vector Tables(IVT), located from 000004h to 0000FFh and 000100hto 0001FFh. These vector tables allow each of themany device interrupt sources to be handled by sepa-rate ISRs. A more detailed discussion of the InterruptVector Tables is provided in Section 7.1 “InterruptVector Table”.

4.1.3 FLASH CONFIGURATION WORDSIn PIC24FJ64GA004 family devices, the top two wordsof on-chip program memory are reserved for configura-tion information. On device Reset, the configurationinformation is copied into the appropriate Configurationregisters. The addresses of the Flash ConfigurationWord for devices in the PIC24FJ64GA004 family areshown in Table 4-1. Their location in the memory mapis shown with the other memory vectors in Figure 4-1.

The Configuration Words in program memory are acompact format. The actual Configuration bits aremapped in several different registers in the configurationmemory space. Their order in the Flash ConfigurationWords does not reflect a corresponding arrangement inthe configuration space. Additional details on the deviceConfiguration Words are provided in Section 24.1“Configuration Bits”.

TABLE 4-1: FLASH CONFIGURATION WORDS FOR PIC24FJ64GA004 FAMILY DEVICES

FIGURE 4-2: PROGRAM MEMORY ORGANIZATION

DeviceProgram Memory

(K words)

Configuration Word

Addresses

PIC24FJ16GA 5.5 002BFCh:002BFEh

PIC24FJ32GA 11 0057FCh:0057FEh

PIC24FJ48GA 16 0083FCh:0083FEh

PIC24FJ64GA 22 00ABFCh:00ABFEh

0816

PC Address

000000h000002h000004h000006h

230000000000000000

0000000000000000

Program Memory‘Phantom’ Byte

(read as ‘0’)

least significant wordmost significant word

Instruction Width

000001h000003h000005h000007h

mswAddress (lsw Address)



4.2 Data Address SpaceThe PIC24F core has a separate, 16-bit wide data mem-ory space, addressable as a single linear range. Thedata space is accessed using two Address GenerationUnits (AGUs), one each for read and write operations.The data space memory map is shown in Figure 4-3.

All Effective Addresses (EAs) in the data memory spaceare 16 bits wide and point to bytes within the data space.This gives a data space address range of 64 Kbytes or32K words. The lower half of the data memory space(that is, when EA = 0) is used for implementedmemory addresses, while the upper half (EA = 1) isreserved for the Program Space Visibility (PSV) area(see Section 4.3.3 “Reading Data From ProgramMemory Using Program Space Visibility”).

PIC24FJ64GA004 family devices implement a total of8 Kbytes of data memory. Should an EA point to alocation outside of this area, an all zero word or byte willbe returned.

4.2.1 DATA SPACE WIDTHThe data memory space is organized inbyte-addressable, 16-bit wide blocks. Data is alignedin data memory and registers as 16-bit words, but alldata space EAs resolve to bytes. The Least SignificantBytes (LSBs) of each word have even addresses, whilethe Most Significant Bytes (MSBs) have oddaddresses.

FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES(1)

0000h07FEh

FFFEh

LSBAddressLSBMSB

MSBAddress

0001h07FFh

1FFFh

FFFFh

8001h 8000h7FFFh

0801h 0800h

2001h

Near

1FFEh

SFRSFR Space

Data RAM

2000h

7FFFh

Program SpaceVisibility Area

Note 1: Data memory areas are not shown to scale.2: Upper memory limit for PIC24FJ16GAXXX devices is 17FFh.

27FEh(2)2800h

27FFh(2)2801h

Space

Data SpaceImplemented

Data RAM

UnimplementedRead as ‘0’



4.2.2 DATA MEMORY ORGANIZATION

AND ALIGNMENTTo maintain backward compatibility with PIC® devicesand improve data space memory usage efficiency, thePIC24F instruction set supports both word and byteoperations. As a consequence of byte accessibility, allEffective Address (EA) calculations are internally scaledto step through word-aligned memory. For example, thecore recognizes that Post-Modified Register IndirectAddressing mode [Ws++] will result in a value of Ws + 1for byte operations and Ws + 2 for word operations.

Data byte reads will read the complete word which con-tains the byte, using the LSb of any EA to determinewhich byte to select. The selected byte is placed ontothe LSB of the data path. That is, data memory and reg-isters are organized as two parallel, byte-wide entitieswith shared (word) address decode but separate writelines. Data byte writes only write to the correspondingside of the array or register which matches the byteaddress.

All word accesses must be aligned to an even address.Misaligned word data fetches are not supported, socare must be taken when mixing byte and word opera-tions, or translating from 8-bit MCU code. If amisaligned read or write is attempted, an address errortrap will be generated. If the error occurred on a read,the instruction underway is completed; if it occurred ona write, the instruction will be executed but the write willnot occur. In either case, a trap is then executed, allow-ing the system and/or user to examine the machinestate prior to execution of the address Fault.

All byte loads into any W register are loaded into theLeast Significant Byte. The Most Significant Byte is notmodified.

A Sign-Extend (SE) instruction is provided to allowusers to translate 8-bit signed data to 16-bit signedvalues. Alternatively, for 16-bit unsigned data, userscan clear the MSB of any W register by executing aZero-Extend (ZE) instruction on the appropriateaddress.

Although most instructions are capable of operating onword or byte data sizes, it should be noted that someinstructions operate only on words.

4.2.3 NEAR DATA SPACEThe 8-Kbyte area between 0000h and 1FFFh isreferred to as the Near Data Space. Locations in thisspace are directly addressable via a 13-bit absoluteaddress field within all memory direct instructions. Theremainder of the data space is addressable indirectly.Additionally, the whole data space is addressable usingMOV instructions, which support Memory DirectAddressing with a 16-bit address field.

4.2.4 SFR SPACEThe first 2 Kbytes of the Near Data Space, from 0000hto 07FFh, are primarily occupied with Special FunctionRegisters (SFRs). These are used by the PIC24F coreand peripheral modules for controlling the operation ofthe device.

SFRs are distributed among the modules that theycontrol and are generally grouped together by module.Much of the SFR space contains unused addresses;these are read as ‘0’. A diagram of the SFR space,showing where SFRs are actually implemented, isshown in Table 4-2. Each implemented area indicatesa 32-byte region where at least one address is imple-mented as an SFR. A complete listing of implementedSFRs, including their addresses, is shown in Tables 4-3through 4-24.

TABLE 4-2: IMPLEMENTED REGIONS OF SFR DATA SPACESFR Space Address

xx00 xx20 xx40 xx60 xx80 xxA0 xxC0 xxE0

000h Core ICN Interrupts —100h Timers Capture — Compare — — —200h I2C™ UART SPI — — I/O300h A/D — — — — — —400h — — — — — — — —500h — — — — — — — —600h PMP RTC/Comp CRC — PPS700h — — System NVM/PMD — — — —

Legend: — = No implemented SFRs in this block


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PIC24FJ64G

A004 FA

MILY

T

it 3 Bit 2 Bit 1 Bit 0 All Resets

W 0000W 0000W 0000W 0000W 0000W 0000W 0000W 0000W 0000W 0000W 0000W 0000W 0000W 0000W 0000W 0800S xxxxP 0000P ter High Byte 0000T ress Register 0000P e Address Register 0000R xxxxS N OV Z C 0000C L3 PSV — — 0000D xxxxL

T

N Bit 2 Bit 1 Bit 0All

Resets

C E CN2IE CN1IE CN0IE 0000C E(1) CN18IE(1) CN17IE(1) CN16IE 0000C UE CN2PUE CN1PUE CN0PUE 0000C E(1) CN18PUE(1) CN17PUE(1) CN16PUE 0000LN

ABLE 4-3: CPU CORE REGISTERS MAPFile

Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 B

REG0 0000 Working Register 0





REG5 000A Working Register 5

REG6 000C Working Register 6

REG7 000E Working Register 7






REG13 001A Working Register 13

REG14 001C Working Register 14

REG15 001E Working Register 15

PLIM 0020 Stack Pointer Limit Value Register

CL 002E Program Counter Low Byte Register

CH 0030 — — — — — — — — Program Counter Regis

BLPAG 0032 — — — — — — — — Table Memory Page Add

SVPAG 0034 — — — — — — — — Program Space Visibility Pag

COUNT 0036 Repeat Loop Counter Register

R 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA

ORCON 0044 — — — — — — — — — — — — IP

ISICNT 0052 — — Disable Interrupts Counter Register

egend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

ABLE 4-4: ICN REGISTER MAP File ame Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3

NEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE(1) CN9IE(1) CN8IE(1) CN7IE CN6IE CN5IE CN4IE CN3I

NEN2 0062 — CN30IE CN29IE CN28IE(1) CN27IE CN26IE(1) CN25IE(1) CN24IE CN23IE CN22IE CN21IE CN20IE(1) CN19I

NPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE(1) CN9PUE(1) CN8PUE(1) CN7PUE CN6PUE CN5PUE CN4PUE CN3P

NPU2 006A — CN30PUE CN29PUE CN28PUE(1) CN27PUE CN26PUE(1) CN25PUE(1) CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE(1) CN19PU

egend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.ote 1: These bits are not available on 28-pin devices; read as ‘0’.

PIC24FJ64G

A004 FA

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39881E-page 34

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Bit 3 Bit 2 Bit 1 Bit 0 All Resets

ADDRERR STKERR OSCFAIL — 0000— INT2EP INT1EP INT0EP 0000

T1IF OC1IF IC1IF INT0IF 0000CNIF CMIF MI2C1IF SI2C1IF 0000

— — SPI2IF SPF2IF 0000— MI2C2IF SI2C2IF — 0000

CRCIF U2ERIF U1ERIF — 0000T1IE OC1IE IC1IE INT0IE 0000CNIE CMIE MI2C1IE SI2C1IE 0000

— — SPI2IE SPF2IE 0000— MI2C2IE SI2C2IE — 0000

CRCIE U2ERIE U1ERIE — 0000— INT0IP2 INT0IP1 INT0IP0 4444— — — — 4444— T3IP2 T3IP1 T3IP0 4444— U1TXIP2 U1TXIP1 U1TXIP0 4444— SI2C1P2 SI2C1P1 SI2C1P0 4444— INT1IP2 INT1IP1 INT1IP0 4444— — — — 4444— T5IP2 T5IP1 T5IP0 4444— SPF2IP2 SPF2IP1 SPF2IP0 4444— — — — 4444— — — — 4444— — — — 4444— — — — 4444— — — — 4444— — — — 4444— LVDIP2 LVDIP1 LVDIP0 4444

VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000

TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAPFile

Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

INTCON1 0080 NSTDIS — — — — — — — — — — MATHERR

INTCON2 0082 ALTIVT DISI — — — — — — — — — —

IFS0 0084 — — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF —

IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — — — — INT1IF

IFS2 0088 — — PMPIF — — — OC5IF — IC5IF IC4IF IC3IF —

IFS3 008A — RTCIF — — — — — — — — — —

IFS4 008C — — — — — — — LVDIF — — — —

IEC0 0094 — — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE OC2IE IC2IE —

IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE — — — — INT1IE

IEC2 0098 — — PMPIE — — — OC5IE — IC5IE IC4IE IC3IE —

IEC3 009A — RTCIE — — — — — — — — — —

IEC4 009C — — — — — — — LVDIE — — — —

IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0

IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0

IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 SPF1IP0

IPC3 00AA — — — — — — — — — AD1IP2 AD1IP1 AD1IP0

IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1P2 MI2C1P1 MI2C1P0

IPC5 00AE — — — — — — — — — — — —

IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0

IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0

IPC8 00B4 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0

IPC9 00B6 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0

IPC10 00B8 — — — — — — — — — OC5IP2 OC5IP1 OC5IP0

IPC11 00BA — — — — — — — — — PMPIP2 PMPIP1 PMPIP0

IPC12 00BC — — — — — MI2C2P2 MI2C2P1 MI2C2P0 — SI2C2P2 SI2C2P1 SI2C2P0

IPC15 00C2 — — — — — RTCIP2 RTCIP1 RTCIP0 — — — —

IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0

IPC18 00C8 — — — — — — — — — — — —

INTTREG 00E0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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PIC24FJ64G

A004 FA

MILY

T

F Bit 3 Bit 2 Bit 1 Bit 0 All Resets

T 0000P FFFFT — TSYNC TCS — 0000T 0000T 0000T 0000P FFFFP FFFFT T32 — TCS — 0000T — — TCS — 0000T 0000T 0000T 0000P FFFFP FFFFT T32 — TCS — 0000T — — TCS — 0000L

T

Bit 3 Bit 2 Bit 1 Bit 0 All Resets

I FFFFI CBNE ICM2 ICM1 ICM0 0000I FFFFI CBNE ICM2 ICM1 ICM0 0000I FFFFI CBNE ICM2 ICM1 ICM0 0000I FFFFI CBNE ICM2 ICM1 ICM0 0000I FFFFI CBNE ICM2 ICM1 ICM0 0000L

ABLE 4-6: TIMER REGISTER MAP

ile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

MR1 0100 Timer1 Register

R1 0102 Timer1 Period Register

1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0


MR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only)

MR3 010A Timer3 Register

R2 010C Timer2 Period Register

R3 010E Timer3 Period Register




MR5HLD 0116 Timer5 Holding Register (for 32-bit operations only)


R4 011A Timer4 Period Register

R5 011C Timer5 Period Register

4CON 011E TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0


egend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

ABLE 4-7: INPUT CAPTURE REGISTER MAPFile

Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

C1BUF 0140 Input Capture 1 Register

C1CON 0142 — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV I

C2BUF 0144 Input Capture 2 Register

C2CON 0146 — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV I

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