Œß[pi¸‹Ýwœy i‡ ı -...
TRANSCRIPT
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P.1
電子構裝基礎概念
呂宗興
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P.2
1.構裝技術簡介
2. IC構裝製程
3.基板類型簡介
4.先進 IC構裝
5.構裝技術之展望
內 容
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P.3
電子構裝之定義及範圍
電腦 通訊 民生
所需技術:電子、機械、物理、化學、材料、光學、可靠性工程、人因工程…..等多重領域之工程技術。
定義:微電子技術之發展日新月異,電子零組件之尺寸不斷縮小,零組件之間必須透過高效能、高可靠性、高密度及低成本之互連(Interconnection),才能建構成一個具有廣泛性功能及實用價值之電子產品;而建構此互連技術之相關工程技藝,被統合稱為電子構裝技術。
應用產品:
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P.4
第二階層構裝
第一階層構裝
第三階層構裝
晶圓(Wafer)
晶片(Chip)
多晶片模組(MCM)單晶片構裝
電子構裝之層級
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P.5
Images
3D Graphics
建構人機介面
協助散熱保護元件
電源供應層
信號分佈層
電子構裝之主要功能
1.有效供應電源
2.提供信號傳輸
3.協助排除耗熱
4.保護電子組件
5.建構人機介面
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P.6
DIP
Dual In-LinePackage
PGA
Pin Grid Array
SOP
Small OutlinePackage
SOJ
Small OutlineJ-Lead
PLCC
Plastic LeadedChip Carrier
QFP
Quad Flat Pack
常見之封裝形式
PBGA
Plastic ball Grid Array
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P.7
PBGA
QFP
TSOP
SOP
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P.8
金線(Gold Wire)晶片(Chip)
晶片座(Die Pad) 銀膠(Silver Epoxy)
引腳(Lead)
單晶片構裝之基本結構
膠體(Epoxy Molding Compound)
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P.9Ball Grid Array (BGA)結構
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P.10
面積陣列構裝之優、缺點
優點:1.在一定表面積下,可提供更多之輸出/輸入接點。2.具薄型化之方便性。3.焊點間距縮小,有利於小型化。4.可使用多層基板設計,有效改善電氣特性。5.具彈性之結構設計,可有效提升散熱性能。6.易於擴充至多晶片模組領域。7.可使用較寬鬆之SMT對位精度及平整度製程要求。
缺點:1.成本較傳統構裝為高。2.因膠體結構之非對稱性,可靠性較傳統構裝差。
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P.11晶片互連技術 (Chip Interconnection)
1.焊線接合(Wire Bonding)─使用金線或鋁線,以熱壓及超音波接合
2.覆晶接合(Flip Chip Bonding)─使用錫鉛迴焊或(非)導電膠固化接合
3.卷帶式接合(TAB─Tape Automatic Bonding)─使用金對金熱壓接合
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P.12
Wire Bonding
Flip Chip Bonding
TAB
1 10 100 1000 10000
接點數/晶片
技術種類
接點數與接合技術之選擇
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P.13
TO DIP
QFP
BGA
TCP
Chip Scale Pacage
Direct ChipAttach
on Board
1970 1980 1990 2000 2010
PTH SMTArea
ArrayFine PitchArea Array
單晶片構裝之演變
PGA
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P.14
1.構裝技術簡介
2. IC構裝製程
3.基板類型簡介
4.先進 IC構裝
5.構裝技術之展望
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P.15
IC構裝製程 -前段
研磨前晶圓
研磨後晶圓
晶片(Chip)
晶圓背面研磨 晶圓切割
晶片黏接
銲線
Wafer BacksideGrinding Wafer Sawing Die Bonding
Wire Bonding
導線架(Leadframe)
說明:1.研磨之主要目地,在控制適當晶片厚度以方便後續製程。2.晶片黏接主要使用材料為銀膠或其他非導電性環氧樹脂,一般需後烘烤1小時以充分熟化膠體。
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P.16
IC構裝製程 -後段正極 負極
Transfer Molding Solder Plating Trimming & Forming
壓模成型 錫鉛電鍍 彎腳成型
說明:1.壓模成型後,通常需1~4小時之後烘烤製程,讓膠體充分熟化。2.一般錫鉛電鍍成分比例,錫90%鉛10%。3.Trimming製程之主要目地,在去除膠渣及導線架不必要之連桿,Trimming製程有時安排於電鍍製程前。
4.後段製程細分時,可包括膠體背印及正印製程。
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P.17
塑膠IC構裝常見之破壞模式
1. 脫層(Delamination)2. 金線斷裂3. 金線短路4. 金球脫落 (lifted bond)5. 金線線弧偏移(Wire sweep)6. 焊墊污染7. 黏晶膠氣孔8. 封裝體破裂9. 晶片龜裂10.晶片覆層(Passivation)龜裂11.封裝體氣孔(Mold void)
晶片(Die)
5 2
3
6
10
4 11
1
9
7
8
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P.18
吸濕氣
暴露於濕氣環境
製程中加熱時產生蒸氣袋
迴焊(Solder Reflow)製程加熱
蒸氣壓增大膠體變形
溫度增高 降溫冷卻
膠體龜裂擴至表面
塑膠構裝之爆米花效應 (Popcorn effect)
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P.19
IC Package熱傳輸路徑
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P.20
1.構裝技術簡介
2. IC構裝製程
3.基板類型簡介
4.先進 IC構裝
5.構裝技術之展望
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P.21基板類型
多層基板
積層式印刷電路板(Laminated PCB)
共燒陶瓷基板(Cofired Ceramics)
薄膜沉積基板(Deposited Thin Film)
Thin film on silicon
Thin film on ceramics
Thin film on metal
軟性基板(Flexible PCB)
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P.22
認識印刷電路板 (PCB)
1.單面板 單層信號層
2.雙面板 雙層信號層
3.多層板 雙層信號層雙層電源層
4.多層板 四層信號層雙層電源層
S
S
S
SPP
S
SPSSP
S
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P.23
1層
2層3曾
4層5層
6層7層
8層
頂疊層夾具
離型紙
1 oz銅箔
B stage(prepreg)
內層板
底疊層夾具
定位銷
熱壓
PCB之疊層與壓合
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P.24
1.構裝技術簡介
2. IC構裝製程
3.基板類型簡介
4.先進 IC構裝
5.構裝技術之展望
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P.25
CSP (Chip Scale Package)
覆晶(Flip Chip )技術。小尺寸。低電感。高 I/O
Chip Scale構裝
Surface Mount。標準化。易於生產。可測性。可重工。可靠性
Definition : chip scale package (CSP) is a package whose package-to-silicon area ratio less than 120 percent.
CSP is derived from existing packages, that is, it can be any type ofpackages.
Silicon
Package area
Silicon area< 1.2
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P.26
CSP之分類
1.硬板中介層(Rigid Substrate Interposer)
2.導線架型式(Leadframe Type)
3.軟板中介層(Flex circuit Interposer)
4.無中介層,壓模成型(Transfer Molding)
5.晶圓層級(Wafer-Level)
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P.27
Flip Chip
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P.28
Flip Chip基本結構
fcPBGA
fcCSP
Super FC
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P.29Multi Chip Module
Definition : Multi chip module (MCM) is a module orpackage which usually contains a high density interconnectsubstrate, several active and passive components, and apackage which can be connected to the next level ofinterconnection.
ChipChip Chip
Chip Chip
Single Chip Module Multi Chip Module (MCM)
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P.30
What is KGD?
has quality and reliability comparable to itsfunctionally equivalent packaged component,
can be interconnected to its next level ofpackaging by wirebond, tape automated bonding,or flip -chip.
Known Good Die (KGD) is a die which has beenmanufactured and delivered in a bare, or minimallypackaged die format, which
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P.31MCM Yield as Function of Die Yield
Source : TechSearch International, Inc.
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P.32
1.構裝技術簡介
2. IC構裝製程
3.基板類型簡介
4.先進 IC構裝
5.構裝技術之展望
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P.33
基板發展幾個重要方向:A.有機基板仍為發展主流。B.滿足Flip Chip及SIP需求之高密度Build-up基板仍需加強發展。C.High Tg基板。D.內藏式功能性基板之挑戰─High Dk及製造參數之精確度。
IC構裝幾個重要課題:A.整合MEMS&3D發展先進構裝之開發。B.SIP(SOP)之挑戰─整合設計、製造服務導向。C.DCA、COB與SMT混載式模組構裝製程服務逐漸興起。
構裝技術發展之重要課題
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P.34
System in Package
Integral Substrate
MEMS / 3D Package
O-E Package / EOCB
Green Packaging
System-in-a-Package
Built-in C
Built-in R
Built-in LGND
Wave guideVccZ-connectionBuilt-in Active
3D Package O-E Device
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P.35
CIB (Chip In Board)
Through Hole
COC (Chip on Chip)
Wire Bonding Wireless Bonding (FCB, others)
3D Packages
Source:JEITA
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P.36CiSP – Chip in Substrate Package
Source: from ITRI (工研院)
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P.37
Ultra Thin Wafer
Source:IZM
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P.38
環保製程之需求
Halogen Free LaminateMaterial
Lead Free SMT
Lead Free Flip Chip
BGA on BoardAlloy: Sn/Ag/Cu
PhosphorousBase Epoxy