physical analysis and design of nanoscale...

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PHYSICAL ANALYSIS AND DESIGN OF NANOSCALE FLOATING-BODYDRAM CELLS

By

ZHICHAO LU

A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL

OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT

OF THE REQUIREMENTS FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA

2010

2

© 2010 Zhichao Lu

3

To my parents

4

ACKNOWLEDGEMENTS

This thesis is a collection of my five "memory" years at Gainesville. It is not only

my research work, but also advice, encouragement, guidance and unrelenting support from

Professor Jerry G. Fossum who served as my advisor during the past five "memory" years.

I have my most sincere gratitude to him. His insights, enthusiasm, approaches to problems,

and being a role model as a researcher and as a person will set the highest standards that I

will be aspiring to always.

I would also like to extend my sincere gratitude to the members of my supervisory

committee (Professors Robert Fox, Jing Guo, Scott E. Thompson, Amlan Biswas and Art

Hebard) for their guidance and willing service. I would like to thank my mentor at IMEC,

Dr. Malgorzata Jurczak, for her insightful perspective on research and encouragement. I

would like to express my gratitude to my colleagues, Dr. Nadine Collaert and Marc

Aoulaiche, for their technical disscusions and friendships.

I am grateful to the Freescale Semiconductor Inc., Samsung Electronics and

SEMATECH for their technical and financial support. Especially, I thank Dr. Rusty Harris

and Dr. Ji-Woon Yang at SEMATECH for providing silicon devices for measurements.

I would also like to thank my fellow students, Murshed M. Chowdhury, Weimin

Zhang, Seung-Hwan Kim, Vishal Trivedi, Shishir Agrawal, Siddharth Chouksey, Zhenming

Zhou, Dabraj Sarkar for their insightful and technical discussions and friendships. I must

say I am fortunate to have known all the friends here who have encouraged and cheered me

up throughout all the years. Especially, I thank Dr. Weimin Zhang for helping a lot when I

first came to Gainesville.

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I would like to thank to my lovely girlfriend Mei Zhao. I am really grateful for her

companionship and for her being so kind and supportive. Meeting her could be one of the

most wonderful things when I was in Gainesville.

This work would not have been possible without the unyielding support of my

parents. I am deeply indebted to them for their love and support.

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TABLE OF CONTENTS

page

ACKNOWLEDGEMENTS ............................................................................................................4

LIST OF TABLES ..........................................................................................................................8

LIST OF FIGURES ........................................................................................................................9

LIST OF ABBREVIATIONS ......................................................................................................11

ABSTRACT..................................................................................................................................13

CHAPTER

1 INTRODUCTION ....................................................................................................... 15

1.1 Scaling Difficulties with Conventional DRAM Cell .......................................... 151.2 Capacitorless DRAM......................................................................................... 171.3 New Physical Insights on "Capacitorless" DRAM Cell ...................................... 20

2 TWO-TRANSISTOR FLOATING-BODY/GATE CELL: A NOVEL LOW-POWERNANOSCALE EMBEDDED DRAM CELL................................................................. 30

2.1 Introduction ...................................................................................................... 302.2 Two-Transistor Floating-Body Cell Concept ..................................................... 322.3 Performance Evaluation of the Floating-Body/Gate Cell.................................... 362.4 Summary........................................................................................................... 41

3 "P+ SOURCE" FLOATING-BODY/GATE CELL: A MANUFACTURABLENANOSCALE EMBEDDED DRAM CELL................................................................. 54

3.1 Introduction ...................................................................................................... 543.2 "P+ Source" Floating-Body/Gate Cell Concept .................................................. 543.3 Operation and Performance of the "P+ Source" Floating-Body/Gate Cell ........... 553.4 Experimental Demonstration of the "P+ Source" Floating-Body/ Gate Cell ....... 563.5 Summary........................................................................................................... 57

4 PHYSICAL INSIGHTS AND MODELING OF GATE-INDUCED DRAIN LEAKAGECURRENT IN FLOATING-BODY CELL ................................................................... 67

4.1 Introduction ...................................................................................................... 674.2 Non-Quasi-Static Hole Redistribution and Its Effect on Gate-Induced Drain

Leakage Current ................................................................................................ 684.3 Body-Bias Dependence of Gate-Induced Drain Leakage Current ....................... 694.4 Model Development for Body Bias-Dependent Gate-Induced Drain Leakage

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Current .............................................................................................................. 714.5 Summary........................................................................................................... 74

5 FLOATING-BODY/GATE CELLS UPGRADED FOR ULTRA-LONG RETENTIONTIME AND ULTRA-FAST WRITE TIME .................................................................. 81

5.1 Introduction ...................................................................................................... 815.2 Floating- Body/Gate Cell Upgraded for Ultra Long Retention Time ................. 815.3 Floating-Body/Gate Cell Upgraded for Ultra Fast Write Time .......................... 905.4 Comparison of the Floating-Body DRAM Cells ................................................ 925.5 Summary........................................................................................................... 94

6 SUMMARY AND SUGGESTIONS FOR FUTURE WORK .......................................110

6.1 Summary..........................................................................................................1106.2 Suggestions for Future Work ............................................................................113

LIST OF REFERENCES............................................................................................................115

BIOGRAPHICAL SKETCH ......................................................................................................120

8

LIST OF TABLES

Table page

2-1 Charging/discharging-current comparison between the FBGC and 1T FBCs...................53

5-1 Performance comparison among the FBGC3, FBGC4 and 1T FBCs. ............................109

9

LIST OF FIGURES

Figure page

1-1 Predicted operation (with IGi body charging) of the IG-FinFET FBC . . . . . . . . 27

1-2 Predicted hole density along the back surface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1-3 Sketch of the perturbation of the energy-band diagram. . . . . . . . . . . . . . . . . . . . . . 29

2-1 The 2T floating-body cell (FBC) in a DRAM array. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2-2 Schematic cross-sectional view of a 2T (n-channel) FBC fabricated . . . . . . . . . . . . . . 44

2-3 UFDG/Spice3-predictedtransient sequential operation of a 2T FBC. . . . . . . . . . . . 45

2-4 Transient sequential operation of a 2T FBC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2-5 The FBGC structure in a DRAM array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2-6 Transient sequential memory operation of an FBGC as depicted in Fig. 2.5. . . . . . . . . 48

2-7 UFDG/Spice3-predictedtransient sequential memory operation of a 2T FBGC . . . . 49

2-8 UFDG/Spice3-predicted transient sequential memory operation of the 2T FBGC . . . . 50

2-9 Worst-case data retention/disturb characteristics of the 2T FBGC in Fig. 2.7. . . . . . . . 51

2-10 UFDG/Spice3-predicted BL2 read-voltage and T2 read-current . . . . . . . . . . . . . . . . . . 52

3-1 The simplified FBGC structure, on SOI, in a DRAM array with two bit lines. . . . . . . . 59

3-2 Transient sequential memory operation of the new FBGC structure . . . . . . . . . . . . . . 60

3-3 Cross-section TEM of the FinFET structure used for both T1 and T2 . . . . . . . . . 61

3-4 Measured current-voltage characteristics of the p+p-n+ gated diode . . . . . . . . . . . . . . . 62

3-5 Measured current-voltage characteristicsof the double-gate nFinFET. . . . . . . . . . 63

3-6 Circuit configuration of the measurement setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3-7 Measured transient sequential write/hold/read operations for ’1’ and ’0’ . . . . . . 65

3-8 Measured transient sequential write/hold/read operations for ’1’ and ’0’ . . . . . . 66

4-1 Drain current-gate voltage characteristics of T1 and holes distribution . . . . . . . . 76

10

4-2 Measured dependence of the GIDL current on the body voltage . . . . . . . . . . . . . . 77

4-3 Cross section of gated diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4-4 Band diagram at the overlap region along the vertical direction . . . . . . . . . . . . . . 79

4-5 Band diagram along the vertical direction with accumulation and depletion . . . . 80

5-1 The FBGC3 structure, on SOI, in a DRAM array with two bit lines. . . . . . . . . . . . . . . 95

5-2 SenTaurus-predicted BTB tunneling current in T1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5-3 BTBT currents with different G-D underlap predicted by SenTaurus. . . . . . . . . . . . . . 97

5-4 ID-VD characteristics of T1 predicted by SenTaurus.. . . . . . . . . . . . . . . . . . . . . . . . . . . 98

5-5 ID-VG characteristics of T2 predicted by SenTaurus.. . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5-6 Transient sequential memory operation of a FBGC3 cell. . . . . . . . . . . . . . . . . . . . . . . 100

5-7 Worst-case charge/data retention characteristics of the FBGC3 . . . . . . . . . . . . . . . . . 101

5-8 Transient sequential memory operation of the FBGC3 with BL1 and BL2 tie together 102

5-9 Transient sequential memory operation of the FBGC3 with optimal pulses. . . . . . . . 103

5-10 Transient sequential memory operation of the FBGC3 with no spacer of T1.. . . . . . . 104

5-11 Data retention characteristics of FBGC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

5-12 Sense margin, ID of T2, and max. number of cells vs. gate work-function of T2. . . . 106

5-13 The FBGC4 structure in a DRAM array with two BLs.. . . . . . . . . . . . . . . . . . . . . . . . 107

5-14 Transient sequential memory operation of a FBGC4 cell. . . . . . . . . . . . . . . . . . . . . . . 108

11

LIST OF ABBREVIATIONS

1T FBC one-transistor floating-body cell

2T FBC two-transistor floating-body cell

BJT bipolar junction transistor

BTBT band to band tunnelling

CMOS complementary metal-oxide-semiconductor

DG double-gate

DIBL drain-induced barrier lowering

DOS density of states

DRAM dynamic random access memory

FB floating body

FBC floating-body cell

FBGC1 floating body/gate cell Ver. 1




FD fully depleted

FET field-effect transistor

GIDL gate-induced drain leakage

ITFET FinFET-based inverted-T FET

LOP low operating power

LSTP low standby power

MOSFET metal-oxide-semiconductor field-effect transistor

nFET n-type field-effect transistor

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nFinFET n-type FinFET

nITFET n-type ITFET

nMOSFET n-type MOSFET

PD partially depleted

pFET p-type field-effect transistor

pMOSFET p-type MOSFET

SCE short-channel effect

SG single gate

SOI silicon-on-insulator

SRAM static random access memory

SOC system-on-chip

UFDG University of Florida double-gate (MOSFET model)

UFPDB University of Florida partially depleted SOI and bulk (MOSFET model)

UTB ultra-thin body

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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy

PHYSICAL ANALYSIS AND DESIGN OF NANOSCALE FLOATING-BODYDRAM CELLS

By

Zhichao Lu

December 2010

Chair: Jerry G. FossumMajor: Electrical and Computer Engineering

This dissertation addresses physical analysis and design issues of nanoscale floating-

body cells (FBC), which are also known as capacitorless dynamic random-access memory

(DRAM) cells. A novel two-transistor floating-body/gate cell (FBGC), and upgraded

versions of it, are proposed and experimentally demonstrated.

As the conventional one-transistor and one-capacitor (1T/1C) DRAM technology is

aggressively scaled, novel device structures and materials have to be introduced to meet

International Technology Roadmap for Semiconductors (ITRS) performance requirements.

Novel device structures and materials bring a lot of processing and integration challenges

to current complementary metal-oxide-semiconductor (CMOS) technology. To avoid these

challenges, capacitorless DRAM, which is based on silicon-on-insulator (SOI) CMOS

including partially depleted (PD) and fully depleted (FD) MOS transistors (MOSFETs), is

attracting a lot of interest. This technology, which uses the floating body of the SOI

MOSFET as the storage element, can potentially replace the conventional 1T/1C DRAM

cell in the near future. The basic working principle of the FBC is to utilize the floating-body

effect inherent in the PD/SOI MOSFET; the FD/SOI MOSFET also shows the floating-body

effect when the substrate, or back gate is biased for accumulation. However, the physical

explanation of the floating-body effect in the FD/SOI device is not clear. Based on

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numerical simulations, physical insights are gained on the effect and on FBC performance,

e.g., the sense margin.

Relying on the physical insights of the floating-body effects, a novel two- transistor

(2T) FBC is proposed. By using the first transistor’s (T1) body to directly drive the second

transistor’s gate, the 2T FBC eliminates the body-factor limitation on the sense margin. The

memory performance is demonstrated with the University of Florida physics-based compact

double-gate MOSFET model (UFDG). The predicted results show that the common impact

ionization-based write method produces too much power dissipation. To resolve this

problem, the 2T-FBC is refined to Ver. 1 of the floating-body/gate cell (FBGC1). The major

feature of FBGC1 is the source tied source to the drain in T1. To improve the

manufacturability of FBGC1, Ver. 2 (FBGC2) is proposed, which in essence is a gated

diode (T1) plus a conventional transistor (T2). Gate-induced drain leakage (GIDL) current

is used to write ’1’ in FBGC2. The performance is demonstrated by 90nm FinFET

technology and also by numerical simulation. One issue with FBGC2 is the short retention

time with bit-line (BL) disturbs. Hence Ver. 3 (FBGC3) is proposed to the resolve this

problem. Unlike FBGC2 which accumulates the channel to get GIDL charging current,

FBGC3 inverts the channel and introduces tunneling current at the source side for charging,

thereby separating the charging mechanisms for write and hold. By optimizing the device

structure, FBGC3 demonstrates ~10s retention time with worst-case disturb. To make

FBGC3 operate faster, Ver. 4 (FBGC4) is proposed. In FBGC4, T1 reverts back to a normal

transistor. However, special designs are made at the source side; n+ and p+ regions are used

to tie the source to the body. The performance, with ~100ps write/read times, is analyzed

by the University of Florida physics-based compact SOI MOSFET model (UFPDB).

ists

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r and

CHAPTER 1

INTRODUCTION

1.1 Scaling Difficulties with Conventional DRAM Cell

The conventional dynamic random access memory (DRAM) cell, which cons

of one transistor and one capacitor (1T/1C), has been the workhorse memory cell in

high-density memory arena for more than three decades [1]-[2]. With the innovations

DRAM structures, and utilization of new materials, the conventional 1T/1C DRAM cel

evolving to the 60nm technology node and 4Gb capacity [3]-[6]. Scaling the DRAM cel

sub-60nm technology nodes, as demanded by high-density storage and low bit cost, is

challenging. Scaling issues are directly related to the requirement of storing a critical

amount of charge on the capacitor for a certain time. To guarantee proper DRAM cel

operation, the sensing signal should be larger than sensing noise to ensure the corre

sensing in the noise environment. Generally, the requirements of the access transisto

the storage capacitance can be summarized as follows [5][7][8]:

, (1.1)

fF/Cell, (1.2)

a fewµA/Cell, (1.3)

few fA/Cell, (1.4)

CsCs CBL+-------------------------

VDD2

------------- 150mV≥⋅

Cs 25≥

Ion ≥

Ioff ≤

15

nd

osed

ode

e V

tive

yond

or

ge

hes is

es

AM

OT)

This

use of

be

where CS is the storage capacitance, CBL is the bit-line (BL) parasitic capacitance (the

typical value is 75fF for one bit line [9]), and VDD is the supply voltage. With regard to the

scalability of the access transistor, maintaining relatively high threshold voltage (Vt), e.g.,

1V, is an effective way to get less than a fA/cell leakage current and severalµA/cell on-

current simultaneously. So-called Localized Asymmetric Channel Doping (L-ASC) [10] a

Recessed Channel Array Transistor (RCAT) [11] are the two approaches that were prop

to solve this problem. L-ASC can eliminate the junction leakage current at the storage n

by decreasing the doping concentration only at the storage node while maintaining tht.

RCAT can significantly suppress short-channel effects (SCEs) by increasing the effec

channel length without area penalty due to its recessed-channel geometry structure. Be

50nm technology node, a body-tied bulk FinFET or a vertical surrouded-gate transist

could be utilized due to their excellent immunity of SCEs, relatively low junction leaka

(undoped body), and high transconductance. But, the disadvantage of these approac

less compatibility to the conventional planar CMOS logic technology. These approach

inevitably require extra fabrication steps which increase the cost of fabrication [12].

Compared with the scalability issues of the access transistor, the scaling

difficulties with the storage capacitors are more serious and ambiguous. Since the DR

storage area becomes physically smaller with scaling, the effective oxide thickness (E

must scale down sharply to maintain non-scalable storage capacitance (~25fF/Cell).

will lead to extraordinary large aspect ratio for trench capacitors or larger cell size in

stacked capacitors. Moreover, dielectric thickness cannot be reduced excessively beca

concern over high tunneling leakage current. High-k material, such as HfSiO, Al2O3, ZrO2,

or Ta2O5 [13], with new capacitor structure, such as Metal-Insulator-Metal [13], could

16

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r

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, it

ced

ign

ways to resolve this problem. Many efforts have been made to investigate these new

materials and structures. But, these methods involve challenges in low-temperature

processing, good adhersion/deposition properties, and sufficiently low tunneling leak

current [14]. In addition, these new materials and structures are not compatible with t

conventional CMOS technology and will increase the bit cost [14]. These unresolved

problems with the 1T/1C DRAM cell have lead to uncertainty in industry over how far

conventional 1T/1C DRAM technology can go.

1.2 Capacitorless DRAM

To overcome the difficulties in scaling the conventional 1T/1C DRAM cell, 1

capacitorless DRAM [15]-[17] has been proposed. The capacitorless DRAM cell, whic

simply a MOSFET with a floating body, i.e., a floating-body cell (FBC), offers several

advantages: (1) no complex capacitor integration technology, which implies better

scalability beyond 50nm technology node; (2) full compatibility of memory and logic

technology, and 4F2 cell area; and (3) better electrical performance, such as low powe

dissipation, high speed, and better sense margin.

Initially, there was considerable interest in the FBC based on the partially

depleted (PD) SOI MOSFET [18] [19], and on the bulk-Si MOSFET [20]. Recently, the

interest moved to fully depleted (FD) SOI MOSFETs [21]-[23] and FD double-gate (D

FinFETs [24]-[26], which have more potential scalability. For the FD (n-channel) cells

is pervasively acknowledged [22][25]-[28] that a hole accumulation layer must be indu

by substrate or back-gate bias (VGbS) to form a deep potential well for hole storage, as

thought to exist naturally in the PD cell [17][23]. The published descriptions of the

capacitorless FBC operation based on the notion of a potential well, and the cell-des

17

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ting-

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35].

rable

implications of it, are inadequate and misleading. Later in this chapter, using numeric

device simulations and analytical modeling, we physically overview the basic operatio

the FBC, clarify the misleading "hole well" concept and revealing new insights that co

lead to optimal cell design.

The advanced CMOS technology, e.g. FinFET technology, could enable sca

of the 1T FBC to gate lengths (Lg) less than 10nm [27][29]-[31]. The basic current-signa

margin of the 1T FBC, defined by the threshold-voltage difference corresponding to t

body-voltage (VBS) variation due to body charging/discharging, is fundamentally restricte

∆Vt = -r∆VBS where the body factor r ~ 0.3 [32] when SCEs are controlled. This restricti

and other issues, e.g. sophisticated current sensing circuits [33], have led to our conce

of a 2T FBC, in which the floating charged/discharged body of one transistor (T1) dire

drives the gate of a second transistor (T2), thereby removing the r-factor restriction in

signal margin. In Chapter 2, we first present a novel 2T-FBC concept, and then demons

a new 2T-FBC configuration, which in essence is a floating-body/gate cell (FBGC) [3

That yields dramatic reduction in power dissipation, in addition to better signal margin

comparable data retention time, and higher density.

The simulations done in Chapter 2 demonstrate that floating-body/gate DRA

cell (FBGC) which we call Ver. 1 (FBGC1), on SOI [34][35], can potentially yield bette

signal margin, less power dissipation, and higher effective density than all other 1T floa

body DRAM cells (FBCs). However, an issue with FBGC1 is the process integration f

tying the body of T1 to the gate of T2, which undermines cell area and memory density [

We address this issue in Chapter 3, where we propose a simplified, easily manufactu

version of the FBGC, the so-called "P+ Source" FBGC [36], or Ver. 2 (FBGC2), which is

18

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ry

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er

e

lso

due

ime

f the

ssue

compatible with conventional, planar SOI and DG-FinFET CMOS technology with ~8F2

cell area. In essence, the simplified "P+ source" FBGC is a gated diode connected to the ga

of a conventional MOSFET through the P+ region. Numerical simulations and

measurements of a fabricated prototype of the new cell demonstrate the basic memo

concept, and also imply significant performance superiority over the 1T FBCs as well as

original version of the FBGC in Chapter 2.

Since the writing scenarios in FBGC [35] [negative gate (word line) voltage

used to write ’1’, and positive gate voltage is used to write ’0’] are different from the

conventional impact ionization-based write methods, the holding conditions under dis

become complicated. Word-line (WL) disturb should be carefully taken care of in both

state and ’0’-state holding. In Chapters 2 and 3, we reveal two facts: (1) ’0’ state und

disturb is more tenuous than ’1’ state under disturb; (2) GIDL current in the holding

conditions is the major killer of the ’0’ retention time. Even though we get longer ’0’

retention time under disturb with the "P+ Source" FBGC (FBGC2), we find that the absolut

value of retention time is still much shorter than the 64ms as required by ITRS [7]. We a

find that the non-quasi-static hole redistribution is significant in the memory transient

operation. In Chapter 4, we seek to gain physical insights of the transient GIDL current

to the non-quasi-static effect and body-bias dependence of GIDL current, which will

determine the worst-case ’0’-state retention time. Based on our physical insights, we

develop an analytical GIDL current model and use it to predict the ’0’-state retention t

with the "P+ Source" FBGC.

With better understanding of the dependence of transient GIDL current on VB

gained in Chapter 4, we propose to modify the design, and optimize the performance o

"P+ Source" FBGC (FBGC2), including acceptable retention time. We address the key i

19

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igate

olve

is

n

s

logic-

h

)

ta is

y-

g

ng-

for FBCs using GIDL current for charging, i.e., the current ratio corresponding to the

charging operation and the ’0’ holding state with disturb. This ratio must be very large

achieve 100ms retention time with reasonable write time and sense margin. We invest

two new FBGC design modifications to get the desired performance in Chapter 5. To res

the shorter worst-case retention time problem, Ver. 3 (FBGC3) is proposed and

demonstrated with numerical simulations. Then, exploiting the design flexibility which

offered by the 2T FBGC cell, we upgrade FBGC3 to Ver. 4 (FBGC4) for faster speed.

Besides maintaining the excellent retention time characteristics in FBGC3, FBGC4 ca

improve write speed, including write ‘1’ and ‘0’, to less than 1ns. These characteristic

mean FBGC4 could be a good candidate to replace the cache memory cell in CMOS

chip design.

1.3 New Physical Insights on "Capacitorless"DRAM Cell

1.3.1 Basic FBC Operation

As noted, the integration problems associated with the capacitor of the

conventional DRAM cell in nanoscale CMOS technology have stimulated the researc

interest in capacitorless DRAM cells. The binary states of the 1T floating-body cells (FBCs

are defined by charging and discharging the body of an SOI MOSFET. The stored da

sensed via a difference, or signal margin, in the channel current (IDS) corresponding to the

Vt variation that results from the body charging/discharging, i.e., from the varying bod

source junction voltage (VBS, the quasi-Fermi potential separation) [22][37]. The chargin

(e.g., by impact-ionization current IGi) and discharging (e.g., by body-drain (B-D) junction

forward bias VBD) of the (n-channel with grounded source) FBC are defined by the floati

20

g

dy

t,

or

ing

body nodal, or (hole) current-continuity equation, which involves discernible intrinsic,

dynamic capacitors:

(1.5)

where CB represents the composite body capacitance that couples the body to other

terminals of the MOSFET; Qp is the hole charge in the body, and IR (generally defined by

the B-S/D p-n junctions [38]) and IG are hole recombination (removal) and generation

(injection) currents linked to the body. In the PD/SOI cell (with thick BOX) during chargin

by IG = IGi, for example, CB comprises the B-S/D junction capacitances defined by the bo

doping density (NB) [38]. Generally, the VBS-dependent B-S capacitance is predominan

including both depletion and diffusion components [37][38]. However, if IG is GIDL current

[23], with the front surface accumulated, CB is augmented by the body-gate capacitance,

~CoxWgLg. During write-‘1’ charging (dQp/dt > 0), CB in (1.5) governs a transient increase

in VBS (∆VBS) related to Qp:

(1.6)

where∆Qp is the injected, stored hole charge associated with∆VBS as defined by CB; Qp0

is defined by NB for PD cells (it is the mentioned VGbS-induced accumulation charge for FD

cells). For IGi charging, the transient can reach steady state, where IGi = IR(VBS) defines

VBS (which is typically about 0.7V); for GIDL charging, VBS < 0, making IR = 0 (for no

gate current), and the steady state is not typically reached [23]. During write-‘0’ discharg

(dQp/dt < 0), IG = 0 and IR can be defined by VBS > 0 as well as VBD > 0; the transient is

IG IR–dQpdt

---------- CB

dVBSdt

---------------= =

Qp Qp0 ∆Qp+ Qp0 CB VBSd

∆VBS

∫+= =

21

se of

the

ick

le-

is

rm

e

r the

thus relatively fast, yielding VBS ~ 0 (<0 when VDS < 0 is applied for faster discharging) in

the steady state. Note that during the IG = IGi charging transient, the gate, or word-line

voltage (VGfS) is raised to induce a channel, and the drain, or bit-line voltage (VDS) is raised

to drive IDS and IGi. Thus, excessive power is consumed as has been generally noted; u

GIDL for I G, without a channel, dramatically reduces this power [23]. However, during

discharging transient, with VGfS > 0 and VDS < 0 as typically used, the write- 0 power

dissipated by the MOSFET in the inverse mode can be excessive too, and this is not

generally noted.

For FD FBCs, with very low NB, CB in (1) is not so clearly defined; a depleted

body renders very small B-S/D junction capacitance. For the FD/SOI MOSFET with th

BOX, the body substrate capacitance is very small too, and there is no significant ho

storage element. (Note that using GIDL for IG in this case, which would require G-S/D

overlap, could make CB the oxide capacitance as noted above.) For IG = IGi charging then,

(1.5) and (1.6) show that the steady-state VBS is reached very quickly, but with virtually no

∆Qp. However, we note that if the substrate is biased negatively to induce strong hole

accumulation charge (Qp0) near the body-BOX interface, as typically done [21][22][27],

large B-S/D junction capacitance is created within the accumulation layer. Indeed, th

capacitance emulates that of the p+-n+ junction [38] in the PD/SOI cell, and is typically the

predominant component of CB. For the FD DG FinFET, the substrate can be biased to fo

the accumulation layer [25] and create CB in the same way. However, if the two gates ar

made independent (IG) [26], the back gate can be biased instead [Okh05][Ban06]. Fo

IG FinFET though, we wonder whether such bias is really needed for CB; could the thin back

oxide (toxb = toxf ~ 2nm) yield an adequate B-Gb capacitance without any VGbS-induced

accumulation?

22

ia 2-

he

We answer this question later, but irrespective of CB, we note that the VGbS-

induced accumulation is still needed for two other reasons. First, the∆Qp-defined data in

the cell cannot be sensed without it because Vt is not dependent on VBS. Indeed, without

strong accumulation charge, Poissons equation in the FD body shows that the Gf-Gb

coupling defines Vt(VGbS), and there is no significant Vt dependence on VBS [39]. We show

later that this need persists even though an accumulation layer tends to form as IGi (or GIDL)

injects holes (∆Qp) into the body and VBS increases. Second, the VGbS-induced

accumulation charge increases the stored-’0’ Vt to Vta (via dVt/dVGbS = -rd ~ -CbCoxb/

[Coxf(Cb+Coxb)] for depletion [39], where Cb = εSi/tSi, Coxf = εox/ toxf, and Coxb = εox/toxb)

such that the VBS-defined lowering of it [22],

(1.7)

for accumulation, where ra = Cb/Coxf ~ 3toxf/tSi, yields a stored-’1’ Vt that is sufficiently

lower than the stored-’0’ Vt for data (current) sensing. Without the VGbS-induced

accumulation, the ’0’-state Vt = Vt(VGbS) is low, and, even though the stored ’1’-state∆Qp

creates an accumulation layer, the ’0’ versus ’1’ Vt margin is prohibitively small, as we now

show.

1.3.2 Simulations and Discussion

We demonstrate our new insights regarding the general operation of FBCs v

D numerical device simulations done with Taurus [40]. We present here results of

simulating the FBC operation of an FD IG FinFET, illustrated in the inset of Fig. 1-1. T

FinFET has a 28nm gate length, with toxf = toxb = 2nm, undoped fin-body with thickness tSi

= 14nm, and midgap gates; the default fin height, or gate width, is 1µm. In Fig. 1.1 we show

∆Vta ra– ∆VBS=

23

l

y

al,

he

.

,

less

the

d

e

in

ly

predicted IDS(t), defined by Vt(t), reflecting the transient sequential operation of the cel

(i.e., write ’1’ (charge body by IGi), hold data, read ’1’, hold data, write ’0’ (discharge bod

with VDS < 0), hold data, and read ’0’ as depicted in the figure) for two cases: VGbS= -1.0V,

which induces a back-surface accumulation layer, and VGbS = 0V, which leaves the

unbiased body fully depleted. For the first case, the predicted FBC operation is norm

albeit with a small signal margin (∆IDS as defined by∆Vta in (3)) that typifies FBCs since

ra < 1. The stored data, sensed via IDS, reflects the charging/ discharging of CB, i.e.,∆Qp(t)

as indicated by the predicted hole densities in Fig. 1-2. Note here that CB includes the

accumulation-defined B-S junction capacitance, as in the FD/SOI FBC, plus the B-Gb

capacitance (~CoxbWgLg), which is comparable to the junction capacitance. Note also t

excessive power was implied by IDS during the write- ’0’ as well as the write- ’1’ operations

However, for the VGbS= 0V case in Fig. 1.1, note that IDS(t) does not reflect any stored data

in accord with our discussion above, and the transients are very fast, implying much

∆Qp stored on the B-Gb capacitance. The predicted hole densities in Fig. 1.2 confirm

small, but finite∆Qp. Since the write- ’1’ IDS for this case implies a relatively high IGi, we

infer, from (1), an effectively low CB even though toxb is thin. These results can be explaine

with reference to the back-surface energy-band diagrams sketched, in accord with th

simulation results, in Fig. 1-3, for this case and for the VGbS= -1.0V case. In the latter case,

the valence bandEv is pinned to the hole quasi-Fermi levelEFp via the high hole density,

and hence the back-surface potential varies as∆φsb= ∆VBS, yielding (3) [22][39]. However,

for the VGbS= 0 case,∆φsb~ 0. This is because the inversion electron density that exists

the body (bulk inversion is prevalent in undoped MOSFETs [41]) during write ’1’ near

pins the conduction bandEc to the electron quasi-Fermi levelEFn as VBS [=(EFn-EFp)/q]

increases. Only when the injected hole density (which defines∆Qp) becomes the

24

in

es

first

IG-

. For

w

gin

ed

or

also

g

predominant carrier near the back surface of the body doesEv begin to followEFp, thus

increasingφsb and lowering Vt accordingly [22][39]. However, at this point VBS is already

near its final, ’1’-state value, and so∆Qp ~ Coxb∆φsb is small and∆Vt ~ 0.

1.3.3 Summary

Using numerical simulations and analytical modeling, we physically and

generically explained the operation of FBC DRAM, comprising a PD/SOI or FD/SOI

MOSFET, or an FD DG or IG FinFET. The notion of a potential well for charge storage

the body was dismissed, and, for the first time, the predominant intrinsic, dynamic

capacitors (bias-dependent CB) that store the body charge, or data, for the various devic

and bias conditions were defined. For FD cells, multiple roles of the VGbS-induced

accumulation layer needed for storing and sensing data was physically defined for the

time; it renders a significant∆Vt dependent on∆VBS, and, in the FD/SOI cell with thick

BOX, it creates a significant B-S junction capacitance for the charge storage. For the

FinFET cell, the created junction capacitance is augmented by the B-Gb capacitance

GIDL charging [23], rather than by IGi, CB is augmented by the B-Gf capacitance. The ne

insights noted herein imply better designs for optimally trading-off the FBC signal mar

(∆IDS defined by∆Vta in (1.7)), data retention time, write speeds, and power. All the not

metrics depend on CB, which has been clearly defined with reference to (1.5) and (1.6) f

the various FBC devices and biases. Indeed, a dynamic CB could be optimally tailored by

device design. For example, use of GIDL for body charging, which reduces power [23],

makes CB in (1.5) for write ’1’ different from that for read ’1’, as we have indicated. Durin

the write-’1’ operation, VBS < 0 [23], making IR = 0 in (1.5) and thus increasing∆Qp for a

given write time, irrespective of CB(write). The larger∆Qp implies longer retention time

25

and

directly, and could also yield improved margin via∆VBS = ∆Qp/CB(read) in the read-’1’

operation; CB(read)is the B-S junction capacitance, dependent on VBS > 0. Also, note from

(1.7) that, for a given∆VBS, ∆Vta can be increased by decreasing tSi or increasing toxf, but

only the former change increases the signal margin, as experimentally shown in [27]

[28], since∆IDS ~ Coxf∆Vta ~ 1/tSi.

26

Predicted operation (with IGi body charging) of the IG-FinFET FBCwith VGb = -1.0V and VGb = 0V. The transient pulsings of the wordline and bit line of the cell are shown in the top plot, and the transientcell currents, which reflect the stored data, are also shown in the plot,the inset of which illustrates the basic structure of the DG-MOSFETFBC.

0.0 10 20 30 40 50 60 70 80 90 100 110-1.6

-1.2

-0.8

-0.4

0.0

0.4

0.8

1.2

1.6

Vol

tage

(V

)

Word LineBit LineVGb=-1.0VVGb=0.0V

0.0 10 20 30 40 50 60 70 80 90 100 110-250

-200

-150

-100

-50

0

50

100

150VGb=-1.0VVGb=0.0V

Time (ns)

I DS

(µA

/µm

)

Write ’1’ Read ’1’ Write ’0’ Read ’0’Hold Hold

n+ n+p- (body) DS

Gf (word line)

Gb (back gate)

toxf

toxb

tSi(bit line)

Hold

Figure 1-1.

27

Predicted hole density along the back surface between source anddrain of the IGFinFET FBC at the ends of the read-’1’ and read-’0’transient operations, for VGb = -1.0V and VGb = 0V. For the formercase, the hole density reflects (Qp0 + ∆Qp), while it reflects only∆Qpfor the latter case. Note that∆Qp is much larger for VGb = -1.0V thanit is for VGb = 0V.

-20 -15 -10 -5 0 5 10 15 20

Position (nm)

103

105

107

109

1011

1013

1015

1017

1019

1021

Hol

e D

ensi

ty (

cm-3

)

Read ’1’, VGb=-1.0VRead ’0’, VGb=-1.0VRead ’1’, VGb=0.0VRead ’0’, VGb=0.0V

Source Channel Drain

Figure 1-2.

28

Sketch of the perturbation of the energy-band diagram across the body-source junction at the back surface of the IG-FinFET FBC caused byVBS > 0 associated with write-’1’ (via IGi) ∆Qp, for VGb = -1.0V andVGb= 0V. For the latter case, the surface potential is hardly changed byVBS sinceEFp is not pinned toEv as it is for the VGbS= -1.0V.

Ec

Ev

qVBS

EFn

EFp q∆φsb

VGbS = -1.0V

Ec

Ev

qVBS

EFn

EFp

q∆φsb

VGbS = 0V

S B

S B

Figure 1-3.

29

ory

(1T)

ave

In

t)

argin,

n

D)

nar

id

D

ulates

hapter

am

ata,

CHAPTER 2

TWO-TRANSISTOR FLOATING-BODY/GATE CELL: A NOVEL LOW-POWERNANOSCALE EMBEDDED DRAM CELL

2.1 Introduction

The conventional DRAM cell requires a stack capacitor or a deep-trench

capacitor for storage, which is leading to prohibitive processing complexity as the mem

technology is scaled [1]. So, study and development of "capacitorless" one-transistor

DRAM cells that utilize the floating body of an SOI MOSFET as the storage element h

intensified [17][21][22][28][42], mainly for CMOS embedded-memory applications [43].

such 1T floating-body cells (FBCs), charging (by impact-ionization or GIDL [23] curren

and discharging (by forward-biased drain/source-junction current) the MOSFET body

define the memory states, and the stored data are sensed via a difference, or signal m

in the channel current (∆IDS) corresponding to the threshold-voltage variation (∆Vt) that

results from the body charging/discharging, i.e., from the varying body-source junctio

voltage (VBS) [44]. The widespread FBC studies, which began with partially depleted (P

SOI MOSFETs [17], have recently focused on fully depleted (FD) devices, including pla

FD/SOI MOSFETs [21][27][45] and FD double-gate (DG) FinFETs [26][28][46], to avo

body-doping issues [26] and to render the FBC more scalable with the CMOS. The F

devices require a substrate, or back-gate bias to create an accumulation layer that em

the PD body, and enables effective charge storage and data sensing as explained in C

1 [44].

While FinFET CMOS technology could enable scaling of the 1T FBC to gate

lengths (Lg) less than 10nm [29], there are other issues that will tend to inhibit mainstre

adaptation of the 1T-DRAM concept: (i) it relies on current-based sensing of the stored d

30

,

e the

e.

tion,

vice/

C

her

g of

r, a

g,

atic

ter

ing

bility

which is less desirable than conventional voltage-based sensing because of varying∆IDS,

and hence more complex sensing circuitry [33], and added power consumption; (ii) it

requires the noted bias-induced accumulation, which complicates the cell/chip design

undermines reliability, and sacrifices layout area; and (iii) because the attainable∆Vt is

fundamentally limited, wide devices, or several paralleled fins, are needed to increas

current to get acceptable∆IDS, thus undermining the memory density actually achievabl

For example, in [46], with the SOI substrate biased at -30V to get the needed accumula

10 fins yielded a current margin of less that 10µA from an Lg = 100nm composite n-channel

DG FinFET.

In this chapter we propose and demonstrate, via process/physics-based de

circuit simulations supported by numerical simulations, a novel two-transistor (2T) FB

[34] for embedded-DRAM applications that can yield much better performance with hig

density than the 1T cells. The 2T concept is conceived from an insightful understandin

the basic FBC operation [44], which in fact belies its "capacitorless" description. Furthe

modification in the 2T-FBC structure enabled by use of GIDL current for body chargin

which in essence creates a floating-body/gate cell (FBGC) [34], is shown to yield dram

reduction in discharging as well as charging [23] power dissipation, in addition to bet

signal margin, higher memory density, and longer data retention. Design and process

issues that need to be addressed for optimal performance and for sustained FBGC via

in nanoscale CMOS are discussed.

31

BC

s are

ly

he

r

r the

ses

of

eric,

2T-

DG

er,

2.2 Two-Transistor Floating-Body Cell Concept

2.2.1 Transient Simulation

Our 2T-FBC [34] idea stems from insights into the actual operation of the 1T F

[44]. First, we note that the variation in Vt that underlies the 1T-FBC operation is typically

much less than the variation in VBS driven by the body charging/discharging:∆Vt = -r∆VBS

with the body factor r ~ 0.3 [32]. This means that wide devices, and large layout area

needed for adequate∆IDS, as mentioned previously. Second, we note that the common

used "potential well" description [21][22][24] of the body charge storage is misleading. T

FBC is not really "capacitorless"; it can actually have more than one intrinsic capacitor (CBi)

supporting the charge (Qp in an nMOSFET) storage [32]:

(2.1)

is the floating-body nodal equation, where CBi, with i = S, D, Gf, Gb, represents the

capacitive coupling of the body to other terminals of the transistor; Qp is the majority-hole

charge in the body, and IG and IR are hole generation (or injection) and recombination (o

extraction) currents. Third, as noted above, voltage-based sensing is not an option fo

1T FBC.

A memory array based on the 2T FBC is illustrated in Fig. 2-1. The cell compri

transistors T1 and T2, with the body (B1) of T1 connected to, or driving the gate (G2)

T2; Cbi in (1) is thus augmented by the gate capacitance of T2. The 2T concept is gen

applicable to any SOI technology. However, FinFETs offer the best scalability, and the

cell structure could be fabricated, without area penalty due to the B1-G2 contact, via the

FinFET-based ITFET technology [44][47] as illustrated in Fig. 2-2. The planar SOI lay

IG IR–dQpdt

---------- CBi

dVBidt

-------------i∑= =

32

The

pe

in,

have

o

a of

that

we

as

we

the

even

.

the

L2)

s we

ate

rent

doped p+, would be used to make the B1-G2 connection of two n-channel DG FinFETs.

FinFET bodies should be left undoped for scalability [44]. Lateral diffusion of the p-ty

dopants in the SOI layer during activation would effectively dope the base of the T1 f

thereby suppressing source-drain leakage current in it. The undoped FinFETs should

near-midgap metal gates, and p+ rather than n+ polysilicon must be used in the gate stack t

enable the B1-G2 connection. As noted in the figure caption, we estimate a unit-cell are

13.75F2, which implies that the potential area per signal margin is much smaller than

of a 1T counterpart cell because of the larger margin afforded by the 2T FBC, which

exemplify later, and the need for a wide device, or multiple fins [28][46], in the 1T FBC

noted previously. Alternatively, a stacked 2T structure, with T2 made in polysilicon (as

justify later) is possible.

The write/erase operations of the 2T FBC are done by charging/discharging

floating body of T1, as in the 1T FBC. But, the stored data are read via T2 with∆VGS2 =

∆VBS1 > |∆Vt|, which implies directly a (1/r)x increase in∆I, or about a 2x (1/2r) memory-

density increase for the same current-signal margin. No substrate biasing is needed,

when the transistors are designed to be FD, like DG FinFETs which we focus on here

However, two bit lines (per string) are needed: one (BL1) connecting all drain nodes of

T1 transistors in a column of the DRAM array for programing the cells, and the other (B

connecting all drain nodes of the T2 transistors in the column for sensing the data. A

discuss later, two bit lines will tend to improve data-retention time, as well as amelior

read-error issues. The gate of T1 is tied to a word line (WL).

The stored data are read by, in essence, driving T2 directly with VBS of T1

(ℜ≡VB1/G2with S2 grounded). Data could therefore be sensed via the induced drain-cur

variation (gm∆VB1/G2) in T2, as in the 1T FBC cells but with much better signal margin

33

AM

2 will

ing

an be

d 1T

r

, and

ation,

f

d by

h

(We

tion.)

B1.

rge

ad

read/

e

, as

because∆VB1G2 > |∆Vt| as noted. However, preferred voltage-based sensing at the

(precharged) drain node of T2 (BL2), similar to the sensing used in the conventional DR

technology, can be used. In this case, the 2T-FBC cell has to be designed such that T

be turned on and off by the charged/discharged T1 body in the ’0’ and ’1’ states,

respectively. (Note that since T2 inverts, stored ’0’ and ’1’ correspond to the T1 body be

charged and discharged, respectively.) For voltage-based sensing, the two FinFETs c

designed with only one fin each, implying much less layout area than a FinFET-base

FBC [28][46] with multiple fins.

We now simulate the basic operation of the FinFET-based 2T FBC using ou

process/physics-based compact model UFDG [48] in Spice3. UFDG is charge-based

hence properly accounts for all important transcapacitances, ensuring charge conserv

and is well-suited for dynamic FBC simulation. The IR and IG modeling in UFDG, including

impact-ionization current (IGi) and GIDL current, is also physical. Note for the T1 body o

the 2T FBC that a predominant charging current on the right-hand side of (1) is define

the gate capacitance of T2: CG2(dVB1/G2/dt) where, in general, CG2 is VB1/G2-dependent.

We assume single-fin Lg = 28nm DG nFinFETs for T1 and T2, with undoped fin-body widt

and height of 14nm and 56nm, respectively, midgap metal gate, and 1nm gate oxide.

neglect gate tunneling current and parasitic capacitance for this preliminary demonstra

We further assume an ideal B1-G2 connection, and the body of T2 is left floating like

The UFDG/Spice3-predicted operation [i.e., write ’0’ (charge T1 body), hold data/precha

BL2, read ’0’, hold data, write ’1’ (discharge T1 body), hold data/precharge BL2, and re

’1’], for I Gi charging of B1, is shown in Fig. 2-3; as indicated, we assumed reasonable

write times of 10ns including pulse rise/fall times of 1ns. The UFDG model predicts th

expected trend of the B1/G2-voltage variation with gate (WL) and drain (BL1) biasing

34

d to

ted

.0V

BL2

nd

del

T

2

T2.

T-

wo

the

e

e the

shown. A typical program window (or VB1/G2 signal margin) of≅0.8V is predicted, as

indicated by the difference of VB1/G2 between the read-’0’ and read-’1’ operations.

Note that appropriate WL pulsing (to 0.1V here) for read operations is neede

move VB1/G2 sufficiently above or below Vt of T2 for stored ’0’ or ’1’, respectively, with

adequate∆Qp storage needed for the former. This operation is confirmed by the predic

transient drain (BL2) voltage of T2, which needs to be precharged before reading (to 1

here). Indeed, with the T1 body charged (stored ’0’), BL2 drops quickly to 0V, as VB1/G2

turns on T2; this corresponds to a read ’0’. With the T1 body discharged (stored ’1’),

remains at its precharged value (1.0V) as VB1/G2 remains well below Vt; this corresponds

to a read ’1’. Efficient reads of both ’0’and ’1’ are demonstrated with reasonable WL a

BL1 voltage pulsings.

Of course there is some uncertainty in the assumed (defaulted) physical mo

parameters in UFDG, e.g., those defining IG (including IGi) and IR. However, this

uncertainty should not undermine our demonstration of the basic functionality of the 2

FBC in Fig. 2-3. We do, however, have some concern about the assumed ideal B1-G

connection and the notion that the floating body of T1 can effectively drive the gate of

Thus, for more definitive corroboration, we do a numerical mixed-mode simulation a 2

FBC structure using Taurus [40]. To allow a 2-D simulation, we define a domain with t

28nm single-gate undoped FD/SOI nMOSFETs, linked by a p+ polysilicon-TiN (with

midgap work function) connect as shown in the inset of Fig. 2-4. Further, to facilitate

mixed-mode simulation, we simply set VDS of T2 to 0.1V and monitor its current (IDS2) to

check the functionality of the cell. Although the assumed 2T structure is simplified, th

simulation results, shown in Fig. 4 for IGi charging of T1, do corroborate the general

operation of the 2T FBC as predicted by UFDG/Spice3. Indeed, the results demonstrat

35

the

he

inite

tive

cur

and/

be

and

can

the

e

’

in

2].

n

basic operation of the cell with nanosecond-scale write/read processes, showing that

floating B1 of T1 can effectively drive G2 of T2 and yield outstanding signal margin. T

margin of the cell, reflected by the predicted IDS2(t), is substantively larger than that of the

1T counterpart [32], even though it is undermined some because of the unexpected f

read-’1’ current. This current is due to the significant Qp stored on the forward-biased B-D

junction of T1 during the write-’1’ (discharge) process, which is supported by substan

IGi with T1 in the inverse mode. This undermining of the current-signal margin will oc

in any FBC unless the WL voltage is kept well below the MOSFET threshold voltage

or the BL voltage is kept near zero during the discharging process.

Data retention of the 2T FBC, subject to BL1 and WL disturbs, is expected to

at least comparable to that of the 1T cell, as exemplified for FinFET-based FBCs in [46]

[30]. But, the enabled use of voltage-based sensing instead of current-based sensing

yield better retention in the 2T-FBC array, as we show and explain later.

2.3 Performance Evaluation of the Floating-Body/Gate Cell

2.3.1 Operation Simulations

Clearly, the 2T FBC affords much more design flexibility for optimizing

performance than does the 1T FBC. A good example is the FBGC [35] (Ver. 1), which

stemmed from our checking the use of GIDL current for body charging [23] to eliminate

substantive write-’0’ (B1-charging) power loss due to T1 channel current, which can b

inferred in Figs. 2.3 and 2.4. Note, in fact, that such power loss occurs in the write-’1

(discharging) operation as well. Fordischarging, a forward bias is established on the body-dra

junction by VDS < 0 and VGS > Vt, and thus high channel current flows in the inverse mode [3

The body-charging power can be virtually eliminated by using GIDL current [23], rather tha

36

ent,

GIDL-

in T1

for

is is

e

ed

8nm

nt

ient,

s

C

ing

he

[23]

impact-ionization current, for charging, but the body-discharging power remains high. A key

feature of the FBGC isthe drain (BL1) of T1 tied to the source, as illustrated in Fig. 2-5. This 2T

configuration, with T1 effecting a floating body/gate on T2, totally eliminates T1 channel curr

and thus the excessive power dissipation when the body of T1 is discharged. Further, with

current charging, it eliminates theundermined signal margin due to IGi noted with reference

to Fig. 2-4 as well. The FBGC has other advantages. All drain-source leakage currents

are eliminated, meaning reduced standby power. Also, T1 can be designed primarily

GIDL current, i.e., with significant gate-source/drain overlap and Leff < Lg, without much

consideration of short-channel effects since it is not crucial in the read operations. Th

not true for 1T FBCs using GIDL-current charging, for which the shorter Leff will tend to

limit L g scalability. And, with T1 now being just a two-terminal (WL and BL1) device, th

fabrication process could be simplified, e.g., by using a stacked structure as mention

previously.

We verify and demonstrate the operation of the 2T FBGC, first by numerical

simulations using Taurus. The 2-D structural domain used is similar to that in Fig. 2-4, with 2

FD/SOI transistors. Thepredicted results for a sequential memory operation, with T2 curre

used for sensing data, are shown in Fig. 2-6, including the floating-B1/G2 voltage trans

which is VGS(t) applied to T2 (but not now VBS of T1 since S1 is not grounded). The result

confirm the basic operation of the FBGC cell based on GIDL-current charging of T1,

showing an outstanding signal margin that isabout 2.5x higher than that achieved in a 1T FB

counterpart in [23] with the same drain bias (0.2V).Note the negligible write-power dissipation

reflected by the transient current in T1, void of any channel current. The B1-discharg

current is about four orders-of-magnitude lower than what is typical in 1T FBCs [17]. T

charging/discharging-current comparison of the FBGC versus the 1T FBCs in [17] and

37

V

ge

d non-

e of

turb

G is

rrent

o

-S/D

used

ble

Fig.

gh,

ore

BL2

cts

GC

uate

made in Table 2-1 clearly reflects the superiority of the FBGC with regard to power

consumption.The 2T FBGC also enables data sensing via the BL2 voltage, for whichB1/

G2(t) must swing through Vt of T2 and the stored charge in B1 must be high enough to ima

an adequate inversion charge in T2. The latter requirement is dependent on the note

quasi-static effect (It will be revisted in chapter 4.), which enables the oxide capacitanc

T1, as well as the gate capacitance of T2, to augment CBi of (1) in the body of T1 [32]. To

demonstrate this operation with realistic FinFETs, and to check the data retention/dis

characteristics with reasonable computational efficiency, we use UFDG/Spice3. (UFD

a quasi-static model, but the noted NQS effect has been accounted for in the GIDL-cu

modeling.) We assume undoped 28nm single-fin DG nFinFETs with a midgap gate. T

avoid significant gate tunneling current as well as reduce parasitic gate-source/drain

capacitance, a pragmatic gate oxide thickness (tox) of 2nm is assumed. The fin width is set

to 14nm for SCE control [29], and the height is set to a reasonable 56nm. A 1.5nm G

overlap in T1 is assumed for reasonable GIDL current, and a 3nm underlap [49] in T2 is

to further reduce the parasitic (fringe) capacitance [50]. Such 2T-FBGC design is doa

using the previously noted ITFET structure [47]. The predicted operation is shown in

2-7. Note that the write-’0’ WL and BL1 voltage pulses (needed for GIDL current) are hi

but the oxide electric field, dependent on tox, gate-silicon work-function differences, surface

potentials, and VB1/G2, is not too excessive anywhere. The memory operation here is m

efficient than that in Fig. 2-6 mainly because of the upgraded T2 design. Note that, with

precharged to 0.5V, the fast BL2 voltage transient, going to 0V or 0.5V, faithfully refle

the stored data directly in this case. This solid voltage-signal margin implies higher FB

memory density, since wide (e.g., multi-fin) devices must be used in the 1T cell for adeq

current margin [46].

38

he

ap,

[49]

L2

ded

xide

ulse

reby

ntly

well.

this

el-

nt

eeded

to

cause

of T1

To demonstrate the benefit of the noted T2-design upgrade, we simulated t

FBGC operation again, but with T2 identical to T1. In this case, T2, with the G-S/D overl

has much higher parasitic capacitance, including increased G-S/D fringe capacitance

as well as the added overlap capacitance. The UFDG/Spice3-predicted B1/G2 and B

voltage transients are contrasted in Fig. 2-8 with those of Fig. 2-7. Although now the ad

parasitic capacitance of T2 must be charged during the write-’0’ process, the larger o

capacitance of T1, where the predominant∆Qp is stored, still controls the VB1/G2 charging

transient. However, the subsequent read-’0’ efficacy is clearly undermined. The WL p

does not bring VB1/G2 up as much because of the added parasitic capacitance of T2, the

yielding slower read time. The write/read-’1’ (discharging) processes are not significa

affected by the added capacitance. However, the ’0’-’1’ signal margin in VB1/G2 is reduced

substantially by the noted read-’0’ effect, which portends shortened retention time as

A BL2 capacitance of 20fF, which is a reasonable estimate for a 512-cell BL

string in the 28nm-FinFET technology, was assumed for the simulations of Fig. 2-8. In

regard, we have checked the simulation results for possible read errors due to chann

leakage currents in unselected cells in the BL string. Looking at the predicted transie

currents in the selected and unselected cells, we estimate that ~1000 cells would be n

to cause an error, although that number is reduced when T2 is not optimally designed

minimize the parasitic capacitance, and the VB1/G2margin is reduced as in Fig. 2-8. These

checks also imply reasonable standby power associated with unselected cells, partly be

the read and write operations are done via separate bit lines and the source and drain

are tied (to BL1).

39

and

oped

s we

f T1

on

9.

e

rbs

)

rite

the

rrent

Note

g

,

e

2.3.2 Data Retention/Disturb Characteristics Simulations

The data retention/disturb characteristics of the 2T FBGC, governed by GIDL

IR currents in T1, are better than those of the counterpart 1T FBC [23] due to the und

body, and can be improved by design optimization enabled by the 2T structure. Also, a

mentioned previously, when GIDL current is used for charging, the gate capacitance o

augments CBi in (1), tending to increase the stored-’0’ charge and lengthen the retenti

time. For the FBGC of Fig. 2-7, UFDG/Spice3 predictions of read-VB1/G2(t) resulting from

worst-case, long-time WL and BL1 disturbs to hold ’1’ and hold ’0’ are shown in Fig. 2-

For comparison, the read-VB1/G2(t) for long-time holds without disturbs is included; thes

results imply ~1s retention times. The undermining hold-’1’ (with B1 discharged) distu

result in GIDL-current charging of B1, and the undermining hold-’0’ (with B1 charged

disturbs result in drain/source-junction IR discharging of B1. The retention times are

implied by VB1/G2(t) relative to Vt of T2, which is indicated in the figure. We note that this

Vt could be tailored to optimize the tradeoff between data-retention times and read/w

performance. The worst cases (holding ’0’ with BL1 disturb and holding ’1’ with WL

disturb) show ~1ms retention times, much longer than the 100ms in [23]. To exemplify

retention time directly, we show in Fig. 2-10, the sensed BL2 voltage versus time

corresponding to the worst-case BL1 hold-’0’ disturb, contrasted with the sensed T2 cu

versus time corresponding to the same disturb. These UFDG/Spice3 predictions give

interesting insights regarding data retention for voltage- versus current-based sensing.

the dramatic increase in the retention time afforded by (one-fin) voltage-based sensin

versus current-based sensing. The latter time is about an order-of magnitude shorter

reflecting why multi-fin devices are needed for current-based sensing. In this case, th

relative loss of the current margin directly tracks the change in VB1/G2 relative to Vt of T2

40

in

, and

nd

ting

reby

,

f T1

lly

wer

d

the

ed

e

caling

te

in Fig. 2-9. However, for voltage-based sensing, the loss of the relative voltage marg

depends on the current-voltage characteristics of T2, as well as the BL2 capacitance

good T2 design with typical capacitance yields a much longer retention time.

2.4 Summary

A novel 2T floating-body cell on SOI for embedded-DRAM was presented, a

its operation was demonstrated and verified via process/physics-based device/circuit

simulations, supported by numerical simulations. The main novelty is the use of the floa

body of one transistor (T1) to directly drive the gate of the second transistor (T2), the

giving dramatic improvement in signal margin while allowing voltage-based sensing.

Physical insight then led to a modification (FBGC [35]) of the basic 2T-FBC structure

enabled by using GIDL current for T1-body charging, in which the source and drain o

are shorted, and both tied to the programming bit line (BL1). The FBGC, which is virtua

a floating-body/gate cell, totally eliminates the write (T1 charging and discharging)-po

dissipation, while yielding better signal margin, longer data retention via voltage-base

sensing, and higher memory density.

The simulation-based demonstration of the FBGC used undoped nanoscale DG

FinFETs, or ITFETs [49], which are potentially scalable to Lg < 10nm [49]. We therefore believe

that FBGC DRAM is similarly scalable, and much more so than a 1T counterpart for which

gate-source/drain overlap (Leff < Lg) needed for GIDL current will limit its scalability.

Because ofthe design flexibility afforded by the 2T FBGC, the GIDL current can be controll

via optimal design of the G-S/D overlap in T1, which is merely a two-terminal charge-storag

structure, with T2 being designed optimally with underlap as discussed herein. We note that s

Lg will tend to reduce the effective storage capacitance of the 2T cell, i.e., the oxide and ga

41

eight

ity).

he

for

capacitances of T1 and T2 which augment the right-hand side of (1) for T1 (although the fin h

could be kept high to offset this reduction without undermining the increased memory dens

Thus, less∆Qp will be stored, although the signal margin will not be undermined. However, t

scaling of the fin thickness with Lg will reduce the S/D-junction IR and IG, implying that the data

retention time will not be significantly affected. Hence, we believe that FBGC DRAM can be

scaled along with the FinFET-CMOS technology. This optimistic projection cannot be made

1T-FBC DRAM, even if a DG FinFET is used.

42

Figure 2-1. The 2T FBC (T1 and T2 enclosed in the dashed square) in a DRAMarray, where B1/G2 represents the floating-body storage node of T1that is tied to the gate of T2. The 2T-FBC concept is applicable toany SOI technology.

B1/G2

T1

T2

Word Line

Bit Line 1 Bit Line 2(Ground)

2T FBC

43

T1 T2

Substrate

BOX

GND BL2 (D2)

BL1 (D1)

WL

p+p+ Poly

P

GND

Metal 1

Metal 2

Metal 3

Silicon

Oxide

Nitride

Silicide

TiN

Figure 2-2. Schematic cross-sectional view of a 2T (n-channel) FBC fabricated

via ITFET technology [47]. The planar SOI layer, doped p+,provides the contact from the (undoped) body of DG FinFET T1 to

the (p+ poly/metal) gate of DG FinFET T2, without area penalty.The WL, BL1, BL2, and GND metal vias are indicated, as is thepitch (P = 2F) of the technology node. Lateral diffusion of dopantsfrom the SOI layer to the base of the T1 fin stops any source-drainleakage current there. For Lg ≅ F/2 (for which tfin ≅ Lg/2 and hfin ≅4tSi [29]), we estimate a unit (two-fin) cell area of <14F2, whichimplies a potential area per margin much less than that of a 1Tcounterpart FBC [18].

44

Figure 2-3. UFDG/Spice3-predictedtransient sequential operation of a 28nmDG nFinFET-based 2T FBC comprising single-fin transistors withheight 56nm; impact-ionization current was used for charging B1,and gate current and parasitic capacitance were neglected. For theread operations, BL2 was precharged to 1.0V; the effective bit-linecapacitance was assumed to be 20fF,which corresponds roughly to a512-bit line in the technology alluded to. Note that VB1/G2is VBS of T1and VGS of T2.

0.0 4 8 12 16 20 24 28 32 36 40 44 48Time (ns)

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

g(

)

Write’0’

WL

BL1

BL2B1/G2

HoldHoldHold

Write ’1’Read ’0’ Read ’1’(Charge B1) (Discharge B1)

45

Figure 2-4. Transient sequential operation of a 2T FBC, analogous to the simulationof Fig. 2-3, predicted by a 2-D, mixed-mode simulation using Taurus.The assumed representative cell structure, with 28nm single-gate FD/SOI nMOSFETs, is shown in the inset of (b), in which the data storageis reflected by the transient current in T2 driven by VBS of T1. Thetransient pulsings of the gate (WL) and drain (BL1) of T1, and the T2drain (BL2) voltage fixed at 0.1V for this simplified simulation areshown in (a). The read-’1’ and read-’0’ operations show the predictedsignal margin,∆IDS2≅ 40µA/µm.

(a)

(b)

0.0 10 20 30 40 50 60 70 80 90 100 110-1.6

-1.2

-0.8

-0.4

0.0

0.4

0.8

1.2

1.6

2.0

Vol

tage

(V

)

Write ’0’

Hold

Read ’0’ Write ’1’

Hold

Read ’1’

Hold

BL1

BL2

WL

0.0 10 20 30 40 50 60 70 80 90 100 110Time (ns)

-10

0

10

20

30

40

50

60

70

80

p+

p -

p - n+n+

n+n+

Word Line

Bit Line 1

Bit Line 2

TiN

TiN

T1

T2

I DS

2 (µ

A/µ

m)

Write ’0’Hold

Read ’0’ Write ’1’Hold

Read ’1’Hold

(0.1V)

46

Figure 2-5. The FBGC structure in a DRAM array. The gate of T2 is driven by thebody of T1. The source and drain of T1 are tied together, therebyeliminating T1-channel and source-drain leakage current, and effectinga floating body/gate on T2.

BL2BL1

WL

GND

T2

T1

B1/G2

47

Figure 2-6. Transient sequential memory operation of an FBGC as depicted in Fig.2-5 predicted by a 2-D mixed-mode numerical simulation using Tauruswith a structural domain similar to that in Fig. 2-4, with 28nm FD/SOItransistors. The applied WL and BL1 voltage pulses, for GIDL-currentcharging, are shown in (a), along with the predicted floating-B1/G2voltage (relative to ground) transient (which is VGSof T2) and the BL2voltage (VDS2) set to 0.2V. The T2 current in (b) reflects the basicmemory operation, showing a current margin of about 50µA/µm. TheT1 current in (b) reflects the negligible power dissipation during the B1discharging (write ’1’) as well as charging (write ’0’).

(a)

(b)

0.0 10 20 30 40 50 60 70 80 90 100 110-2.1

-1.8

-1.5

-1.2

-0.9

-0.6

-0.3

0.0

0.3

0.6

0.9

Vol

tage

(V

)

BL1BL2

B1/G2

WL

Write ’0’ Hold Read ’0’ Hold Write ’1’ Hold Read ’1’

0.0 10 20 30 40 50 60 70 80 90 100 110Time (ns)

-10-5

0.0

510

1520

25

3035

40

45

5055

Cur

rent

(µA

/µm

)

T1 Current

T2 Current


Sig

nal M

argi

n≅ 5

0µA

/µm

negligible write current

48

Figure 2-7. UFDG/Spice3-predictedtransient sequential memory operation of a2T FBGC designed with undoped 28nm DG single-fin nFinFETs withheight and width of 56nm and 14nm, respectively, and 2nm gate oxide;T2 is designed with 3nm G-S/D underlap, whereas T1 has 1.5nmoverlap to enable GIDL-current charging. The applied WL and BL1voltage pulses are shown, along with the predicted floating B1/G2(relative to ground) and BL2 voltage transients; the BL2 capacitancewas assumed to be 20fF. The voltage-based sensing, via BL2 with a0.5V precharge, shows a solid signal margin with fast (<10ns) write/readtimes.

0.0 5 10 15 20 25 30 35 40 45 50Time (ns)

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

Vol

tage

(V

)

Write ’0’Hold

Read ’0’Hold

Write ’1’ Read ’1’

BL1

WL

B1/G2

BL2

Hold

49

Figure 2-8. UFDG/Spice3-predicted transient sequential memory operation of the2T FBGC of Fig. 2-7, but with T2 identical to T1, with G-S/D overlap.The predicted B1/G2 and BL2 voltage transients are compared withthose of Fig. 2-7. Note the undermined read-’0’ operation due to theadded parasitic capacitance of T2.

Write ’0’Hold

Read ’0’Hold

Write ’1’ Read ’1’

B1/G2

BL2

Hold

Heavy Curves: T2 w/ OverlapLight Curves: T2 w/ Underlap

0.0 5 10 15 20 25 30 35 40 45 50Time (ns)

-1.2

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

Vol

tage

(V

)

50

Figure 2-9. Worst-case data retention/disturb characteristics of the 2T FBGC in Fig.2-7. reflected by UFDG/Spice3 predictions of the read-B1/G2 voltageafter lengthy data (’0’ and ’1’) holds subject to continuous WL and BL1disturbs as indicated. The WL and BL1 disturbs are those thatundermine the data storage, as given in the in Fig. 2-7. The data holdswithout the disturbs are included for comparison. The T2 thresholdvoltage is superimposed to indicate retention times.

10-7 10-6 10-5 10-4 10-3 10-2

Time (s)

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

VB

1/G

2 (V

)

Holding w/o Disturb / Read

Holding w/ BL1 Disturb / ReadHolding w/ WL Disturb / Read

Stored ’0’

Stored ’1’

Vt of T2

51

Figure 2-10. UFDG/Spice3-predicted BL2 read-voltage (after 8ns read time as in Fig.2-7) and T2 read-current (with VDS2= 0.2V applied) of the 2T FBGC inFig. 2-7 after the lengthy worst-case ’0’ (B1 charged) holds subject tothe continuous BL1 disturb (-0.9V) in Fig. 2-8. Note the much longerworst-case retention time (~1ms) yielded by the voltage-based sensing,which is governed by the current-voltage characteristics of T2 as well asthe BL2 capacitance (assumed to be 20fF).

Voltage Sensing of ’0’

Current Sensing of ’0’

(BL2 is precharged to 0.5V)

(VDS2 = 0.2V)

0.0

0.1

0.2

0.3

0.4

0.5

BL2

Vol

tage

(V

)

10-7 10-6 10-5 10-4 10-3 10-2

Time (s)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

T2 C

urrent (mA

/fin)

Holding ’0’ w/ BL1 Disturb / Read

52

Table 2-1.Charging/discharging-current comparison between theFBGC and 1T FBCs

Current (A/µm) FBGCImpact

ionization GIDL

Charging 1.3x10-8 4.0x10-5 1.5x10-8

Discharging 1.2x10-7 8.0x10-4 >1x10-3

53

(T2),

lls

e to

he

n this

,

ith

the

nce

re

cell

g.,

CHAPTER 3

"P+ SOURCE" FLOATING-BODY/GATE CELL: A MANUFACTURABLENANOSCALE EMBEDDED DRAM CELL

3.1 Introduction

In Chapter 2, we suggested a novel 2T FBC in which the floating charged/

discharged body of one transistor (T1) directly drives the gate of a second transistor

thereby removing the body-factor limitation of the signal margin inherent in 1T DRAM ce

[32]. Via simulations, we demonstrated the superior signal margin of the 2T cell relativ

the 1T FBCs, and we showed how the power dissipation is reduced dramatically in a

floating-body/gate version of the 2T structure (FBGC1).

An issue of the FBGC1 is the process integration for tying the body of T1 to t

gate of T2, which undermines cell area and memory density. We address this issue i

chapter, proposing a simplified, easily manufacturable version of the FBGC (FBGC2)

which is compatible with conventional, planar SOI and DG-FinFET CMOS technology w

≅8F2 cell area. Numerical simulations and measurements of a fabricated prototype of

new cell demonstrate the basic memory concept, and also imply significant performa

superiority over the 1T FBCs, as well as the FBGC1.

3.2 "P+ Source" Floating-Body/Gate Cell Concept

The new version of the FBGC is illustrated in Fig. 3-1. The distinguishing featu

of this simplified cell is the p+ region of T1, which replaces the n+ source in the original 2T-

FBGC structure [35]; T1 is now a gated diode. The p+ "source" enables an easy, direct

connection of the T1 body to the gate of the T2 MOSFET as indicated in the figure. The

can thus be easily processed in any SOI technology, using planar or quasi-planar (e.

54

,

to

ed

T2.

ells

nce,

ign

s,

l

es,

lap in

t

ge

basic

T2

FinFET) devices (or even in bulk Si with T1 in polysilicon). GIDL tunneling current in T1

controlled by the word line (WL = G1) and the programming bit line (BL1 = D1), is used

charge the floating body/gate (B1/G2), i.e., write a ’1’. A forward bias on the diode, defin

by BL1 and the B1/G2 voltage (VB1/G2), is used to discharge B1/G2, i.e., write a ’0’. The

stored data can be sensed via voltage or current from the read bit line (BL2 = D2) tied to

For current sensing, the BL2 voltage can be high for increased margin, unlike in 1T c

subject to read-disturbs. In addition to easing the manufacturing of the FBGC, the p+

"source" enhances the transient G1-B1 coupling via the fringe/overlap G1-"S1" capacita

which can be exploited to improve the cell performance as we show. Indeed, the des

flexibility afforded by the new FBGC structure distinguishes it from all the 1T DRAM cell

and can yield superior overall performance.

3.3 Operation and Performance of the "P+ Source" Floating-Body/Gate Cell

We verify and demonstrate the operation of the new FBGC first by numerica

simulation using Taurus [40]. The 2-D structural domain used for the (mixed-mode)

simulation is what is shown in Fig. 3-1. We assume 28nm FD/SOI nMOSFET structur

with T1 being a gated diode as described above. The p+ "S1" is tied directly to G2. The

assumed gaussian source/drain lateral doping profile defines about a 2nm G-S/D over

both devices; the T2 threshold voltage (Vt) is about 0.2V. Predicted results for a transien

sequential memory operation are shown in Fig. 3-2, including the floating-B1/G2 volta

transient. The results, with nanosecond-scale write and read times, demonstrate the

operation of the cell, showing that the floating body of T1 effectively drives the gate of

and yields outstanding signal margin. The predicted T2 current margin (220µA/µm for VBL2

55

1

e

in a

or

M

BJT

gh-k

ible

s of

e

d-

= 0.2V) is more than 4x-larger than what we predicted for the original 28nm FBGC in a

similar simulation [35], and more than 10x-larger than that predicted for the 1T-FBC

counterpart [23]. We attribute the dramatic increase in the margin to the added WL-B

capacitive coupling mentioned above, which is especially significant at times when th

intrinsic gate capacitance is small during the transient operation of the cell. It results

larger read ’1’ - read ’0’ margin for VB1/G2 (0.75V vs. 0.41V for the original FBGC [35]),

which can be optimally positioned relative to Vt of T2. The high margin, which can be made

even higher via higher VBL2 as noted, implies high effective density (margin per area) f

the new FBGC. With the direct B1-G2 connection, the simplified FBGC cell size is≅8F2,

which is much smaller than the original FBGC [35] and comparable to the 1T/1C DRA

cell. Further, the predicted write-power is negligible since there is no T1 channel (or

[42]) current, unlike in the 1T DRAM cells.

3.4 Experimental Demonstration of the "P+ Source" Floating-Body/Gate Cell

Discrete DG nFinFETs and FinFET-based gated diodes were fabricated at

SEMATECH. The devices have undoped, 20nm fin-bodies, TiN gates, and Hf-based hi

dielectric with EOT = 1.3nm, Which is shown in Fig. 3-3. The FinFET gate length (Lg) is

120nm, and that for the p+-p--n+ gated diode is 500nm. Measured current-voltage

characteristics of the gated diode, in Fig. 3-4. show adequate GIDL current, with neglig

gate tunneling current (even with the long Lg). Measured current-voltage characteristic

the FinFET with a high Vt of almost 0.5V (as for long Lg [51]) is shown in Fig. 3-5. W

demonstrate the memory function of the new FBGC using a prototype created by har

56

nis

se of

BGC;

ich

arly

age

Such

nger

ed

o in

BGC

nal

r

by

high

be

e new

wiring B1 of a gated diode to G2 of a FinFET at a probe station. The circuit configuratio

shown in Fig. 3-6.

The demonstration is thus based on slow transient measurements becau

stray capacitance. We first demonstrate the voltage-based sensing enabled by the F

measured results of sequential write/hold/read operations for ’1’ and ’0’, wh

correspond to Fig. 3-2, are shown in Fig. 3-7. The functionality of the new cell is cle

exhibited; the T1 body effectively drives the T2 gate, and the T2 drain (~BL2) volt

transient indicates the stored data with a solid margin set by the supply voltage.

voltage sensing is perhaps the preferred option for the new FBGC because of lo

retention times [33], (which can be generally optimized due to design flexibility afford

by the 2T cell) and lower power, as well as less sophisticated sensing circuitry. Als

Fig. 3-8 we show measured results of a current-sensing operation of the new F

prototype. We have used a higher bit-line voltage (VBL2) for high margin, enabled by the

2T cell as noted above. The FD body of T2 prevents any read-induced Vt shifts, e.g., due

to impact ionization-current charging. The results in Fig. 3-8 show a very high sig

margin of 340mA/mm, even with the high Vt. This is a record current margin, even highe

than that reported for the BJT-based FBC [42].

3.5 Summary

We have demonstrated a simplified, superior version of the FBGC,

numerical simulation and fabrication/measurement. The new 2T cell offers very

signal margin and ultra-low power dissipation. Retention times are anticipated to

comparable to, or longer than, those of 1T FBCs. The eased fabrication process of th

57

igh

re, at

FBGC makes it compatible with planar or quasi-planar CMOS technology, with h

effective density. It can thus enable manufacture of embedded DRAM in the near futu

low cost and with superior performance.

58

Figure 3-1. The simplified FBGC structure, on SOI, in a DRAM array with two

bit lines. The p+ "source" of T1 (now a gated diode) facilitates theB1-G2 connection in the technology, and it improves the cellperformance because of additional WL-B1 capacitive coupling.

p - n+n+

WL

BL1

BL2

T2

B1/G2

p - n+p+

T1

59

Figure 3-2. Transient sequential memory operation of the new FBGC structure (FD/SOI-based with undoped thin bodies, midgap work function (TiN)gates.) inFig. 3-1 predicted by a 2-D mixed-mode numerical simulationusing Taurus. The applied WL and BL1 voltage pulses, for GIDLcharging, are shown in (a), along with the predicted floating-B1/G2voltage transient; the BL2 voltage is set to 0.2V for current sensing. TheT2 current in (b) reflects the basic memory operation, showing a signalmargin of 220µA/µm.

-2.1

-1.8

-1.5

-1.2

-0.9

-0.6

-0.3

0.0

0.3

0.6

0.9

1.2

Vol

tage

(V

)

0.0 10 20 30 40 50 60 70 80 90 100Time (ns)

-50-30-101030507090

110130150170190210230250

T2

Cur

rent

(µA

/µm

)



BL1

WL

B1/G2

Sig

nal M

argi

n≅ 2

20µA

/µm

VBL2 = 0.2V

60

Figure 3-3. Cross-section TEM of the FinFET structure used for both T1 (gateddiode) and T2 (standard diffused DG transistor) of the new-FBGCprototype. The fin dimensions are 20nm wide by 80nm tall. Theinset is a high-resolution TEM of the gate stack showing the scaledHf-based dielectric with ALD TiN metal.

61

Figure 3-4. Measured current-voltage characteristics (per twice fin height) of the

p+p-n+ gated diode formed from a double-gate nFinFET structure with

a p+ "source" (S = B); Lg = 500nm, EOT ~ 1.3nm, and tSi ~ 20nm. Thebody current (IB) is the GIDL current.

ID

IB

IG

I (A

/µm

)10-7

10-8

10-9

10-10

10-11

VG (V)

0.0-0.2-0.4-0.6-0.8-1.0-1.2

G

D

B

VD=1.2V, VB=0

62

Figure 3-5. Measured current-voltage characteristics (per twice fin height) ofthe double-gate nFinFET; Lg = 120nm, EOT ~ 1.3nm, and tSi ~20nm.

VDS=1.2V

VDS=0.05V

I DS

(A/µ

m)

10-3

10-4

10-5

10-6

10-7

10-8

10-9

10-10

10-11

10-12

10-13

VGS (V)

1.20.90.60.30.0-0.3-0.6-0.9-1.2

63

Figure 3-6. Circuit configuration of the measurement setup. The body of T1 isconnected to the gate of T2 via cable.

WL

BL1

BL2

BL2’

RL

B1/G2

T2T1

~60pF (stray capacitance)

64

Figure 3-7. Measured transient sequential write/hold/read operations for ’1’and ’0’ in the new-FBGC prototype. The voltage-based sensingoption (with inverse logic) is clearly demonstrated via VBL2’, withlow RL = 100KΩ. The stray capacitance (~60pF) of the external B1-G2 wire underlies the abnormally slow transient.

0V

0V

0V

0V

-1.2V

1.7V

-1.7V

0.7V

-0.8V

1.2V

Hold

Write ’1’ Read ’1’ Write ’0’ Read ’0’

HoldHold

VB1/G2

VBL2’

VBL1

VWL

Time

65

Figure 3-8. Measured transient sequential write/hold/read operations for ’1’and ’0’ in the new-FBGC prototype, demonstrating current sensing(with inverse logic). The circuit shown in Fig. 3-6 was used, withhigh RL = 200Ω and VBL2 = 1.2V, which yields a 340µA/µmmargin reflected by the 136mV variation of VBL2’.

0V

0V

0V

0V

-1.2V1.7V

-1.7V

0.7V

-0.8V

1.2V

Hold

Write ’1’ Read ’1’ Write ’0’ Read ’0’

HoldHold

VB1/G2

VBL2’

VBL1

VWL

Time (250µs/div)

136mV

VBL2’1.2V

’0’

’1’

0.8VV

olta

ge S

enss

ing

Cur

rent

Sen

sing

66

er,

der

IDL

ing

ng,

ich

ses

e the

in

t

e

nd

vily

le to

ng

CHAPTER 4

PHYSICAL INSIGHTS AND MODELING OF GATE-INDUCED DRAIN LEAKAGECURRENT IN FLOATING-BODY CELLS

4.1 Introduction

To avoid excessive write-’1’ power dissipation, FBCs, such as 1T cells and

FBGCs, utilize the GIDL current to charge the body of the storage device [23]. Howev

due to the floating body of the SOI MOSFET, the formation of strong accumulation un

the gate, which enables the band-to-band (BTB) tunneling process, is undermined in

nanoseconds operations. Hence, the transient GIDL current is different from the DC G

current. Normally, transient GIDL current is smaller than the DC GIDL current. By keep

the WL bias relatively low, the ’1’ state can be safely stored. However, for ’0’-state holdi

negative WL bias and positive BL disturb voltages tend to generate GIDL current, wh

will charge up the body and destroy the ’0’ state [23][30]. In the FBCs, especially the

nonclassical-MOSFET FBCs with undoped and thin body (which significantly suppres

the thermal generation current in the PN junctions), GIDL current has been proven to b

major killer of the ’0’-state retention time. It limits this disturb retention time to <100ms

most of the FBCs being examined.

In this chapter, we study the hole redistribution in the nanoseconds transien

operations and its impact on the GIDL current. Based on a better understanding of th

transient GIDL current, we attain physical insights on optimizing the applied biases a

device structure. The electrical performance of FBGC2 presented in Chapter 3 is hea

based on the performance of T1, which is a three-terminal gated-diode. So, it is possib

optimize the write-’1’ time and the ‘0’ state retention time in the FBGC design by tuni

the body bias. But due to lack of body-voltage dependence modeling, the numerical

67

e,

, an

and

ates

se

s more

GIDL

ded

on-

ion

IDL

tage

holes

B

tact

ause

cess

nt,

the

simulation tools cannot predict the BTB tunneling current reliably. To resolve this issu

based on our physical insights on the body voltage-dependent BTB tunneling current

analytical model is developed to describe the GIDL current in two cases: depletion case

accumulation case. The model, which is consistent with experimental data, demonstr

that, for given negative gate bias and positive drain bias, the GIDL current will increa

when the body voltage decreases, and tends to saturate when the body voltage become

negative, i.e., the channel becomes depleted. Due to the saturated characteristics on

current, it is difficult to reduce the unwanted GIDL current in holding-‘0’ state with BL

disturb by tuning body voltage. So, a novel device structure or write mechanism is nee

to resolve the conflict between the write-’1’ and hold-’0’ operations.

4.2 Non-Quasi-Static Hole Redistribution and Its Effect on GIDL current

Any FBC body charging process via GIDL current is associated with a fast, n

quasi-static (NQS) redistribution of holes in the floating body. But, this NQS redistribut

has not been previously acknowledged [23]. For example, in the FBGC, to enable the G

during charging, WL voltage drops to negative voltage and BL increases to positive vol

in 1ns. However, since the body is isolated from the substrate, it cannot supply enough

to establish a surface accumulation condition in T1 needed for the gate-controlled BT

tunneling of electrons to the drain/source suddenly. The holes in the body to gate con

will migrate to the surface of the T1 and the body voltage drops to more negative to c

more thermal generation current to establish the accumulation layer. This physical pro

results in the transient GIDL charging current which is different from the DC GIDL curre

as exemplified in Fig. 4-1. Predicted drain current-gate voltage characteristics of T1 in

68

ayer

ime

ity,

nt

le

n

tion

e

on

nite

ed in

eter

[54]

FBGC, without T2 tied to B1, for varying VGS sweep times are shown, along with

corresponding hole-density distributions across the body.Initially, the transient GIDL

current is much smaller than the DC GIDL current due to the less strong accumulation l

which degrades the electron tunneling probability form body to drain. After a certain of t

(1ms), the strong accumulation layer is former and enables a larger tunneling proabil

hence GIDL current increases. The NQS effect is reflected, revealing that fast-transie

GIDL current flows, but is less than the DC GIDL current, which is hence not a reliab

metric for FBC design, e.g., for defining the crucial WL and BL voltage pulses.

4.3 Body-Bias Dependence of Gate-Induced Drain Leakage Current

As we described in the introduction, GIDL current is very important in the

operation of FBCs and retention time prediction. Hence, a good understanding and a

accurate physical modeling of BTB tunneling is needed. Note that the numerical simula

tools is inadequate to model the GIDL current with body bias [40]. It cannot predict th

correct current when VB is approaching to VD and eventually VB equals VD. The tunneling

theory predicts that the tunneling current should drop with VB approaching VD and reach

zero when VB=VD. The measurement data also exemplify the GIDL current dependence

the body bias, as shown in Fig. 4-2. However, the numerical simulation tools predict fi

current when VB=VD.

1-D BTB tunneling analytical model has been developed for GIDL current in

[52]. But, the model ignores the body bias dependence. Quasi-2D model is also propos

[53][54]. Model in [53] considers the body bias dependence by adding a empirical param

to represent the lateral field. Therefore, this model is not physics based model. Model in

69

l

model

the

n is

drain.

can

les

the

wo

ing

the

n

ap

is a physics based model, but it is a complicated integral-form equation. No analytica

dependence can be seen there. Based on the previous work, we develop an analytical

for GIDL current.

Fig. 4-3 is the cross-sectional view of the gated diode which used to derive

GIDL current model. The band diagram along the vertical direction at the overlap regio

shown in Fig. 4-4. Actually, the band-to-band tunneling process is 2-D problem. We

suppose to neglect the reverse-biased PN junction leakage current between body and

Due to very high vertical electrical field at the overlap region near the surface, electron

tunnel from the valence band to the conduction band, as shown in Fig. 4-4. Then, ho

which are left in the surface are swept to the body by the lateral electrical field. From

band diagram figures in Fig. 4-4, we can see the tunneling current is determined by t

factors: (1) the vertical electrical field which implies the actual tunneling path; (2) the

overlap region between conduction band and valence band, which implies the tunnel

probability. These two factors have dependence on VB, hence, the tunneling current is a

function of VB.

Refer to the measurement data in Fig. 4-2, we can qualitatively go through

GIDL current dependence on VB. Fig. 4-2 shows that GIDL current is almost saturated whe

VB goes to more negative and demonstrate strong dependence on VB when VB is close to

VD. It is can be explained qualitatively like this. We suppose VG is negative enough and VD

is positive enough to cause very high vertical electrical field for tunneling at the overl

region. Therefore, the GIDL current is a strong function of VB. If V B is close to VD, e.g. VB

goes to VD=1.2V, it means that VGB is sufficient to induce a strong accumulation in the

channel. This implies VB can tune the vertical electrical field and overlap between

70

4-

d

. 4-5.

DL

d

n V

ows

conduction band and valence band through the accumulation layer, as shown in Fig.

5.Vice verse, if VB becomes more negative, e. g. VB is close to VG, the channel region tends

to be depleted. This implies VB cannot tune the vertical electrical field and conduction ban

and valence band overlap due to the absence of the accumulation layer, as shown in Fig

4.4 Model Development for Body Bias-Dependent Gate-Induced Drain Leakage Cur-rent

Based on above qualitative analysis, we build up an analytical model for the

GIDL current. We will use the model to physically interpret the body bias-dependent GI

current. The GIDL current will be separately modeled in two cases: depletion case an

accumulation case. In depletion case, GIDL current has very weak or no dependence oB.

It will saturate with channel becomes depleted. In accumulation case, GIDL current sh

strong dependence on VB.

A: Depletion Case:

Assuming depletion[55], the overlap region forms a depletion layer and the

vertical electrical field Esi can be expressed as

(4.1)

where N0 is the doping concentration in the drain region or overlap region,εSi is the

dielectric constant of the silicon, and q is the electron charge; x is the depletion width

normal to the Si-SiO2 interface. From Gaussian law, at the Si-SiO2 interface, the electrical

displacement should be continuous:

(4.2)

ESi

qN0εSi----------x=

ESiεSi Eoxεox=

71

OS

as

.

where Eox is the electrical field across the oxide;εox is the dielectric constant of the oxide.

The depletion with x can be expressed as [38]

(4.3)

whereψs is the surface potential or band bending in the band diagram. From [38], the M

system along the vertical direction in the gate-drain overlap region can be expressed

(4.4)

where tox is the gate oxide thickness; VFB is the G-D flat band voltage. Combining with (1),

(2), (3) and (4), we express the band bending as

(4.5)

From (1)-(5), the vertical electrical field Esi and band bending can be calculated

Referring to [38][56], we express the three-terminal band-to-band tunneling as

(4.6)

where m0 is the electron mass and h is the Plank constant.

B: Accumulation Case:

x2εSiψs

qN0------------------=

Eox

VGD VFB– ψs–

tox--------------------------------------------=

ψs VGD VFB–( ) qN0εSit2ox

ε2ox

------------

VGD VFB–( ) qN0εSit2ox

ε2ox

------------+

2

VGD VFB–( )2–

–

+=

J2m0q

3ψsESi

πh2

Eg1 2⁄

---------------------------------------8π 2m0Eg

1 2⁄

3qESih---------------------------------------–

exp=

72

t of

on is

in the

egion.

9),

In the accumulation case, (4.1) is needed to be revised due to the unneglec

high hole concentration at the gate-drain overlap region. (4.1) can be rewritten as

(4.7)

where p is the hole concentration in the G-D overlap region. Since strong accumulati

established in the channel and the overlap region, we suppose the hole concentration

channel at the center is almost the same as the hole concentration at the G-D overlap r

Then, the hole amount under the gate can be expressed as

(4.8)

where VFB(GB) is the gate-to-body flat-band voltage. We also have from (4.4)

(4.9)

where VFB(GD) is the gate-to-drain flat-band voltage. Combining (4.2), (4.7), (4.8) and (4.

we get

(4.10)

εSiESiq N0x p xd

0

xDep

∫+

=

p xd

0

xDep

∫VGB VFB GB( )– ψ0–( )

q----------------------------------------------------------------

εoxtox---------–=

Eox

VGD VFB GD( )– ψs–

tox----------------------------------------------------------=

ψs VGD VFB GD( )–( )= VGB VFB GB( )– ψ0–( ) qN0εSit2

ox

ε2ox

-------------

qN0εSit2

ox

ε2ox

------------- 2

2 VGD VFB GD( )–( ) VGB VFB GB( )– ψ0–( )+[ ]qN0εSit2

ox

ε2ox

-------------+

–

+ +

73

ase.

.6);

l

.10).

same

el in

.,

e

tate

ct on

e

n

f the

With (4.6), we can calculate the band-to-band tunneling current in the accumulation c

Regarding the depletion case, the GIDL current is determined by (4.5) and (4

(4.6) indicates GIDL is a function of band bending (ψs) which is shown in (4.5). From the

expression ofψs in (4.5),ψs is not a function of VB. So, the GIDL current is not a function

of VB, which is consistent with the experimental data in Fig. 4-2. It implies, for a given

structure, GIDL current will saturate when VB becomes negative and makes the channe

depleted. As for the accumulation case, the GIDL current is determined by (4.6) and (4

Unlike the depletion case,ψs is a function of VB, as indicated in (4.10) and (4.7). So, the

GIDL current in accumulation case is a function of VB. Equation (4.10) also implies thatψs

will decrease as VB becomes more positive. Smallerψs results in smaller tunneling current

as indicated in (4.6). The experimental data as shown in Fig. 4-2 also demonstrate the

trendency as the model predicts. Based on this qualitative analysis with the GIDL mod

two regions, we found that the GIDL current can be significantly reduced by applying

positive VB. But, unfortunately, when the FBGC is in hold-’0’ state with BL disturbs, i.e

VG is biased at < -1V and VD is biased at > 1V, the GIDL current is not a function of VB

and the current level is high enough to destroy the ‘0’ state in several miliseconds. Th

model tells us it is not possible to reduce the unwanted GIDL current in the hold-‘0’ s

to improve the retention time.

4.5 Summary

NQS hole redistribution in the nanoseconds transient operations and its impa

the GIDL current are analyzed in this chapter. Relying on a better understanding of th

transient GIDL current, we get physical insights on the dependence of GIDL current o

body-voltage. By optimizing the applied biases and device structure, the performance o

74

sed

L

olve

od to

T1 which is a three-terminal gated-diode can be improved. But, since GIDL current is u

for write-‘1’ and it also the major current to destroy the ‘0’-state in hold-’0’, there is no W

and BL biases combination can realize the desire DRAM performance. In order to res

this problem, innovations have to be proposed. Chapter 5 will demonstrate a new meth

resolve this problem.

75

Figure 4-1. A) Drain current-gate voltage characteristics of T1, biased asshown in the inset, predicted by Taurus for sweeps of VGS from1.2V to -1.5V with sweep times ranging from infinite (DC) to 1nsas indicated. The nearly constant currents seen are displacementcurrents in the G-D parasitic capacitance. The fast transients reflectfinite times for holes to accumulate at the surface of the UTB, asshown in B) by the predicted hole distributions across the body (atthe center of the channel) for the various sweep times in A). Note,however, that there is an initial, fast NQS accumulation of holes,which is enhanced by more negative VGS, that supports the GIDLcurrent virtually instantaneously.

-1.5 -1.2 -0.9 -0.6 -0.3 0.0 0.3 0.6 0.9 1.2VGS (V)

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

I DS

(A/µ

m)

DC

1ns10ns100ns1µs10µs100µs1ms1s

p+p - n+n+

TiN

0.000 0.005 0.010 0.015 0.020 0.025Distance (µm)

1017

1018

1019

1020

Hol

e C

once

ntra

tion

(cm-3

)

0.5V

VGS(t)

Floating Body p+ Region

DC

1ns10ns100ns1µs10µs100µs1ms1s

A

B

76

Figure 4-2. Measured dependence of the GIDL current on the body, or junctionvoltage of the diode.

-1.2 -0.9 -0.6 -0.3 0.0 0.3 0.6 0.9 1.2

VB(V)

10-12

10-11

10-10

10-9

10-8

10-7

I B(A

/µm

)

VG

VD=1.2V

VB

VG: -1.4V to -0.8V

77

Figure 4-3. Cross section of gated diode.

n+

p-

oxide

Gate

+

-VG

+

-VB

+

-VD

Depletion RegionMetallurgical Junction

Vertical Direction

x

78

Figure 4-4. Band diagram at the overlap region along the vertical direction withthe equilibrium condition.

EFn=EFp=EF

Oxide

DrainGate

qVG

qVGD

Ec

Ev

Electron

79

Figure 4-5. A) Band diagram at the overlap region along the vertical directionwith accumulation at the surface. B) Band diagram at the overlapregion along the vertical direction with depletion at the surface.

EFn

Oxide

DrainGate

qVG

qVGD

qVBD

EFp

EFn

Oxide

DrainGate

qVG

qVGDqVBD

EFp

Ec

Ev

Ec

Ev

A

B

80

the

he

time

0.05fF/

ded for

e NQS

the

read,

ieve

BGC

sistor

ad to

The

most

CHAPTER 5

FLOATING-BODY/GATE CELLS UPGRADED FOR ULTRA-LONGRETENTION TIME AND ULTRA-FAST WRITE TIME

5.1 Introduction

As we discussed in Chapter 4, the GIDL-current ratio of the charging operation and

’0’ holding state with disturb determines the program time and the retention time of FBCs. T

ITRS requires that the charging time should be less than 10ns and the worst-case retention

should be longer than 64ms [7]. We suppose the storage capacitance of the FBCs is about

cell. Based on these parameters [7][30], we can roughly estimate the charging current nee

a DRAM FBC to be ~10-7A/cell, and the leakage current under disturb to be ~10-15A/cell. If GIDL

current is used to charge the body in FBCs, even though the body-bias dependence and th

effect can reduce the GIDL current some in the ’0’ holding state, it is still very difficult to meet

108 current ratio shown above. Since a 1T FBC uses only one transistor to perform write and

the design flexibility in this regard is limited. It seems that GIDL-based 1T FBCs cannot ach

the 108 current ratio, and the state-of-the-art experimental data prove this [23]. However, the F

is a different case. Due to its unique 2T structure, using one transistor to write and another tran

to read, the FBGC offers more design flexibility to reach a higher GIDL-current ratio. In this

chapter, we will explore two FBGC design upgrades to get a higher current ratio that will le

longer retention time, and to faster speed as well.

5.2 Floating-Body/Gate Cell Upgraded for Ultra-Long Retention Time

5.2.1 Rationale

Retention time is a key performance indicator to qualify the emerging memory cell.

state-of-the-art experimental data have demonstrated that the worst-case retention time of

81

nts a

citance,

e FBC

ld be

e gate-

hich

e BL

rary,

iller

me

, ’0’-

’-state

rlap

mory

gher

than

FBCs is shorter than 100ms [30]. The small storage capacitance inherent in the FBC prese

serious concern regarding retention time. Since the excess holes are stored on the gate capa

which is supported by negative gate bias during holding, the major storage capacitance of th

is on the order of a few fF/µm, (e.g., 1fF/µm for Lg = 65nm with tox = 3nm), which is three orders

smaller than that of the conventional 1T/1C-DRAM capacitance. In order to meet the DRAM

retention time requirement of the ITRS [7], i.e., 64ms for worst case, the leakage current shou

minimized to be lower than ~ 10-14A/µm. Two physical mechanisms, i.e., Shockley-Read-Hall

(SRH) recombination and BTB tunneling, result in the loss of stored data, if we suppose th

oxide tunneling current has been well controlled to be lower than ~10-15A/µm. For the case of the

holding-’1’ state, negative BL disturb voltage leads to recombination at the drain junction w

tends to discharge the body. In fact, with a carefully designed junction profile and less negativ

voltage in write ’0’, a ’1’-state retention time longer than 1s can be achieved [18]. On the cont

for the case of holding-’0’, due to the classical G-S/D overlap structure with conventional

MOSFET-based FBCs, even with a well-defined junction, the BTB tunneling current is the k

of the retention time. BTB tunneling current, i.e., GIDL current, limits the ’0’-state retention ti

to be shorter than 100ms for most FBCs. Because of the write- time requirement of DRAM

state retention time in the worst case is close to ~10µs for GIDL-based FBCs [23]. A design

innovation, i.e., gate-source/drain non-overlap/underlap, has been proposed to increase ’0

retention time in the BJT-based FBC [57]. Unfortunately, FBCs with G-S/D non-overlap/unde

need higher BL voltage to drive the parasitic BJT to be latched, which is the basis of the me

operation. Therefore, higher BL voltage will also cause higher electrical field which leads to hi

unwanted GIDL current in the BL-disturb case, and the ’0’-state retention time tends to be less

82

ion,

C

ers

shold

ic

d

ys a

to

ds to

thus

s a

m

rrier-

clear,

BC,

y,

(i.e.,

T1)

100ms. Fundamentally, since G-S/D overlap is vital to perform fast charging in FBC operat

realization of long ’0’-state retention time is very challenging in FBC design.

Beyond that, the relative high operation voltages (e.g., > 2.5V) needed in the FB

writing schemes lead to many concerns of the DRAM reliability [58]. For example, hot carri

generated by the high electrical field in the write operations can cause variations in the thre

voltage or the parasitic BJT turn-on voltage (Von or BVCEO), which in turn undermine the yield of

the FBC technology. At the same time, high-voltage operation will also imply higher dynam

power. The dynamic power is proportional to CV2 [8], where C is the capacitance for charging an

V is the operation voltage. Since FBCs need to be refreshed periodically, decreasing V pla

significant role in reducing the dynamic power, and therefore the total power dissipation.

In summary, even though a very long gate-drain (G-D) underlap has been shown

increase the ’0’ retention time (in a BJT-based FBC) by decreasing the GIDL current, it ten

undermine the write-’1’ process, which is enhanced by G-D overlap. Higher BL voltages are

needed, portending cell-reliability issues and power dissipation issues. This tradeoff reflect

fundamental problem of (1T) FBCs: long retention times require suppression of a mechanis

needed for writing data fast (<10ns). The higher operating voltages (>2.5V) result in hot ca

and high field-induced MOSFET degradations, and higher dynamic power. Indeed, there is a

unavoidable tradeoff among power dissipation, write time, and data retention, which, with

questionable reliability, undermines the FBC viability.

More FBC design flexibility is needed. As mentioned in previous chapters, the 2T F

or floating-body/gate cells (FBGC1 and FBGC2) [35][36], which provide such flexibilit

are proposed. We show herein, via numerical simulations, how the FBGC in Chapter 3

FBGC2, which solves the process-integration problem of tying the body of one device (

83

lem)

urbs

bit

,

-D

T1

an

L1)

tion

the

is

ses

cts

’ and

nel

now

to the gate of the other (T2), but does not resolve the noted short retention-time prob

can be modified (to FBGC3) to achieve very long retention times under worst-case dist

while maintaining good DRAM performance, including large signal margin and low

operating power, and implying good reliability.

5.2.2 FBGC3 Concept, Operation, and Performance

Our ultimate FBGC3 is evolved from FBGC2. The structure of FBGC3 (with two

lines) is illustrated inFig. 5-1; T1 and T2 can be ofarbitrary SOI design, even with fully depleted

ultra-thin bodies. The structure is almost the same as FBGC2, except for the added long G

underlap in T1 (which is actually a gated diode). A key difference between the two cells is how

is charged (i.e., how ’1’ is written). In FBGC2, the charging is done via GIDL current under

accumulation condition, defined by a negative word-line (WL) bias and a positive bit-line (B

bias. This operation, with G-D overlap to enhance the GIDL current, leads to short ’0’ reten

time under BL1 disturb, as in the 1T FBCs. Incorporating a long G-D underlap to suppress

BL1-disturb effect does not render FBGC2 generally viable because the write-’1’ operation

undermined; a write-’1’/hold-’0’ charging-current ratio of ~108, which is needed for acceptable

FBC memory operation [7], is impossible to achieve by any combination of WL and BL1 bia

when the added effect of WL disturb (to hold-’1’) is adequately controlled. This dilemma refle

the fundamental problem noted before.

The noted design dilemma is resolved by FBGC3, which separates out the write-’1

hold-’0’ BTB tunneling currents. The write-’1’ process is now done by inverting the T1 chan

via positive WL bias, inducing a high-field n+-p+ junction in the overlapped- “source” region of T1

(indicated in Fig. 5-1) where the body-charging BTB tunneling (with positive BL1 bias) now

occurs. The hold-’0’ process, with the channel region accumulated (via negative WL bias), is

84

ing

iting

ite

of

ff,

2)

s, as

t,

be

0]-

nce

d with

-D

is

L and

dissociated with the write-’1’ process, and the GIDL current induced by BL1 disturb can be

effectively minimized (via the underlap) to get acceptable ’0’ retention time without undermin

the write-’1’ process. Further, FBGC3, unlike FBGC2, can use the same WL voltage for wr

both ’1’ and ’0’, enabling row programming in a memory array and virtually doubling the wr

speed while eliminating WL-disturb effects. And, unlike FBGC2, FBGC3 enables the option

using only one bit line (i.e., tying BL1 and BL2 in Fig. 5-1), albeit with a performance tradeo

which will be discussed later in this chapter.

In FBGC3, T1 is now like a tunneling FET (with its source/body tied to the gate of T

in which the on-state (charging) current depends on the gate (WL) and drain (BL1) voltage

well as the body voltage (VB1/G2) [59]. This BTB tunneling current, comparable to GIDL curren

can be adequate for fast write ’1’, but the gate-source overlap is crucial. (The current could

increased significantly by using a Ge-based heterostructure for T1 [59].) The SenTaurus [6

predicted BTB tunneling current-voltage characteristics shown inFig. 5-2 reveal the importance

of the overlap (> 1nm) as well as sensitivity to bias (VGS). Note, in FBGC3 operation, that the

charging current will decrease with increasing VB1/G2since the drain and gate voltage are

effectively reduced. This is evident in the write-’1’ process as illustrated by operation-seque

simulations to be discussed later. So, the tunneling FET T1 has to be asymmertically designe

overlap at the “p+ source” side and underlap at the n+ drain side. To get longer ’0’ retention time

with BL disturb, BTB tunneling current should be eliminated when WL is negative. The G-D

underlap design is very important to reduce the unwanted BTB tunneling (GIDL) current

effectively. For a given G-S overlap of 1nm, predicted BTB tunneling currents with different G

underlap are shown inFig. 5-3.The simulation results suggest at least 20nm of G-D underlap

needed to keep the tunneling current lower than 10-15A/µm, and thus yield long ‘0’-state retention

time. Note also that the G-D underlap reduces the parasitic capacitance associated with the W

85

he

s

.

y-

share

1/G2

rrents

G-

ize the

ling

nar

t the

e

by a

1/G2

BL1, which is very helpful in reducing the dynamic power. Predicted I-V characteristics of t

asymmetrical T1 are shown inFig. 5-4.From Fig. 5-4, we find that the threshold voltage of T1 i

relative high, i.e., close to 1V. With VGS< 1V, we find the BTB tunneling current is smaller than

10-7A/µm, which implies that >1V operation is needed to guarantee FBGC3 works properly

Optimization of T2 is easier than T1. First of all, T2 should be a CMOS technolog

compatible MOSFET. The major goal of the optimization is to set the Vt of T2 properly to achieve

higher sense margin. In our simulation, for 28nm n-type FD/SOI MOSFET, Vt is set at 0.3V. The

predicted ID-VG characteristics of T2 are shown inFig. 5-5.Another important constraint for T2

optimization is the possible read-’0’ error due to the leakage current in unselected cells which

the BL2. The worst case is that all the unselected cells are in the ’1’-state, which has higher B

voltages and which tends to turn-on T2 of the unselected cells. By checking the transient cu

in the simulations, we estimated ~105 cells can be connected to BL2 without reading error. The

S/D fringe capacitances, as well as the overlap capacitance, should also be reduced to minim

dynamic power dissipation.

We now demonstrate the FBGC3 memory operation via numerical simulations,

showing its superior performance and data retention inFig. 5-6. We use SenTaurus [60] for the

simulations, selecting the physical and representative Hurkx BTB- and trap-assisted-tunne

models (for charging) and doping-dependent carrier lifetimes with maximum values of 10-7s (for

discharging). SenTaurus prediction of a basic memory sequence of FBGC3, comprising pla

28nm FD/SOI UTB devices in Chapter 3, is illustrated in Fig. 5-6. Our simulations showed tha

G-D underlap length in T1 must be >20nm to adequately suppress the GIDL current; so, w

assumed 30nm. Note in Fig. 5-6 the novel write-’1’ process, with channel inversion induced

+2V WL bias; a +1.2V BL1 bias drives adequate BTB tunneling in the induced n+-p+ junction that

charges the T1 body (B1/G2) quickly, that is, charges all the capacitance associated with B

86

e G-S/D

must

ling

hole

. 5-6

ed

on,

s. We

ly by

ap

ias

n the

ess in

tal

at of

ver,

rea

node [35]. Note that since T2 (with a threshold voltage of≅0.3V) is turned on during the write-’1’

process, its gate capacitance is predominate. However, the parasitic capacitances, e.g., th

fringing capacitance of T2, are important and must be controlled [35]. Note also that FBGC3

withstand a read (with positive WL bias) disturb when holding a ’0’; that is, some BTB tunne

can occur during read, which can undermine the hold ’0’. This charging, due to VB1/G2 < 0 with

inversion, is reflected by VB1/G2(t) during the read-’0’ process in Fig. 3; it stops as VB1/G2

approaches VBL1 = 0. Further, T2 is off and its gate capacitance is low, and hence very little

charge is stored. This disturb is not a serious problem. The predicted current margin in Fig

(≅70µA/µm with VBL2 = 0.2V) is very good. By tweaking the WL and BL1 pulses, we increas

the margin to >80µA/µm, but, given the unavoidable uncertainties of numerical device simulati

the important message here is that FBGC3 yields much better margins that the 1-FET FBC

note that voltage-based sensing [35] can also be used with FBGC3.

The SenTaurus-predicted worst-case retention characteristics, defined exclusive

BL1 disturbs (VBL1 = 1.2V for hold-’0’ and VBL1 = -0.8V for hold-’1’, for the FBGC3 of Fig. 5-

6), are shown in Fig. 5-7. Acomposite retention time of ~10s is predicted! The long G-D underl

effectively suppresses the BL1 disturb-induced GIDL during hold ’0’, without significantly

affecting the write-’1’ process as evident in Fig. 5-6. During hold ’1’, the body-drain forward b

in T1 due to the BL1 disturb is low, and thus so is the hole recombination rate. Uncertainties i

modeling of the carrier generation and recombination in SenTaurus imply some equivocaln

the predicted retention time, but its dramatic length, which is consistent with the experimen

result in [61][62], cannot be disputed.

Of course, the FBGC3 area is larger than that of 1T FBCs, but is about equal to th

conventional 1T/1C DRAM. We feel the area-performance tradeoff is well worthwhile. Howe

a stacked version of FBGC3 is feasible (even with T2 in bulk Si), which would resolve the a

87

d G-D

t not

wn in

uce

ional

d

fully

two

ized

V

ltage

to -

sed

ld

-

y

ring

issue. Also, the obvious issues of scalability (with reduced storage (gate) capacitance, fixe

underlap in T1 for GIDL suppression, and relatively high operating voltages) are concerns, bu

so much as for 1T FBCs because of FBGC3 design flexibility afforded by its 2T structure.

BL1 and BL2 can also be tied together to perform the memory operation, as sho

Fig. 5-8. Thesignal margin is reduced. However, tying BL1 and BL2 together is helpful to red

the complexity and power of the peripheral circuits and makes FBGC3 looks like the convent

1T/1C DRAM. Further, it offers the possibility of utilizing current DRAM peripheral circuits

without any revision.

5.2.3 Design Optimization

Based on the optimization of T1 and T2, FBGC3 is re-designed for improve

performance, i.e., sense margin, retention time, dynamic power, and reliability. By care

analyzing the results in the previous FBGC3 operation sequence simulation, we found

issues with the FBGC3 bias schemes and the performance of the FBGC3 can be optim

by tweaking the WL and BL pulses. First, we observed two facts: VBL1 for write-’0’ is -

0.8V, but can be higher to perform the same write-‘0’operation in less than 10ns; andB1/

G2 for hold ’1’ does not have to be as low as -0.6V. Based on these facts, the BL1 vo

for write ’0’ can be raised to -0.4V, and the WL voltage for holding can be also raised

0.5V. Under these biasing schemes, the B1/G2-to-D1 PN junction is slightly forward-bia

in the holding-’1’ state with BL1 disturb. It implies ‘1’-state worst-case retention time cou

be very long. And, -0.4V VB1/G2 in hold-’1’ is also low enough to turn off T2 to avoid read

’0’ error. Raising WL voltage during holding can also beneficial to ’0’-state retention b

reducing voltage difference between WL and BL1 which will result in unwanted GIDL

current. Second, in order to increase the signal margin, a more positive WL pulse du

88

ese

. The

1

ly

BL

t, due

cy

nd in

en

the

G-S

-S

n in

, the

s

’0’-

read can be applied to get higher sense margin through WL to B1/G2 coupling. With th

improvements, the memory operation sequence is re-simulated, as shown in Fig. 5-9

results demonstrate 10µA/µm sense margin improvement. For the hold-’1’ state with BL

disturb, as mentioned before, the retention time should be very long due to the slight

forward-biased B1/G2-to-D1/S1 junction. For hold-’0’ state with BL1 disturbs, the

retention time should be longer than in the previous simulation, since less negative VWL

sould suppress the BTB tunneling current.

The issues listed above are obvious and can be fixed by tweaking the WL and

pulses. But, the capacitance coupling between the terminals is more complicated. Firs

to WL-to-B1/G2 capacitance coupling at the beginning of write ’1’, the charging efficien

decreases significantly. When WL is raised for write ’1’, VB1/G2will increase through G-S

fringe capacitance and gate capacitance. With increasing VB1/G2, the effective WL-to-B1/

G2 voltage, which is VGS of T1, will reduce. Effective BL1-to-B1/G2 voltage which is VDS

of T1 will reduce too. Both of these changes tend to decrease BTB tunneling current, a

turn decrease operation speed. Due to G1-S1 coupling, the VB1/G2 for hold ’1’ is still

relative negative even with the WL holding voltage of -0.5V. This is not necessary. Ev

though the WL-to-B1/G2 coupling could be helpful to raise the B1/G2 voltage in read,

total coupling effect is negative. Therefore, to resolve the coupling issue, reducing the

fringe capacitance could be considered. By adding an air spacer or void region, the G

fringe capacitance is reduced in simulation. The predicted- operation results are show

Fig. 5-10. Note that, in order to decrease dynamic power and improve retention time

operation voltages for all terminals are re-designed. For example, for write ’1’, VBL1 is

0.9V; for write ’0’, VBL1 is -0.3V; for read, VWL is 1.2V. The data retention characteristic

are shown in Fig. 5-11. The improvement of retention time is obvious, especially for

89

to

V

cell

read-

rror.

th

hich

.

the

ing

GC4

t T1

e

rite

state retention time with BL disturb. Tuning the work-function of T2 is an effective way

improve sense margin. In principle, increasing the work-function of T2, which tends to

decrease the Vt of T2, results in higher sense margin, as shown in Fig. 5-12. But lowert

of T2 could cause possible read-’0’ error. Since a large number of unselected hold-’1’

and intented read-’0’ cell share the same BL2, to guarantee the read-’0’ operation, the

’0’ current must be much greater than the hold-’1’ leakage current to avoid read-’0’ e

The read-’0’ and hold-’1’ currents for the same BL2 voltage is plotted in Fig. 5-12. Wi

lower T2 gate work-function, the hold-’1’ current becomes close to read-’0’ current. It

implies fewer memory cells can share the same BL2. The number of memory cells, w

is determined by the ration of read-’0’ current to hold-’1’ current, is shown in Fig. 5-12

With the midgap gate of T2, ~105 memory cells can be loaded in the same BL2.

5.3 Floating-Body/Gate Cell Upgraded for Ultra-Fast Write Time

The write time of FBGC3 is ~10ns. For a potential replacement of the SRAM cell,

write speed should be <1ns. In this regard, we propose another FBGC design modification

(FBGC4) that gives ultra-fast write times, in addition to good DRAM performance includ

large signal margin, low operating power,and very long charge-data retention times under

worst-case conditions. Further, very goodreliability is implied because of low-voltage

operation enabled by FBGC4.

Whereas FBGC2 (Chapter 3) [36] and FBGC3 structured T1 as a gated diode, FB

reverts back to the T1 MOSFET structure of FBGC1 (Chapter 2). The novelty of FBGC4 is tha

has a body-tied-to-source (BTS) structure; i.e., T1 is a BTS/SOI MOSFET with its B1/S1

connected to the gate (G2) of T2 as illustrated inFig. 5-13 .This new design enables T1 to charg

and discharge G2 for write ’1’ and write ’0’, via channel current, which can yield ultra-fast w

90

via

aving

citor

moved

arge

sistor

itor

ince

. The

s

d

me

d

as

the

note

ven

times (~100ps) at low WL and BL1 voltages (~1V). For hold ’1’, the G2 charge is transferred,

fast diffusion, to B1 for storage on the gate capacitance of T1, now biased in accumulation. Le

the charge on G2 for hold, which emulates the conventional 1T/1C DRAM cell with the capa

replaced by the gate of T2, is not viable since the charge is too small. The charge must be

from G2 to B1, and this is enabled by the innovative BTS of T1. This transfer of the stored ch

to B1 for hold ’1’ also avoids a false read operation without having to add a read access tran

to the cell [63][64]. The novelty of FBGC4 then enables use of a MOSFET in lieu of the capac

in conventional DRAM. Our 2T concept allows memory operation with small stored charge s

the charge, in B1, is used to drive T2 for reading data without being significantly expended

other memory operations of FBGC4 are virtually the same as in the previous FBGC design

[35][36].

We demonstrate the basic memory sequence of FBGC4 using our physics-base

compact model for PD/SOI or bulk-Si nMOSFETs, UFPDB (Ver. 2.5) [65], in Spice3. We assu

90nm PD/SOI MOSFETs. UFPDB/Spice3-predicted memory transients are shown inFig. 5-14.

Note the novel write-’1’ and write-’0’ processes, which use T1 channel current to charge an

discharge the gate of T2. This is an ultra-fast process, done with low WL and BL1 voltages

indicated in Fig. 5-14. The stored charge is moved to B1 for holding ’1’ by dropping the WL

voltage negative, which removes the T1 channel and creates an accumulation layer to hold

stored charge. We predict a T2 current-signal margin of approximately 30µA/µm, which, as for

FBGC in general, is much better than margins typically achieved with 1T FBCs. We further

that the very long retention times, due in part to a long G-S/D underlap in T1 [34], can be e

better in FBGC4 because of the low operational voltages enabled [66].

91

t

BC.

e 1T

-

less”

chip

he

ate

ted

tion

ime,

e

nse

p is

erent

rrier

y.

sed

h of

5.4 Comparison of the Floating-Body DRAM Cells

Since the first FBC was demonstrated in [15], FBC has evolved from impac

ionization-based FBC to GIDL-based FBC, and eventually to the popular BJT-based F

Table 5-1 gives performance comparisons of FBGC3 and FBGC4 versus representativ

FBCs.

The most attractive properties of the first 1T FBC, which is impact ionziation

based FBC, are the small unit cell area and the “capacitorless” technology. “Capacitor

process intergraion offers the possibility of embedded memory solution for system-on-

(SoC) design. The ~4F2 unit cell area implies more memory cells can be crammed on t

chip. In order to realize low-power application, GIDL-based FBC is proposed to elmin

the write-’1’ power. While maintaing the good electrical characteristics of impact

ionization-based FBC, GIDL-based FBC reduces the write-’1’ power. But, due to unwan

GIDL current which is caused by the G-to-D overlap design on these FBCs, short reten

time is the major issue with these two kinds of FBCs. Besides the short time retention t

r-limited sense margin is also another important issue with these FBCs. By utilizing th

parasitic BJT in nMOSFET, BJT-based FBC was proposed to resolve the r-limited se

margin issue. Since BJT-based FBC mainly relies on the parasitic BJT, G-to-D underla

designed to improve the retention time some. In general, BJT-based resolves the inh

problems with FBCs, but due to its ultra high operation voltage which leads to hot-ca

degradation, the reliability problem becomes very serious. After several thousands of

cycling or endurance test, BJT-based FBC will fail to perform the memory functionalit

Therefore, in terms of the reliability, BJT-based FBC is not a promising candidate. Ba

on the performance data in the first three columns in Table 5-1, it is very clear that eac

92

ent of

3

drive

based

p

e

4

kable

0’,

ical

C3

gic

on

and

are

d

C3

-

wer

them has some disadvantages which restrict these cells from being a good replacem

the conventional DRAM cell.

Unlike 1T FBCs, as shown in the fourth and fifth columns of Table 5-1, FBGC

and FBGC4 demonstrated superior performances. Since using body of T1 to directly

the gate of T2, FBGC3 and FBGC4 demonstrate the comparable sense margin as BJT-

FBC. But, due to the flexibility which is given by 2T structure, by optimize T1 with underla

at drain side and overlap at souce side, FBGC3 improves the worst-case retention tim

dramatically without undermining sense margin. Drain-side underlap design in FBGC

guarantees the worst-case retention time can be as long as ~10s. Besides the remar

improvement of worst-case retention time, since channel current is used to write-’1’/’

SRAM-compariable write speed (~100ps) is achieved in FBGC4. Even though peroid

refresh is needed for FBGC4, ultra-high operation speed makes FBGC4 could be a

promising candidate to replace the SRAM on the chip. Regarding reliability, since FBG

and FBGC4 operation voltages are compatible with the current CMOS logic device

operation voltage, the reliability of FBGC3 and FBGC4 could be the same as CMOS lo

device. Especally, since FBGC4 relies on the channel current and its maxium operati

voltage is not higher than 1V, it could be a hot carrier-free device with careful design

optimization. Finally, we have to point out that the unit cell areas of FBGC3 and FBGC4

larger than 4F2. But, it is worthwhile to make the tradeoff between the electrical

performance and the unit cell area. Moreover, if FBGC3 and FBGC4 can be structure

vertically, i.e., with T1 sitting on T2, the area problem can be resolved. In summary, FBG

and FBGC4 demonstrate superior electrical performance over 1T FBCs, and the area

performance tradeoff is worthwhile, in particular for embedded application. Due to its lo

93

C4

long

DL

the

in

AM

sing,

ted)

ss

ly

the

voltage bias schemes, superior performance, and design flexibility, FBGC3 and FBG

could also be more scalable than 1T FBC.

5.5 Summary

We believe FBGC3 has the potential to replace conventional 1T/1C DRAM in

conjunction with future nanoscale CMOS technology. Its projected performance, with very

retention time and design flexibility for ensuring reliability, make it superior to the 1T FBC

counterparts. The long G-D underlap in T1 will improve reliability, while suppressing the GI

current for ’0’ retention, yet does not affect the tunneling current for write ’1’. By optimizing

cell area, FBGC3 could be a good candidate to replace the conventional 1T/1C DRAM cell

stand-alone memory chips.

FBGC4 is proposed for embedded DRAM and to be a potential replacement for SR

cell due to its ultra fast write speed, long retention time, and fully CMOS compatible proces

with only ~1/3 of the SRAM cell area. We demonstrated FBGC4 using PD/SOI (partially deple

MOSFETs, for which much technological work has been done to optimize the BTS. We stre

though, with regard to FBGC4 scalability, that the MOSFETs in FBGC4 can be FD/SOI (ful

depleted) devices as well, including FinFETs, since high BTS resistance is not an issue in

memory operation.

94

.
Figure 5-1. The FBGC3 structure, on SOI, in a DRAM array with two bit lines. T1
is designed with gate underlap at the drain and gate overlap at the sourceThe body/source of T1 drives the gate of T2.

p - n+n+

WL

BL1

T2

B1/G2

p - n+p+

T1

Overlap (Tunnel Region) Underlap

BL2

95

Figure 5-2. SenTaurus-predicted BTB tunneling current in T1 (Lg = 28nm, tox =2nm, tSi = 14nm, tBOX = 50nm, G-D underlap = 30nm, undoped body,and midgap gate) versus the G-S overlap length;VB = 0.0V, VDS= 1.0V.The GIDL current (for VGS < 0) is effectively suppressed by the notedunderlap.

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5VGS (V)

10-18

10-17

10-16

10-15

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

I DS

(A/m

m)

G-S Overlap = 1nmG-S Overlap = 0nm (abrupt)G-S Overlap = -1nm (underlap)

96

Figure 5-3. BTB tunneling currents in T1 (Lg = 28nm, tox = 2nm, tSi = 14nm, tbox =50nm, overlap = 1nm, VDS = 1.0V) with different G-D underlappredicted by Sentaurus.

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5VGS (V)

10-18

10-17

10-16

10-15

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

I DS

(A/µ

m)

10nm20nm30nm

97

Figure 5-4. ID-VD characteristics of T1 (Lg = 28nm, tox = 2nm, tSi = 14nm, tbox =50nm, overlap = 1nm) predicted by Sentaurus.

0.0 0.5 1.0 1.5VDS (V)

0.00

0.05

0.10

0.15

0.20

0.25

I (µA

/µm

)

VGS=1.5VVGS=1.2VVGS=1.0VVGS=0.5V

98

Figure 5-5. ID-VG characteristics of T2 (Lg = 28nm, tox = 2nm, tSi = 14nm, BOX =50nm) predicted by Sentaurus, high VDS = 1.2V, low VDS= 0.2V.

-0.5 0.0 0.5 1.0VGS (V)

0.0

100

200

300

400

500

I DS

(µA

/µm

)

-0.5 0.0 0.5 1.010-15

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

99

Figure 5-6. Transient sequential memory operation of a FBGC3 cell (WL, BL1,BL2, and B1/G2 voltages, and the BL2 current showing the signalmargin), comprising FD/SOI UTB MOSFETs with with Lg = 28nm, tox= 2nm, tSi = 14nm, tBOX = 50nm, T1 overlap = 5nm, T1 underlap =30nm, undoped bodies, and midgap gates, as predicted via 2-Dsimulation with SenTaurus. Note that VBL2 is fixed at 0.2V, whichcauses the BL2 current during write ’1’; this current would beeliminated via BL2 pulsing in actual memory operation, therebyyielding very low overall dynamic power

0.0 20 40 60 80Time (ns)

-1.6

-1.2

-0.8

-0.4

0.0

0.4

0.8

1.2

1.6

2.0

2.4

Vol

tage

(V

)

0.0 20 40 60 80Time (ns)

-40.0

0.0

40

80

120

160

200

240

280

320

360

400

BL2

Cur

rent

(µA

/µm

)BL1

WL

B1/G2



BL2

Signal Margin ≅ 70µA/µm

100

,
Figure 5-7. Worst-case charge/data retention characteristics of the FBGC3 of Fig. 3as reflected by the predicted read B1/G2 voltage while holding ’0’ and’1’ with continuous BL1 disturbs as indicated. The bias voltages for thememory operation are the same as those in Fig. 5-6.
10-6 10-5 10-4 10-3 10-2 10-1 100

Time (s)

-1.3

-1.2

-1.1

-1.0

-0.9

-0.8

-0.7

-0.6

-0.5

VB

1/G

2 (V

) ’1’ hold with BL1 = -0.8V disturb’0’ hold with BL1 = +1.2V disturb

10

101

Figure 5-8. Transient sequential memory operation of the FBGC3 with BL1 andBL2 tie together.

0.0 20 40 60 80Time (ns)

-1.6

-1.2

-0.8

-0.4

0.0

0.4

0.8

1.2

1.6

2.0

2.4

Vol

tage

(V

)

0.0 20 40 60 80Time (ns)

-400

-300

-200

-100

0.0

100

200

300

400

500

Cur

rent

(µA

/µm

)



Signal Margin≅ 25µA/µm

BL1&2

WL

B1/G2

102

Figure 5-9. Transient sequential memory operation of the FBGC3 with optimalpulses.

0.0 20 40 60 80Time (ns)

-1.6

-1.2

-0.8

-0.4

0.0

0.4

0.8

1.2

1.6

2.0

2.4

Vol

tage

(V

)

0.0 20 40 60 80Time (ns)

-40

0.0

40

80

120

160

200

240

280

Cur

rent

(µA

/µm

)


BL1

WL

B1/G2



103

Figure 5-10. Transient sequential memory operation of the FBGC3 with no spacer ofT1.

0.0 20 40 60 80Time (ns)

-40

0.0

40

80

120

160

200

240

280

Cur

rent

(V

)



BL1

WL

B1/G2


0.0 20 40 60 80Time (ns)

-1.2

-0.8

-0.4

0.0

0.4

0.8

1.2

1.6

2.0

2.4

Vol

tage

(V

)

104

Figure 5-11. Data retention characteristics of FBGC3 in Fig. 5-10. The operationvoltages for write and read are the same as in Fig. 5-10.

10-6 10-5 10-4 10-3 10-2 10-1 100 101

Time (s)

-0.8

-0.6

-0.4

-0.2

0.0

0.2

VB

1/G

2 (V

)

'0'state with BL1=-0.3V disturb'1'state with BL1=0.9V disturb

105

Figure 5-12. Sentaurus-Predicted A) sense margin, B) drain current of T2 in read-’0’and hold-’1’ and C) the maxim number of cells in the same BL2 as thefunction of gate work-function of T2. The WL and BL pulses andsimulation domain are the same as the pluses and simulation domain inFig. 5-6.

4.2 4.3 4.4 4.5 4.6 4.750

100

150

200

250

300

350

400

Sen

se M

argi

n (I D

of T

2) (µ

A/µ

m)

4.2 4.3 4.4 4.5 4.6 4.710-1610-1510-1410-1310-1210-1110-1010-910-810-710-610-5

I D o

f T2

(A/µ

m)

Iread-'0'Ihold-'1'

4.2 4.3 4.4 4.5 4.6 4.7Gate Work-Function of T2 (V)

101

102

103

104

105

106

107

Num

ber

of C

ells

in B

L2 (

=I read

-'0'/I

hold

-'1')

A

B

C

106

Figure 5-13. The FBGC4 structure in a DRAM array with two bit lines, including atop view of T1. As indicated, T1 is a BTS/SOI MOSFET with its bodytied to its source. Also, T1 is designed with gate-source/drain underlapto suppress GIDL for hold-’0’. The body/source of T1 drives the gate ofT2 for reading data without significantly affecting the stored charge inT1.

p - n+n+

WL

BL1

T2

B1/S1/G2

p - n+n+/p+

T1

Underlap

BL2

n+n+

p+

B1/S1/G2

107

Figure 5-14. Transient sequential memory operation of a FBGC4 cell (WL, BL1, andB1/G2 voltages, and the BL2 current showing the signal margin),comprising 90nm PD/SOI nMOSFETs (Lg = 90nm, tox = 2nm, tSi =

120nm, n+ poly gates; Vt ≅ 0.4V) as predicted by UFPDB/Spice3device/circuit simulation; the BL2 bias is fixed at 0.2V. Note thatthe fixed VBL2 causes the BL2 current during write ’1’; this currentwould be eliminated via BL2 pulsing in actual memory operation,thereby yielding very low overall dynamic power.

0 0.25 0.5 0.75 1Time (ns)

-40

-20

0

20

40

60

80

100

120

140

160

180

200

T2

Cur

rent

(µA

/µm

)

0 0.25 0.5 0.75 1Time (ns)

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Vol

tage

(V

)


Signal Margin ≅ 30µA/µm

BL1WL

B1/G2


108

Table 5-1. Performance comparison among FBGC3, FBGC4 and 1T FBCs.

II-basedFBC

GIDL-basedFBC

BJT-basedFBC FBGC3 FBGC4

Sense Margin ~50µA ~30µA ~50µA ~80µA ~30µA

Retention Time ~10ms ~100µs ~800ms ~10s ~10s

Write Time ~10ns ~10ns <2ns ~10ns ~100ps

Cell Area 4F2 4F2 4F2 ~8F2 ~10F2

Reliability like CMOS like CMOSVery Bad (hot

carrier) like CMOS like CMOS

109

the

e

ined

PD/

r

nsic,

s

first

IG-

. For

.

nal

s

d

use

CHAPTER 6SUMMARY AND SUGGESTIONS FOR FUTURE WORK

6.1 Summary

This dissertation addressed physical insights and design considerations of

floating-body DRAM cell. The floating-body/gate cell (FBGC) was proposed and

demonstrated with superior electrical performance over other FBCs. The major

contributions of the research are summarized as follows.

In Chapter 1, the floating body effect in FD/SOI and PD/SOI MOSFETs wer

carefully studied. Supported by numerical simulations and analytical modeling, we ga

physical insights and generically explained the operation of FBC DRAM, comprising a

SOI or FD/SOI MOSFET, or an FD DG or IG FinFET. The notion of a potential well fo

charge storage in the body was dismissed, and, for the first time, the predominant intri

dynamic capacitors (bias-dependent CB) that store the body charge, or data, for the variou

devices and bias conditions were defined. For FD cells, multiple roles of the VGbS-induced

accumulation layer needed for storing and sensing data were physically defined for the

time; it renders a significant∆Vt dependent on∆VBS, and, in the FD/SOI cell with thick

BOX, it creates a significant B-S junction capacitance for the charge storage. For the

FinFET cell, the created junction capacitance is augmented by the B-Gb capacitance

GIDL charging, rather than by impact ionization, CB is augmented by the B-Gf capacitance

The new insights noted herein imply better designs for optimally trading-off the FBC sig

margin, data retention time, write speeds, and power.

In Chapter 2, a novel 2T floating-body cell on SOI for embedded DRAM wa

presented, and its operation was demonstrated and verified via process/physics-base

device/circuit simulations, supported by numerical simulations. The main novelty is the

110

stor

ed

bled

cell

d

e

ign

eing

nd T2

ill not

.

is

led

gh

of the floating body of one transistor (T1) to directly drive the gate of the second transi

(T2), thereby giving dramatic improvement in signal margin while allowing voltage-bas

sensing. Physical insight then led to a modification of the basic 2T-FBC structure, ena

by using GIDL current for T1-body charging, in which the source and drain of T1 are

shorted, and both tied to the programming bit line. This is the Ver. 1 floating-body/gate

(FBGC1). FBGC1 totally eliminates the write (T1 charging and discharging)-power

dissipation, while yielding better signal margin, longer data retention via voltage-base

sensing, and higher memory density.

The simulation-based demonstration of the FBGC1 used undoped nanoscale DG

FinFETs, or ITFETs, which are potentially scalable to Lg < 10nm. We therefore believe that

FBGC1 is similarly scalable, and much more so than a 1T counterpart for which thegate-source/

drain overlap (Leff < Lg) needed for GIDL current will limit its scalability. Because of th

design flexibility afforded by the 2T FBC, the GIDL current can be controlled via optimal des

of the G-S/D overlap in T1, which is merely a two-terminal charge-storage structure, with T2 b

designed optimally with underlap as discussed herein. We note that scaling Lg will tend to reduce

the effective storage capacitance of the 2T cell, i.e., the oxide and gate capacitances of T1 a

(although the fin height could be kept high to offset this reduction without undermining the

increased memory density). Thus, fewer holes will be stored, although the signal margin w

be undermined. However, the scaling of the fin thickness with Lg will reduce the S/D-junction

recombination current, implying that the data retention time will not be significantly affected

Hence, we believe that FBGC1 can be scaled along with the FinFET-CMOS technology. Th

optimistic projection cannot be made for 1T-FBCs, even if a DG FinFET is used.

In Chapter 3, we demonstrated a simplified, superior Ver. 2 of the FBGC, cal

FBGC2, by numerical simulation and fabrication/measurement. FBGC2 offers very hi

111

new

e, at

ient

d

ck of

B

we

h are

body

rent

in

te

the

GC3

cing

is

signal margin and ultra-low power dissipation. Retention times are anticipated to be

comparable to, or longer than, those of 1T FBCs. The eased fabrication process of the

FBGC makes it compatible with planar or quasi-planar CMOS technology, with high

effective density. It can thus enable manufacture of embedded DRAM in the near futur

low cost and with superior performance.

In Chapter 4, we examined the hole redistribution in the nanoseconds trans

operations and its impact on the GIDL current. Based on better understanding of the

transient GIDL current, we gained physical insights to optimize the applied biases an

device structure. The electrical performance of the "P+ source" FBGC is heavily based on

the performance of the T1, which is a three-terminal gated-diode. However, due to la

body voltage dependence modeling, numerical simulation tools cannot predict the BT

tunneling current reliably in the long retention time simulation. To resolve this issue,

derived the expressions for the GIDL current in depletion and accumulation cases whic

determined by body bias. We found that the GIDL current increases with decreasing

voltage. With more negative body voltage which makes channel depleted, the GIDL cur

saturates. Our derivation of the GIDL current which is supported by preliminary

experimental data, implies that it is impossible to reduce the unwanted GIDL current

holding-’0’ state by tuning VB. Therefore, innovations are needed to improve the ‘0’-sta

retention time in FBGC design.

In Chapter 5, to resolve the short worst-case retention time issue associated with

FBGC2, we refined it and proposed Ver. 3 FBGC. The key difference between FBGC2 and FB

is the charging method. In FBGC3, write-’1’ is performed by inverting the channel and introdu

BTB tunneling current at source side. Therefore, the conflict between write-’1’ and hold-’0’

resolved. Its projected performance, with ultra-long retention time and design flexibility for

112

will

he

in

e at

ts

rent

holes

ed on

rated

to

the

TS

ns.

ate

’ is

rent.

ensuring reliability, make it superior to the 1T FBC counterparts. The long G-D underlap in T1

improve reliability, while suppressing the GIDL current for ’0’ retention, yet does not affect t

tunneling current for write ’1’. FBGC3 has the potential to replace conventional 1T/1C DRAM

conjunction with future nanoscale CMOS technology.

Since FBGC2 and FBGC3 rely on BTB tunneling current for body charging,

which is relative small, the write time is several nanoseconds. To make FBGC operat

faster speed, including write ’1’ and write ’0’, Ver. 4 (FBGC4) was proposed. Due to i

ultra-fast write speed, FBGC4 could be a potential replacement for the SRAM cell. In

FBGC4, T1 is reverted to a conventional MOSFET. The key feature is the source side

design: n+ and p+ regions are used to tie the body to the source of T1. The channel cur

can then be utilized to charge/discharge the cell. During the holding state, the excess

can be transferred from the gate of T2 via the body-to-source connection, and are stor

the gate of T1. This configuration can resolve the read-disturb issue. We have demonst

FBGC4 using PD/SOI MOSFETs, for which much technological work has been done

optimize the body- t-source (BTS) tie. With regard to FBGC4 scalability, we note that

MOSFETs in FBGC4 can be FD/SOI devices as well, including FinFETs, since high B

resistance is not an issue in the memory operation.

6.2 Suggestions for Future Work

In Chapter 5, FBGC3 and FBGC4 were studied based on numerical simulatio

Experimental demonstration of these novel DRAM cell will be necessary to further valid

the viability. With regard to FBGC3, the demonstration of the ultra-long retention time

should be the most urgent task. Our experimental work on FBGC2 shows that write-’1

not a problem. We need to verify the function of the underlap to reduce the GIDL cur

Further, the junction and surface recombination characteristics should be minimized

113

rain

the

e

nd

the

ll as

re

hly

tal

i,

through processing; e.g., using non-silicide processing to get a good quality body-to-d

junction. Endurance or cycling test with FBGC3 and FBGC4 must be done to assess

reliability characteristics. Further, a good sense amplifier circuit design that utilizes th

feature of quasi-nondestructive readout to effectively reduce the refresh-busy rate, a

therefore can realize a low-power DRAM chip, is called for. And last, but not least, is

issue of process-induced variations of the underlap and overlap lengths of T1, as we

threshold-voltage fluctuation which can severely impact the sense margin and therefo

cause failure in read. The sources of the process-induced variations must be thoroug

examined so that we can guarantee good yield and memory performance. Experimen

prototyping of FBGC4 and FBGC3 is being done at Grace Semiconductor in Shangha

China, in these regards.

114

or

for

R

y

ogy

nd

gand

to

blerm

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119

120

BIOGRAPHICAL SKETCH

Zhichao Lu was born in Hubei, China. He received the Bachelor of Enigneering.

degree in electrical engineering from Tianjin University, Tianjin, China, in 2002, Master of

Science degree in electrical engineering from the Tsinghua University, Beijing, China, in

2005, and Doctor of Philosophy degree from the University of Florida, Gainesville, FL, in

2010. From January 2010 to November 2010, he was an intern atInter-university Micro-

Electronics Center (IMEC),Leuven, Belgium, working on nanoscale floating-body memory

cells (FBC) design. His research interests involve nanoscale complementary metal-oxide-

semiconductor (CMOS)device design and analysis, floating body memory cells design and

analysis, and modeling of nonclassical nanoscale CMOS devices, and the applications in

device/circuit design optimization.

physical analysis and design of nanoscale...

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