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Pipelining Philipp Koehn 26 March 2018 Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

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Page 1: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

Pipelining

Philipp Koehn

26 March 2018

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 2: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

1Laundry Analogy

6pm 7pm 8pm 9pm 10pm 11pm

Task A

Task B

Task C

Task D

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 3: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

2Laundry Pipelined

x

6pm 7pm 8pm 9pm 10pm 11pm

Task A

Task B

Task C

Task D

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 4: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

3Speed-up

• Theoretical speed-up: 3 times

• Actual speed-up in example: 2 times

– sequential: 1:30+1:30+1:30+1:30 = 6 hours

– pipelined: 1:30+0:30+0:30+0:30 = 3 hours

• Many tasks → speed-up approaches theoretical limit

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 5: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

4

mips instruction pipeline

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 6: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

5MIPS Pipeline

• Fetch instruction from memory

• Read registers and decode instruction(note: registers are always encoded in same place in instruction)

• Execute operation OR calculate an address

• Access an operand in memory

• Write result into a register

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 7: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

6Time for Instructions

• Breakdown for each type of instruction

Instruction Instr. Register ALU Data Register Totalclass fetch read oper. access write time

Load word (lw) 200ps 100ps 200ps 200ps 100ps 800ps

Store word (lw) 200ps 100ps 200ps 200ps 700ps

R-format (add) 200ps 100ps 200ps 100ps 600ps

Brand (beq) 200ps 100ps 200ps 500ps

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 8: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

7Pipeline Execution

InstructionFetch

Reg.read ALU Data

accessReg.write

InstructionFetch

Reg.read ALU Data

accessReg.write

InstructionFetch

lw $t1, 100($t0)

lw $t2, 104($t0)

lw $t3, 108($t0)

200 400 600 800 1000 1200 1400 1600 1800

InstructionFetch

Reg.read ALU Data

accessReg.write

InstructionFetch

Reg.read ALU Data

accessReg.write

lw $t1, 100($t0)

lw $t2, 104($t0)

lw $t3, 108($t0)

200 400 600 800 1000 1200 1400 1600 1800

InstructionFetch

Reg.read ALU Data

accessReg.write

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 9: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

8Speed-up

• Theoretical speed-up: 4 times

• Actual speed-up in example: 1.71 times

– sequential: 800ps + 800ps + 800ps = 2400ps

– pipelined: 1000ps + 200ps + 200ps = 1400ps

• Many tasks → speed-up approaches theoretical limit

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 10: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

9Design for Pipelining

• All instructions are 4 bytes→ easy to fetch next instruction

• Few instruction formats→ parallel op decode and register read

• Memory access limited to load and store instructions→ stage 3 used for memory access, otherwise operation execution

• Words aligned in memory→ able to read in one instruction

(aligned = memory address multiple of 4)

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 11: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

10

hazards

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 12: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

11Hazards

• Hazard = next instruction cannot be executed in next clock cycle

• Types

– structural hazard

– data hazard

– control hazard

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 13: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

12Structural Hazard

• Definition: instructions overlap in resource use in same stage

• For instance: memory access conflict

1 2 3 4 5 6 7i1 FETCH DECODE MEMORY MEMORY ALU REGISTER

i2 FETCH DECODE MEMORY MEMORY ALU REGISTER

conflict

• MIPS designed to avoid structural hazards

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 14: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

13Data Hazard

• Definition: instruction waits on result from prior instruction

• Exampleadd $s0, $t0, $t1

sub $t0, $s0, $t3

– add instruction writes result to register $s0 in stage 5– sub instruction reads $s0 in stage 2

⇒ Stage 2 of sub has to be delayed

• We overcome this in hardware

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 15: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

14Graphical Representation

IF

add $s0,$t0,$t1

200 400 600 800 1000

ID MEM WBEX

• IF: instruction fetch

• ID: instruction decode

• EX: execution

• MEM: memory access

• WB: write-back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 16: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

15Add and Subtract

IF

add $s0,$t0,$t1

200 400 600 800 1000

ID MEM WBEX

IF

sub $t0,$s0,$t3

ID MEM WBEX

• Add wiring to circuit to directly connectoutput of ALU for next instruction

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 17: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

16Load and Subtract

IF

lw $s0,20($t0)

200 400 600 800 1000

ID MEM WBEX

IF

sub $t0,$s0,$t3

ID MEM WBEX

bubble bubble bubble bubble bubble

1200

• Add wiring from memory lookup to ALU

• Still 1 cycle unused: "pipeline stall" or "bubble"

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 18: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

17Reorder Code

• Code with data hazard

lw $t1, 0($t0)

lw $t2, 4($t0)

add $t3, $t1, $t2

sw $t3, 12($t0)

lw $t4, 8($t0)

add $t5, $t1, $t4

sw $t5, 16($t0)

• Reorder code (may be done by compiler)

lw $t1, 0($t0)

lw $t2, 4($t0)

lw $t4, 8($t0)

add $t3, $t1, $t2

sw $t3, 12($t0)

add $t5, $t1, $t4

sw $t5, 16($t0)

• Load instruction now completed in time

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 19: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

18Control Hazard

• Also called branch hazard

• Selection of next instruction depends on outcome of previous

• Exampleadd $s0, $t0, $t1

beq $s0, $s1, ff40

sub $t0, $s0, $t3

– sub instruction only executed if branch condition fails

→ cannot start until branch condition result known

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 20: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

19Branch Prediction

• Assume that branches are never taken→ full speed if correct

• More sophisticated

– keep record of branch taken or not

– make prediction based on history

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 21: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

20

pipelined data path

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 22: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

21Datapath

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 23: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

22Pipelined Datapath

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 24: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

23

load

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 25: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

24Load: Stage 1

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 26: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

25Load: Stage 2

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 27: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

26Load: Stage 3

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 28: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

27Load: Stage 4

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 29: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

28Load: Stage 5

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 30: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

29

store

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 31: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

30Store: Stage 1

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 32: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

31Store: Stage 2

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 33: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

32Store: Stage 3

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 34: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

33Store: Stage 4

DataMemory

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 35: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

34Store: Stage 5

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 36: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

35

add

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 37: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

36Add: Stage 1

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 38: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

37Add: Stage 2

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 39: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

38Add: Stage 3

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 40: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

39Add: Stage 4

DataMemory

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 41: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

40Add: Stage 5

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 42: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

41

write to register

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 43: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

42Which Register?

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 44: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

43Problem

• Write register

– decoded in stage 2

– used in stage 5

• Identity of register has to be passed along

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 45: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

44Data Path for Write Register

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 46: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

45

pipelined control

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 47: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

46Pipelined Control

• At each stage, information from instruction is needed

– which ALU operation to execute

– which memory address to consult

– which register to write to

• This control information has to be passed through stages

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 48: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

47Pipelined Control

IF ID EX MEM WB

WB WB WB

M M

EX

Con

trol

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018

Page 49: Philipp Koehn 26 March 2018 · MIPS Pipeline 5 Fetch instruction from memory Read registers and decode instruction (note: registers are always encoded in same place in instruction)

48Control Flags

ALU

Add

InstructionMemory

Address

InstructionRegisters

Read register 1

Read register 2

Write register

Writedata

Read data 1

Read data 2 Data

Memory

Address

Writedata

Zero

ADD

Result

Sele

ctor

Sele

ctor

Signextended

ShiftLeft

PC

Sele

ctor

4

Readdata

IF:Instruction Fetch

ID: Instruction decoderregister file read

MEM: Memory access

EX: Execute /address calculate

WB:Write Back

Register Write

Memory R/W

ALUOperation

MemoryTo

Register

ALUSource

Branch(req. add. logic)

Philipp Koehn Computer Systems Fundamentals: Pipelining 26 March 2018


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