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Peter Gttlicher | TIPP 2011 | Chicago, June 11 th 2011 | Page 1 Peter Gttlicher, DESY For CALICE collaboration Chicago, June 11 th, 2011 A concept for power cycling the electronics of CALICE-AHCAL with the train structure of ILC

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Peter Gttlicher | TIPP 2011 | Chicago, June 11 th 2011 | Page 2 Outline Introduction: ILC, ILD, AHCAL for CALICE Motivation for power cycling Building blocks for power cycling Summary

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Peter Gttlicher | TIPP 2011 | Chicago, June 11 th 2011 | Page 3 Accelerator and Detector for e + e - Technology: -Superdonducting cavitities 1.3 GHz -Bunch structure within trains 1ms long trains, 199ms break, . bunch to bunch 337ns ILC: International Linear Collider e + e - collider with 0.5 -1 TeV e+e+ e-e- Collision point with detectors Technology: -High granularity calorimeters -e.g. CALICE-AHCAL-barrel 4 million readout channels 60 thousand channels per m 3 Need Option: For factor 100 by switching off the fast analogue electronics for 99.5% of the time Low power per channel: 40W/channel can be reached by power cycling Introduction

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Peter Gttlicher | TIPP 2011 | Chicago, June 11 th 2011 | Page 4 Interconnects with flex foils for signals, GND and power AHCAL: Analog-Hadron- CALorimeter for ILD Scintillator tiles with SiPM readout Plugged to the back of a Readout board 12 x 12 tiles 36x36 cm 2 Cassette: 2.2m long structures: 864 channels Control electronics and power connections ASICs for - analogue signals, - local storage while train - ADCs - data transfer Layer: composed out of 3 cassettes: 2600 channels Sampling sandwich with 48 layers each 3 mm scintillator + 2.5 mm electronics, infrastructure +12 mm stainless steel 3cm Introduction

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Peter Gttlicher | TIPP 2011 | Chicago, June 11 th 2011 | Page 5 Motivation: Power Cycling to avoid active Cooling With - Stainless steel - Long structure Heat Electronics with 1% power cycle 25W/channel SiPM I dark +15W/channel Need Power cycling To keep heat up below 0.5 0 C Simplified model: -No heat transfer radial bad due to sandwich -Cylindrical symmetry -Symmetry at IP-plane Mechanical design constraint: - No cooling within calorimeter to keep homogeneity and simplicity - Cooling only at service end Solution: Parabel + Fourier terms 0.0 0.5 1.0 1.5 2.0 z = Position along beam axis [m] Temperature increase [K] 0.0 0.1 0.2 0.3 Z=0m Z=2.2m Motivation

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Peter Gttlicher | TIPP 2011 | Chicago, June 11 th 2011 | Page 6 Building Blocks for the Power System 1. Planes with scintillators and SiPMs, ASICs and PCBs 4. Power supply 2. End of layer electronics DAQ is Optical: No issue for EMI 3. cable Building blocks

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Peter Gttlicher | TIPP 2011 | Chicago, June 11 th 2011 | Page 7 ASIC for fast SiPM Signals consuming Low Power Bunches from collider (ILC/CLIC): A train every 200ms Algorithm for power cycling: The ASIC switches the current of the functional blocks OFF. ASIC gets supplied all the time with voltage. PCB electronics and instruments stabilize the voltage L. Raux et al., SPIROC Measurement: Silicon Photomultiplier Integrated Readout Chips for ILC, Proc. 2008 IEEE Nuclear Science Symposium (NSS08) Functional tasks of the ASIC: -Amplify the SiPM signal and generate self trigger -Store an identified signal: 16 per train: capacitor pipeline -Digitize -Multiplexed data transfer even with more ASICs 0.5% needed ADC Digital data transfer RAM ASIC: SPIROC-2b SiPM Amp. Fast amplifiers: 1ms ADCs 3.2ms Common analogue parts, e.g. DACs, C-pipeline Digital control: 150ms >20s ON before train 1s Building blocks Power ON for:

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Peter Gttlicher | TIPP 2011 | Chicago, June 11 th 2011 | Page 8 ASIC as current switch Measurements: - Inductive current probes Slow: 0.25 50MHz Fast: 30MHz-3GHz - Setup: ASIC+ capacitors on a PCB - Expectation is ~ 1mA/channel ~40mA/ASIC, summed over all pins GND pin (1 of 2) of ASIC Expected waveform, Amplitude is arb. units. High pass of probe Measured currents at the GND-supply of ASIC Slow probe Fast probe GND pin (1 of 2) of ASIC Voltage pin (1 of 3) for preamplifier Tantal capacitor 0 200 400 600 [ns] time -20 0 20 40 60 [ns] time System has to deal with: EMI: electromagnetic interference -5Hz from train repetition to few 100MHz -2.2A for a layer, 3.4kA for AHCAL-barrel Building blocks

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Peter Gttlicher | TIPP 2011 | Chicago, June 11 th 2011 | Page 9 Current loops To do: -Controlling return currents -Keeping loops small -Avoid overlapping with foreign components. Capacitive coupling To do: -Keep common mode voltage stable -Guide induces currents to source -Keep GND-reference closer than foreigns Electro Magnetic Interference in a Power Cycled System Reference ground : -Need good definition -Any induced/applied current produces voltage drops -Separation between reference / power return / safety or controlling currents and keeping currents within own volume and instrumentation Guideline: Avoiding emission avoids in most cases picking up of noise reference return Safety. PE Building blocks

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Peter Gttlicher | TIPP 2011 | Chicago, June 11 th 2011 | Page 10 Keeping the high Frequencies local 36 x 36 cm PCB with scintillators, SiPMs LED 144mA switched current Part of a thin cassette between absorber layer of HCAL GND d PCB = 50-60m Vsupply GND Layer structure of PCB: By that one get -a thin PCB and also -A good high frequency capacitor 60pF/cm 2 -Layout with short distance to via maintain the performance. Simulation model: two diomensional delay line 1cm x 1cm Building blocks

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Peter Gttlicher | TIPP 2011 | Chicago, June 11 th 2011 | Page 11 Tantal Voltage for ASIC stabilized by local discrete Capacitors Total: 12 Tantal/4 ASICs + 17 ceramics + PCB PCB, alone Tantal, AVX, 33F Murata, 100nf Murata, 10nf Murata, 2.2nf Murata, 1nf Ceramics X7R 1kHz 1MHz 1GHz Impedance Z=|U|/|I| Frequency 90 0 -90 0 U to I phase shift 0 ASIC is supported over wide frequency range with Z< 0.1 144mA generates