Performance Comparison of PI and P Compensation in Average-Current-Controlled Three-Phase Six-Switch Boost PFC Rectifier

Laszlo Huber, Misha Kumar, and Milan M. Jovanović

Delta Products Corporation P.O. Box 12173

5101 Davis Drive Research Triangle Park, NC 27709, USA

Abstract – In this paper, it is shown that in the three-phase

six-switch boost PFC rectifier with average-current control and unbalanced input-voltage and/or input-current sensing gains, the current controller with proportional (P) compensation exhibits lower total harmonic distortion (THD) and higher power factor (PF) compared with that of proportional and integral (PI) compensation. It is also shown that the P compensation with input-voltage feedforward is effective in improving output-voltage transient response with respect to input-voltage changes only if duty-cycle feedforward is also implemented. Finally, it is shown that zero-sequence-signal (ZSS) injection, in addition to enabling the output-voltage regulation in a wider input-voltage range, also improves the THD of the input currents.

I. INTRODUCTION

Today, active three-phase PFC rectifiers need to meet very challenging performance requirements. In the majority of applications, the input current of active three-phase PFC rectifiers is required to have a total harmonic distortion (THD) less than 5% and a power factor (PF) greater than 0.99 [1]. One of the most cost-effective topologies that can meet these requirements is the three-phase six-switch boost PFC rectifier [2], which is usually implemented without neutral-point connection.

Many control methods that can achieve a high quality of input currents in the three-phase six-switch boost PFC rectifier are available [3], [4]. Generally, approaches using direct control of input current result in better quality of the input currents compared to those using direct power control [5]. Today, the control circuit is usually implemented with digital technology. One direct current control method, well suited for digital implementation, is average current control [6], [7]. Fundamentally, the average current control of the three-phase six-switch boost PFC rectifier can be implemented with three independent current controllers with a common triangular carrier [5], [8]. With appropriate zero-sequence-signal (ZSS) injections, advanced control methods can be achieved which are equivalent to different continuous and discontinuous space vector modulation methods [9]-[12].

In the average current control, the voltage controller is usually implemented with PI compensation (for better regulation of the output voltage, which has to follow the reference output voltage with minimum error), whereas, the current controller can be implemented with PI or P compensation [5], [13]. The average current control in most implementations also includes voltage feedforward (VFF), ZSS injection, and duty-cycle feedforward (DFF). With

VFF, it can be achieved that the output voltage is practically insensitive to the line voltage variations. ZSS injection is, generally, required to achieve output-voltage regulation in an entire input voltage range. In fact, with ZSS injection, the amplitude of the effective input voltage can be reduced by up to 15% [11]. Finally, DFF is mostly employed when current controllers with PI compensation are used to reduce the phase shift between a phase voltage and phase current and, consequently, improve the PF [14].

Despite the fact that the design considerations for the current controllers in three-phase rectifiers are almost identical to those for single-phase rectifiers, the performance of the three-phase three-wire rectifiers under unbalanced conditions (caused by unbalanced input voltages and/or unbalanced input-voltage and/or input-current sensing gains) can be significantly different from that of single-phase rectifiers due to the coupling of the input phase currents.

In this paper, it is shown that in the three-phase six-switch boost PFC rectifier with average-current control and unbalanced input-voltage and/or input-current sensing gains, the current controller with P compensation exhibits better performance, i.e., lower THD and higher PF, compared with that of the PI compensation. It is also shown that the DFF, in addition to reducing the phase shift between the respective input voltages and currents in the implementation of PI compensation, significantly improves the effectiveness of VFF in the P-compensation implementation. Finally, it is shown that ZSS injection improves the THD of input-currents in both current controllers with PI and P compensation. The operation with PI and P compensation is illustrated with Matlab/Simulink simulation waveforms and experimentally verified on a 3-kW prototype.

II. POWER STAGE AND CONTROL CIRCUIT

The simplified circuit diagram of the three-phase six-switch boost PFC rectifier used in this study is shown in Fig. 1. The evaluation circuit was designed with the following basic specifications:

input phase-voltage range 120 ± 15% Vrms line-frequency range 45-65 Hz nominal output voltage 400 V maximum output power 3 kW

The switches are implemented with an IGBT six-pack module [15]. The switching frequency is selected as fsw = 20 kHz, which is the maximum recommended fsw for the selected IGBT module. The values of boost inductors and output filter capacitors are La = Lb = Lc = 1 mH and Cp = Cn = 2240 µF, respectively.

978-1-4799-2325-0/14/$31.00 ©2014 IEEE 935

The block diagram of the average current control that is implemented with digital signal processor (DSP) TMS320F2808 from TI [16] is also shown in Fig. 1. For average current control, the input phase-to-phase voltages, phase currents, and the output voltage are sensed. The input phase-to-phase voltages and the output voltage are sensed by using differential amplifiers, whereas, the phase currents are sensed by using Hall sensors and differential amplifiers. The sensed voltages and currents are converted to digital signals through the 12-bit analog-digital converter (ADC) of the DSP. The input voltage range of the ADC is 0-3 V, i.e., the full-scale range FSR = 3 V. As only positive voltages can be applied to the input of the ADC, the bipolar phase-to-phase voltages and the bidirectional phase currents are scaled to ±FSR/2 and level shifted by FSR/2. The output signals of the DSP are the digital PWM (DPWM) gate signals for the bottom switches Sxn, xϵ{a,b,c}. The gate signals for the upper switches, generally, are the complementary signals of the bottom switches. The DPWM is implemented with a triangular carrier, i.e., up-down counter. As the clock frequency of the DSP is fsysclock = 100 MHz, the peak value of the triangular carrier (i.e., the maximum counter value) is Cpk = fsysclock/(2fsw) = 2500. All the sensed signals are sampled at the peak of the triangular carrier.

As shown in Fig. 1, the average current control is implemented with VFF (block KmAB/C2). The voltage controller is implemented with PI compensation so that the voltage-loop bandwidth is 10 Hz in steady-state operation (to meet the strict THD requirements on phase currents) and 100 Hz during load transients (to reduce the output voltage overshoot and undershoot). The current controller with PI

and P compensation is designed so that the current-loop bandwidth is 2 kHz and 2.5 kHz, respectively, which both result in 45o phase margin. The PI compensation also includes a conditional anti-windup implementation [17].

It is also shown in Fig. 1 that the control implementation includes ZSS injection and DFF. The ZSS signal is obtained as the negative average of the positive and negative envelopes of the input phase voltages (symmetrical ZSS) [9]. The DFF signal for each phase is obtained directly from the corresponding phase voltage. It should be noted that without DFF, the ZSS signal can also be obtained from the output signals of the current controllers. However, when DFF is employed, the duty cycle of the switches in steady-state operation is dominated by the DFF signals and, therefore, the ZSS injection obtained from the output signals of the current controllers is not effective.

Finally, it should be noted that in order to meet the dead-time requirements for the IGBT module [15] and taking into account the propagation delay times of the optocouplers in the interface circuit between the DSP and IGBT module [18], the duty cycle range is limited from Dmin,Lim=0.07 to Dmax,Lim=0.93.

III. PERFORMANCE COMPARISON OF CURRENT

CONTROLLERS WITH PI AND P COMPENSATION

A. Steady-State Operation

First, steady-state performance comparison of current controllers with PI and P compensation implemented only with VFF, i.e., without ZSS injection and DFF, is done. The

p

n LINE VOLTAGE

SENSINGvs K

PHASE CURRENT SENSING

cs K

OUTPUT VOLTAGE

Sap Sbp Scp

San Scn

v o

v a0

v b0

v c0

L

L

L

i a

i b

i c

Sbn

+

-

a

b

c

C p

C n

ANTIALIASING

FILTER

LOW-PASS

FILTER

ANTIALIASING

FILTER

Phase A

VOLTAGE CONTROLLER

ADC

1FSR

13

ADC

Phase B

Phase C

v oref *

v EA *

i aref *i *

a K AB

C 2m

v a0 *

B

A C

v ca*

v ab*

v o*

ADC

1FSR

1FSR

*v a0 AVG

CURRENT CONTROLLER

DPWM

S an Sap

v ZSS*

v a0 *

ZSS INJECTION

DUTY-CYCLEFEEDFORWARD +

ZSSv a0 * v *

v oref *

+

GENERATOR

ZERO-SEQUENCE

SIGNAL (ZSS)

v ZSS*

v b0 *

v c0 *

Offset1.5V

FSR 2

Offset1.5V

DSP

12

*

D an *

* - notation for digital values

D CCa *

SENSING

Fig. 1 Simplified circuit diagram of power stage and block diagram of control circuit

936

comparison is performed at balanced input voltages for both balanced and unbalanced sensing gains. As an example, simulated waveforms of phase voltages and inductor currents at nominal phase voltage of 120 Vrms and 2-kW load with PI and P compensation are presented in Figs. 2 and 3, respectively. The inductor-current waveforms in Figs. 2(b) and 3(b) are obtained with balanced sensing gains (Kvsab= Kvsbc= Kvsca and Kcsa= Kcsb= Kcsc), while the inductor-current waveforms in Figs. 2(c) and 3(c) are obtained with unbalanced current-sensing gains (Kcsa=0.9Kcsb, Kcsb=Kcsc).

With balanced sensing gains, the waveform of the inductor currents with both PI and P compensation is almost perfectly sinusoidal with THDs slightly greater than 2%. However, as shown in Fig. 2, the inductor currents with PI compensation are significantly phase shifted with respect to the phase voltages (ϕ ~16.5o), which results in a reduced PF.

With unbalanced current-sensing gains, the quality of the inductor currents with P compensation is almost the same as that with balanced sensing gains (THDa = THDb = 2.08%, THDc= 2.11%). However, with unbalanced current-sensing gains, the quality of the inductor currents with PI compensation is noticeably deteriorated compared to that with balanced sensing gains (THDa = 4.4%, THDb = 4.84%, and THDc = 8.07%). This behavior can be explained by considering the output signal of the current controllers and the duty-cycle limits.

In steady-state operation, with balanced sensing gains, without ZSS injection and DFF, the output signal of the current controllers is sinusoidal with amplitude

pko

m*max,CC C

V

VD , (1)

which is scaled to the peak value of the triangular carrier.

Fig. 2 Simulated waveforms of phase voltages and inductor currents in steady-state operation (120Vrms, 2kW) with PI compensation (with VFF, without ZSS injection and DFF): (a) phase voltages [V], inductor currents [A] at (b) balanced sensing gains , and (c) unbalanced current-sensing gains (Kcsa=0.9Kcsb, Kcsb=Kcsc)

At the nominal phase voltage of 120 Vrms,

10612500400

1202

*

max,CCD . (2)

Considering the duty-cycle limits, the linear-operation range is determined as

107525002

0709302500

2

..DDD Limmin,Limmax,*

Lim,CC .(3)

From (2) and (3), it can be concluded that in this design the margin to compensate errors, such as dc offsets and unbalanced sensing gains, is very narrow, i.e.,

%.D*CC 321

1061

10611075

. (4)

This narrow margin for compensation of errors has a detrimental effect on the current controllers with PI compensation. The simulations show that the output signal of the current controllers with PI compensation contains a negative dc offset such that even with balanced sensing gains the minimum duty cycle is very close to the minimum limit. This dc offset (dc error) is generated by the integrator due to the limited dc gain of the integrator. Then, with unbalanced current-sensing gains, the minimum duty cycle in phases “b” and “c”, which have larger current-sensing gain than phase “a”, becomes saturated, resulting in distorted phase currents as shown in Fig. 2(c).

Generally, for a given input voltage, the duty-cycle saturation margin can be increased by selecting a higher output voltage and/or extending the available duty-cycle range. Both approaches increase the difference between the required maximum (minimum) duty cycle and the duty-cycle limits. However, both approaches also suffer from major drawbacks that make them impractical in any applications.

Fig. 3 Simulated waveforms of phase voltages and inductor currents in steady-state operation (120Vrms, 2kW) with P compensation (with VFF, without ZSS injection and DFF): (a) phase voltages [V], inductor currents [A] at (b) balanced sensing gains, and (c) unbalanced current-sensing gains (Kcsa=0.9Kcsb, Kcsb=Kcsc)

-200

-100

0

100

200

-10

-5

0

5

10

0.2833 0.2861 0.2889 0.2917 0.2944 0.2972 0.30.3

10

5

0

-5

-10

-200

-100

0

100

200

-10

-5

0

5

10

0.2833 0.2861 0.2889 0.2917 0.2944 0.2972 0.3-10

-5

0

5

10

Va0 Vb0 Vc0

Ia Ib Ic

Ia Ib Ic

(a)

(b)

(c) t[sec]

ϕ~16.5º

THDc=2.02% THDa=2.02% THDb=2.01%

THDa=4.4% THDb=4.84%THDc=8.07%

Va0Vb0

Vc0

Ia

Ib

Ic

Ia

Ib

Ic

(a)

(b)

(c) t[sec]

THDc=2.08% THDa=2.08% THDb=2.08%

THDc=2.11% THDa=2.08% THDb=2.08%

937

Besides increasing the size and cost of the output filter, increasing the output voltage of the three-phase front end beyond 420-450 V prevents the use of downstream dc-dc converters for single-phase applications that are typically designed for 340-420-V range. Widening the duty-cycle limits requires lowering the switching frequency and/or selecting faster switches and faster interface circuits, if available. Lowering the switching frequency below 20 kHz is not desirable because of increased size of magnetic components and possible audio-noise issues.

It should be noted that the implementation with PI compensation is more sensitive to unbalanced current-sensing gains than to unbalanced voltage-sensing gains. For example, with Kvsab=0.9Kvsbc, Kvsbc=Kvsca, the THD of the inductor currents with PI compensation is almost the same as that with balanced sensing gains (THDa = 2.08%, THDb =2.04%, and THDc = 1.94%). In fact, a 10% mismatch in phase-to-phase voltage sensing gains results in only 5% mismatch in phase-to-neutral voltage sensing gains.

The power factor of the inductor currents with PI compensation can be vastly improved by implementing DFF. As shown in Fig. 4(b), with DFF, the phase shift of the phase currents with respect to the phase voltages is ϕ ~1.5o, which is a significant reduction compared to ϕ ~16.5o without DFF in Fig. 2(b). The phase-shift reduction with DFF can be explained by noticing that with DFF, the duty cycle of the switches in steady-state operation is dominated by the DFF signals, which are proportional to the phase voltages, while the effect of the output signals of the current controllers on the duty cycles is practically negligible. However, it should be also noted that with DFF, the distortion of the inductor currents with PI compensation and with unbalanced current-sensing gains is approximately the same as that without DFF, as it can be seen in Figs. 2(c) and 4(c).

Fig. 4 Simulated waveforms of phase voltages and inductor currents in steady-state operation (120Vrms, 2kW) with PI compensation (with VFF and DFF ,without ZSS injection): (a) phase voltages [V], inductor currents [A] at (b) balanced sensing gains, and (c) unbalanced current-sensing gains

(Kcsa=0.9Kcsb, Kcsb=Kcsc)

The THD of the inductor currents with PI compensation and with unbalanced current-sensing gains can be improved by implementing ZSS injection, as illustrated in Fig. 5(c). In fact, with symmetrical ZSS injection, which is implemented in this paper, the effective amplitude of the input phase voltages is reduced by 15% [11]. As a result, the maximum duty cycle is proportionally reduced,

9022500400

8501202

.D*

max,CC , (5)

and, therefore, more margin is available for compensation of errors, i.e.,

%.D*CC 219

902

9021075

. (6)

This increased margin is sufficient to keep the duty cycle of the switches away from saturation at nominal phase voltage of 120 Vrms. However, at maximum phase voltage of 138 Vrms, even with ZSS injection, the inductor currents are distorted with unbalanced current-sensing gains, as shown in Fig. 6(c).

Finally, it should be noted in Fig. 5(b) that with ZSS injection, the THD of the inductor currents with PI compensation and balanced sensing gains is improved compared to that without ZSS injection shown in Fig 4(b). Specifically, the THD of the inductor currents is reduced from ~2.1% to ~1.6%. This is the result of the reduced peak-to-peak ripple in the inductor currents around the peak value of the phase voltages, as it can be observed by comparing Figs. 4(b) and 5(b).

ZSS injection also improves the THD of inductor currents with P compensation. Specifically, at 120-Vrms phase voltage and balanced sensing gains , the THD of the inductor

Fig. 5 Simulated waveforms of phase voltages and inductor currents in steady-state operation (120Vrms, 2kW) with PI compensation (with VFF , DFF, and ZSS injection): (a) phase voltages [V], inductor currents [A] at (b) balanced sensing gains, and (c) unbalanced current-sensing gains

(Kcsa=0.9Kcsb, Kcsb=Kcsc)

-200

-100

0

100

200

-10

-5

0

5

10

0.2833 0.2861 0.2889 0.2917 0.2944 0.2972 0.3

-10

-5

0

5

10

-200

-100

0

100

200

-10

-5

0

5

10

0.2833 0.2861 0.2889 0.2917 0.2944 0.2972 0.3-10

-5

0

5

10

Va0 Vb0 Vc0

Ia Ib Ic

Ia Ib Ic

(a)

(b)

(c) t[sec]

THDc=2.09% THDa=2.1% THDb=2.09%

THDc=7.55% THDa=4.2% THDb=4.3%

Va0Vb0

Vc0

Ia

Ib

Ic

Ia

Ib

Ic

(a)

(b)

(c) t[sec]

THDb=1.8%

THDa=1.61% THDc=1.61%

THDc=1.79% THDa=1.7%

THDb=1.62%

938

currents with P compensation and with ZSS injection is reduced to ~1.7% from ~2.1% without ZSS injection.

B. Operation with Phase-Voltage Transients

Performance comparison of current controllers with PI and P compensation during phase-voltage transients is performed first with balanced input voltages and balanced sensing gains, and for a control implemented with VFF and ZSS injection, and without DFF. In this evaluation, the phase voltage is stepped from 102Vrms to 138Vrms and back to 102Vrms at 2-kW load. It should be noted that ZSS injection was necessary to achieve output-voltage regulation in the entire input voltage range from 102 Vrms to 138 Vrms. During the phase-voltage transients, the voltage-loop bandwidth was 10 Hz. Key simulated waveforms with PI and P compensation are presented in Figs. 7 and 8, respectively. It can be seen in Fig. 7 that the output voltage with PI compensation and VFF is almost insensitive to input voltage transients. The output voltage overshoot and undershoot when the amplitude of the input phase voltages step changes between 144 V and 195 V is around 3-4 V. However, as shown in Fig. 8, despite the VFF, the output voltage with P compensation exhibits a significant overshoot and undershoot (~20V) when the amplitude of the input phase voltages steps up from 144 V to 195 V and steps down from 195 V to 144 V, respectively. As can be seen from the waveforms in Figs. 7 (b) and (e), in the implementation with PI compensation the sensed inductor currents follow the reference currents, whereas in the implementation with P compensation the sensed inductor currents are very different from the reference currents, as shown in waveforms in Figs. 8 (a) and (e). This behavior of the P compensation can be explained by analyzing the output signal of the current controllers. For simplicity, the ZSS injection is not included in the following considerations.

Fig. 6 Simulated waveforms of phase voltages and inductor currents in steady-state operation (138Vrms, 2kW) with PI compensation (with VFF, DFF, and ZSS injection): (a) phase voltages [V], inductor currents [A] at (b) balanced sensing gains, and (c) unbalanced current-sensing gains

(Kcsa=0.9Kcsb, Kcsb=Kcsc)

In steady-state operation, without DFF and ZSS injection, the current controllers generate the desired duty cycles. Using the notations in Fig. 1, the following relationship can be written at the peak value of the phase voltage,

pk

o

mm

cs

FFmvs

*EAm

vs

mp CV

VI

FSR

K

KV

FSRK

VVFSR

K

KK

22

2

, (7)

where, the first and second term in the bracket represent the reference current and sensed current, respectively, Kp is the gain of the P compensation, and KFF is the conversion factor from rms to average value, i.e.,

90

2

2

.V

VK

m

m

FF

. (8)

The peak value of the sensed current Im can be expressed through the input-output power balance as

m

om V

PI

3

2 , (9)

where, efficiency of 1 is assumed. After substituting (9) into (7), it is obtained that

2

2

3

2

2 mp

pko

cs

m

FFvs*EA V

VoK

CP

FSR

K

FSRK

KKV , (10)

Fig. 7 Key simulated waveforms at phase-voltage transients 102Vrms 138Vrms 102Vrms, 2-kW load, with PI compensation (with VFF and ZSS injection, without DFF): (a) phase voltages [V], (b) inductor currents [A], (c) output voltage and reference output voltage, (d) output of voltage controller [digital value in Q12 format], (e) reference phase currents [A], (f) duty cycles [digital values scaled to Cpk=2500]

-200

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0

100

200

-10

-5

0

5

10

0.2833 0.2861 0.2889 0.2917 0.2944 0.2972 0.3-10

-5

0

5

10

-200

0

200

-10

0

10

395

400

405

1900

2000

2100

-10

0

10

0.25 0.3 0.35 0.4 0.450

1000

2000

Va0 Vb0 Vc0

Ia Ib Ic

Ia Ib Ic

(a)

(b)

(c) t[sec]

THDc=6.47% THDa=3.64% THDb=3.64%

THDc=1.87% THDa=1.87% THDb=1.88%

Vb0Vc0

IaIb

Ic

IarefIbref

Icref

Vo

(a)

(b)

(c)

(d)

(e)

(f) t[sec]

Voref

VEA*

Dan*

Dbn*

Dcn*

3.6V 2.6V

I(a,b,c) follow I(a,b,c)ref

Vo

Voref

Va0

939

where, it is shown that the voltage controller output *EAV

varies proportionally to the square of the peak value of the phase voltages Vm. In fact, this variation is significant, as shown in Fig. 8(d). The voltage controller output *

EAV changes approximately between 0 and -850 (in Q12 format) when the amplitude of the input phase voltages step changes between 144 V to 195 V. Due to the slow voltage loop, *

EAV slowly changes, resulting in significant overshoot and undershoot in the output voltage.

The transient performance of the P compensator with VFF can be vastly improved when DFF is also implemented. The effect of the DFF at phase-voltage transients with P compensation is presented in Fig. 9. It can be seen in Fig. 9 that the output voltage with P compensation, when VFF is used with DFF, becomes practically insensitive to input voltage transients.

It should be noted that with DFF, the sensed inductor currents with P compensation properly follow the reference currents, as seen comparing waveforms in Figs. 9 (b) and (e). This behavior of the P compensation can be explained by considering the generation of the switch duty cycles. In steady-state operation with DFF, the switch duty cycles are dominated by the DFF signals, whereas, the effect of the output signals of the current controllers on the duty cycles can be neglected, i.e., the output signals of the current controllers can be considered as zero. By equating with zero the left-hand side of (7) which represents the output of the current controllers , and by using (9) , it is obtained that

om

FFcsvs*EA P

FSRK

KKKV

2

2

3 , (11)

Fig. 8 Key simulated waveforms at phase-voltage transients 102Vrms 138Vrms 102Vrms, 2-kW load, with P compensation (with VFF and ZSS injection, without DFF): (a) phase voltages [V], (b) inductor currents [A], (c) output voltage and reference output voltage, (d) output of voltage controller [digital value in Q12 format], (e) reference phase currents [A], (f)

duty cycles [digital values scaled to Cpk=2500]

where it is shown that the voltage-controller output is independent of the peak value of the phase voltages. In fact, when the amplitude of the input phase voltages step changes between 144 V to 195 V, the voltage controller output *

EAV

changes only by approximately ±10 around 2240 (in Q12 format) to compensate the small changes in the output voltage due to the fact that the inductor currents cannot instantly change.

In the case of the PI compensation, when VFF is used with DFF, the output voltage overshoot and undershoot is practically negligible (less than 1 V) when the amplitude of the input phase voltages step changes between 144 V to 195 V.

IV. EXPERIMENTAL RESULTS

Experimental waveforms of phase voltage va0 and phase currents ia, ib, and ic in steady-state operation, at nominal phase voltage of 120 Vrms and 2-kW load, at balanced input voltages and practical input-voltage and input-current sensing gains are presented in Figs. 10-13. The waveforms in Figs. 10 and 11 are obtained with PI and P compensation, respectively, for operation with VFF and ZSS injection, and without DFF. The waveforms in Figs. 12 and 13 are obtained with PI and P compensation, respectively, for operation with VFF and DFF, and without ZSS injection. These results are in agreement with the simulation waveforms and, generally, verify that the current controller with PI compensation is more sensitive to unbalances in the input-voltage and input-current sensing gains than the current controller with P compensation. Comparing the measured currents and PFs with PI compensation in Figs. 10 and 12, it can be seen that

Fig. 9 Key simulated waveforms at phase-voltage transients 102Vrms 138Vrms 102Vrms, 2-kW load, with P compensation (with VFF, ZSS injection, and DFF): (a) phase voltages [V], (b) inductor currents [A], (c) output voltage and reference output voltage, (d) output of voltage controller [digital value in Q12 format], (e) reference phase currents [A], (f) duty cycles

[digital values scaled to Cpk=2500]

-200

0

200

-10

0

10

380

400

420

-1000

-500

0

-10-505

10

0.2 0.25 0.3 0.35 0.40

1000

2000

-200

0

200

-10

0

10

399.5

400

400.5

2220

2240

2260

-10

0

10

0.3 0.35 0.4 0.45 0.50

1000

2000

Dan Dbn Dcn

VEA

Va0 Vb0 Vc0

Ia Ib Ic

Iaref Ibref Icref

Vo

(a)

(b)

(c)

(d)

(e)

(f)

t[sec]

Voref Voref

Vo

18V

19.5 V

*

* * *

I(a,b,c) do not follow I(a,b,c)ref

Va0Vb0

Vc0

Ia

Ic

Ib

Vo

VEA

Iaref

Ibref

Icref

Dan

Dcn

(a)

(b)

(c)

(d)

(e)

(f)

t[sec]

Voref 0.45V

0.3V

I(a,b,c) follow I(a,b,c)ref

*

Dbn**

Vo

Voref

*

940

Fig. 10 Experimental waveforms of phase-voltage Va0 and phase currents Ia,

Ib, Ic in steady-state operation (120Vrms, 2kW) with PI compensation

(with VFF and ZSS injection, without DFF) .

Fig. 11 Experimental waveforms of phase-voltage Va0 and phase currents Ia,

Ib, Ic in steady-state operation (120Vrms, 2kW) with P compensation (with VFF and ZSS injection, without DFF).

Fig. 12 Experimental waveforms of phase-voltage Va0 and phase currents Ia,

Ib, Ic in steady-state operation (120Vrms, 2kW) with PI compensation (with VFF and DFF, without ZSS injection).

Fig. 13 Experimental waveforms of phase-voltage Va0 and phase currents Ia,

Ib, Ic in steady-state operation (120Vrms, 2kW) with P compensation (with VFF and DFF, without ZSS injection).

DFF improves the PF with PI compensation from 0.956-0.959 to 0.998. The THD measurements in Figs. 10 and 11 compared to those in Figs. 12 and 13 show that ZSS injection improves the quality of the input currents in both current controllers with PI and P compensations.

V. SUMMARY

In this paper, it is shown that in the three-phase six-switch boost PFC rectifier with average-current control and unbalanced input-voltage and/or input-current sensing gains, the current controller with P compensation exhibits better performance, i.e., lower THD and higher PF, compared with that of the PI compensation. The sensitivity of the current controller with PI compensation to unbalances in the sensing gains is the result of the relatively small margin in the linear operation range (due to the limits of the switch duty cycles), which is available for compensation of various parameter mismatches. The simulations show that the output signal of the current controller with PI compensation contains a negative dc offset such that even with balanced sensing gains the minimum duty cycles are close to the minimum limit. Then, with unbalanced current-sensing gains, the minimum duty cycles become saturated.

It is also shown that the DFF, in addition to reducing the phase shift between the respective input voltages and currents in the implementation with PI compensation, significantly improves the effectiveness of VFF in improving the output-voltage transient response with respect to input-voltage changes in the P-compensation implementation. This behavior of the current controller with P compensation is the result of the variation of the voltage-controller output *

EAV with the changes of the input-voltage amplitude. Without DFF, *

EAV varies with the square of the input-voltage

amplitude, whereas, with DFF, *EAV is independent of the

input-voltage amplitude.

100V/div

5A/div

4msec/div

Ia Ib Ic

Va0

THDa=5.48% PFa=0.9591

THDc=4.83% PFc=0.9564

THDb=4.86% PFb=0.956

100V/div

5A/div

4msec/div

Ia Ib Ic

Va0

THDa=2.78% PFa=0.9988

THDc=2.76% PFc=0.9983

THDb=3.11% PFb=0.9976

100V/div

5A/div

4msec/div

Ia Ib Ic

Va0

THDa=5.7% PFa=0.998

THDc=6.49% PFc=0.9977

THDb=6.31% PFb=0.9977

100V/div

5A/div

4msec/div

Ia Ib Ic

Va0

THDa=4.45%PFa=0.9981

THDc=4.26% PFc=0.9978

THDb=4.4% PFb=0.9971

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Finally, it is shown that ZSS injection improves the THD of input-currents in both current controllers with PI and P compensation. This is the result of the reduced peak-to-peak ripple in the inductor currents around the peak value of the phase voltages. In addition, ZSS injection increases the margin in the linear operation range for compensation of various parameter mismatches.

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