Performance Analysis of Different Arbitration Algorithms of the AMBA AHB Bus

Massimo Conti, Marco Caldari, Giovanni B. Vece, Simone Orcioni, Claudio Turchetti

DAC 2004, June 7-11, 2004

San Diego, California, USA

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Abstract

Bus performances are extremely important in a platform-based design. System Level analysis of bus performances gives important information for the analysis and choice between different architectures driven by functional, timing and power constraints of the System-on-Chip. This paper presents the effect of different arbitration algorithms and bus usage methodologies on the bus AMBA AHB performances in terms of effective throughput and power dissipation. SystemC and VHDL models have been developed and simulations have been performed.

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Outline

Abstract What’s the problem Introduction AMBA Bus and SystemC models Simulations and results

Inter-burst idle insertion Arbitration algorithms

Conclusion

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What’s the problem

System-level design and IP modeling is the key to fast SoC innovation Innovate quickly High level of abstraction Fast simulation IP reuse

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Introduction

Use SystemC to quickly try out different design alternatives: to confirm the best possible architecture HW/SW partition performance parameters Power consumption

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AMBA Bus and SystemC models AMBA AHB can be decomposed in the

following main blocks: One arbiter A decoder Some multiplexing logic

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Arbitration algorithms

Priority with break Priority Priority with waiting time control Short Job First Short Job First with waiting time control

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Experiment environment introduction Three masters and one slave: M1, M2 and DM

(default master) Transmits sequences of 512 bytes for a total of 5k

bytes for each master M1 transmits each packet of 512 bytes in different

ways: 1 burst of 128 beats 2 bursts of 64 beats 4 bursts of 32 beats 8 bursts of 16 beats 16 bursts of 8 beats

M2 transmits 10 bursts of 128 beats each Idle period of a length 4, 8, 16 Data bus : 32 bit

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Important characteristic

M1 intentionally divides its transmission in bursts to enable the use of the bus by other master during its idle periods

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Results

There is no inter-burst of master that bursts length is 128 beats

Waiting time is not effected by the inter-burst idle length

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Results (cont.)

Input signals : HSELx HWRITE HTRANS HSIZE HBURST HRESET HMASTER HMASTLOCK

Output signals HREADY HSPLIT

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Results (cont.) Results in table 1-5 are

useful to evaluate the bus performance High priority master use

short burst the low priority one : Waiting time decrease Switching activity

increases

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Results (cont.)

Traffic generator HIGH: random sequence

of 8 or 16 beats bursts LOW: random sequence o

f single or 4 beats bursts Priority order : M1 high ..

M5 low Algo. 2 penalize low prio

rity master Algo. 5 penalize long len

gth burst

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Conclusion

SystemC accurate model of the AMBA AHB bus

Models are used to evaluate the performance A reduction of bus power dissipation of more t

han 22%