Character Design and Stamp Algorithms for Character Projection Electron-Beam Lithography

Peng Du, Wenbo Zhao, Shih-Hung Weng,Chung-Kuan Cheng, Ronald GrahamCSE Dept., University of California, San Diego, CACharacter Design and Stamp Algorithms for Character Projection Electron-Beam LithographyOutlineIntroductionProblem FormulationCharacter Design for Wire LayoutsCharacter Design and Stencil Compaction for Via LayoutsExperimental ResultsConclusionIntroductionElectron Beam Lithography (EBL)Variable Shaped Beam (VSB)a set of variant rectangles to assemble the layoutCharacter Projection (CP)a limited number of characters on a stencil still constrains the improvement of throughput

Problem Formulation(1) Design a limited set of characters and put them in a stencil(2) Match the characters against the layout with smaller number of shotsProblems for Wire Layout Implementationwire layout is partitioned into blocks with size cx cy objective is to design a set of characters with size cx cy Since the wire layout is generally dense, we assume different characters do not share the same area in the stencilux, uy to denote the pitches (unit distances)L = cx / ux and H = cy / uy as the number of wires in vertical and horizontal directions in a block

5Problems for Wire Layout ImplementationWe have the following assumptions on the capability of CP technology when characters are stamped to the layout:(1) A type of character can be used multiple times (2) Arbitrary position can be chosen for a character to be stamped on the layout (3) A character can be masked so that only a rectangular window of it is exposed (4) The same area of the wire layout can be stamped for multiple times which corresponds to an "OR" operationAn example for "stamp" process

Problems for Via Layout Implementationobjective is to design a set of characters with size cx cyassume that the via layout has the same block size and pitches in each layerthe via layout is generally sparse, several characters may share the same area in the stencilSxSy grids with unit size uxuy

Problems for Via Layout Implementationan example that three characters are compacted into a stencil with much smaller size than the total size of the characters

Character Design for Wire LayoutsN1: There is a single wire and the segment in the block above is not empty. We extend the wire to fill the block except the top grid.N2: There is a single wire and the segment in the block above is empty. We extend the wire to fill the block. N3: There are two wires and the segment in the block above is empty. First we extend the two wires so that they touch the top and bottom boundary respectively. Then we extend both two wires so that the split between them shrinks to a single grid. The grid position is chosen from a prescribed set Sg whose size is determined by available types of characters.We choose Sg to be a set of grids with fixed distance between neighbors in our experiments. If grids in the split and Sg are disjoint, we reduce the split into an arbitrary grid in it.Others: The layout remains unchanged. We implement the segment using VSBNormalization of the wire layout

Character Design for Wire LayoutsType 1: Containing a single empty grid whose position belongs to Sg.Type 2: Containing a single empty grid on the top.Type 3: Containing only one wire and no empty grids.Type 4: Containing more than two wires or a single empty grid whose position is not in Sg.

Character Design for Wire Layoutsnormalized segmentsType 1: around 4%Type 2 & Type 3: around 95%Type 4: around 1%the total number of different types of characters is

Character Design for Wire Layoutsgreedy algorithm to match characters with the layout

First, we split the layout into several rows with a heightcy. For each row, we organize the segments into groups whichare separated by segments of Types 1 and 4. Each group startswith a segment of Type 1 or 4 followed by segments of Types2 and 3. Now we match the characters greedily in each groupas long as the bound Bg is not exceeded. The segments withType 4 will be omitted in the stamp process and we assumethat they can be implemented separately by VSB14Character Design for Wire LayoutsIn order to achieve a balance between the overhead and the stamp performance, we split the wire layout into rows with different heights less than cy by a dynamic programming algorithm.OPT(h) = c1overhead c2performanceCharacter Design and Stencil Compaction for Via Layoutsthe vias distributed randomly and sparsely in the layoutIn order to limit the number of different characters, we restrict that all paths walk in top-right directionTherefore, the number of different characters with path length k or less is

Character Design and Stencil Compaction for Via LayoutsIn order to compact all characters with path length three into a stencil with limited area, we first place multiple off diagonal lines with different gaps w = 1, 2, . . . , L + H 2 We call an area between two adjacent off-diagonal lines as a belt.

Character Design and Stencil Compaction for Via Layouts

the location of a middle via v2 below v1 can only be chosen in the L-shape dotted area in order to avoid the overlap and save the stencil area as much as possible

18Character Design and Stencil Compaction for Via Layoutsfinding a permutation of 1, 2, . . . ,w to Minimal

Traveling Salesman Problem (TSP)

Implement the layoutconstruct a directed acyclic graph G(V,E) where the vertex set V contains all vias and an edge (u, v) E if and only if via v is in the first quadrant of u the bounding box of u and v can be contained in the rectangle L H.Vertex disjoint path cover of graph GMinmum path cover P* of GFor each path in P*, we greedily split it into paths satisfying: (1) the length of them is three or less(2) the bounding box of them can be contained in a character.Wire Layout Experimental Results

Wire Layout Experimental Results

Wire Layout Experimental Results

Wire Layout Experimental Results

Via Layout Experimental Results

ConclusionCharacter design stencil compaction and layout matching algorithms for both wire and via layoutFor the wire layout, we normalize the wires by dummy fills to alleviate the chaotic structure and design characters accordinglyFor the via layout, we compact a large amount of characters onto a stencil and devise a path cover algorithm to realize the layout. Experimental results show that our framework can greatly improve the throughput of manufacturing over VSB.