Development of the new timing system for

the ISTTOK Tokamak

Bernardo B. Carvalho1, Antonio Batista1, Jorge Sousa 1, Horacio Fernandes1,

bernardo.carvalho@tecnico.ulisboa.pt

1Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, Av. Rovisco Pais 1, 1049-001 Lisboa, Portugal

The ISTTOK timing system was successfully replaced by a modular

Event Based FPGA based hardware. Event management in progress.

Integration on ISTTOK completed (Linux Drivers, Firesignal Node)

Currently being adapted to other Tokamaks (e.g . COMPASS)

Main References:[1] “ISTTOK real-time architecture,“, IS Carvalho, P Duarte, H Fernandes, DF Valcárcel, PJ Carvalho, C Silva, et al

Fusion Engineering and Design 89 (3), 195-203

[2] “A VME timing system for the tokamak ISTTOK” CAF Varandas, B Carvalho, H Fernandes, J Sousa, JAC Cabral,

Review of scientific instruments 66 (5), 3382-3384

[3] “Standard Hardware API Design Guide”, Guideline for designing Hardware Access APIs for MTCA.4 Systems,

2016, PICMG

[4] “FireSignal—data acquisition and control system software”, A Neto, H Fernandes, A Duarte, BB Carvalho, J Sousa, DFValcárcel, Fusion Engineering and Design 82 (5-14), 1359-1364

This work was supported by the Fundação para a Ciência e Tecnologia through the Instituto de Plasma e Fusão Nuclear, a research

institute of Instituto Superior Técnico, The views expressed in this poster are the sole responsibility of the authors

• In AC operation the current inversion phase is critical for the

number of plasma semi-pulses that could be attained

• Need an ATCA/MARTe based real-time control system, capable to

monitor the plasma and generate the optimized power supplies

and other actuator references in a 50us control cycle [1].

• Need for a new timing and trigger system

• New hardware based on a high performing FPGA (Xilinx Kintex 7)

Events can be programmed in

1. Deterministic Mode

• PCIe Programming

• Firesignal Interface [4]

• Firesignal GUI Configuration Panel

2. Event Mode (Real Time)

• Received by Software Layer (PCIe)

• Via SFP (Aurora) and MARTe Nodes

• Low profile ATX 1U I/O expandable

• Hosted in a PC server case based on COTS components

• Allows Insertion of one or more modules

• Kintex 7 FPGA Enclustra KX1 plug-in-module

Timing Module Structure

Conclusion

IntroductionSFP CASE

U77-A1118-200T

SFP CASEU77-A1118-200T

LLC 0743370016

168 PIN FPGA CONNECTOR BFX10A-168P-SV1

168 PIN FPGA CONNECTOR AFX10A-168P-SV1

32 DIFF PAIRS

32 DIFF PAIRS

LVDSSN65LVDM1677DGG

LVDSSN65LVDM1677DGG

LVDSSN65LVDM1677DGG

LVDSSN65LVDM1677DGG

GBETHERNETL834-1G1T-S7

GBETHERNETL834-1G1T-S7

SATAEXPRESS

78757-0001

LEMOEPY.00.250.NTN

TRANSCEIVERSN74AVC4T774PW

MINI USBUSB-M26FTR

USB TO UARTCP2103GM

JTAG87833-1420

100 MHZOSCILLATOREG-2121CA

2.5V

2.5V 2.5V

2.5V 12V

RESSETABLE FUSEMF-LSMF300 3A

12V2.5V 3.3V

3.3V

2.5V

3.3V

SFP0744410001

SFP0744410001

3.3V 3.3V

ATX 1 U Format

New Timing system specifications

Timing Channels

• Max to 64 I/O optical timing channels (up to 8 sets of 8 inputs)

• Max 256 channels in 1U format (4 modules); 512 in 2U

(8 modules); 2048 in 4U (32 modules).

• 2 SFP ports on the front panel;

• 4 single ended signals that can be used for external clocks,

external triggers, synchronization between modules, etc. (LEMO

connectors).

• Ethernet (RJ-45 port) for IEEE-1588-2008 (PTP) synchronization

(~50 ns RMS)

Time Specifications

• Pre-programmed or Event Base Triggering

• One or more absolute time counters (32 or 64 bit).

• Time resolution programmable as 10 ns or 100 ns;;

• Max time span of 40 s and 400 s respectively (with 32-bit

registers; 64-bit upgradeable).

Timing module hardware

diagram

The ISTTOK is a small tokamak,

large aspect ratio and fully ohmic

• Operated since 2015 at an AC regime[1]

• Up to one second duration plasma

• Max 40 current inversions.

Former control system (since 1992) was fully

deterministic, an in-house developed in VME [2]

• Only pre-programed event

• 1 us max resolution

• With Different scales for delays, time resolution

had to be adjusted and/or several channels

chained together

• Limited register space,

• Low flexibility

• Complex operator interface.

Programing Model

“Firesignal”

Programing

Panel

Kintex

KX1 FPGA

Timing module PCB

main Board

ISTTOK standard rack 3U

PC installation

with I/O fiber connectos

ISTTOK AC Pulse #34327.

With pre-programmed inversion timing.

Each Trigger channel

configured with three

32-bit registers:

1. Event Configure

• 4 bit –Pulse Mode

• 28 bit- Pulse Number

count

2. Event Delay

3. Pulse Period

Time

Event Delay (32 bit)

Start

MODE 1: Step after a programmable Delay

Event Delay (32 bit)Pulse Period (32 bit)

Time

Pulse Period (32 bit)

Number of Pulses =2 (28 bit)

MODE 2: Square Clock after Delay

MODE 3: Programmable number of pulses after Delay

Timing Module

PCIe Bus X1

CablePCIe Interface X1 Gen2

KINTEX FPGA Firmware

PCIe Registers

SHAPI STANDARDRegister

Timing Output Registers

Timing Input Registers

PCIe Interface

Card

Timing Channel Out 0

SFP

Timing Channel Out 0

Ouputs

Inputs

FPGA Firmware Diagram

Timing Base Board:

• ATX format

• SATA type connectors

• Quartz-stabilised oscillator

(200Mhz)

• Ethernet (RJ-45 port)

• Two SFP Ports

• LVDS Connectors

• JTAG Programing

FPGA Module FW Project

• Kintex 7 FPGA, XC7K160T or

XC7K325T options

• PCIe x1 Cable Interface

• SHAPI Register Set [3]

• Clock DCM PLL

• Optional Microblaze Soft CPU

for Ethernet and IEEE1588

synchronizing

30th Symposium on Fusion Technology, 16-21 September 2018, Giardini Naxos, Sicily, Italy

ATX 1U compact format

system installation