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PCI-1751

48-bit Digital Input/Output Card for PCI Bus

Users Manual

CopyrightThis documentation and the software included with this product arecopyrighted 1998 by Advantech Co., Ltd. All rights are reserved.Advantech Co., Ltd. reserves the right to make improvements in theproducts described in this manual at any time without notice.

No part of this manual may be reproduced, copied, translated ortransmitted in any form or by any means without the prior writtenpermission of Advantech Co., Ltd. Information provided in this manualis intended to be accurate and reliable. However, Advantech Co., Ltd.assumes no responsibility for its use, nor for any infringements of therights of third parties which may result from its use.

AcknowledgmentsPC-LabCard is a trademark of Advantech Co., Ltd. IBM and PC aretrademarks of International Business Machines Corporation. MS-DOSand Windows are trademarks of Microsoft Corporation. Intel andPentium are trademarks of Intel Corporation.

CE notificationThe PCI-1751, developed by ADVANTECH CO., LTD., has passed theCE test for environmental specifications when shielded cables are usedfor external wiring. We recommend the use of shielded cables. Thiskind of cable is available from Advantech. Please contact your localsupplier for ordering information.

Part No. 2003175100 1st EditionPrinted in Taiwan August 1998

ContentsChapter 1 General Information ............................. 1

Introduction .......................................................................... 2Chapter 2 Installation .............................................. 5

Initial Inspection .................................................................. 6Unpacking ............................................................................ 6Jumper Settings................................................................... 7PCI-1751 Block Diagram .................................................. 10Pin Assignments................................................................. 11Installation Instructions ..................................................... 12

Chapter 3 Operation .............................................. 13Operation ........................................................................... 14Digital I/O Ports ................................................................. 14Timer/Counter Operation .................................................. 17Interrupt Function .............................................................. 19

Appendix A Function of 8254 Counter Chip ...... 23Appendix B Register Format of PCI-1751 ......... 31

Chapter 1 General Information 1

1General Information

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2 PCI-1751 User's Manual

Introduction

The PCI-1751 is a 48-bit DI/O and counter/timer card with PCI bus. Itprovides you with 48 bits of parallel digital input/output as well as 3timers. It emulates mode 0 of the 8255 PPI chip, but the bufferedcircuits offer a higher driving capability than the 8255.

The card emulates two 8255 PPI chips to provide 48 DI/O bits. TheI/O bits are divided into six 8-bit I/O ports: A0, B0, C0, A1, B1 and C1.You can configure each port as either input or output via software.The dual interrupt handling capability provides users the flexibility togenerate interrupts to a PC. A pin in the connector can output adigital signal simultaneously with the card's generating an interrupt.This card uses a high density SCSI 68-pin connector for easy andreliable connections to field devices.

Two other features give the PCI-1751 practical advantages in anindustrial setting. When the system is hot reset (the power is notturned off) the PCI-1751 retains the last I/O port settings and outputvalues if the user has set jumper JP4 to enable this feature. Otherwise,port settings and output values reset to their safe default state, or tothe state determined by other jumper settings. The PCI-1751's otheruseful feature is it supports both wet and dry contacts, allowing it tointerface with other devices more easily.

Numbering Convention

All numbers given in this manual are in decimal format unlessspecifically noted otherwise. In particular, where a register address isgiven as (Base + 32), the decimal number "32" should be added to thebase value.

Features

• 48 TTL level digital I/O lines.

• Emulates mode 0 of 8255 PPI

• Buffered circuits provide higher driving capability

Chapter 1 General Information 3

• Interrupt handling

• Interrupt output pin for simultaneously triggering external deviceswith the interrupt

• High density SCSI 68-pin connector

• Output status readback

• Two 16-bit timers can be cascaded to one 32-bit timer, and cangenerate watchdog timer interrupts

• One 16-bit event counter can generate event interrupts

• Keeps port I/O settings and digital output states after hot systemreset

• Supports dry contact and wet contact

Applications

• Industrial AC/DC I/O devices monitoring and control

• Relay and switch monitoring and control

• Parallel data transfer

• Sensing the signals of TTL, DTL, CMOS logic

• Driving indicator LEDs

Specifications

I/O channels: 48 digital I/O lines

Programming mode: 8255 PPI mode 0

Input Signal

• Logic high voltage: 2.0 to 5.25 V

• Logic low voltage: 0.0 to 0.80 V

• High level input current: 20 µA

• Low level input current: -0.2 mA


Output Signal

• Logic high voltage: 2.4 V minimum.

• Logic low voltage: 0.4 V maximum

• High level input current: 15 mA maximum (source)

• Low level input current: 24 mA maximum (sink)

• Driving capability: 15 LS TTL

Interrupt Source

• PC00, PC04, PC10, PC14, Timer 1 and Counter 2.

Transfer Rate(This value depends on software and speed of computer.)

• Typical: 1 MB/sec (tested under DOS, Pentium® 100 MHz CPU)

• Maximum: 1.5 MB/sec

Connector: One SCSI-II 68-pin female connector

Power consumption: 5 V @ 850 mA (Typical)

5 V @ 1.0 A (Max.)

Operating temperature: 0 ~ 70º C (32º F ~ 158 ºF)

Storage temperature: -20 ~ 80º C(-4º F ~ 176º F)

Humidity: 5% ~ 95% non-condensing

Dimension: 170 x 100 mm (6.9" x 3.9")

Chapter 2 Installation 5

2Installation

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Initial InspectionBefore starting to install the PCI-1751, make sure there is no visibledamage on the card. We carefully inspected the card both mechani-cally and electrically before shipment. It should be free of marks andin perfect order on receipt.

As you unpack the PCI-1751, check it for signs of shipping damage(damaged box, scratches, dents, etc.) If it is damaged or fails to meetits specifications, notify our service department or your local salesrepresentative immediately. Also, call the carrier immediately andretain the shipping carton and packing materials for inspection by thecarrier. We will then make arrangements to repair or replace the unit.

UnpackingThe PCI-1751 contains components that are sensitive and vulnerableto static electricity. Discharge any static electricity on your body toground by touching the back of the system unit (grounded metal)before you touch the board.

Remove the PCI-1751 card from its protective packaging by graspingthe card's rear panel. Handle the card only by its edges to avoid staticdischarge which could damage its integrated circuits. Keep theantistatic package. Whenever you remove the card from the PC,please store the card in this package for its protection.

You should also avoid contact with materials that hold static electrici-ty such as plastic, vinyl and styrofoam.

Check the product contents inside the packing. There should be onecard, one CD-ROM, and this manual. Make sure nothing is missing.


Jumper SettingsWe designed the PCI-1751 with ease-of-use in mind. It is a "plug andplay" card, i.e. the system BIOS assigns the system resources such asbase address and interrupt automatically. There are only two func-tions with 11 jumpers to be set by the user. The following sectiondescribes how to configure the card. You may want to refer to thefigure below for help in identifying card components.

Figure 2-1: Location of connectors and jumpers

Jumper Settings to Set Ports as Input orOutput by Software

By shorting the upper two pins of jumpers JPA0, JPB0, JPC0L, JPC0H,JPA1, JPB1, JPC1L or JPC1H, a user sets the corresponding ports to beconfigurable as input or output ports by software. (JPA0 means jumperfor port A0, JPB0 means jumper for port B0, etc.) The initial state ofeach port after system power on or reset will be set as input logic 1(voltage high), provided that no external signals are connected, andprovided jumper JP4 does not determine otherwise (see Jumper J4discussion below).


Using Jumpers to Set Ports as Output Ports

By shorting the lower two pins of the jumpers JPA0, JPB0, JPC0L,JPC0H, JPA1, JPB1, JPC1L or JPC1H, a user sets the correspondingports to be output ports. (JPA0 means jumper for port A0, JPB0means jumper for port B0, etc.) Shorting the lower two pins of aport's jumper pins disables the port from being software configurableas an input port. The initial state of each of these ports after systempower on or reset will be logic 0 (voltage low), unless jumper JP4determines otherwise. (See Jumper JP4 below.)

Jumper JP4 Restores Ports to Their Condi-tion Prior to Reset

Jumper JP4 gives the PCI-1751 a new and valuable capability. With JP4enabled, the PCI-1751 "memorizes" all port I/O settings and outputvalues, and, in the event of a "hot" reset, the settings and outputvalues present at the port just prior to reset are restored to each portfollowing reset. This feature applies to both ports set by software, andto ports configured as output ports via jumper. Depending on theapplication, this capability may allow a card to be reset withoutrequiring a complete shutdown of processes controlled by the card(since port values are left unchanged and are interrupted only momen-tarily).

Complete loss of power to the chip clears chip memory. Thus, even ifJP4 is enabled, if the power to the card is disconnected, the card'sinitial power-on state will be the default state (for software-set ports)or the state of an output port with voltage low output (for jumper-setports).

When jumper JP4 is not enabled, power-off or reset results in portsreturning to their default state (for software-set ports) or returning tothe state of output port with voltage low output (for jumper-set ports).


Select Clock Source of Timers and Counter

Jumpers JP1, JP2 and JP3 are used to select the clock source of Timer0, Timer 1 and Counter 2, respectively. Short the upper two pins ofthe jumpers to select an external clock source, or short the lower twopins to select an internal clock source. However, the internal clocksource of Timer 1 is connected to the output of Timer 0, so shortingthe upper two pins of JP2 results in the cascading of Timer 0 andTimer 1 as a 32-bit timer.

srepmuJfosemaN srepmuJfosemaN srepmuJfosemaN srepmuJfosemaN srepmuJfosemaN noitpircsednoitcnuF noitpircsednoitcnuF noitpircsednoitcnuF noitpircsednoitcnuF noitpircsednoitcnuF

1A,0AstroprofsrepmuJ:1APJ,0APJ

1B,0BstroprofsrepmuJ:1BPJ,0BPJ

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Table 2-1: Summary of jumper settings

1

1

1

1

1

1


PCI-1751 Block Diagram

Figure 2-2: PCI-1751 block diagram

Timer 1

Timer 0


1 352 363 374 385 396 407 418 429 4310 4411 4512 4613 4714 4815 4916 5017 5118 5219 5320 5421 5522 5623 5724 5825 5926 6027 6128 6229 6330 6431 6532 6633 6734 68

PA10PA11PA12PA13PA14PA15PA16PA17GNDPB10PB11PB12PB13PB14PB15PB16PB17GNDPC10PC11PC12PC13PC14PC15PC16PC17GNDCNT0_CLKCNT0_GCNT1_CLKCNT1_GCNT2_CLKCNT2_GVCC

PA00PA01PA02PA03PA04PA05PA06PA07GND

PB00PB01PB02PB03PB04PB05PB06PB07GND

PC00PC01PC02PC03PC04PC05PC06PC07GND

CNT0_OUTGND

CNT1_OUTGND

CNT2_OUTINT_OUT

VCC

Pin Assignments

Description of pin use:

PA00 ~ PA07: I/O pins of Port A0

PA10 ~ PA17: I/O pins of Port A1

PB00 ~ PB07: I/O pins of Port B0

PB10 ~ PB17: I/O pins of Port B1

PC00 ~ PC07: I/O pins of Port C0

PC10 ~ PC17: I/O pins of Port C1

CNT0_OUT, CNT1_OUT andCNT2_OUT: Output pins ofCounter/Timer 0, 1 and 2

CNT0_CLK, CNT1_CLK andCNT2_CLK: External clock sourceof Counter / Timer 0, 1 and 2

CNT0_G, CNT1_G and CNT2_G:Gate control pins of Counter / Timer0, 1 and 2

INT_OUT: Interrupt output. Thispin changes to logic 1 whenever thePCI-1751 generates an interrupt, and returns to logic 0 when theinterrupt is cleared.

GND: Ground

VCC: +5 VDC

voltage output


Installation Instructions

The PCI-1751 can be installed in any PCI slot in the computer. Howev-er, refer to the computer user's manual to avoid any mistakes anddanger before you follow the installation procedure below:

1. Turn off your computer and any accessories connected to thecomputer.

Warning! TURN OFF your computer power supply wheneveryou install or remove any card, or connect anddisconnect cables.

2. Disconnect the power cord and any other cables from the back ofthe computer.

3. Remove the cover of the computer.

4. Select an empty 5 V PCI slot. Remove the screw that secures theexpansion slot cover to the system unit. Save the screw to securethe interface card retaining bracket.

5. Carefully grasp the upper edge of the PCI-1751. Align the hole inthe retaining bracket with the hole on the expansion slot and alignthe gold striped edge connector with the expansion slot socket.Press the card into the socket gently but firmly. Make sure the cardfits the slot tightly.

6. Secure the PCI-1751 by screwing the mounting bracket to the backpanel of computer.

7. Attach any accessories (68-pin cable, wiring terminal, etc.) to thecard.

8. Replace the cover of your computer. Connect the cables youremoved in step 2.

9. Turn the computer power on.

Chapter 3 Function Description 13

3Operation

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Operation

This chapter describes the operating characteristics of the PCI-1751.The driver software provided allows a user to access all of the card'sfunctions without register level programming. Please see the User'sManual for the driver bundled with this card for more information. Forusers who prefer to implement their own bit-level programming to drivethe card's functions, information useful for making such a program isincluded in this chapter.

Digital I/O Ports

Introduction

The PCI-1751 emulates two 8255 programmable peripheral interface(PPI) chips in mode 0, but with higher driving capability than astandard 8255 chip. Each of the 8255 chips has 24 programmable I/Opins that are divided into three 8-bit ports. The total 48 DI/O pins fromboth chips are divided into 6 ports, designated PA0, PB0, PC0, PA1,PB1 and PC1. Each port can be programmed as an input or an outputport. The I/O pins in port A0 are designated PA00, PA01,..., PA07; thepins in port B0 are designated PB00, PB01,..., PB07, etc. These portnames are used both in this manual and in the software library. Referto Section 2.5, Pin Assignments.

8255 Mode 0

The basic functions of 8255 mode 0 include:

• Two 8-bit I/O ports - port A (PA) and port B (PB)

• Port C is divided into two nibble-wide (4-bit) I/O ports:- PC upperand PC lower

• Any port can be used for either input or output.

• Output status can be read back.


Interrupt Function of the DIO Signals

Two I/O pins (PC00 and PC10) can be used to generate hardwareinterrupts. A user can program the interrupt control register (Base +32) to select the interrupt sources. Refer to "Interrupt Function" in thischapter for details about interrupt control.

Input/Output Control

A control word can be written to a port's configuration register(Base+3 for port 0 and Base+7 for port 1) to set the port as an input oran output port, unless the ports are set as output ports via jumpers(refer to Section 2.3, Jumper Settings). Table 3-1 shows the format of acontrol word.

Table 3-1: Bit map of port configuration register

Note: A control word has no effect if the corresponding port is set asan output port by a jumper.

Warning! Before setting any port as an output port via soft-ware, make sure that a safe output value has alsobeen set. An output voltage will appear at the pinsimmediately following the control word taking effect.If no output value was specified, the value will beindeterminate (either 0 or 1), which may cause adangerous condition.

D7 D6 D5 D4 D3 D2 D1 D0

Don'tcare

Don'tcare

Don'tcare

PortA0: output1: input

Port Chigherbits0: output1: input

Don'tcare

Port B0: output1: input

Port Clowerbits0: output1: input


Initial Configuration

The initial configuration of each port depends on the input/outputjumper setting of each port, on the setting of the jumper JP4, and onwhether the power was actually disconnected or whether the systemwas hot reset.

If jumper JP4 is not enabled, all ports configured by software areautomatically set as input ports during system start up or reset, with adefault signal level of logic 1 (high). All ports set via jumpers asoutput ports are set as output ports during system start up or reset,signal level logic 0 (0 V).

If the jumper JP4 is enabled and the initial configuration is caused by areset, all ports will return to the states they had just prior to the reset.The reset must be a "hot" reset (power not disconnected) for enabledJP4 to return ports to their prior values. Otherwise, the card behavesas though JP4 were not enabled. Refer to "Jumper settings" in Chapter2 for more information.

Dry Contact Support for Digital Input

Each digital input channel accepts either dry contact or 0 ~ 5 VDC

wetcontact inputs. Dry contact capability allows the channel to respondto changes in external circuitry (e.g., the closing of a switch in theexternal circuitry) when no voltage is present in the external circuit.Figure 3-1 shows external circuitry with both wet and dry contactcomponents, connected as an input source to one of the card's digitalinput channels.

Figure 3-1: Wet and dry contact inputs

1.5 K Ω0.5 W

PC 5V

10 K Ω

Buffer

Dry Contact : Open High Close Low

Wet Contact : 2 .0~5.25 V D C High 0~0.8 V D C Low

External Internal

Resistorin

Parallel


Note: For wet contact configurations, a malfunction mayoccur if the internal resistance of the voltage sourceis significant (> 1.5 kΩ). It is advisable to connect a1.5 kΩ resistor in parallel with such a voltage sourceto avoid a voltage rise inside the voltage source.

Timer/Counter Operation

Introduction

The PCI-1751 includes one 8254 compatible programmable timer/counter chip which provides three 16-bit counters, designated asTimer 0, Timer1 and Counter 2. Each has 6 operation modes. Timer 0and Timer 1 can be used separately or can be cascaded to create one32-bit timer. Both Timer 1 and Counter 2 can generate interrupts to thecomputer. Please refer to Appendix A for more information on theoperation modes of the counter chip. The block diagram of the timer/counter system is shown in Figure 3-2.

Figure 3-2: Timer and counter structure


Timer 0 & 1:Two 16-bit Timers or One 32-bit Timer

Timer 0 and Timer 1 of the counter chip can be used separately or canbe cascaded to create a 32-bit programmable timer by setting jumperJP2. By setting the clock source of Timer 1 to be an external source,you can user Timer 0 and Timer 1 as two separate 16-bit timers. Bysetting the clock source of Timer 1 to be the output of Timer 0 (internalsource) these two timers are cascaded to become one 32-bit timer.

Setting jumper JP1 sets the clock source of Timer 0 to be external, andthis allows Timer 0 and Timer 1 to be cascaded into a 32-bit eventcounter.

Counter 2

Counter 2 can be a 16-bit timer or an event counter, selectable bysetting JP3. When the clock source is set for an internal source,Counter 2 is a 16-bit timer; when set as an external source, thenCounter 2 is an event counter. Counter 2 is set as mode 0 (interrupt onterminal count) in the driver provided by Advantech.

Timer/Counter Frequency and Interrupt

The input clock frequency of the counter/timers is 10 MHz. The outputof both Timer 1 and Counter 2 can generate interrupts for the system(refer to section 3.3). The maximum and minimum timer interruptfrequency is (10 MHz)/(2)=(5 MHz) and (10 MHz)/(65535*65535)=0.002328 Hz, respectively.

The gates of the counter/timers are internally pulled to +5 V when gatecontrol is enabled, but a user can also set it using the connector pins(CNT0_G, CNT1_G and CNT2_G).


Interrupt Function

Introduction

Two lines in each I/O port (C0 and C4) and two of the three counteroutputs (Timer 1 and Counter 2) are connected to the interruptcircuitry. The "Interrupt Control Register" of the PCI-1751 controlshow the combination of the 6 signals generates an interrupt. Twointerrupt request signals can be generated at the same time, and thenthe software can service these two request signals by ISR. The dualinterrupt sources provide the card with more capability and flexibility.

IRQ Level

The IRQ level is set automatically by the PCI plug and play BIOS andis saved in the PCI controller. There is no need for users to set the IRQlevel. Only one IRQ level is used by this card, although it has twointerrupt sources.

Interrupt Control Register (Base + 32)

The "Interrupt Control Register" (Base + 32) controls the interruptsignal source, edge and flag. Table 3-2 shows the bit map of theinterrupt control register. The register is a readable/writable register.When writing to it, it is used as a control register, and when readingfrom it, it is used as a status register.

Table 3-2: Interrupt control register bit map

Port # Port 1 Port 0

Bit # D7 D6 D5 D4 D3 D2 D1 D0

Abbreviation F1 E1 M11 M10 F0 E0 M01 M00


M00 and M01: "mode bits" of port 0

M10 and M11: "mode bits" of port 1

E0, E1: triggering edge control bits

F0, F1: flag bits

Interrupt Source Control

The "mode bits" in the interrupt control register determine the allow-able sources of signals generating an interrupt. Bit 0 and bit 1 deter-mine the interrupt source for port 0, and bit 4 and bit 5 determine theinterrupt source for port 1, as indicated in Figure 3-3. Table 3-3 showsthe relationship between an interrupt source and the values in themode bits.

Figure 3-3: Interrupt sources


Table 3-3: Interrupt mode bit values

Interrupt Triggering Edge Control

The interrupt can be triggered by a rising edge or a falling edge of theinterrupt signal, selectable by the value written in the "triggering edgecontrol" bit in the interrupt control register, as shown in Table 3-4.

Table 3-4: Triggering edge control bit values

Interrupt Flag Bit

The "interrupt flag" bit is a flag indicating the status of an interrupt. Itis a readable and writable bit. Read the bit value to find the status ofthe interrupt, write "1" to this bit to clear the interrupt. This bit mustbe cleared in the ISR to service the next incoming interrupt.

Table 3-5: Interrupt flag bit values

Port 1 Port 0

M11 M10 Description M01 M00 Description

0 0 Disable interrupt 0 0 Disable interrupt

0 1 Source = PC10 0 1 Source = PC00

1 0 Source = PC10 & PC14 1 0 Source = PC00 & PC04

1 1 Source = Counter 2 1 1 Source = Timer 1

E0 or E1 Triggering edge of interrupt signal

1 Rising edge trigger

0 Falling edge trigger

F0 & F1 Interrupt status

Read 1 Interrupt exists

0 No interrupt

Write 1 Clear interrupt

0 Don't care

Appendix A Function of 8254 counter Chip 23

AFunction of 8254Counter Chip

AP

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ND

IX


The Intel 8254The PCI-1751 uses the Intel 8254 compatible programmable intervaltimer/counter. The popular 8254 offers three independent 16-bit downcounters. Each counter has a clock input, control gate and an output.You can program each counter for maximum count values from 2 to65535.

The 8254 has a maximum input clock frequency of 10 MHz. ThePCI-1751 provides 10 MHz input frequencies to the counter chip froman on-board crystal oscillator.

On the PCI-1751, the 8254 chip's Timer 0 and Timer 1 can be usedseparately or can be cascaded to create a 32-bit programmable timerby setting JP2. When the clock source of Timer 1 is from an externalsource, you can user Timer 0 and Timer 1 as two independent 16-bittimers. When the clock source of Timer 1 is set to be the output ofTimer 0 (internal source) the two timers are cascaded as a 32-bittimer. When the clock source of Timer 0 is provided externally bysetting JP1, Timers 0 and 1 can be used as a 32-bit event counter.Refer to section 2.3.3 for details of jumper settings.

Counter Read/Write and ControlRegisters

The 8254 programmable interval timer uses four registers at addressesBASE+24, BASE+25, BASE+26 and BASE+27 for read, write andcontrol of counter functions. Register functions appear below:

Register FunctionBASE+24 Counter 0 read/writeBASE+25 Counter 1 read/writeBASE+26 Counter 2 read/writeBASE+27 Counter control word

Since the 8254 counter uses a 16-bit structure, each section of read/write data is split into a least significant byte (LSB) and most signifi-cant byte (MSB). To avoid errors it is important that you make read/write operations in pairs and keep track of the byte order.


The data format for the control register appears below:

BASE+27 8254 control, standard mode

Bit D7 D6 D5 D4 D3 D2 D1 D0Value SC1 SC0 RW1 RW0 M2 M1 M0 BCD

Description:

SC1 & SC0 Select counter

Counter SC1 SC00 0 01 0 12 1 0Read-back command 1 1

RW1 & RW0 Select read/write operation

Operation RW1 RW0Counter latch 0 0Read/write LSB 0 1Read/write MSB 1 0Read/write LSB first, 1 1then MSB

M2, M1 & M0 Select operating mode

M2 M1 M0 Mode0 0 0 0 programmable one shot0 0 1 1 programmable one shotX 1 0 2 Rate generatorX 1 1 3 Square wave rate generator1 0 0 4 Software triggered strobe1 0 1 5 Hardware triggered strobe


BCD Select binary or BCD counting

BCD Type0 Binary counting 16-bits1 Binary coded decimal (BCD) counting

If you set the module for binary counting, the count can be anynumber from 0 up to 65535. If you set it for BCD (Binary CodedDecimal) counting, the count can be any number from 0 to 9999.

If you set both SC1 and SC0 bits to 1, the counter control register is inread-back command mode. The control register data format thenbecomes:

BASE+27 8254 control, read-back modeBit D7 D6 D5 D4 D3 D2 D1 D0Value 1 1 CNT STA C2 C1 C0 X

CNT = 0 Latch count of selected counter(s).

STA = 0 Latch status of selected counter(s).

C2, C1 & C0 Select counter for a read-back operation.

C2 = 1 select Counter 2



If you set both SC1 and SC0 to 1 and STA to 0, the register selectedby C2 to C0 contains a byte which shows the status of the counter.The data format of the counter read/write register then becomes:

BASE+24/25/26 Status read-back mode

Bit D7 D6 D5 D4 D3 D2 D1 D0Value OUT NC RW1 RW0 M2 M1 M0 BCD

OUT Current state of counter output

NC Null count is 1 when the last count written to the counterregister has been loaded into the counting element


Counter Operating Modes

MODE 0 Stop on Terminal Count

The output will be initially low after you set this mode of operation.After you load the count into the selected count register, the outputwill remain low and the counter will count. When the counter reachesthe terminal count, its output will go high and remain high until youreload it with the mode or a new count value. The counter continuesto decrement after it reaches the terminal count. Rewriting a counterregister during counting has the following results:

1. Writing to the first byte stops the current counting.

2. Writing to the second byte starts the new count.

MODE 1 Programmable One-shot

The output is initially high. The output will go low on the countfollowing the rising edge of the gate input. It will then go high on theterminal count. If you load a new count value while the output is low,the new value will not affect the duration of the one-shot pulse untilthe succeeding trigger. You can read the current count at any timewithout affecting the one-shot pulse. The one-shot is retriggerable,thus the output will remain low for the full count after any rising edgeat the gate input.

MODE 2 Rate Generator

The output will be low for one period of the input clock. The periodfrom one output pulse to the next equals the number of input counts inthe counter register. If you reload the counter register between outputpulses, the present period will not be affected, but the subsequentperiod will reflect the value.

The gate input, when low, will force the output high. When the gateinput goes high, the counter will start from the initial count. You canthus use the gate input to synchronize the counter.

With this mode the output will remain high until you load the countregister is loaded. You can also synchronize the output by software.


MODE 3 Square Wave Generator

This mode is similar to Mode 2, except that the output will remain highuntil one half of the count has been completed (for even numbers), andwill go low for the other half of the count. This is accomplished bydecreasing the counter by two on the falling edge of each clock pulse.When the counter reaches the terminal count, the state of the output ischanged, the counter is reloaded with the full count and the wholeprocess is repeated.

If the count is odd and the output is high, the first clock pulse (afterthe count is loaded ) decrements the count by 1. Subsequent clockpulses decrement the count by 2. After time-out, the output goes lowand the full count is reloaded. The first clock pulse (following thereload) decrements the counter by 3. Subsequent clock pulses decre-ment the count by two until time-out, then the whole process isrepeated. In this way, if the count is odd, the output will be high for(N+1)/2 counts and low for (N-1)/2 counts.

MODE 4 Software Triggered Strobe

After the mode is set, the output will be high. When the count isloaded, the counter will begin counting. On terminal count, the outputwill go low for one input clock period then go high again.

If you reload the count register during counting, the new count will beloaded on the next CLK pulse. The count will be inhibited while theGATE input is low.

MODE 5 Hardware Triggered Strobe

The counter will start counting after the rising edge of the trigger inputand will go low for one clock period when the terminal count isreached. The counter is retriggerable.


Counter Operations

Read/Write Operation

Before you write the initial count to each counter, you must firstspecify the read/write operation type, operating mode and countertype in the control byte and write the control byte to the controlregister (BASE+27).

Since the control byte register and all three counter read/writeregisters have separate addresses and each control byte specifies thecounter it applies to (by SC1 and SC0), no instructions on the operat-ing sequence are required. Any programming sequence following the8254 convention is acceptable.

There are three types of counter operation: read/load LSB, read /loadMSB and read /load LSB followed by MSB. It is important that youmake your read/write operations in pairs and keep track of the byteorder.

Counter Read-back Command

The 8254 counter read-back command lets you check the count value,programmed mode and current states of the OUT pin and Null Countflag of the selected counter(s). You write this command to the controlword register. The format is as shown at the beginning of this section.

The read-back command can latch multiple counter output latches.Simply set the CNT bit to 0 and select the desired counter(s). Thissingle command is functionally equivalent to multiple counter latchcommands, one for each counter latched.

The read-back command can also latch status information for selectedcounter(s) by setting STA bit = 0. The status must be latched to beread; the status of a counter is accessed by a read from that counter.The counter status format appears at the beginning of the chapter.


Counter Latch Operation

Users often want to read the value of a counter without disturbing thecount in progress. You do this by latching the count value for thespecific counter then reading the value.

The 8254 supports the counter latch operation in two ways. The firstway is to set bits RW1 and RW0 to 0. This latches the count of theselected counter in a 16-bit hold register. The second way is toperform a latch operation under the read-back command. Set bits SC1and SC0 to 1 and CNT = 0. The second method has the advantage ofoperating several counters at the same time. A subsequent readoperation on the selected counter will retrieve the latched value.

Counter ApplicationsThe 8254 compatible programmable interval timer/counter on yourPCI-1751 interface card is a a very useful device. You can programtimers 1 and 2 to serve as timers, event counters, square wave genera-tors, or as a watchdog to generate regular interrupts at a fixed interval.


BRegister Format ofPCI-1751

AP

PE

ND

IX


Register Format of PCI-1751

Base Address +(Decimal)

Function

Read Write

0 Port A0 Port A0

1 Port B0 Port B0

2 Port C0 Port C0

3Port 0 Configuration

Register

4 Port A1 Port A1

5 Port B1 Port B1

6 Port C1 Port C1

7Port 1 Configuration

Register

8 ~ 23 Reserved Reserved

24 8254 Counter 0 8254 Counter 0



278254 Control

Register

28 Reserved Reserved




32Interrupt Status

RegisterInterrupt Control

Register

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