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PCB Systems Properties Reference

Product Version 14.2January 2002

1999-2002 Cadence Design Systems, Inc. All rights reserved.Printed in the United States of America.

Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA

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1. The publication may be used solely for personal, informational, and noncommercial purposes;2. The publication may not be modified in any way;3. Any copy of the publication or portion thereof must include all original copyright, trademark, and other

proprietary notices and this permission statement; and4. Cadence reserves the right to revoke this authorization at any time, and any such use shall be

discontinued immediately upon written notice from Cadence.

Disclaimer: Information in this publication is subject to change without notice and does not represent acommitment on the part of Cadence. The information contained herein is the proprietary and confidentialinformation of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence’s customerin accordance with, a written agreement between Cadence and its customer. Except as may be explicitly setforth in such agreement, Cadence does not make, and expressly disclaims, any representations or warrantiesas to the completeness, accuracy or usefulness of the information contained in this document. Cadence doesnot warrant that use of such information will not infringe any third party rights, nor does Cadence assume anyliability for damages or costs of any kind that may result from use of such information.

Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth inFAR52.227-14 and DFAR252.227-7013 et seq. or its successor.


Contents

PCB Systems Properties ................................................................................. 11

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Definition of a Property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Concept HDL Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ALLOW_CONNECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ALT_SYMBOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15BIDIRECTIONAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16BLOCK=TRUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16BN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17BODY_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17BODY_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17BUBBLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17BUBBLE_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17CLASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18COMMENT_BODY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18COMP_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18COMP_NAME_SUFFIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19HAS_FIXED_SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19HDL_CONCAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20HDL_LSBTAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20HDL_MSBTAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20HDL_NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20HDL_PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21HDL_POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21HDL_REPLICATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21HDL_SLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21HDL_SYNONYM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22HDL_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22INPUT_LOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23JEDEC_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

January 2002 3 Product Version 14.2


LAST_MODIFIED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23LOCATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23MAKE_BASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23MERGE_NC_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24MERGE_POWER_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25NC_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25NEEDS_NO_SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26NO_BACKANNOTATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26NO_IO_CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27NO_LOAD_CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28OUTPUT_LOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28OUTPUT_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29PACK_IGNORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30PACK_SHORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30PACK_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31PART_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31PHYS_DES_PREFIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31PIN_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32PIN_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33PIN_NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33PN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33POWER_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33POWER_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34REF_DES_PATTERN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34REUSE_ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34REUSE_ALT_MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34REUSE_INSTANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34REUSE_MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35ROOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35ROTATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35SEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36SEC_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36SIG_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36SUBDESIGN_MASTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36



SUBDESIGN_SUFFIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37TECH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38UNKNOWN_LOADING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38VER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38VHDL_CONCAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38VHDL_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39VHDL_SLICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39VLOG_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39XY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Simulation Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40LIBRARYn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41NO_REP_PRIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42MODEL_DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44MODEL_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45PORT_ORDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46REMOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47SDFDELAYTYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50SDFFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50SDFSCALEFACTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51SDFSCALETYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51SIM_BIND_VIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51SIM_MAP_VIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52SPLIT_INST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53SPLIT_INST_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53USEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54VERILOG_LIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54VERILOG_MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55VERILOG_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55VHDL_MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56VHDL_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56VHDL_SCALAR_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56VHDL_VECTOR_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57VHDL_INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57VLOG_NET_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57



Allegro/APD Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58ALIGNED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65ALT_SYMBOLS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65AUTO_GENERATED_TERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66AUTO_RENAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66BOARD_THICKNESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66BOM_IGNORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66BOND_PAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66BUS_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66C_TEMPERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66CLIP_DRAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67CLIP_DRAWING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67CLK_2OUT_MAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67CLK_2OUT_MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67CLK_SKEW_MAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67CLK_SKEW_MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68CLOCK_NET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68COMPONENT_WEIGHT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68CURRENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68DENSE_COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68DFA_DEV_CLASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68DIFFERENTIAL_PAIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69DIFFP_2ND_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69DIFFP_LENGTH_TOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69DRIVER_TERM_VAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69ECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69ECL_TEMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69EDGE_SENS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70ELECTRICAL_CONSTRAINT_SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70EMC_COMP_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70EMC_CRITICAL_IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70EMC_CRITICAL_NET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70EMC_RUN_DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70FAILURE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70FILLET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71FIRST_INCIDENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71



FIX_ALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71FIXED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71FIXED_T_TOLERANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71FP_BOARD_CLEARANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71FP_NOTES_TEXT_BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71FP_REFDES_TEXT_BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72FP_ROOM_NAME_TEXT_BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72HARD_LOCATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72HEAT_SINK_FACTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72IDF_OWNER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72IMPEDANCE_RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73INSERTION_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74J_TEMPERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74LEAD_DIAMETER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74LOAD_TERM_VAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74LOGICAL_PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74MAX_BOND_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74MAX_BVIA_STAGGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75MAX_EXPOSED_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75MAX_FINAL_SETTLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75MAX_OVERSHOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76MAX_PARALLEL (PARALLELISM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76MAX_PEAK_XTALK (MAX_PEAK_CROSSTALK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76MAX_POWER_DISS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77MAX_SSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77MAX_UNDERSHOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77MAX_VIA_COUNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77MAX_XTALK (MAX_CROSSTALK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77MIN_BOND_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77MIN_BVIA_GAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78MIN_BVIA_STAGGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78MIN_FIRST_SWITCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78MIN_HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79MIN_LINE_WIDTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79MIN_NECK_WIDTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79



MIN_NOISE_MARGIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79MIN_SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80NET_PHYSICAL_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80NET_SCHEDULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80NET_SPACING_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80NO_DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80NO_GLOSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80NO_LIN2SHAPE_FAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80NO_PIN_ESCAPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80NO_RAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81NO_RIPUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81NO_ROUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81NO_SHAPE_CONNECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81NO_SWAP_GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81NO_SWAP_GATE_EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81NO_SWAP_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82NO_TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82NO_VIA_CONNECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82PACKAGE_HEIGHT_MAX and PACKAGE_HEIGHT_MIN . . . . . . . . . . . . . . . . . . . . 82PARALLELISM (MAX_PARALLEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82PIN_ESCAPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82PIN_SIGNAL_MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83PINUSE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83PLACE_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83PLATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83PROBE_NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83PROPAGATION_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84PULSE_PARAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85RATED_CURRENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85RATED_MAX_TEMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85RATED_POWER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85RATED_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85RATSNEST_ SCHEDULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85REF_DES_FOR_ASSIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87RELATIVE_PROPAGATION_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87REUSE_ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89



REUSE_INSTANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89REUSE_MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89REUSE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89REUSE_PID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89ROOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90ROOM_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90ROUTE_PRIORITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90ROUTE_TO_SHAPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90SAME_NET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90SCHEMATIC_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91SHIELD_NET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91SHIELD_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91SHORTING_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91SIGNAL_MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91SLOTNAME. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91SOLDER_BALL_HEIGHT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92SPIF_CONSTANTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92SPIF_TURRET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92STUB_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92SUBNET_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92SWAP_GROUP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93SYS_CONFIG_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94T_TEMPERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94TEMPORARY_PACKAGE_SYMBOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94TERMINATOR_PACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94TESTER_GUARDBAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95THERMAL_RELIEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95THICKNESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95TIMING_DELAY_OVERRIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95TOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95TOPOLOGY TEMPLATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95TOPOLOGY_TEMPLATE_REVISION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96TOTAL_ETCH_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96TS_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96UNFIXED_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96VALUE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97



VIA_LIST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97VOLT_TEMP_MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97VOLTAGE_LAYER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97VOLTAGE_SOURCE_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97WEIGHT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98WIRE_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98XTALK_ACTIVE_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98XTALK_IGNORE_ NETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98XTALK_SENSITIVE_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Constraint Manager Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99CLK_2OUT_MAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100CLK_2OUT_MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100CLK_SKEW_MAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100CLK_SKEW_MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100CLOCK_NET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100DIFFERENTIAL_PAIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101MAX_SSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101MAX_UNDERSHOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101MAX_VIA_COUNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101MAX_XTALK (MAX_CROSSTALK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101MIN_FIRST_SWITCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101MIN_HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102MIN_NOISE_MARGIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102MIN_SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102NET_SCHEDULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102PROPAGATION_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103PULSE_PARAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104RATSNEST_ SCHEDULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104RELATIVE_PROPAGATION_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105STUB_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107TIMING_DELAY_OVERRIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107TOTAL_ETCH_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107XTALK_ACTIVE_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108XTALK_IGNORE_ NETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108XTALK_SENSITIVE_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108



PCB Systems Properties

Overview

Properties serve important and varied functions. They are used to convey a wide range ofinformation about the design and to control analysis processes. A property is a name / valuepair that can be attached to certain objects in a design to convey almost any information.

A number of predefined properties are used by tools in the PCB design flow to recordinformation needed by the Timing Verifier, the Simulator, and the Packager. Other propertiescan be defined by the user to convey information to design programs, or to be passed throughto other systems (such as simulators, physical design systems, and so on).

Properties also provide a mechanism for adding physical information to schematics (whichrepresent only a logical design), that can be passed on to the Packager and other physicaldesign systems.

A property consists of a name by which the property is known (property name) and anassociated value (property value). Properties can be attached to certain objects on anyschematic in Concept HDL. Property name/value pairs can be attached to symbols, signals,and pins. Properties can also be attached to an entire schematic by attaching them to aDEFINE body or a page border.

Definition of a Property

A property is a name / value pair assigned to a particular object. For Allegro/APD, theproperty name is an identifier—that is, a string of not more than 32 characters that includesletters, digits, and underscores ( _ ) and starts with a letter. Some examples of propertynames are:

SIZEROUTE_PRIORITYMY_PROP_NAMETHE_40TH_NAMESATURDAY1027COST_OF_PARTPIN_NUMBERPART_NAME


PCB Systems Properties ReferencePCB Systems Properties

Notice that the underscore is used instead of a space. Spaces are not allowed in propertynames because a space delimits a property name from a property value.

A property value is associated with each property name. The property value is a string of upto 255 printable characters for Concept, and 1023 printable characters for Allegro/APD.Allegro/APD allows all printable characters except the single quote (’) and the exclamationpoint (!). Property values can be empty.

Here are some representative property values:

125oct82 10:31:46.03(SIZE + 4) / 5 + 35 MOD AThis is a long property valueValue with chars @#$%*()~}{[]><

A property always consists of the property name and its associated value. You can attach aproperty to a component, symbol, pin, or a net. The term component refers to the logicalcharacteristics of a library part. In the earlier releases of Concept, it was called body.

On the other hand, a symbol is the symbolic representation of a library component that youadd to your design. This drawing defines the shape, pins, and general properties of the librarycomponent.

Concept HDL Properties

Property Attach To Tools that use this property

ALLOW_CONNECT Component, Symbol,Net, Pin

ERC-DX, CheckPlus

ALT_SYMBOLS Component Packager XL, CheckPlus, Allegro

BIDIRECTIONAL Pin ERC-DX, CheckPlus

BLOCK=TRUE Symbol Concept HDL

BN Pin Concept HDL

BODY_NAME Component Concept HDL, Packager XL

BODY_TYPE Symbols Concept HDL

BUBBLED Component Concept HDL



BUBBLE_GROUP Component Concept HDL

CLASS Component Concept HDL, Packager XL, Allegro

COMMENT_BODY Component Concept HDL

COMP_NAME Component Packager XL

COMP_NAME_SUFFIX Component Packager XL

FAMILY Component Packager XL

GROUP Section, Component Packager XL, Allegro

HAS_FIXED_SIZE Component Concept HDL

HDL_CONCAT Symbol Concept HDL

HDL_LSBTAP Symbol Concept HDL

HDL_MSBTAP Symbol Concept HDL

HDL_NOT Symbol Concept HDL

HDL_PORT Symbol Concept HDL

HDL_POWER Component Concept HDL

HDL_REPLICATE Symbol Concept HDL

HDL_SLASH Symbol Concept HDL

HDL_SYNONYM Symbol Concept HDL

HDL_TAP Symbol Concept HDL

INPUT_LOAD Physical pin ERC-DX, CheckPlus

JEDEC_TYPE Component Packager XL, CheckPlus, Allegro

LAST_MODIFIED DRAWING symbol Concept HDL

LOCATION Component Concept HDL, Packager XL, Allegro,Variant Editor

MAKE_BASE Net Concept HDL, Packager XL

MERGE_NC_PINS Component, Symbol Packager XL

MERGE_POWER_PINS Component, Symbol Packager XL

NC_PINS Component, Symbol Packager XL

NEEDS_NO_SIZE Component ERC-DX, CheckPlus




NO_BACKANNOTATE Component Packager XL

NO_IO_CHECK Component, Pin ERC-DX, CheckPlus

NO_LOAD_CHECK Component, Pin ERC-DX, CheckPlus

OUTPUT_LOAD Pin ERC-DX, CheckPlus

OUTPUT_TYPE Pin Packager XL, ERC-DX

PACK_IGNORE Component Packager XL

PACK_SHORT Pin Packager XL

PACK_TYPE Component Concept HDL, Packager XL

PART_NAME Component Concept HDL, Packager XL

PATH Component Concept HDL

PHYS_DES_PREFIX Component Packager XL

PIN_GROUP In chips.prt file Packager XL

PIN_NAME Symbol Concept HDL

PIN_NUMBER Pin Packager XL

PN Pin Concept HDL

POWER_GROUP Pin Packager XL

POWER_PINS Pin Concept HDL, Packager XL

REF_DES_PATTERN Component

REUSE_ID Component, Symbol

REUSE_ALT_MODULE Component Packager XL, Allegro

REUSE_INSTANCE Component Packager XL, Allegro

REUSE_MODULE Component Packager XL, Allegro

ROOM Component Packager XL, Allegro

ROTATE Component Packager XL

SEC Component Concept HDL, Packager XL

SEC_TYPE Component Concept HDL

SIG_NAME Net Concept HDL




ALLOW_CONNECT

Allows different types of outputs to be connected without producing errors whenOUTPUT_TYPE properties are checked. You can use the ALLOW_CONNECT property on alibrary component or in a logical design. Value is TRUE.

If the ALLOW_CONNECT property is attached to a net, it applies to all output pins on the net.When attached to a symbol, it applies to all output pins on the symbol. When attached to apin, it applies only to the pin to which the property is attached.

ALT_SYMBOLS

The ALT_SYMBOLS property lets you specify a list of alternate package symbol names thatcan be used to substitute the primary package symbol during interactive placement. Thesesymbols can be accessed using the ALT_SYMBOLS property to switch to a different symbol(one symbol at a time) through the entire list.

Syntax

ALT_SYMBOLS =([TOP:] symbol_name [,symbols_name...][;BOTTOM: symbol_name][,symbol_name...])

SIZE Component Concept HDL

SUBDESIGN_MASTER Component, Symbol Packager XL

SUBDESIGN_SUFFIX Symbol Packager XL

TECH Component CheckPlus

UNKNOWN_LOADING Component, Pin ERC-DX, CheckPlus

VER Component Packager XL

VHDL_CONCAT Symbol Concept HDL

VHDL_MODE Pin, Net Concept HDL

VHDL_SLICE Symbol Concept HDL

VLOG_MODE Pin, Net Concept HDL

XY Component Concept HDL




Note: The open and close parentheses () are mandatory. If you do not add theseparentheses, the following error would be generated:

Error in ALT_SYMBOLS property for device <device_name>:’Encountered an errorwhile parsing alternate symbol.’

Examples

■ ALT_SYMBOLS = (TOP:SOIC14, DIP14_3; BOTTOM:DIP14_3)

In this example, you can place the component on the TOP layer using symbols SOIC 14and DIP 14_3, whereas to place a component on the BOTTOM layer, you can only usethe symbol DIP14_3.

■ ALT_SYMBOLS = (SOIC14, DIP14_3)

In this example, you can use SOIC14 or DIP14_3 to place components on either TOP orBOTTOM layers.

■ ALT_SYMBOLS = (SOIC14)

In this example, you can use only SOIC14 to place component on either TOP orBOTTOM layers.

The ALT_SYMBOLS property has the following attributes defined in the defaultcdsprop.paf file:

inherit(cell), permit(cell), uppercasevalue

This property will now be inherited by all components of a hierarchical block of which theyform a part.

The ALT_SYMBOLS property and its value(s) will always appear in uppercase in thepstxprt.dat and pstchip.dat files irrespective of the case you specify on theschematic instance, part table file (.ptf) or chips.prt files.

BIDIRECTIONAL

Indicates that a pin is both an input and an output pin. A pin is not considered bidirectionalunless this property is attached. This property is stored in pin section of the chips file.

BLOCK=TRUE

Attached to the origin of a block. This property distinguishes a symbol as being editable bythe block command set (badd, bpadd, and so on). Only symbols generated from blockcommands can be edited by block commands.



BN

Attached to the pin of a tap symbol. The bit number property specifies the bit on a bus thatyou want to tap. The TAP symbol is attached between the bus and the net to be tapped offthe bus. Value is INTEGER or a range (for example, <1..0>).

BODY_NAME

Specified in the chips.prt file and defines the logical cell name associated with the definedphysical part.

BODY_TYPE

The BODY_TYPE property specifies certain special symbols. It can be given the followingvalues:

BUBBLED

Attached automatically to bubbled pins to indicate that only low-asserted signals may beconnected to them.

Note: This property should never be entered, assigned, or attached by the user.

BUBBLE_GROUP

Attached to the origin of a component. This property is used on the symbol drawing to indicatewhich pins must bubble simultaneously due to their logical association with each other. EachBUBBLE_GROUP property defines one bubble group.

COMMENT The symbol is a comment and to be totally ignored. This propertyreplaces the previous COMMENT_BODY property.

FLAG_BODY The symbol is used to indicate an I/O signal. Used by HDL Direct toprocess module interface signals.

PLUMBING The symbol is a plumbing symbol. Standard plumbing symbols areMERGER, NOT, SYNONYM, and so on. These are used to ’plumb’ signals inthe schematic.



CLASS

Defines a logical grouping for the component. This property is stored in body section of thechips file, and is passed in the pstchip file to Allegro.

COMMENT_BODY

Attached to components that have no electrical meaning. Concept HDL ignores componentswith this property, omitting them from the netlist.

COMP_NAME

If you add the COMP_NAME property to a schematic instance that has component definitionproperties, the value of the COMP_NAME is used as the name for the alternate physical part.

If you do not specify the COMP_NAME property, the values of the component definitionproperties are appended to the physical part name. This is the default naming mechanism.

Syntax

COMP_NAME = <value>

ExampleCOMP_NAME = RES100

COMP_NAME_SUFFIX

If you add the COMP_NAME_SUFFIX property to a schematic instance that has componentdefinition properties, the value of COMP_NAME_SUFFIX is added to the end of the physicalpart name.

If you do not specify the COMP_NAME_SUFFIX property, the values of the componentdefinition properties are appended to the physical part name. This is the default namingmechanism.

If the part name is 74LS00 and you add a COMP_NAME_SUFFIX of “VERSION 2”, the newname will be “74LS00-VERSION 2.”



Syntax

COMP_NAME_SUFFIX = <value>

ExampleCOMP_NAME_SUFFIX = 100

If this property is assigned to a schematic instance of the physical part type 74LS00, thisschematic instance would be named as 74LS00-100 during packaging.

FAMILY

The FAMILY property specifies the logic family for the part.

ExampleFamily=‘74LSTTL’;

GROUP

The GROUP property identifies schematic instances that are to be packaged together. Thisproperty lets you control packaging assignments without having to keep track of specificreference designators and sections.

See GROUP on page 72 in the Allegro Properties section for how this property value is usedin Allegro.

HAS_FIXED_SIZE

Attached to the nonvectored version of a component when one version of the component canbe sized. This property passes size information to the simulation primitives to define the finalsize of the component. The HAS_FIXED_SIZE property is a required property and should notbe changed.

The HAS_FIXED_SIZE property identifies those symbols that have a fixed size. Thesesymbols should not be given a SIZE property. The HAS_FIXED_SIZE property has thefollowing functions:

■ Specifies that the symbol it attaches to has a fixed known size (specified in the propertyvalue).

■ Causes an error message if a SIZE property is found.



Many of the symbols in the standard libraries have this property attached to them. It is usedfor versions of physical parts that display all sections. The vectored version of the symboltypically represents a one bit section of the part. The second symbol version represents allsections of the part. If the part has, for example, four sections, then the second symbolversion will be given a HAS_FIXED_SIZE="4" property to specify that it represents four bits.This is important since the models (for the Timing Verifier and Logic Simulator) are modeledas one-bit sections with the SIZE property specifying the actual number of bits for each instance. The HAS_FIXED_SIZE property causes a “default” 8 property to be attached tosupport the models. The presence of a user assigned SIZE property on these symbols isalways an error since none of the pins of the symbol or the definition of the symbol use theSIZE property.

The HAS_FIXED_SIZE property can be attached as a default symbol property (attached tothe ORIGIN) or it can also be attached to the symbol when used in a schematic.

HDL_CONCAT

Specifies to the netlister that the component should be treated as a concatenation or mergesymbol. These symbols allow you to merge smaller width signals into a bussed signal or takea bussed signal and break it into smaller width signals.

HDL_LSBTAP

Specifies to the netlister that the component should be treated as a tap symbol that breaksout the lower 8 bits of the bussed signal.

HDL_MSBTAP

Specifies to the netlister that the component should be treated as a tap symbol that breaksout the upper 8 bits of the bussed signal.

HDL_NOT

When you attach the HDL_NOT property to a symbol, the symbol is converted to a NOTsymbol.



HDL_PORT

Specifies to the netlister that the component should be treated as a port symbol, indicatingthe signal is an interface to the upper level of hierarchy.

HDL_POWER

Add the HDL_POWER property on a symbol that you want to use as a power or ground symbol.Concept HDL reads this property to identify power and ground symbols on the schematic.

If an unnamed signal is connected to an instance that has the HDL_POWER property,Concept HDL treats the signal as a global signal and assigns it the same name as the valueof the HDL_POWER property. For example, if an unnamed signal is connected to an instancethat has the HDL_POWER=GND property, Concept HDL assigns the GND\G name to the signal.If you want to assign some other name to the signal, you must name the signal.

Concept HDL also assigns the SIG_NAME=<HDL_POWER property value>\G propertyon the pin to which the unnamed signal is connected. From Concept HDL 14.2, you cannotmodify the SIG_NAME=<HDL_POWER property value>\G property automaticallyassigned on pins.

HDL_REPLICATE

Add the HDL_REPLICATE property on an instance that you want to use to replicate signals.

You must add the HDL_REPLICATE property only on instances that have two pins. The inputpin name must be INPUT and output pin name must be OUTPUT<SIZE-1..0>.

You must also add the SIZE property on the instance on which you have added theHDL_REPLICATE property. The property SIZE on the instance determines the number oftimes the signal connected to the pin INPUT has to be replicated.

The instance that has the HDL_REPLICATE property works like the REPLICATE symbol inthe standard library.

HDL_SLASH

You can convert a symbol to a SLASH symbol by attaching the HDL_SLASH property to thesymbol.



HDL_SYNONYM

Add the HDL_SYNONYM property on a two pin device that you want to use to specify anothername for a signal. The instance that has the HDL_SYNONYM property works like theSYNONYM symbol in the standard library.

HDL_TAP

Specifies to the netlister that the component should be treated as a tap symbol that breaksout a set of bits indicated by the value of the BN property.

If a tapped signal is unnamed, Concept HDL assigns it the same base name as the name ofthe signal that is being tapped, along with the bits specified as the value of the BN propertyon the tap symbol.

In the above example, Concept HDL automatically assigns the name INT<2> to the tappedsignal, where INT is the base name of the signal that is being tapped and 2 is the value ofthe BN property on the tap symbol. Move the mouse pointer over the signal to view the signalname. If you want to assign some other name to the signal, you must name the signal.

Concept HDL also automatically assigns the SIG_NAME=base name of signal beingtapped<value of BN property on tap symbol> property on the output pin of thetap symbol. In the above example, Concept HDL assigns the SIG_NAME=INT<2> propertyto the output pin of the tap symbol. From Concept HDL 14.2, you cannot modify theSIG_NAME=base name of signal being tapped<value of BN propertyon tap symbol> property automatically assigned on the output pin of tap symbols.



INPUT_LOAD

Specified in the chips.prt file and indicates the load a pin presents when it is used as aninput or when not driving the signal. An input pin should always have the INPUT_LOADproperty. An output pin should carry an INPUT_LOAD property whenever that pin can alsoplace an input load on the signal—for example, a tri-state or an open collector output alsopresents a load when not driving the signal. This load must be considered when calculatingthe load of the entire net.

JEDEC_TYPE

Specifies the footprint to be used in the Allegro design for the component in the logical netlist.This property is typically placed in the chips file body section. Its value can be overridden byan entry in a physical part table. This is normally the case when describing components likeresistors and capacitors that have a large number of physical parts all sharing the samelogical part

LAST_MODIFIED

Attached to the DRAWING symbol. This property signifies the last modification date and timewhen the drawing was saved to the hard disk.

LOCATION

Lets you control packaging by assigning a particular physical part to a logical component ona design. Value is any alphanumeric string. Use Text – Property to attach LOCATIONproperties to components on a drawing.

When you use the LOCATION property and Component – Section to make physical partassignments, Packager XL and the physical design system do not override the assignments.If you include a LOCATION property after packaging a design, you must repackage the designfor Packager XL to use the specified information.

MAKE_BASE

When two signals are aliased or synonymed, Concept HDL selects one of the signal namesas the base signal. The name of the base signal becomes the name of correspondingphysical net in Allegro. You may want the name of a particular aliased or synonymed signalto be passed to Allegro as the physical net name.



Add the MAKE_BASE=TRUE property on a signal to declare the name of the signal as the basesignal name for all its aliases or synonyms. You can also suffix \BASE to a signal name todeclare it as the base signal name.

MERGE_NC_PINS

You use the MERGE_NC_PINS property when you have the NC_PINS property specified inyour chips.prt or ptf file and you need to add a few more NC_PINS in a PPT in the ptf fileor in the schematic instance.

Note: You can define only one MERGE_NC_PINS or MERGE_POWER_PINS property at anylevel: schematic instance, Physical Part Table (ptf) file or chips.prt files.

Syntax

MERGE_NC_PINS = ( pin#,pin#,pin#...)

Examples

Given the following property assignments:

The primitive for the schematic instance in the pstchip.dat file will have NC_PINS =‘(1A,1B,1C,1D,1E,1F,1G)’.

The MERGE_NC_PINS property on the PPT is applied to the NC_PINS property on thechips.prt creating an intermediate NC_PINS= ‘(1A,1B,1C,1D,1E)’.

The MERGE_NC_PINS on the schematic instance is applied to the intermediate NC_PINSfrom the previous step creating NC_PINS = ‘(1A,1B,1C,1D,1E,1F,1G)’.

The MERGE_NC_PINS property has the following attributes in the default cdsprop.paf file:


This property will now be inherited by all components of the hierarchical block of which theyform a part.

The MERGE_NC_PINS property and its value(s) will always appear in uppercase in thepstxprt.dat and pstchip.dat files irrespective of the case you specify on the schematicinstance, ptf file, or chips.prt files.

...in the schematic: ...in the ptf file: ...in the chips.prt:

MERGE_NC_PINS='(1F, 1G)' MERGE_NC_PINS='(1D,1E)' NC_PINS='(1A,1B,1C)'



MERGE_POWER_PINS

You may require to add a few pins to an existing POWER_PINS or NC_PINS property. Addingthe POWER_PINS or NC_PINS property at a higher level re-specifies the entire property.Currently, there is no way to add additional pins to an existing NC_PINS property. Instead twonew properties, MERGE_POWER_PINS and MERGE_NC_PINS, provide this capability.

MERGE_NC_PINS='(1F, 1G)' MERGE_NC_PINS='(1D,1E)' NC_PINS='(1A,1B,1C)'

Use MERGE_POWER_PINS when you want to add additional power pins rather than overridethe existing POWER_PINS definition as would be the case if you used the POWER_PINSproperty. Refer to the POWER_PINS property for more information.

Syntax

MERGE_POWER_PINS = (<supply>:pin# [,pin#...];[<supply>:pin#[,pin#...])

Example

Given the following assignments:

The MERGE_POWER_PINS property has the following attributes defined in the defaultcdsprop.paf file:


This property will now be inherited by all components of a hierarchical block of which theyform a part.

The MERGE_POWER_PINS property and its value(s) will always appear in uppercase in thepstxprt.dat and pstchip.dat files irrespective of the case you specify on theschematic instance, ptf file, or chips_prt files.

NC_PINS

The NC_PINS property specifies the assignment of pins which are present on a physicalpackage but do not have any logical connections. These pins do not play any role in thelogical simulation but need to be taken into consideration during board layout.

The NC_PINS property has the following syntax:

...in the ptf file: ...in the chips.prt:

MERGE_POWER_PINS=(VCC:15); POWER_PINS=(VCC:14; GND:7)



NC_PINS=’(pin list,pin list, ...)’;

where pin list can be a single pin or a range of pins or any combination of the two. Therange description can include alphanumeric pin designators and can be in increasing ordecreasing order.

NEEDS_NO_SIZE

The NEEDS_NO_SIZE property is used to identify those symbols that do not need SIZEproperty. It is an error to attach a SIZE property to these symbols. The NEEDS_NO_SIZEproperty has the following functions

■ Specifies that the symbol it attaches to does not need a SIZE property

■ Causes an error message to be produced if a SIZE property is found.

Many of the symbols in the standard libraries have this property attached to them. Mostnotable are the NOT and MERGE symbols. These symbols automatically conform to the widthsof the signals they are attached to. The presence of the SIZE property on these symbols isalways an error since none of the pins of the symbol or the definition of the symbol use theSIZE property.

The NEEDS_NO_SIZE property can be attached as a default symbol property or it can alsobe attached to the symbol when used in a schematic.

NO_BACKANNOTATE

You use this property when you do not want properties updated in the schematic. Forexample, to disable the backannotation of all properties on an instance, specify the followingproperty in the schematic:

NO_BACKANNOTATE = ALL

Note: The NO_BACKANNOTATE property is specified in the schematic.

Using NO_BACKANNOTATE

You can use this property to prevent the backannotation of the master view of a subdesign. Ifyou want to preserve the hard SEC and hard PN properties in instances of a reused block,you must place the NO_BACKANNOTATE property on those instances in the schematic.

To disable backannotation on an instance:



➤ Add the NO_BACKANNOTATE property to the instance. This will disable backannotationon the instance and on each of its pins.

The NO_BACKANNOTATE property preserves the property value on the instance anddiscards the backannotation value.

Syntax

NO_BACKANNOTATE = property [property property ...]

Example

To prevent the reassignment of LOCATION for a particular instance, you would specify theNO_BACKANNOTATE property as NO_BACKANNOTATE=LOCATION.

To specify multiple properties:

➤ List them separated by spaces:

NO_BACKANNOTATE=COMPONENT_WEIGHT LOCATION SEC

Note: You can add the NO_BACKANNOTATE property on a block. The NO_BACKANNOTATEproperty added on a block applies to its child blocks too.

If you add the NO_BACKANNOTATE = ALL property on a block and then package the design,Packager-XL will display an info message stating that the NO_BACKANNOTATE = ALLproperty is set for the block and Packager-XL will not backannotate it. This message isrecorded in the pxl.log file.

If you add the NO_BACKANNOTATE = ALL property on a read-only block and save it inConcept HDL, it generates an error stating that write permissions do not exist for concernedpage. Concept HDL skips changes to such blocks.

NO_IO_CHECK

Suppresses input and output checks on a particular component, pin, or net and takes thesevalues:

The NO_IO_CHECK property can be attached to library components or in your drawings.

LOW Suppresses the “0 state” I/O check.

HIGH Suppresses the “1 state” I/O check.

BOTH or TRUE Suppresses both the “0 state” and the “1 state” I/O check.



Attaching the property to a net applies the property to all pins on the net. When used as acomponent property, it applies to all pins on the component. As a pin property, it applies onlyto that pin.

NO_LOAD_CHECK

Suppresses device loading calculations on a pin-by-pin basis and takes these values:

The NO_LOAD_CHECK property can be attached to library components or in your drawings.When used as a component property, it applies to all pins of the component. As a pin property,it applies only to that pin.

OUTPUT_LOAD

Specifies the load presented by a pin when used as an output pin. If a pin does not have theOUTPUT_LOAD property, it is assumed to be an input pin. When an output pin is bi-directionalor tri-state, both the INPUT_LOAD and OUTPUT_LOAD properties must be attached to the pin.

LOW Suppresses the “0 state” I/O check.

HIGH Suppresses the “1 state” I/O check.

BOTH or TRUE Suppresses both the “0 state” and the “1 state” I/O check.



OUTPUT_TYPE

The OUTPUT_TYPE property is added to the output pins of open-collector, open-emitter, andtri-state devices. The property serves the following purposes:

■ Allows two or more output pins to be tied together

■ Specifies the type of output so that only compatible outputs can be connected together(an OC output cannot be tied to a TS output)

■ The second value of the property specifies the logic function that is created when two ormore output pins are tied together

The OUTPUT_TYPE property provides information that Packager XL needs.

Each output pin that can be connected to other output pins must have an OUTPUT_TYPEproperty. The property value specifies the pin type and also the logic function created by tyingthe outputs together. The syntax of OUTPUT_TYPE property is

OUTPUT_TYPE=’(output type,logic function)’;

The output type variable can be open collector, open emitter, or tri-state(TS). The logic function variable can be AND, OR, or tri-state (TS). You need tomake sure that there is no space after the comma in the property value.

You can combine the output type and logic functions as follows:

Tri-state pins need both INPUT_LOAD and OUTPUT_LOAD properties. When a pin is in tri-state mode, the tri-state loading is specified as the INPUT_LOAD.

OUTPUT_TYPE=’(OC,AND)’ Open Collector, AND logic function

OUTPUT_TYPE=(OE,OR) Open Emitter, OR logic function

OUTPUT_TYPE= (TS,TS) Tri-state, tri-state logic function



PACK_IGNORE

The PACK_IGNORE property identifies the parts that will be ignored when packaging thedesign. The PACK_IGNORE property can only be specified in the schematic.

The PACK_IGNORE property excludes the schematic instances from being packaged.

■ If the schematic instance is a primitive, it is ignored and therefore not packaged. Thenetlist output from Packager XL will not reference this part. Nets connected to thisschematic instance are left unconnected.

■ If the instance is a hierarchical block, then the underlying hierarchy is removed.

Use of the PACK_IGNORE property may result in unconnected nets.

Syntax

PACK_IGNORE = <value>

ExamplePACK_IGNORE = TRUE;

Note: Packager XL does not look at the value of the PACK_IGNORE property. If the propertyis present, the instance is ignored.

PACK_SHORT

The PACK_SHORT property specifies the shorting of pins of a part.

The PACK_SHORT property can be specified in the schematic.

Multiple groups of pins, each group having two or more pins, can be shorted. You must uselogical schematic pin names with this property.

You should use the PACK_SHORT property in conjunction with the PACK_IGNORE property tospecify shorting for nets attached to the instance.

Syntax

PACK_SHORT=(<group1>)(<group2>)[<group3>]

where <group> indicates (logicPin1, logicPin2 ... [logicPinN])



Example

Consider the assignment, PACK_SHORT = (A1, B1, Y1) (A2, B2) shorts together:

■ The nets attached to logic pins A1, B1, and Y1.

■ The nets attached to pins A2 and B2.

PACK_TYPE

Specifies the type of package used for a part. Packager XL uses the PACK_TYPE property todetermine which physical part entry in the chips.prt file to use when selecting physicalparts.

PART_NAME

The PART_NAME property is used to specify the name of a primitive component. WhenPackager XL chooses a primitive component it first looks at the name of the component.Normally, this name is just the name of the primitive component. There are times, however,when it is desired to have the primitive component name be different from the logicalcomponent name.

For example, the LSTTL library components are called LS00, LS01, LS02, and so on. Eachpart, however, is known in the Compiler expansion file as 74LS00, 74LS01, and so on. sincethis is a more explicit name. The ‘74’ that is left off the logical component name makes thename easier to type. Of course, giving the LS00 the PART_NAME 74LS74 is counter-productive. The PART_NAME properties are found in the body section of the chips file for thecomponent.

PATH

Automatically attached to each component in a drawing as it is created to uniquely identify it.Values are I1, I2, I3. These are unique across a page of a design.

If you modify the value of the PATH property on a component, do not use \ (back slash) in thevalue of the PATH property.

PHYS_DES_PREFIX

Specifies the reference designator prefix for the default Packager XL naming pattern.



The PHYS_DES_PREFIX property lets you specify the reference designator prefix for thedefault Packager-XL naming pattern.

You can specify the PHYS_DES_PREFIX property in the chips file, the ptf file or in theschematic.

Using PHYS_DES_PREFIX

PHYS_DES_PREFIX is typically used to identify classes of parts such as resistors (R),capacitors (C) and inductors (L).

By default, Packager-XL searches for the PHYS_DES_PREFIX property when assigning areference designator value. If the property is not found it assumes the value ofPHYS_DES_PREFIX property as ‘U’.

You can use the REF_DES_PATTERN directive or property to modify the default namingscheme.

Syntax

PHYS_DES_PREFIX = <value>

ExamplePHYS_DES_PREFIX = R

PIN_GROUP

You use the PIN_GROUP property to identify the pins on a part that can be swapped.

You can specify the PIN_GROUP property in the chips file.

Using PIN_GROUP

A group of pins are swappable if they are logically equivalent and belong to the same section.If you swap two nets between two pins within a swappable group (two or more logical pinswith the same PIN_GROUP value), you do not alter the logical function of the circuit is notbeing altered.

Syntax

PIN_GROUP=<value>



ExamplePIN_GROUP = A

A common example of pin swapping occurs for the inputs of a NAND gate. The two input pinsare physically equivalent in terms of logical function, loading, and propagation delay frominput to output. If you swap the nets to the input pins, the logic of the circuit does not change.

PIN_NAME

Used in a symbol drawing, this property defines the pin’s name. Value is STRING.

PIN_NUMBER

The PIN_NUMBER property provides the logical to physical mapping for the pin. Each pin ofevery library component (and all package outlines of a component) must have aPIN_NUMBER property. Packager XL gets the following information from the PIN_NUMBERproperty:

■ Physical pin number of the pin

■ Number of sections of the component in a package

■ Pin numbers for each section

There must be one pin number for each pin in each section. For example, if a package hasfour sections (as in LS00), there must be four pin numbers associated for each pin. Thepackager prints an error message when a pin is found without a PIN_NUMBER property orwithout the correct number of pins per section.

PN

Assigns a physical pin number (specified in the chips.prt file) to a logical pin in theschematic. Used to perform manual pin swaps on physical parts. The Component – SwapPins menu command in Concept HDL assigns this property.

POWER_GROUP

POWER_GROUP is a special property that modifies the POWER_PINS property at any givenlevel. Multiple occurrences of POWER_GROUP are allowed in the chips.prt file and theschematic instance. Only a single occurrence is allowed in the PPT. At each level of physical



part processing (chips.prt, ptf and schematic instance), the POWER_PINS property isderived and the POWER_GROUP property is applied to the resulting POWER_PINS.

POWER_PINS

Specifies power and ground pins that exist on the physical part but are not shown on theschematic symbol. Typically, the POWER_PINS property is specified in the chips file, but youcan also specify it in the ptf file or in the schematic.

REF_DES_PATTERN

The REF_DES_PATTERN property lets you specify a pattern to use when assigning areference designator to a particular part type or instance. You can specify theREF_DES_PATTERN property in the chips file, the ptf file and the schematic.

REUSE_ID

This property is for Cadence internal use only.

REUSE_ALT_MODULE

You can assign the REUSE_ALT_MODULE property to use multiple physical modules for thesame logical module. For example, assume that you have a logical module namedbase_level and you have three physical modules base_level1, base_level2, andbase_level3 corresponding to the logical module. Now, by selectingREUSE_ALT_MODULE= base_level3, you can put the base_level3 module on the board.

Note: The REUSE_ALT_MODULE property is not supported by Allegro in the PSD 14.2release.

REUSE_INSTANCE

The REUSE_INSTANCE property is assigned while using modules. If you do not assign theREUSE_INSTANCE property on the reuse block when instantiating it in Concept HDL,Packager-XL uses <reuse_block_name>_<subdesign_suffix> to generate aunique value for REUSE_INSTANCE. Allegro uses the REUSE_INSTANCE property todifferentiate between multiple instances of a reuse module.



You can assign the SUBDESIGN_SUFFIX property on a reused block in Concept HDL tospecify the suffix to be added to all reference designators in a subdesign module. If you havenot specified the SUBDESIGN_SUFFIX property on the reused block in Concept HDL,Packager-XL will generate a unique number for the subdesign and use it as theSUBDESIGN_SUFFIX property. This default number starts from 1 and increments by 1 forsubsequent blocks.

Note: Unlike other schematic properties, the REUSE_INSTANCE property defined on thetopmost block wins in case of nested blocks.

REUSE_MODULE

By default, Packager-XL uses the REUSE_NAME property to name modules. You can assignthe REUSE_MODULE property to assign a custom name to a module. You need theREUSE_MODULE property when you are creating multiple modules for the same design witheach module having a different layout. In such cases, you can use the REUSE_MODULEproperty to assign different names to different instances of modules. When you are placingmodules on a board, you can use the REUSE_MODULE property to choose the appropriatemodule in the board.

The order of precedence for determining the .mdd filename that Allegro looks for is:

■ REUSE_MODULE

■ REUSE_NAME (default)

The REUSE_NAME property is always assigned by Packager-XL and is always equal to thelogical design name in Concept HDL. You cannot change this property. If you want to assigna different module name for the .mdd file than the logical design name in Concept HDL, usethe REUSE_MODULE property.

ROOM

Controls the placement of parts in Allegro/APD. Packager XL tries to package togethercomponents that have the same ROOM value.

ROTATE

This property indicates the rotation of an instance of the component. This property isassigned, when you select the Edit – Rotate menu command in Concept HDL.



SEC

Assigns a logical component to a particular section within a physical part.The Component – Section menu command in Concept HDL assigns this property.

SEC_TYPE

Identifies the package type in the chips.prt file used to get pin number assignments whensectioning a part. The Component – Section menu command in Concept HDL assigns thisproperty.

SIG_NAME

Attached to a signal. Concept HDL interprets all signals with the same name as being thesame signal and uses this property to connect signals across multipage drawings.

SIG_NAME values must be legal HDL signal names. These name restrictions apply:

■ Names must start with a letter.

■ Names must use only letters, numbers, and underscores. You cannot include spaces orother characters in names.

■ Names cannot be VHDL and Verilog keywords.

■ HDL Direct is not case sensitive; HDL Direct treats two names that differ only inuppercase or lowercase as the same name.

For more information on HDL Direct naming conventions, see the HDL Direct User Guide.

SIZE

Attached to a body. Used to specify the width of pin names, signal names, and to define sizeexpansion. Using the SIZE property can greatly minimize the number of parts andinterconnections.

SUBDESIGN_MASTER

The SUBDESIGN_MASTER property identifies which instance in a top level design will be usedby the GEN_SUBDESIGN directive to generate subdesign state files.

The SUBDESIGN_MASTER property is specified in the schematic.



If the top-level design includes multiple instances of a subdesign, you may specify a particularinstance, whose packaging is most optimal, as the source for the subdesign state file.

To specify a particular instance with optimal packaging, attach the SUBDESIGN_MASTERproperty to a particular instance of the subdesign.

If you do not specify this property, the first instance of the subdesign to be parsed by theCompiler is used as the default SUBDESIGN_MASTER.

Note: Packager XL does not look at the value of the SUBDESIGN_MASTER property. If theproperty is present, the instance is used to generate the subdesign state files.

Syntax

SUBDESIGN_MASTER = <value>

ExampleSUBDESIGN_MASTER = TRUE

SUBDESIGN_SUFFIX

The SUBDESIGN_SUFFIX property specifies the suffix to be added to all referencedesignators in a subdesign module. The SUBDESIGN_SUFFIX property is specified in theschematic.

To create unique reference designators within instances of subdesigns, append a suffix to thereference designator found in the subdesign master.

For example, a reference designator of U1 in a subdesign master could become U1_1 for oneoccurrence of that subdesign. The SUBDESIGN_SUFFIX property lets you control theassignment of suffixes to subdesign instances and facilitates the association of packages inthe board layout with the schematic design.

Note: Each SUBDESIGN_SUFFIX must be unique across all subdesign modules. That is,you cannot have SUBDESIGN_SUFFIX = 1 on more than one subdesign even when thesubdesigns themselves are different. This minimizes the possibility of reference designatorcollisions. If there are duplicates, a warning is generated and one of the duplicates is ignored.

Syntax

SUBDESIGN_SUFFIX = <string>



Example

To assign a suffix 3 to instance 1P of subdesign SUB1, add the following property to 1P onthe schematic:

SUBDESIGN_SUFFIX 3

This causes all reference designators in instance 1P of subdesign SUB1 to have a suffix 3attached to them.

TECH

The TECH property is used to select the correct interface element for the mixed signal (Digitaland Analog circuits) simulation. Some examples are given below:

TECH= ’74LS’;

TECH= ’74HC’;

TECH= ’100K’;

UNKNOWN_LOADING

Turns off load checking. The UNKNOWN_LOADING property can be attached to librarycomponents or in your drawings. When used as a component property, it applies to all pinsof the component. As a pin property, it applies to the entire net to which the pin is attached.Attaching NO_LOAD_CHECK to a pin with UNKNOWN_LOADING on a pin, load checking issuppressed only for that pin.

VER

This property defines the version of the instance of a component used in a schematic. Youcan replace a schematic component with its next version by using Component – Versionmenu command. Two versions of a component may differ graphically but functionally, they arethe equivalent representation of the component.

VHDL_CONCAT

Add the VHDL_CONCAT property on the symbol for a component that you want to use for:

■ Merging a number of signals, ports, or signal aliases into a group and then route thegroup to a port or instance with a single wire.

■ Splitting a vectored signal or port into a number of signals of smaller width.



Ensure that the name of the output pin of the symbol is the highest alphanumeric value of allthe pins on the symbol. For example, if the input pins are named AA, DD, and FF, the outputpin cannot be named BB.

VHDL_MODE

The VHDL_MODE property allows you to specify the direction of ports for the generated VHDLdescription. To specify the direction of ports, add the VHDL_MODE property to interface signalsor to pins on the symbol.

Note: If a port has several pins, you need to attach the property on only one of the pins.

For more information on declaring port modes, see “Declaring Port Modes” in the Workingwith Libraries and Components chapter of the Concept HDL User Guide.

VHDL_SLICE

Specifies to the netlister that the component should be treated as a tap symbol that breaksout a set of bits indicated by the value of the BN property on the pin on the component.

VLOG_MODE

The VLOG_MODE property allows you to specify the direction of ports for the generated Verilogdescription. To specify the direction of ports, add the VLOG_MODE property to interface signalsor to pins on the symbol.

Note: If a port has several pins, you need to attach the property on only one of the pins.

Add property... To...

VHDL_MODE=IN Declare the direction of the port as input

VHDL_MODE=OUT Declare the direction of the port as output

VHDL_MODE=INOUT Declare the direction of the port as inout

VHDL_MODE=BUF Declare the port as a buffer port

VHDL_MODE=LINKAGE Declare the port as a linkage port


VLOG_MODE=INPUT Declare the direction of the port as input



For more information on declaring port modes, see “Declaring Port Modes” in the Workingwith Libraries and Components chapter of the Concept HDL User Guide.

XY

Defines the x,y Concept HDL coordinate. The X and Y values range between -16000 and16000, and indicate where the particular instance is placed in the schematic.

Simulation Properties

This section describes the properties that are supported for simulation.

VLOG_MODE=OUT Declare the direction of the port as output

VLOG_MODE=INOUT Declare the direction of the port as inout

VLOG_MODE=BUF Declare the port as a buffer port

VLOG_MODE=LINKAGE Declare the port as a linkage port

Property Attached To Tools that use this property

LIBRARYn Symbol,

In map file

Simulation Netlister

NO_REP_PRIM Component, Symbol Simulation Netlister

MODEL_DIR Component, Symbol Simulation Netlister

MODEL_FILE Component, Symbol Simulation Netlister

PORT_ORDER In map file,Component

Simulation Netlister, Concept HDL

REMOVE Component, Symbol Simulation Netlister

SDFDELAYTYPE Symbol Simulation Netlister

SDFFILE Symbol Simulation Netlister

SDFSCALEFACTOR Symbol Simulation Netlister

SDFSCALETYPE Symbol Simulation Netlister




LIBRARYn

The LIBRARYn property provides a library name to be used in a VHDL library clause in theentity and architecture text generated for the schematic. Use the following syntax:

LIBRARYn = library_name

where n is a unique number and library_name is the name of the library.

Note: When you use this property on a VHDL_DECS symbol, it does not override the valueof the library clauses specified for the VHDL netlisting options in the Output tab of theConcept Options dialog box. Instead, the libraries you specify on the VHDL_DECS symbolare appended to the list of libraries you specified for the VHDL netlisting options in the Outputtab of the Concept Options dialog box.

SIM_BIND_VIEW Component, Symbol Simulation Netlister

SIM_MAP_VIEW Component, Symbol Simulation Netlister

SIZE Component, Symbol Simulation Netlister, Concept HDL

SPLIT_INST Component, Symbol Simulation Netlister

SPLIT_INST_NAME Component, Symbol Simulation Netlister

USEn Symbol Simulation Netlister

VERILOG_LIB Component, Symbol Simulation Netlister

VERILOG_MODEL Component, Symbol,In Verilog map file


VERILOG_NAME In Verilog map file Simulation Netlister

VHDL_MODEL Component, Symbol,In VHDL map file


VHDL_NAME In VHDL map file Simulation Netlister

VHDL_SCALAR_TYPE Symbol, Pin, Signal Simulation Netlister

VHDL_VECTOR_TYPE Symbol, Pin, Signal Simulation Netlister

VHDL_INIT Symbol, Signal Simulation Netlister

VLOG_NET_TYPE Symbol, Pin, Signal Simulation Netlister

Property Attached To Tools that use this property



NO_REP_PRIM

Use the NO_REP_PRIM=TRUE property on an instance:

■ if you do not want the instance to be replicated in the netlist or

■ if you do not want to pass the SIZE parameter with the correct value to the behavioralmodel.

Note: When the property NO_REP_PRIM=TRUE is not found on an instance, theConcept HDL netlister automatically replicates the instance in the netlist with the actual valueof the SIZE property specified on the instance.

In the figure given below, an instance of component ls00 has the property SIZE=4.

The instance will be replicated four times in the netlist as below:

SN74LS00 page1_i1__1 (._1A(/* unconnected */),

._1B(/* unconnected */),

._1Y(/* unconnected */),

._2A(/* unconnected */),






._4A(a[0]),

._4B(b[0]),

._4Y(c[0]));












._4A(a[1]),

._4B(b[1]),

._4Y(c[1]));










._4A(a[2]),

._4B(b[2]),

._4Y(c[2]));










._4A(a[3]),

._4B(b[3]),

._4Y(c[3]));

Now, if you add the NO_REP_PRIM=TRUE property on the instance, the instance will not bereplicated in the netlist (see netlist sample below).

SN74LS00 page1_i1 (._1A(a[0]),

._1B(b[0]),

._1Y(c[0]),

._2A(a[1]),

._2B(b[1]),

._2Y(c[1]),



._3A(a[2]),

._3B(b[2]),

._3Y(c[2]),

._4A(a[3]),

._4B(b[3]),

._4Y(c[3]));

Note: The NO_REP_PRIM property is effective only when its value is TRUE. For all othervalues, the property is ignored.

MODEL_DIR

The MODEL_DIR property is used when you want to bind different instances of a componentto different model libraries. This property is used to specify the directory that contains themodel to be used for binding the component. The syntax used is

MODEL_DIR = <path_to_the_model_library>

While specifying the location of the model library, ensure that only backslash (/) is used as aseparator. Within the directory specified, you must have a file <model_name>.v thatcontains the model definition.

For example, consider that LS00 is instantiated in a design and the model used for simulatingthe LS00 component is ls00. If you add the MODEL_DIR property set to models_ver forinstance-specific binding, then the models_ver directory must have a file ls00.v,otherwise the Concept HDL netlister will generate a warning and ignore the MODEL_DIRproperty.

Values assigned to the MODEL_DIR property are case-sensitive.

Caution

Before using the MODEL_DIR property for specifying the model library,ensure that the component binding is correct. In case you do not want touse the default configuration, use the SIM_BIND_VIEW orSIM_MAP_VIEW property to specify the correct view for binding thecomponents.

A part of the netlist that is generated after the MODEL_DIR property is attached to LS00 isshown below. The simulation model is ls00, and the value assigned to the MODEL_DIRproperty is wrapper_ver. The additions in the netlist because of the MODEL_DIR propertyare in bold typeface.



‘uselib dir = wrappers_ver libext=.v

ls00 page1_i2 (.a(b),

.b(unnamed_1_ls00_i2_b),

.\y* (unnamed_1_ls00_i2_y));

defparam page1_i2.size = 1;

‘uselib

Notice that when the MODEL_DIR property is attached to a component, a ‘uselib statementgets added in the simulation netlist. The ‘uselib compiler directive specifies the locationwhere Verilog-XL should look for the definitions of modules and user-defined primitives(UDPs) used in the schematic design. The model file extension should be .v. This isindicated by libext=.v in the ‘uselib statement.

MODEL_FILE

The MODEL_FILE property is very similar to the MODEL_DIR property, except that theMODEL_FILE property is used to specify the location of a verilog file containing the modeldefinition for simulating the component. To specify the MODEL_FILE property on an instance,add the following:

MODEL_FILE = <path>/verilog.v

where path is the location of the verilog.v file containing the model definition. Whilespecifying the path, ensure that only backslash(/) is used. Notice that the file specified by theMODEL_FILE property is always a verilog file.

Caution

Before using the MODEL_FILE property for specifying the model library,ensure that the component binding is correct. In case you do not want touse the default configuration, use the SIM_BIND_VIEW or theSIM_MAP_VIEW properties to specify the correct view for binding thecomponents.

A part of the netlist that is generated after the MODEL_FILE property is attached to LS00 isshown below. The additions in the netlist because of the MODEL_FILE property are in boldtypeface.

// begin instances

‘uselib file = ./models_ver/ls00/vlog_behavioral/verilog.v

ls00 page1_i1 (._1A(/* unconnected */),











._4A(a),

._4B(sel),

._4Y(unnamed_1_ls00_i1_y));

‘uselib

Note: You can specify either the MODEL_FILE property or the MODEL_DIR property onan instance. In case both the properties are specified on a single instance, theMODEL_DIR property is ignored.

The MODEL_DIR and MODEL_FILE properties, which are used for providing instance-specificmodel binding, are understood only by the Verilog-XL simulator. For instance-specific bindingusing NC Verilog simulator, use the VERILOG_LIB property.

PORT_ORDER

The PORT_ORDER property specified in the Verilog map file is used if the PositionMapping check box in the Netlist tab of the Concept HDL Digital Simulation Interface isselected. If the Position Mapping check box is selected, the Concept HDL pins will bemapped to model ports by position in the netlist.

Syntax

PORT_ORDER = (port1, port2 ...);

Use this property to specify the port ordering for a module described in an external library.

■ If the port is a vector, a full description for the port (such as A[3:0]) is required. Thevector information is useful for Concept HDL to reconstruct the bus connected to the port.

■ If the PORT_ORDER property is not specified for a part in an external library,Concept-HDL uses the PIN_NUMBER information for making the connection by position.The PIN_NUMBER information is read from the chips.prt file.

■ If the Position Mapping check box in the Netlist tab of the Concept HDL DigitalSimulation Interface is selected and neither a PORT_ORDER nor a PIN_NUMBERproperty is specified, Concept HDL displays an error message.



Note: The order of precedence to get the port order information is the following:

1. Read the verilog.v file to get the port names.

2. If there is no verilog.v file, then use the Verilog names in the verilog.map file.

3. If there is no verilog.v file and there is a PORT_ORDER property in theverilog.map file, then use the PORT_ORDER property.

4. If there is no verilog.v file and no PORT_ORDER property in the verilog.mapfile, use the order from the chips.prt file.

REMOVE

This body property is used either on bodies in the library or on instances of bodies in theschematic design.

Syntax

REMOVE LINK | EXCLUDE | AUTO | FALSE

The syntax is explained below:

LINK

Removes the component and connects the pins of the component. For example, useREMOVE=LINK on resistors.

If you have attached property REMOVE=LINK on the resistor, for simulation, the resistor isreplaced with a wire of same connectivity. So signal ABC is alias to signal RESET.

Note: The resistor will be visible in the packaging netlist.

The netlist generated by Concept HDL is given below:

module remove (reset );



output reset;

// global signal glbl.vcc;

wire abc;

alias_bit alias_inst1 (abc, glbl.vcc);

alias_bit alias_inst2 (abc, reset);

endmodule

EXCLUDE

Removes the component and all nodes on the component. For example, useREMOVE=EXCLUDE on capacitors and non-series terminating resistors.

Once you have attached the property REMOVE=EXCLUDE on the resistor, for simulation, theresistor is replaced by an open.

Note: The resistor is visible in the packaging netlist.

The netlist generated by Concept HDL is given below:

module remove (reset );

output reset;

// global signal glbl.vcc;

wire abc;

alias_bit alias_inst1 (abc, glbl.vcc);

endmodule

AUTO

Removes the component and connects the pins of the component if the component isconnected between two internal nodes. If one pin of the component is connected to a powersupply, for example VCC, Concept HDL replaces the component with a pullup in thesimulation netlist. If one pin of the component is connected to a ground, for example GND,



Concept HDL replaces the component with a pulldown in the Verilog netlist. For example, useREMOVE=AUTO on resistors.

In this example, the property REMOVE=AUTO is attached to resistors R1 and R2. ResistorR1 is connected to the power symbol VCC, resulting in a pullup in the netlist. Resistor R2 isconnected to the ground symbol GND, resulting in a pulldown in the netlist.

The netlist generated by Concept HDL is shown below:

pulldown (abc);

pullup (reset);

To use the REMOVE=AUTO property on a component

1. Specify the name of the ground symbol (for example, GND and GNDD) in the Supply 0field in the Verilog Netlist dialog box.

To access the Verilog Netlist dialog box, do the following:

a. In Concept HDL, choose Tools > Options.

The Concept Options dialog box appears.

b. Select the Output tab.

Ensure that the Create Netlist check box is selected.

c. Click the Options button against the Verilog check box.

The Verilog Netlist dialog box appears.

2. Specify the name of the power symbol (for example, VCC and VDC) in the Supply 1 fieldin the Verilog Netlist dialog box.

3. Attach the REMOVE=AUTO property to the component.



4. Connect a wire to this component.

5. Add a power symbol, such as VCC or GND, that is added to the SUPPLY1 or SUPPLY0list, to one of the terminals of the component. This results in a pullup or pulldown net.

Note: If you use the REMOVE=AUTO property on a component that has only one pin in eachsection and

❑ If one of the terminals is connected to a power symbol that is declared as SUPPLY1or SUPPLY0, then Concept HDL changes it to a pullup or pulldown.

❑ If a power symbol is not declared as SUPPLY1 or SUPPLY0, Concept HDL treatsthe REMOVE=AUTO property as the REMOVE=LINK property.

FALSE

If the REMOVE property is defined on the symbol of a component, the property will beavailable on every instance of the component you place in your design. If you do not want touse the REMOVE property on a specific instance of the component in your design, specifythe REMOVE=FALSE property on that instance. Concept HDL will ignore the REMOVEproperty on an instance if the value of the property is FALSE.

SDFDELAYTYPE

This property defines the scale type. The values that can be assigned to this property areMINIMUM, TYPICAL, and MAXIMUM.

The default value assigned to the property is TYPICAL.

SDFFILE

The SDFFILE property is specified on the instances of a component in the schematic.SDFFILE is the name of the SDF file. For example, ./data/design.sdf.

When this property is added to a component, the netlister inserts the $sdf_annotatedirective in the netlist. After specifying the SDFFILE property, if you do not specify otherspecial properties such as SDFDELAYTYPE, SDFSCALEFACTOR, and SDFSCALETYPE,the default values of these properties are added in the netlist.



SDFSCALEFACTOR

The SDFSCALEFACTOR property defines the scale factor. The scale factor could be<real|integer>:<real|integer>:<real|integer>.

The default value is 1:1:1.

SDFSCALETYPE

This property defines the scale type. The possible scale types are FROM_MINIMUM,FROM_TYPICAL, FROM_MAXIMUM, and FROM_MTM.

The default value of the SDFSCALETYPE property is FROM_MTM.

SIM_BIND_VIEW

The SIM_BIND_VIEW property is used to specify the binding for the Verilog models thatappear in the mapped netlist. If you are using wrappers for simulation, specify a wrapper viewname as the value for this property. If you are using map files for simulation, the propertyvalue should be a binding for the mapped Verilog model.

Example

If you are using a lsoo part in the schematic and specify

SIM_BIND_VIEW=vlog_model

the lsoo part is bound to the vlog_model view of lsoo. However, if you have specified

VERILOG_MODEL=TTLOO

and

SIM_BIND_VIEW=vlog_model

the lsoo part is bound to the vlog_model view of TTL00.

If you are using parts having shared pins (physically different pins, with the same pin nameon different symbols) you must specify the wrapper’s view name also as the property valuefor the SIM_BIND_VIEW property. Concept HDL finds the location of the wrapper from thisview.

The SIM_BIND_VIEW property must be placed on any one of the split parts if there arecommon or shared pins across different split parts. If the same property SIM_BIND_VIEW or



the same parameter is found on more than one instance of the same SPLIT_INST_NAMEgroup, Concept HDL takes the property from the instance having lower path values andignores the property from the other instances in the same split instance group. For moreinformation, see “SPLIT_INST_NAME” on page 53.

SIM_MAP_VIEW

This is an instance property that overrides the default map file viewlist specified in thesimulation configuration. For example, if the default map file viewlist for the cfg_verilogsimulation configuration is swift_map, you can specify

SIM_MAP_VIEW=vlog_map

to override the map view binding.

SIZE

The SIZE property is used to specify the width of pin names and signal names and to definesize expansion. Using the SIZE property can greatly minimize the number of parts andinterconnections.

The SIZE property, when used inside the hierarchy, generates specific versions of a module.Ultimately, the SIZE property is propagated down to the primitive level. Most of the primitivesin Concept HDL use the SIZE property to specify the number of bits of the primitive. The valueof the SIZE property can be fixed or variable (SIZE=SIZE). In this case, the size of theprimitive is taken from the SIZE property attached to the component being modeled.

For simple primitives, the SIZE property is interpreted as multiple instances of the primitive.The bits of a bus connected to a sized pin of a primitive are split between the replicatedinstances of the primitive. For example, if bus A<1..0> is connected to a sized pin of a BUFprimitive with SIZE=2, the bit A<0> is connected to the first instance and the bit A<1> isconnected to the second instance. Simple SIZED primitives are translated by Concept HDLas multiple instances of the primitive.

For more complex primitives, the SIZE property cannot be directly interpreted as a replicationof the primitive. In an example of an ADDER primitive with SIZE greater than two, theCarryOut of one stage needs to be connected to the CarryIn of the next stage. To accuratelymodel the SIZE property on this type of primitive, the primitive must be described as aparameterized behavioral Verilog model.

■ When the property NO_REP_PRIM is found in the library description for a primitive,Concept HDL does not replicate this primitive or pass the SIZE parameter with thecorrect value to the behavioral model.



■ When the property NO_REP_PRIM=TRUE is not found in the library description for aprimitive, Concept HDL assumes it to be a simple gate and automatically replicates thisgate with the actual value of SIZE.

SPLIT_INST

All split parts of a device must have a SPLIT_INST property set to TRUE attached to thesymbol (by the librarian developing the split parts). If this property is not attached to thesymbols, the property cannot be attached to the split parts you use in your schematic.

In the simulation netlist, all parts with the SPLIT_INST property set to TRUE are merged intoa single instance. In cases where the schematic has multiple instances of a split part, thenalong with the SPLIT_INST property set to TRUE, you should also have the $LOCATIONproperty specified on all split parts. A group of split parts of the same device is known as splitinstance group. Parts having same value for the $LOCATION property form one split instancegroup.

For example, suppose there is a large pin count device, ASYM_PART, which is split into fourparts. All the four split parts must have the SPLIT_INST property set to TRUE, attached tothem. Now if a schematic has only one instance of all four ASYM_PART split parts, theConcept HDL netlister will merge all devices into a single instance in the simulation netlist.The instance name in the generated netlist will be ASYM_PART_SPLIT_1. But in case thereare multiple instances of a ASYM_PART split part, Concept HDL netlist will generate awarning and use internal logic to group the parts into different split inst groups.

To remove this warning you must attach the $LOCATION property with the same value on allsplit parts that should form a single split inst group. When you save a schematic inConcept HDL, all split parts with the same value for the $LOCATION property are merged intoa single instance in the netlist.

SPLIT_INST_NAME

Attach the $SPLIT_INST_NAME property on all split parts that have to be merged into asingle instance in the simulation netlist. By default, the value assigned to the$SPLIT_INST_NAME property is ?. If the default value is used, in the simulation netlist allsplit parts are merged into a single instance named <device_name>_split_1.

For example, consider a device, ASYM_PART, which is split into four parts. All four parts havethe $SPLIT_INST_NAME property set to ?. Concept HDL netlister reads the property andmerges the four split parts to generate one instance of the part with the instance name asasym_part_split_1.



If you need multiple instances of a split part, you should specify the property$SPLIT_INST_NAME with different values for each instance. The property value becomesthe becomes the instance name in the simulation netlist and therefore, must be the same forall split parts in a split inst group.

For example,

■ Attach the SPLIT_INST_NAME property set to INST_FIRST to all the body drawings ofthe split part for the first instance.

■ Attach the SPLIT_INST_NAME property set to INST_SECOND for the second instance.

The output in the netlist will be

SPLIT_PART INST_FIRST(.....);

SPLIT_PART INST_SECOND(.....);

Caution

Do not use the instance name in the following format:i<integer>This can cause a naming conflict because Concept HDL generatesinstance names such as I1P, I2P, and so on.

USEn

The USEn property provides names to be used in VHDL use clauses in the entity andarchitecture generated for the schematic. Use the following syntax:

USEn = library_name

where n is a unique number and library_name is the name of the library.

Note: When you use this property on a VHDL_DECS symbol, it does not override the valueof the use clauses specified for the VHDL netlisting options in the Output tab of the ConceptOptions dialog box. Instead, the values you specify on the VHDL_DECS symbol areappended to the list of use clauses you specified for the VHDL netlisting options in the Outputtab of the Concept Options dialog box.

VERILOG_LIB

To support instance-specific binding for a library in the NC Verilog simulation flow, you haveto attach the VERILOG_LIB property on the instance of the part. For example, if ls00 isinstantiated on a drawing, you have to add the following for instance-specific library bindingsupport:



VERILOG_LIB=lsttl_models

where VERILOG_LIB is the property name and lsttl_models is the associated Veriloglogical library name.

The property will be transferred in the netlist as

ls00 ( *VLOG_LIB="lsttl_models") inst1...

NC Verilog will parse the netlist file (verilog.v), and wherever it finds such an attribute, it willsearch the logical library to find the model for the ls00 part.

VERILOG_MODEL

The VERILOG_MODEL property is used to change the name of the Verilog modulegenerated or to select a specific MODEL entry in a Verilog map file. Place this property in thelibrary description for a primitive, in a physical part table, or directly on an instance.

Syntax

VERILOG_MODEL=name

Example

VERILOG_MODEL=SN74LS00

By default, the name of the Verilog module generated is the same name as the originalDRAWING name unless the part has a PART_NAME property defined. Use theVERILOG_MODEL property to specify the exact name of the Verilog module. AVERILOG_MODEL property placed on an instance overrides the same property placed in thelibrary.

VERILOG_NAME

The VERILOG_NAME property specifies the actual name of the Verilog model. Internally, allnames for modules are lowercase. If the name of the module you are using is eitheruppercase or contains a mixture of lowercase and uppercase characters, use theVERILOG_NAME property to specify how the module name will appear in the netlist.

Syntax

VERILOG_NAME=’name’



Example

VERILOG_NAME=’TTL00’

VHDL_MODEL

The VHDL_MODEL property is used to change the name of the VHDL module generated orto select a specific MODEL entry in a VHDL map file. Place this property in the librarydescription for a primitive (chips.prt file), in a physical part table, or directly on an instance.

Syntax

VHDL_MODEL=name

Example

VHDL_MODEL=SN74LS241

By default, the name of the VHDL module generated is the same name as the originalDRAWING name unless the part has a PART_NAME property defined. Use theVHDL_MODEL property to specify the exact name of the VHDL module. A VHDL_MODELproperty placed on an instance overrides the same property placed in the library.

VHDL_NAME

The VHDL_NAME property specifies the actual name of the VHDL model. Internally, allnames for modules are in lowercase. If the name of the module you are using is eitheruppercase or contains a mixture of lowercase and uppercase characters, use theVHDL_NAME property to specify how the module name will appear in the netlist.

Syntax

VHDL_NAME=’name’

Example

VHDL_NAME=’SN74LS153’

VHDL_SCALAR_TYPE

Legal Values: STD_LOGIC, BIT, and all other legal VHDL scalar types

The VHDL_SCALAR_TYPE property sets the default VHDL logic type for all scalar ports andsignals in your drawing. You can place a VHDL_DECS symbol on your drawing and attach



the VHDL_SCALAR_TYPE property to it to specify the default VHDL logic type for all scalarports and signals in your drawing. If you do not use this property on the VHDL_DECS symbol,all scalar ports and signals in your design will be of type STD_LOGIC.

You can change the VHDL logic type for a specific scalar port by attaching theVHDL_SCALAR_TYPE property to a pin of the port. You can change the VHDL logic type fora specific scalar signal by attaching the property to the signal.

VHDL_VECTOR_TYPE

Legal Values: STD_LOGIC_VECTOR, BIT_VECTOR, and all other legal VHDL vector types

The VHDL_VECTOR_TYPE property sets the default VHDL logic type for all vectored portsand signals in your drawing. You can place a VHDL_DECS symbol on your drawing andattach the VHDL_VECTOR_TYPE property to it to specify the default VHDL logic type for allvectored ports and signals in your drawing. If you do not use this property on theVHDL_DECS symbol, all vectored ports and signals in your design will be of typeSTD_LOGIC_VECTOR.

You can change the VHDL logic type for a specific vectored port by attaching theVHDL_VECTOR_TYPE property to a pin of the port. You can change the VHDL logic type fora specific vectored signal by attaching the property to the signal.

VHDL_INIT

The VHDL_INIT property allows you to specify the initial value of a signal for VHDL. TheVHDL_INIT property can also be attached to the pins of a symbol. When the VHDL_INITproperty is attached to a power symbol or to its pin, the power signal gets assigned that valuein the VHDL netlist generated by Concept HDL.

VLOG_NET_TYPE

Legal values: WIRE, WAND, WOR, and all other legal Verilog types

The VLOG_NET_TYPE property sets the default Verilog logic type for all ports and signals inyour drawing. You can place a VERILOG_DECS symbol on your drawing and attach theVLOG_NET_TYPE property to it to specify the default Verilog logic type for all ports andsignals in your drawing. If you do not use this property on the VERILOG_DECS symbol, allthe ports and signals in your design will be of type WIRE.



You can change the Verilog logic type for a specific port by attaching the VLOG_NET_TYPEproperty to a pin of the port. You can change the Verilog logic type for a specific signal byattaching the property to the signal.

Allegro/APD Properties

Property Attach toProperty can beassigned in theschematic?

ALIGNED Bond pad (Via) no

ALT_SYMBOLS Device yes

AUTO_GENERATED_TERM Component no

AUTO_RENAME Reference Designator(Component)

no

BOARD_THICKNESS Board no

BOM_IGNORE Component yes

BOND_PAD Bond pad (Via) no

BUS_NAME Net yes

CLIP_DRAW Design (board), Symbol no

CLIP_DRAWING Connect line, Device,Pin, Filled rectangle,Line, Rectangle, Shape,Symbol, Via, Void

no

CLK_2OUT_MAX Net, Pin no

CLK_2OUT_MIN Net, Pin no

CLK_SKEW_MAX Net, Pin no

CLK_SKEW_MIN Net, Pin no

CLOCK_NET Net yes

COMPONENT_WEIGHT Reference Designator(Component)

yes

CURRENT Reference Designator(Component)

yes



C_TEMPERATURE Reference Designator(Component)

yes

DENSE_COMPONENT Reference Designator(Component)

yes

DFA_DEV_CLASS Board, Symbol no

DIFFERENTIAL_PAIR Net yes

DIFFP_2ND_LENGTH Net no

DIFFP_LENGTH_TOL Net no

DRIVER_TERM_VAL Net no

ECL Net yes

ECL_TEMP Net yes

EDGE_SENS Net, Xnet, ECSet no

ELECTRICAL_CONSTRAINT_SET Net yes

EMC_COMP_TYPE Component, Device yes

EMC_CRITICAL_IC Component, Device yes

EMC_CRITICAL_NET Net yes

EMC_RUN_DIR Board no

FAILURE_RATE Reference Designator(Component)

no

FILLET Connect Line no

FIRST_INCIDENT Net, Xnet, ECSet no

FIX_ALL Reference Designator(Component)

yes

FIXED Reference Designator(Component), Symbol,Connect Line, Filledrectangle, Line, Net,Pin, Rectangle, Shape,Via

yes




FIXED_T_TOLERANCE TPoint no

FP_BOARD_CLEARANCE Board no

FP_NOTES_TEXT_BLOCK Board no

FP_REFDES_TEXT_BLOCK Board no

FP_ROOM_NAME_TEXT_BLOCK Board no

GROUP Function Designator yes

HARD_LOCATION Reference Designator,Function Designator

yes, but not seen inschematic asLOCATION

HEAT_SINK_FACTOR Reference Designator(Component)

yes

IDF_OWNER All Objects no

IMPEDANCE_RULE Net, ECSet no

INSERTION_CODE Device yes

J_TEMPERATURE Reference Designator(Component)

yes

LEAD_DIAMETER Board, Symbol no

LOAD_TERM_VAL Net no

LOGICAL_PATH Function Designator(Component)

yes, but assigned byPXL. Not user defined.

MAX_BOND_LENGTH Net, Connect Line no

MAX_BVIA_STAGGER Net no

MAX_EXPOSED_LENGTH Net, ECSet yes

MAX_FINAL_SETTLE Net, ECSet yes

MAX_OVERSHOOT Net, ECSet yes

MAX_PARALLEL (PARALLELISM) Net, Connect Line,ECSet

no




MAX_PEAK_XTALK(MAX_PEAK_CROSSTALK)

Net no

MAX_POWER_DISS Device, ReferenceDesignator(Component)

yes

MAX_SSN Net no

MAX_UNDERSHOOT yes

MAX_UNDERSHOOT Net, Connect Line yes

MAX_VIA_COUNT Net, ECSet yes

MAX_XTALK (MAX_CROSSTALK) Net no

MAX_XTALK (MAX_CROSSTALK) Net, Connect Line no

MIN_BVIA_GAP Net no

MIN_BVIA_STAGGER Net no

MIN_FIRST_SWITCH Net, ECSet no

MIN_HOLD Net, Pin yes

MIN_LINE_WIDTH Net, Connect Line yes

MIN_NECK_WIDTH Net, Connect Line yes

MIN_NOISE_MARGIN Net, ECSet yes

MIN_SETUP Net, Pin yes

NET_PHYSICAL_TYPE Net, Constraint Area(Shape, Rectangle)

yes

NET_SCHEDULE Net, ECSet no

NET_SPACING_TYPE Net, Constraint Area(Shape, Rectangle)

yes

NO_DRC Pin, Via no

NO_GLOSS Net yes

NO_LIN2SHAPE_FAT Connect Line no




NO_PIN_ESCAPE Reference Designator(Component), Net, Pin

yes

NO_RAT Net yes

NO_RIPUP Net yes

NO_ROUTE Reference Designator(Component), Net

yes

NO_SHAPE_CONNECT Pin, Via yes

NO_SWAP_GATE Reference Designator,Function Designator

yes, but assigned byPXL. See PXLdocumentation.

NO_SWAP_GATE_EXT Function Designator yes, but assigned byPXL. See PXLdocumentation.

NO_SWAP_PIN Reference Designator,Function Designator,Pin

yes, but assigned byPXL. See PXLdocumentation.

NO_TEST Net yes

NO_VIA_CONNECT Pins, Vias no

PACKAGE_HEIGHT_MAX andPACKAGE_HEIGHT_MIN

Rectangle, Shape no

PARALLELISM (MAX_PARALLEL) Connect Line, Net no

PIN_ESCAPE Reference Designator,Pin

yes

PIN_SIGNAL_MODEL Pin no

PINUSE Pin yes, but assigned byPXL. See PXLdocumentation.

PLACE_TAG Reference Designator(Component)

no

PLATING Shape no




PROBE_NUMBER Net yes

PROPAGATION_DELAY Net, ECSet no

PULSE_PARAM Net, Xnet, Bus, Diff Pair no

RATED_CURRENT Device yes

RATED_MAX_TEMP Device yes

RATED_POWER Device yes

RATED_VOLTAGE Device yes

RATSNEST_ SCHEDULE Net, ECSet no

REF_DES_FOR_ASSIGN Function no

RELATIVE_PROPAGATION_DELAY Net, ECSet no

REUSE_ID Component, Symbol

REUSE_INSTANCE Component yes

REUSE_MODULE Component yes

REUSE_NAME Component yes

REUSE_PID Component, Symbol

ROOM Reference Designator,Function Designator

yes

ROOM_TYPE Room Boundary no

ROUTE_PRIORITY Net yes

ROUTE_TO_SHAPE Net no

SAME_NET Nets no

SCHEMATIC_NAME Board yes, but passed byPXL, not userassigned

SHIELD_NET Net yes

SHIELD_TYPE Net yes

SHORTING_SCHEME Pin, Via no




SIGNAL_MODEL Reference Designator(Component)

yes

SLOTNAME Function no

SOLDER_BALL_HEIGHT Symbol no

SPIF_CONSTANTS Board no

SPIF_TURRET Cline, Frect, Shape no

STUB_LENGTH Net, ECSet yes

SUBNET_NAME Pin yes

SWAP_GROUP Function Designator yes, but assigned byPXL. not user-assigned.

SYS_CONFIG_NAME Board no

T_TEMPERATURE Reference Designator(Component)

yes

TEMPORARY_PACKAGE_SYMBOL no

TERMINATOR_PACK Device no

TESTER_GUARDBAND Net, Pin no

THERMAL_RELIEF Thermal Connect Line no

THICKNESS Layout Cross Section no

TIMING_DELAY_OVERRIDE Net, Pin no

TOL Device yes

TOPOLOGY TEMPLATE Net yes

TOPOLOGY_TEMPLATE_REVISION Net, ECSet yes

TOTAL_ETCH_LENGTH Xnet, net, bus or diff pair yes

TS_ALLOWED Net yes

UNFIXED_PINS Board, Symbol no

VALUE Discrete Device yes




ALIGNED

Attached to bondpads in APD. Prohibits the attached bondpad from going out of alignmentwhen the MOVE or SPIN commands are invoked. The property is set by the tool, dependingupon configurations invoked in the Options tab.

ALT_SYMBOLS

Attach to a device (through a device file). List of alternate package symbol names that can besubstituted for the primary package symbol during interactive placement.

The syntax for an alternate symbol definition in the device file is

PACKAGEPROP ALT_SYMBOLS ’(Subclass:Symbol,...;Subclass:Symbol,...)’

■ Subclass—Either TOP (or T) for top layer, or BOTTOM (or B) for bottom layer

■ Symbol—Standard Allegro/APD package symbol name

For example, an alternate symbol definition for component 74LS373 might be

PACKAGEPROP ALT_SYMBOLS ’(TOP:SOIC20;BOTTOM:SOIC20,SOIC20_PE)’

VIA_LIST Net no

VOLT_TEMP_MODEL Pin yes

VOLTAGE Reference Designator(Component)

yes

VOLTAGE_LAYER Net yes

VOLTAGE_SOURCE_PIN Pin yes

WEIGHT Pin no

WIRE_LENGTH Net yes

XTALK_ACTIVE_TIME Net, ECSet no

XTALK_IGNORE_ NETS Net no

XTALK_SENSITIVE_TIME Net, ECSet no




AUTO_GENERATED_TERM

SPECCTRAQuest internally generated property. Not accessible to the user.

AUTO_RENAME

Attach to a reference designator (component). Indicates the component is to be included inthe next automatic renaming process. Value is TRUE.

BOARD_THICKNESS

Generated automatically by Allegro/APD and attached to a board (design). Specifies board(or layout) thickness. Allegro/APD computes the thickness by adding all layer thicknesses inthe cross section. Cadence recommends that you do not assign the BOARD_THICKNESSproperty.

BOM_IGNORE

A reserved property for parts in a design. BOM_IGNORE specifies a string value attached to acomponent instance. Any component instance that has this property with a non-blank valueis not displayed in the Bill of Materials report.

BOND_PAD

Generated automatically by APD and attached to bond pads created during the automatic orinteractive wire bond process.

BUS_NAME

Attach to a net. Name of net to be treated as a bus by interactive and automatic routing.Concept adds this property automatically for signals identified as part of a bus. You can alsoattach this property interactively. Value is a string.

C_TEMPERATURE

Generated and attached to a reference designator (component). Defines the casetemperature for the component in degrees centigrade.



CLIP_DRAW

Generated automatically by Allegro/APD and attached to the design, in the format CLIP_n,where n is the total number of times, plus one, that the paste operation was used in the layoutor symbol drawing. You can use the CLIP_n value to track the number of times clipboardinformation has been pasted into a drawing. CLIP_DRAW always stores one more than thecurrent number of operations.

You can change the CLIP_n value to another number by editing the property interactively(using the Process – Edit – Property option).

CLIP_DRAWING

Generated automatically by Allegro/APD in the format CLIP_n, where n is the number oftimes that an element in a clipboard file was pasted into a layout or symbol drawing. Allegro/APD attaches this property to all elements (connect lines, pins, filled rectangles, lines,rectangles, shapes, symbols, vias, and voids) except text, in a clipboard file whenever youpaste the clipboard file into a layout or symbol drawing.

For example, if the property CLIP_DRAWING = CLIP_3 is attached to a pin, it means thatthe pin in a clipboard file has been pasted into a particular design or symbol drawing as partof the third paste operation.

CLK_2OUT_MAX

The maximum delay from the active clock range at a latch to the output change.

CLK_2OUT_MIN

The minimum delay from the active clock range at a latch to the output change.

CLK_SKEW_MAX

Used by the Timing Setup/Hold tab of the constraint manager. Defines the maximum skew inthe clock signal between the launching and latching components. This property defines avalue in nanoseconds and can be attached to either the data net or a pin in the data net.



CLK_SKEW_MIN

Used by the Timing Setup/Hold tab of the constraint manager. Defines the minimum skew inthe clock signal between the launching and latching components. This property defines avalue in nanoseconds and can be attached to either the data net or a pin in the data net.

CLOCK_NET

The CLOCK_NET property is related to the SpecctraQuest timing spreadsheet and the File –Import – Timing command. The Import Timing command adds this property on a net to storethe name of the net that is used to clock the net’s data.

For example, if there is a net DATA1, that is clocked by net CLOCK1, then DATA1 would getthe CLOCK_NET property added with the a value of CLOCK1.

COMPONENT_WEIGHT

Attach to a reference designator (component). Used by automatic placement to determine therelative importance of components. Value is an integer from 0 to 100. All components havea default weight of 50.

CURRENT

Attach to a reference designator (component). Defines the current consumed by thecomponent in amperes. Used by Thermax and Viable.

DENSE_COMPONENT

Attach to a reference designator. Indicates the component is heavily connected to othercomponents. Ratsnesting attempts to put the pins on these components at the end of theirnet schedule. Also, the automatic router routes connections to a dense component first. Valueis TRUE.

DFA_DEV_CLASS

Used to classify devices as per the DFA required classification. As of now, the only legal valueis AL. It labels a component as Axial.



DIFFERENTIAL_PAIR

Attach to a net. The name of the differential pair. To create a differential pair, assign two netswith a DIFFERENTIAL_PAIR property that have the same name. Used by automatic routingand constraint checking.

DIFFP_2ND_LENGTH

Attach to a net. The secondary differential pair maximum line–to–line length. This is themaximum length a pair of nets can run at a distance apart specified by the SecondaryDifferential Pair Maximum line–to–line separation. Used by automatic routing and DRCchecking.

DIFFP_LENGTH_TOL

Attach to a net. The allowable difference between the total lengths of two differential pair nets.The value is either an absolute distance or a percentage of total net length. Used byautomatic routing and DRC checking.

DRIVER_TERM_VAL

Attach to a net. The value of a terminator component to be added to the driver end of the net.Used by the automatic terminator assignment program.

ECL

Attach to a net. Identifies a high speed net. Value is either TRUE or FALSE. Used byautomatic routing and ratsnest scheduling. If the ECL property is attached to a net, Allegro/APD assumes a stub length of zero and a ratsnest schedule ofSOURCE_LOAD_DAISY_CHAIN.

You can override this property by assigning the STUB_LENGTH property or the RATSNEST_SCHEDULE property.

ECL_TEMP

Attached to nets to be processed by the terminator assignment program in incremental mode.



EDGE_SENS

This constraint property defines whether or not a receiver pin is sensitive to non-monotonicityin the waveform. The value of this constraint shows which edges of the waveform aresensitive, that is, rising edge only, falling edge only, both edges, or neither edge.

ELECTRICAL_CONSTRAINT_SET

Attach to a net. The name of the Electrical Constraint Set to apply to the net. Any net thatdoes not have an ELECTRICAL_CONSTRAINT_SET property has the default ECSet.

EMC_COMP_TYPE

String that specifies a variable that identifies the component type. Used by EMControl.

EMC_CRITICAL_IC

String that identifies the class of a critical IC. Used by EMControl.

EMC_CRITICAL_NET

String that identifies the class of a critical net. Used by EMControls.

EMC_RUN_DIR

When you save changes to the EMC Initialization form, the EMC run directory name is storedin a design-level property called EMC_RUN_DIR. Used by EMControl.

FAILURE_RATE

Generated by Viable and attached to a reference designator (component). The component’srate in failures in units that correspond to the calculation method (usually failures per millionhours) used by Viable.



FILLET

Attach to connect lines. Indicates the connect lines are for filleting around a pad or line join.Prevents DRC from identifying dangling connect lines Value is TRUE. This property isassigned by the pad fillet glossing function.

FIRST_INCIDENT

This constraint property defines whether a signal is required to switch on the first incidentwave. The value of this constraint shows which edges of the waveform must switch on thierfirst incident wave. The legal values are rising edge only, falling edge only, both edges orneither edge.

FIX_ALL

Attach to a reference designator (component). Indicates that no swapping can be performedon this component, its functions, or its pins.

FIXED

Attach to components, symbols, nets, pins, vias, clines, lines, filled rectangles, rectangles,and shapes. Indicates that the object cannot be moved or deleted, the automatic router isnot to rip up connections in the net, and that glossing is not to be performed on the net.Value is TRUE.

FIXED_T_TOLERANCE

Attach to a Tpoint. Specifies a radius around a Tpoint that the router can route to the Tpoint.

FP_BOARD_CLEARANCE

SPECCTRAQuest internally generated property. Not accessible to user.

FP_NOTES_TEXT_BLOCK




FP_REFDES_TEXT_BLOCK


FP_ROOM_NAME_TEXT_BLOCK


GROUP

Attach to a function designator (gate). The name of the group to which the componentbelongs. Allegro/APD assigns functions that have the same GROUP property value to thesame component. The grouping of components lets you control the assignment of functionsto components.

HARD_LOCATION

Attach to a reference designator (component) or a function designator (gate). Prevents thereference designator of a component from being automatically or interactively renamed.Value is TRUE.

HEAT_SINK_FACTOR

Attach to a reference designator (component). A number used as a multiplier to representincreased surface area. Used by Thermax.

IDF_OWNER

IDF 3.0 allows entities to be owned be Electrical tool (like Allegro) or a mechanical tool. It maybe edited by the user to change the ownership. Legal values are ECAD and MCAD.



IMPEDANCE_RULE

Attach to a net. Specifies an impedance restriction between any two pins on a net or betweenany pin and Tpoint connection on a net. Used by DRC checking and routing.

If a connection has an impedance constraint specified by both an IMPEDANCE_RULEproperty and an electrical constraint set, the IMPEDANCE_RULE value is used.

The format of the IMPEDANCE_RULE property in the $A_PROPERTIES section of a netlist is

IMPEDANCE_RULE{[pin1]:[pin2]:[impedance]:

[tolerance]:}... ; netname

The legal values for pin1 and pin2 are:

pin1:pin2 Check the impedance of the connection between the specifiedpin pair. Specify the refdes and pin number for both pins of thepin pair. Either refdes and pin number can reference a Tpoint,which is specified as T.number. Both pins or Tpoints must be apart of the net to which the property is attached.

D:R Check the impedance of the longest driver/receiver pin pair in thenet. If no driver/receiver pin pairs are found, treat the propertyvalue as if the :: impedance : tolerance format werespecified.

AD:AR Check every driver/receiver pin pair combination in the net. If nodriver/receiver pin pairs are found, treat the property value as ifthe :: impedance : tolerance format were specified.

:: Check the longest and shortest pin pair combination in the net.All terminator pins in the net are ignored in the search for thelongest and shortest pin pair.

impedance The impedance constraint value in ohms expressed as a decimalnumber.

tolerance The tolerance for an impedance value specified as a value inohms or a percentage. A percentage must be followed by a %(percent sign).

netname Name of the net to which the impedance applies.



INSERTION_CODE

Attach to a device (through a device file). Specifies the Universal Component InsertionMachine to be used. Used by the Allegro/APD CIMLink and SDRC interfaces.

The syntax of the INSERTION_CODE property in the device file is

PACKAGEPROP INSERTION_CODE <property value>

Allowable property values are VCD, RADIAL, DIP, MULTIMOD, SIP, ZIP, AXIAL, and SMD.

J_TEMPERATURE

Attached to a reference designator (component). Defines the junction temperature for thecomponent in degrees centigrade.

LEAD_DIAMETER

Used to specify the Lead diameter of a pin's lead. This is used in calculating the span valueused in Lead span audit of DFA.

LOAD_TERM_VAL

Attach to a net. The value of a terminator component to be added to the load end of the net.Used by the terminator assignment program.

LOGICAL_PATH

Automatically generated and attached to a function designator (gate) by the netlist importprocess (netrev). It is used to backannotate Concept schematics. You cannot change thisproperty interactively.

MAX_BOND_LENGTH

Attach to a net or connect line. The maximum length of bonding wire for a net. A bonding wireis any connect line on an Etch subclass of type bonding wire.



MAX_BVIA_STAGGER

Attach to a net. The maximum distance between the connect point of one pin or via (the pinor via’s x,y location) and the connect point of the other, where the two pins or vias are on thesame net and have a single connect line joining them.

MAX_EXPOSED_LENGTH

The MAX_EXPOSED_LENGTH electrical constraint is a length check for the total length of etchallowed on the outer etch/substrate subclasses that exist above plane layers for EMC control.

Any and all external etch lengths are added and compared to the value in constraints.(External means any layer that does not have a plane between it and air.)

TOP <-------- externalINNER1 <-------- externalVCC PlaneINNER2INNER3GND PlaneINNER4 <--------- externalBOTTOM <--------- external

MAX_FINAL_SETTLE

Attach to a net. Defines the maximum final settle delay for driver/receiver pin pairs in the Xnetof which this net is part. A maximum final settle delay for a rising (falling) edge is the time fromwhen the driver starts switching to when the receiver passes up (down) through the Vil (Vih)switching threshold for the final time.

The format of the MAX_FINAL_SETTLE property in the $A_PROPERTIES section of thenetlist is:

MAX_FINAL_SETTLE [[pin1]:[pin2]:delay:]... ; netname

Buried Via Stagger Size




pin1:pin2 Apply the given delay constraint to the specified pin pair whereeach pin is defined as refdes.pin#. The pin pair must form adriver/receiver pair in the Xnet of which this net is a part.

AD:AR Apply the given delay constraint to each driver/receiver pin paircombination in the Xnet of which this net is apart.

delay The maximum switch delay constraint that is to be applied to thespecified driver/receiver pin pairs. This is a decimal numberdefining delay in nanoseconds.

netname Name of a net that is part of the Xnet to which the max final settleconstraint is to be applied.

MAX_OVERSHOOT

Attach to a net. The maximum voltage overshoot tolerated by the net. The default value is 600mV.

MAX_PARALLEL (PARALLELISM)

Attach to a net or connect line. The value is a character string of up to four different lengthsand distances. Separate each length–distance value by a colon (:). Separate each length–distance pair by a semicolon (;). For example:

<len1>:<sep1>;<len2>:<sep2>;<len3>:<sep3>;<len4>:<sep4>

MAX_PEAK_XTALK (MAX_PEAK_CROSSTALK)

Defines the high and low state maximum peak crosstalk constraints. Values is a string. Theformat of the string is

<high_value>:<low_value>

See also MAX_XTALK (MAX_CROSSTALK).



MAX_POWER_DISS

Attach to device (through a device file), or a reference designator (component). Themaximum power dissipation in watts for the component. If a value is not set on the referencedesignator, then netin attaches the PACKAGEPROP MAX_POWER_DISS from the device file,if one exists. If this property is attached directly to the reference designator, this propertyoverrides one taken from the device file. Used by Thermax.

The syntax for the MAX_POWER_DISS property in the device file is

PACKAGEPROP MAX_POWER_DISS <watts>

MAX_SSN

Attach to a net. The maximum noise allowed on a net due to simultaneous switching.

MAX_UNDERSHOOT

Attach to a net or connect line. The maximum undershoot tolerated by this net. Undershootis a voltage swing back into the mid-range after the nominal steady state high or low level hasbeen crossed. The default value is 250 mV.

MAX_VIA_COUNT

Attach to a net. The maximum via count for a net.

MAX_XTALK (MAX_CROSSTALK)

Defines the high and low state maximum crosstalk constraints. Value is a string. The formatof the string is


See also MAX_PEAK_XTALK (MAX_PEAK_CROSSTALK).

MIN_BOND_LENGTH

Attach to a net or connect line. The maximum length of bonding wire for a net. A bonding wireis any connect line on an Etch subclass of type bonding wire.



MIN_BVIA_GAP

Attach to a net. The minimum spacing between the connect points of two buried vias that donot share a common layer.

MIN_BVIA_STAGGER

Attach to a net. The minimum distance between the connect point of one pin or via (the x,ylocation of the pin or via) and the connect point of the other, where the two pins or vias areon the same net and have a single connect line joining them:

MIN_FIRST_SWITCH

Attach to a net. Defines the minimum first switch delay for driver/receiver pin pairs in the Xnetof which this net is a part. A minimum first switch delay for a rising (falling) edge is the timefrom when the driver starts switching to when the receiver first passes the Vil (Vih) switchingthreshold.

The format of the MIN_FIRST_SWITCH property in the $A_PROPERTIES section of a netlistis

Buried Via Gap

Buried Via Stagger Size



MIN_FIRST_SWITCH [[pin1]:[pin2]:delay:]... ; netname




delay The minimum first switch delay constraint that is to be applied tothe specified driver/receiver pin pairs. This is a decimal numberdefining delay in nanoseconds.

netname Name of a net that is part of the Xnet to which the min first switchconstraint is to be applied.

MIN_HOLD

Used by the Timing Setup/Hold tab of the Constraint Manager. It defines the minimum holdtime of a data signal relative to a clock signal. The value of the property is in nanosecondsand can be attached to either the data net or a pin of the data net.

MIN_LINE_WIDTH

Attach to a net. The minimum width of net or line.

MIN_NECK_WIDTH

Attach to a net. The minimum neck width of net or line.

MIN_NOISE_MARGIN

Attach to a net. The minimum noise margin tolerated by this net. The default value is 0 mV.



MIN_SETUP

Used by the Timing Setup/Hold tab of the Constraint Manager. It defines the minimum setuptime of a data signal relative to a clock signal. The value of this property is in nanosecondsand can be attached to either the data net or a pin of the data net.

NET_PHYSICAL_TYPE

Attach to a net or constraint area. The type of the Physical Constraint Set to be applied.

NET_SCHEDULE

Works with RATSNEST_SCHEDULE and reflects if the DRC system ensures that the schedulewas met when the net is routed. Values are Verify or Do Not Verify. For moreInformation, see RATSNEST_ SCHEDULE on page 85.

NET_SPACING_TYPE

Attach to a net or constraint area. The type of the Spacing Constraint Set to be applied.

NO_DRC

Attach to pins or vias to disable DRC checking against the pin or via.

NO_GLOSS

Attach to a net. Indicates this net should not be glossed. Value is TRUE.

NO_LIN2SHAPE_FAT

Attach to a connect line. Excludes the line from being fattened by the fatten command. Valueis TRUE.

NO_PIN_ESCAPE

Attach to a reference designator, net, or pin. Indicates the Pin Escape Router is not to placepin escapes on this component, net, or pin during routing. Value is TRUE.



NO_RAT

Attach to a net. Indicates nets with this property will not display ratsnests for unconnectedpins. Value is TRUE.

NO_RIPUP

Attach to a net. Indicates the etch on this net is not to be ripped up (removed) by the automaticrouter. Any connections on a net added after you assign this property can be ripped up. Valueis TRUE.

NO_ROUTE

Attach to a net or reference designator (component). Indicates any missing connections onthis net should not be routed. Value is TRUE.

NO_SHAPE_CONNECT

Attach to a pin or via. When this property is attached to a pin, Allegro/APD does not create aconnection between the pin (that passes through a shape with the same net) and a shape.When this property is attached to a via, Allegro/APD does not create a connection betweenthe via (that passes through a shape that is on the same net) and a shape. Value is TRUE.

NO_SWAP_GATE

Attach to a reference designator or function designator (gate). Indicates the functions withinthe component cannot be swapped. The function stays fixed in its current slot in thecomponent. Value is TRUE.

NO_SWAP_GATE_EXT

Attach to a function designator. This function cannot be swapped with one from anothercomponent. However, it can be swapped among slots within its current component. Value isTRUE.



NO_SWAP_PIN

Attach to a reference designator, function designator (gate), or pin. Indicates that pins on thiscomponent or function cannot be swapped, either interactively or automatically. Value isTRUE.

NO_TEST

Attach to a net. Indicates that test points are not to be added during test point generation.Value is TRUE.

NO_VIA_CONNECT

Attach to pins or vias to permit a shorting point for different GNDs.

PACKAGE_HEIGHT_MAX and PACKAGE_HEIGHT_MIN

Attach to rectangle and shape objects on class or subclass.

PACKAGE KEEPOUT/(Any)

PACKAGE_GEOMETRY/PLACE_BOUND_TOP (or) BOTTOM

Value of properties represents package and part symbol keepout heights.

This property is equivalent to the HEIGHT property in Concept HDL.

PARALLELISM (MAX_PARALLEL)

Attach to a net or connect line. The value is a character string of up to four different lengthsand distances. Separate each length–distance value by a colon (:). Separate each length–distance pair by a semicolon (;). For example:

<len1>:<sep1>;<len2>:<sep2>;<len3>:<sep3>;<len4>:<sep4>

PIN_ESCAPE

Attach to a reference designator or a pin. Indicates Allegro/APD is to place a pin escape onevery pin of this component when the Pin Escape Router is run. Value is TRUE.



PIN_SIGNAL_MODEL

This property defines a pin level override for a buffer model used in signal integritysimulations. This is used internally by the software for implementing programmable buffers.Users are discouraged from using this property to specify their own pin level overrides forbuffer model.

PINUSE

Attach to a pin to indicate its pin type. This value overrides any pinuse value specified in thedevice file. Pinuse code values are: IN, OUT, BI, TRI, OCA, OCI, POWER, GROUND, NC, andUNSPEC.

PLACE_TAG

Attach to a reference designator (component). Indicates the component is to be placed duringthe next automatic placement session. Value is TRUE. You must remember to remove thePLACE_TAG property before placing another group of components.

PLATING

Attach to a shape. Indicates the shape is to be attached to a plating bar. Used by APD.

PROBE_NUMBER

Attach to a net. A positive integer that represents the test probe to be used for testing the net.



PROPAGATION_DELAY

Note: This property replaces DENSE_COMPONENT beginning with Allegro/APD version14.0.

Defines the minimum and maximum propagation delay constraint between any pair of pins orrat-Ts in an extended net (Xnet). Value is a string, the format of which is

<pin_pairs>:<min>:<max>[<pin_pairs>:<min>:<max>]...

where each <pinpairs>:<min>:<max> defines a minimum and maximum propagationdelay constraint between one or more pin or rat-T pairs in an extended net. The format for<pin_pairs> is:

<pin_pair> defines a generic pin or rat-T pair

AD:AR every driver and receiver pin pair in the extended net

D:R the longest and shortest driver and receiver pair in the extendednet

L:S the longest and shortest pin pairs in the extended net (previouslydefined as "::")

The <min> and <max> fields define the minimum and maximum propagation constraintsapplied to the selected pin pairs—except when the D:R and L:S pin pair formats are specified.When the latter is the case, the <min> value is applied only to the shortest pin pair and the<max> value is applied only to the longest pin pair. Both the <min> and <max> values areformatted as <value_with_units> where the legal value types are:

PROP_DELAY the constraint is a delay value

PERCENTAGE the constraint is a percentage of the manhattan distancebetween the pins

DB_DIMENSION the value is a length measurement

If the <min> and <max> value has no units, it is assumed that the value is aDB_DIMENSION and the units of the drawing are design units.

Either the <min> or <max> field can be omitted as long as the colon separators arespecified.



PULSE_PARAM

This is used by the Net – Timing – Setup/Hold tab of the Constraint Manager spreadsheetto store the description of a clock pulse. The value of this property is a string of the followingformat:

<frequency>:<duty_cycle>:<jitters>:<cycle_to_measure>

RATED_CURRENT

Attach to a device (through a device file). The rated current limit, in amperes. Used by Viable.

RATED_MAX_TEMP

Attach to a device (through a device file). The nominal operating temperature of a device indegrees centigrade.

RATED_POWER

Attach to a device (through a device file). The nominal power dissipation. Used by Viable.

RATED_VOLTAGE

Attach to a device (through a device file). The nominal voltage of the device. Used by Viable.

RATSNEST_ SCHEDULE

Attach to a net. The type of ratsnest calculation to be done by Allegro/APD for this net.Thepossible values are:

■ MIN_TREE indicates the net should be ratsnested with the minimum spanning treealgorithm. This can form Ts at pins.

■ MIN_DAISY_CHAIN indicates a minimum length daisy-chain schedule is to be formed.

■ SOURCE_LOAD_DAISY_CHAIN indicates that a source-to-load ECL daisy-chainschedule is to be used.

■ FAR_END_CLUSTERwill automatically place a single Tpoint in a schedule at a calculatedlocation.



The Tpoint is automatically placed when the last component on net is placed. No ratsnestwill be visible until then. All pins with a PINUSE = INPUT will be scheduled from theTpoint. If there are multiple drivers present they will be classified as main line and otherdrivers. The main line driver is the longest driver/receiver pair on the net. All other driversare daisy chained together. If there is a terminator pin on the net it will be connected tothe Tpoint.

If it is not referenced in a DELAY_RULE the Tpoint will be placed along the main lineapproximately 90% from the main line driver to the furthest receiver pin.

If there is a terminator pin on the net, but the net has no driver pin present, the net isterminated. In this case the terminator pin is scheduled first, as the main line driver.

STAR specifies a ratsnest similar to FAR_END_CLUSTER without the Tpoint added.

All of the driver pins are daisy-chained together and all of the receiver pins are connectedto one end of the daisy- chain.

The following will be the designation of pins with the pinuse for the STAR andFAR_END_CLUSTER algorithms:

■ Power, ground, loadout, tri, OCA, OCL will all be treated as DRIVERs

■ Loadin pins are always LOADs

■ Pins with BI will always be DRIVERS, unless there are no LOADs and no unspecifiedpins.

■ Unspecified pins are always LOADS, unless there are no DRIVERS and no BIs.

■ If there are no DRIVERS and no LOADS, all pins will be daisy-chained together.

Be aware of the following special conditions related to the RATSNEST_SCHEDULEproperty:

■ If there is no RATSNEST_SCHEDULE property specified for a net, then a MIN_TREEschedule is assumed.

Driver1

Driver2

Driver3 Load1

Load2

Load3

Ratsnest line: Main Line Driver:

Tpoint



■ If a MIN_TREE schedule is selected explicitly or by default and the TS_ALLOWEDconstraint has been set to TS_NOT_ALLOWED, then a MIN_DAISY_CHAIN schedule isgenerated instead.

■ If a MIN_TREE schedule is selected explicitly or by default and the net contains an ECLproperty, then the SOURCE_LOAD_DAISY_CHAIN schedule is generated instead.

■ The NORAT net property still operates normally and independently of theRATSNEST_SCHEDULE constraint.

■ If a net’s schedule is user defined, then Allegro/APD ignores the value of theRATSNEST_SCHEDULE constraint.

REF_DES_FOR_ASSIGN

Reference designator attached automatically to a function (gate) by Allegro/APD whenloading a preassigned netlist using netin. It is the field used by Gate Assignment as the firstchoice when choosing a component for assigning the function. This field is reserved evenafter gate assignment and/or swapping and can then be compared to the referencedesignator of the component that contains the function.

RELATIVE_PROPAGATION_DELAY

This property replaces MATCHED_DELAY in version 14.0. Electrical constraint attached topin pairs on a net. Specifies a group of pin pairs that are required to have interconnectpropagation delays that match a specified delta (offset) and tolerance. ARELATIVE_PROPAGATION_DELAY group has one or more reference pin pairs againstwhich all other pin pairs in the group are compared.

The format of a relative propagation delay as a property is

<gp>:<scope>:<p1>:<p2>:<delta>:<tol>[:<gp>:<scope>:<<p1>:<p2>:<delta>:<tol>]...

Where:

gp Defines the name of the matched group

scope Defines whether the constraint is unique to a net or extended net,or global to the entire design. Legal values are

L for local to the net/extended net

G for global to the design. This value has meaning only forconstraint values that come from a constraint set. When



"flattened" to a specific net/extended net, the group name ismodified to make it unique for the net if the scope value is L. Ifthe value is G, the group name is assigned as is. If the scopevalue is omitted, L is assumed.

<p1>/<p2> Defines the two pins and/or rat_Ts in the pin pair. These can bespecific pins AD:AR, D:R, or L:S

The pin1 and pin2 syntax supports the following variations for defining pin pairs:

pin1:pin2 Add the specified pin pair to the matched group. Specify therefdes and pin number for both pins of the pin pair. Either pin'srefdes and pin number can reference a T point, which is specifiedas T.<number>. Both pins or T points must be a part of the net towhich the property is attached.

D:R Add the longest driver/receiver pin pair combination in the net tothe matched group. If no driver/receiver pin pairs are found, treatthe property value as if the group ::: tolerance format wasspecified.

AD:AR Add every driver/receiver pin pair combination in the net to thematched group. If no driver/receiver pin pairs are found, treat theproperty as if the group ::: tolerance format was specified.

L:S Add the longest pin pair in the net to the matched group. Allterminator pins in the net are ignored in the search for the longestpin pair.

delta is the delta expressed as either a delay or a length. If notspecified, a default of 0 is assumed.

tol is the tolerance of the match expressed as either a delay, alength, or a percentage. If not specified, a default of 5% isassumed.

One pin pair is always selected as the target pin pair. following these rules:

■ If only one pin pair has no delta value, it is selected.

■ If all of the pin pairs have delta values, the pin pair with the smallest delta is selected.

■ If there is more than one pin pair with the smallest delta value, the one with the longestpin pair length is selected.



■ If there is more than one pin pair without a delta value, the one with the longest pin pairlength is selected.

The CHECK_MIN_DELAYS environment variable associated with the obsolete MAX_DELAYconstraint does not apply to relative delays. Instead, you can usethe environment variableCHECK_UNROUTED_RELATIVE_PROP_DELAYS when youwant the DRC checker to check unrouted pin pairs based on themanhattan distance of their ratsnest connections.

REUSE_ID


REUSE_INSTANCE

Attach to an instance of a reused block in Concept HDL. The value of this block uniquelyidentifies the instance of the block. In Allegro/APD, the property is used to uniquely identifyan instance of a reused module. Value is a string.

REUSE_MODULE

Represents the name of the MDD file that Allegro will load when it finds this property on thecomponents in a reuse module.

REUSE_NAME

Represents a module definition name and is stored within the module file and the design inwhich the module resides. Identifies which definition should be used for each moduleinstance. Value is a string.

REUSE_PID




ROOM

Attach to a reference designator (component) or function designator. Indicates that thefunction is to be assigned to a component containing other functions in the same room. Valueis a string.

ROOM_TYPE

Attach to a room boundary. If the value HARD is specified, the following DRC is performed:

■ Any component assigned to the room (using the ROOM component property) must becompletely placed inside the room boundary.

If any part of the component package place bound area is outside the room boundary, aDRC marker is positioned in the center of the package symbol.

■ No component can be placed in any hard room to which it is not assigned.

If a component package is placed such that any part of its place bound area is within ahard room, and the component is not assigned to that room, a DRC marker is placed atthe center of the package symbol.

ROUTE_PRIORITY

Attach to a net. A positive integer that represents the routing priority for the net. Allegro/APDroutes the net according to the priority order. Nets with the lowest number have the highestpriority. If you want certain nets routed first, tag those critical nets with a ROUTE_PRIORITYproperty value of 1.

ROUTE_TO_SHAPE

Attach to a net. Directs Allegro/APD to route pins on a net to any other point on the net; therouter can connect to a shape or bus that is part of the net. It is used primarily with power andground nets. Value is TRUE.

SAME_NET

Attach to a net. Specifies whether elements in the same net are to be checked for spacingviolations. Value is TRUE.



SCHEMATIC_NAME

Attached automatically by Allegro/APD to an Allegro/APD board (design). The name of theschematic from which the layout logic (netlist) was derived. Cadence recommends that youdo not use this property.

SHIELD_NET

This property causes a "shield" statement to be added to the "net" statement. The value isthe name of the net to use for shielding the net that the property is attached to. Allows theuser to control SPECCTRA.

SHIELD_TYPE

If the property is also a SHIELD_NET property, the value of this property is used in a "type"statement within the "shield" statement. The value should be one of the SPECCTRAkeywords "parallel", "tandem", or "coax". For example in the .dsn file:

(net sig1 ...... (shield on (type parallel) (use_net GND)))

where GND was from the SHIELD_NET property and parallel was from the SHIELD_TYPEproperty. Allows the user to control SPECCTRA.

SHORTING_SCHEME

Attached automatically by APD to selected pins or vias in the nets or subnets that connect topower or ground planes when using the Route – Define Short command.

SIGNAL_MODEL

Attach to a reference designator (component). Name of the Packaged Device Model, whichdefines the electrical, I/O models and package parasitics used by SigNoise to characterizedevices for simulations.

SLOTNAME

Attached automatically to a function by Allegro/APD when loading a preassigned netlist withnetin. During gate assignment, this slot name is the first choice when choosing the slot ina component. This slot name is reserved even after gate assignment and/or swapping, andcan then be compared to the slot that contains the function.



SOLDER_BALL_HEIGHT

Specifies the height of the solder ball of a package. The value is in the current design unit.This property is required for the PNC interface.

SPIF_CONSTANTS

For Cadence internal use only. The value is taken as a colon (:) delimited list. Each value isplaced in the .dsn file as a "constant" statement. It controls nothing in SPECCTRA. (It's usedin our Mentor-to-SPECCTRAQuest interface.)

SPIF_TURRET

For Cadence internal use only. The value is added in a "turret" statement within the "path"statement. It controls nothing in SPECCTRA. (Used in the Mentor-to-SPECCTRAQuestinterface.)

STUB_LENGTH

Attach to ECL nets. The maximum length allowed for a stub, in database units. TheSTUB_LENGTH property overrides the ECL property, which indicates the net does not allowstubs. A value of zero for the STUB_LENGTH property means no stubs.

SUBNET_NAME

Used by APD. Attach to one or more pins on the same net. You identify a subnet with a subnetname, either in the netlist or interactively through the Edit – Properties command.

For example, if pins U4.1, U10.6 and U17.20 have the SUBNET_NAME value called ABC,then those pins form the subnet ABC.



SWAP_GROUP

Attach to a function designator. Controls swapping for functions generated by Concept bodiesthat have the HAS_FIXED_SIZE property. The HAS_FIXED_SIZE property tells theConcept, Compiler, and Packager applications that a single schematic symbol (body) hasmore than one function. The value for SWAP_GROUP is a string.

For example, if you create a schematic using the bodies in the following illustration, any of thefour gates can be swapped in either Swap Group A or Swap Group B, but swapping is notallowed between the two Swap Groups.

The property HAS_FIXED_SIZE = 4B means there are four functions represented by onebody. The fact that multiple functions are represented by a single body needs to be passedto Allegro/APD to control the interactive and automatic swapping algorithms.

Example of Schematic Bodies

During fet2a processing, any schematic body with the HAS_FIXED_SIZE = n property willautomatically be assigned a SWAP_GROUP = x property in Allegro/APD, where x is the logical

path name to the schematic symbol in Concept. Functions within the same swap group canbe swapped with one another but not outside the swap group.

In Allegro/APD, this example translates to four functions within the SWAP_GROUP property,although this represents one half of a 244 Allegro/APD body. Swapping is allowed betweenthe four functions in Swap Group A above or between the functions in Swap Group B but noswaps are allowed between groups A and B.

LS244

A3

A2

A1

A0

Y3

Y2

Y1

Y0

OE

LS244

A3

A2

A1

A0

Y3

Y2

Y1

Y0

OE

Swap Group A Swap Group B

17

15

13

11

19

3

5

7

9

8

6

4

2

1

12

14

16

18



This component contains Swap Group A and Swap Group B and is represented as follows:

SYS_CONFIG_NAME

The system configuration name is saved as a property within the board database.

T_TEMPERATURE

Generated by Thermax and attached to a reference designator (component). Defines thecase top temperature for the component in degrees centigrade.

TEMPORARY_PACKAGE_SYMBOL

SPECCTRAQuest internally generated property. Not user accessible.

TERMINATOR_PACK

Attach to a device (through a device file). Indicates the device contains terminator resistors.Value is TRUE. Used by the terminator assignment program in Allegro/APD to match thecorrect terminator with the appropriate net to be terminated.

The syntax of the TERMINATOR_PACK property in the device file is:

PACKAGEPROP TERMINATOR_PACK

dip20_3

VCC

GND



TESTER_GUARDBAND

Used by the Timing Setup/Hold tab of the Constraint Manager. It can be used to define afudge factor for the setup and hold calculation. The value is in nanoseconds and can beattached to either a net or a pin of a net, where the net is the data net of a timing check.

THERMAL_RELIEF

Automatically added to a thermal connect line by autovoid.

THICKNESS

Attach to a layout cross section. Thermax uses it to derive the thickness of a shape that islocated on a coating subclass.

TIMING_DELAY_OVERRIDE

A user defined delay that can be specified to override any First Switch or Final Settle delaysthat are computed for a net. This value is used by the Constraint Manager when checkingsetup and hold violations for a net.

TOL

Attach to a device (through a device file). The percent tolerance used by the Allegro/APDGenRad interface to prepare the .ckt file.

The syntax of the TOL property in the device file is

PACKAGEPROP TOL <tolerance in percent>

TOPOLOGY TEMPLATE

Attaches to a net. It was used in version 13.6 to record the name of the topology template thatwas assigned to the net. In version 14.0 this information is recorded as part of an ECset butthe property remains for compatibility with 13.6 drawings. This value can be upreved to 14.0ECset assignments using the Audit – Topology Templates command in the ConstraintManager.



TOPOLOGY_TEMPLATE_REVISION

This property is no longer used in 14.0. In this release, a topology template is imported by theConstraint Manager to create an ECset and then the ECset is assigned to nets or Xnet. Therevision of the topology template is now stored as part of the ECset and is therefore no longerstored as a property on the net.

TOTAL_ETCH_LENGTH

Use this property as an override to the constraint by the same name. The value of thisproperty is a string with a format of <min>:<max>, where both <min> and <max> are etchlength values with optional units. If no units are specified, then the units of the drawing will beassumed. Either value is optional. If only a max value is specified, the leading colon isrequired. If only a min value is defined, the trailing colon is optional.

By default, this constraint will be empty, that is, it will contain neither a min nor a max value.The constraint will be visible and active in Allegro expert and designer, APD andSPECCTRAQuest. Edits to the property at the net level will bubble up to the Xnet level.

TS_ALLOWED

Attach to a net. Specifies whether T connections can be made and the location of the Tconnections. Values are:

■ PINS ONLY—Ts are only allowed at a pin. Note that whether Ts are legal at a pin iscontrolled by this net’s schedule.

■ PINS & VIAS ONLY —Ts can only be created at a pin or via.

■ ANYWHERE —Ts can be formed at a pin, via, or on a connect line.

■ NO Ts ALLOWED —Ts are not legal.

This property overrides the constraint rule for all layers. When the property is found on aconnect line, it overrides the constraint value for only that connect line on that subclass.

UNFIXED_PINS

Attached to a board file or symbol drawing or symbol to allow movement of symbol pins inMove or Spin commands. Removal of the property does not undo instance edits.



VALUE

Attach to a discrete device (through a device file). The device value used by the Allegro/APDGenRad interface to prepare the .ckt file.

The syntax of the VALUE property in the device file is

PACKAGEPROP VALUE <device value>

device value is the value of the discrete part, for example, resistance.

VIA_LIST

Attach to a net. A list of the via names (wildcards allowed) that can be used for connectionsin this net.

VOLT_TEMP_MODEL

Attach to a pin. The voltage temperature model for the pin. Used by Viable.

VOLTAGE

Attach to a reference designator (component). The voltage for this component. Used duringanalysis processing. Used by SigNoise.

VOLTAGE_LAYER

Attach to a net. Designates the net as a voltage net. The Prevail pin escape route will use thevalue of the VOLTAGE_LAYER property to designate the plane subclass for which the netshould be considered. Used by Prevail.

VOLTAGE_SOURCE_PIN

Attach to a pin. Identifies the voltage source when there are no independent voltage planes.Used by EMControl.



WEIGHT

Attach to a net. A number from 0 to 100. Allegro/APD uses the weight value during automaticplacement and automatic gate swapping. A high weight value tells Allegro/APD to make thosenets as short as possible.

WIRE_LENGTH

Attach to a net. Specifies the length of a routed connection for calculating a transmission linedelay on a BONDING_WIRE layer. Used by SigNoise.

XTALK_ACTIVE_TIME

Attach to a net. The time when this net is active (changing voltage). Used by SigNoise todetermine when this net will have an effect on other nets. Also used by constraints forcrosstalk analysis.

XTALK_IGNORE_ NETS

Attach to a net. A list of names (wildcards allowed) to be ignored by SigNoise when doingcrosstalk analysis of the net with this property. The ignore names can mean one of thefollowing:

■ A net name

■ The name value of an ELECTRICAL_CONSTRAINT_SET property.

SigNoise ignores a neighbor net as a source of crosstalk if the primary (victim) net hasan IGNORE = NEIGHBOR NET PROPERTY on it. Also used by constraints.

XTALK_SENSITIVE_TIME

Attach to a net. A list of times when this net is noise sensitive to voltage changes of anothernet. Used by constraints and SigNoise to determine when this net will be affected by othernets.



Constraint Manager Properties


CLK_2OUT_MAX Net, Pin no

CLK_2OUT_MIN Net, Pin no

CLK_SKEW_MAX Net, Pin no

CLK_SKEW_MIN Net, Pin no

CLOCK_NET Net yes

DIFFERENTIAL_PAIR Net yes

MAX_SSN Net no

MAX_UNDERSHOOT yes

MAX_UNDERSHOOT Net, Connect Line yes

MAX_VIA_COUNT Net, ECSet yes

MAX_XTALK (MAX_CROSSTALK) Net no

MAX_XTALK (MAX_CROSSTALK) Net, Connect Line no

MIN_FIRST_SWITCH Net, ECSet no

MIN_HOLD Net, Pin yes

MIN_NOISE_MARGIN Net, ECSet yes

MIN_SETUP Net, Pin yes

NET_SCHEDULE Net, ECSet no

PROPAGATION_DELAY Net, ECSet no

PULSE_PARAM Net, Xnet, Bus, Diff Pair no

RATSNEST_ SCHEDULE Net, ECSet no

RELATIVE_PROPAGATION_DELAY Net, ECSet no

STUB_LENGTH Net, ECSet yes

TIMING_DELAY_OVERRIDE Net, Pin no



CLK_2OUT_MAX

The maximum delay from the active clock range at a latch to the output change.

CLK_2OUT_MIN

The minimum delay from the active clock range at a latch to the output change.

CLK_SKEW_MAX

Used by the Timing Setup/Hold tab of the constraint manager. Defines the maximum skew inthe clock signal between the launching and latching components. This property defines avalue in nanoseconds and can be attached to either the data net or a pin in the data net.

CLK_SKEW_MIN

Used by the Timing Setup/Hold tab of the constraint manager. Defines the minimum skew inthe clock signal between the launching and latching components. This property defines avalue in nanoseconds and can be attached to either the data net or a pin in the data net.

CLOCK_NET

The CLOCK_NET property is related to the SpecctraQuest timing spreadsheet and the File –Import – Timing command. The Import Timing command adds this property on a net to storethe name of the net that is used to clock the net’s data.

For example, if there is a net DATA1, that is clocked by net CLOCK1, then DATA1 would getthe CLOCK_NET property added with the a value of CLOCK1.

TOTAL_ETCH_LENGTH Xnet, net, bus or diff pair yes

XTALK_ACTIVE_TIME Net, ECSet no

XTALK_IGNORE_ NETS Net no

XTALK_SENSITIVE_TIME Net, ECSet no




DIFFERENTIAL_PAIR

Attach to a net. The name of the differential pair. To create a differential pair, assign two netswith a DIFFERENTIAL_PAIR property that have the same name. Used by automatic routingand constraint checking.

MAX_SSN

Attach to a net. The maximum noise allowed on a net due to simultaneous switching.

MAX_UNDERSHOOT

Attach to a net or connect line. The maximum undershoot tolerated by this net. Undershootis a voltage swing back into the mid-range after the nominal steady state high or low level hasbeen crossed. The default value is 250 mV.

MAX_VIA_COUNT

Attach to a net. The maximum via count for a net.

MAX_XTALK (MAX_CROSSTALK)

Defines the high and low state maximum crosstalk constraints. Value is a string. The formatof the string is


See also MAX_PEAK_XTALK (MAX_PEAK_CROSSTALK).

MIN_FIRST_SWITCH

Attach to a net. Defines the minimum first switch delay for driver/receiver pin pairs in the Xnetof which this net is a part. A minimum first switch delay for a rising (falling) edge is the timefrom when the driver starts switching to when the receiver first passes the Vil (Vih) switchingthreshold.

The format of the MIN_FIRST_SWITCH property in the $A_PROPERTIES section of a netlistis

MIN_FIRST_SWITCH [[pin1]:[pin2]:delay:]... ; netname






delay The minimum first switch delay constraint that is to be applied tothe specified driver/receiver pin pairs. This is a decimal numberdefining delay in nanoseconds.

netname Name of a net that is part of the Xnet to which the min first switchconstraint is to be applied.

MIN_HOLD

Used by the Timing Setup/Hold tab of the Constraint Manager. It defines the minimum holdtime of a data signal relative to a clock signal. The value of the property is in nanosecondsand can be attached to either the data net or a pin of the data net.

MIN_NOISE_MARGIN

Attach to a net. The minimum noise margin tolerated by this net. The default value is 0 mV.

MIN_SETUP

Used by the Timing Setup/Hold tab of the Constraint Manager. It defines the minimum setuptime of a data signal relative to a clock signal. The value of this property is in nanosecondsand can be attached to either the data net or a pin of the data net.

NET_SCHEDULE

Works with RATSNEST_SCHEDULE and reflects if the DRC system ensures that the schedulewas met when the net is routed. Values are Verify or Do Not Verify. For moreInformation, see RATSNEST_ SCHEDULE on page 85.



PROPAGATION_DELAY

Note: This property replaces DELAY_RULE beginning with Allegro/APD version 14.0.

Defines the minimum and maximum propagation delay constraint between any pair of pins orrat-Ts in an extended net (Xnet). Value is a string, the format of which is

<pin_pairs>:<min>:<max>[<pin_pairs>:<min>:<max>]...

where each <pinpairs>:<min>:<max> defines a minimum and maximum propagationdelay constraint between one or more pin or rat-T pairs in an extended net. The format for<pin_pairs> is:

<pin_pair> defines a generic pin or rat-T pair

AD:AR every driver and receiver pin pair in the extended net

D:R the longest and shortest driver and receiver pair in the extendednet

L:S the longest and shortest pin pairs in the extended net (previouslydefined as "::")

The <min> and <max> fields define the minimum and maximum propagation constraintsapplied to the selected pin pairs—except when the D:R and L:S pin pair formats are specified.When the latter is the case, the <min> value is applied only to the shortest pin pair and the<max> value is applied only to the longest pin pair. Both the <min> and <max> values areformatted as <value_with_units> where the legal value types are:

PROP_DELAY the constraint is a delay value

PERCENTAGE the constraint is a percentage of the manhattan distancebetween the pins

DB_DIMENSION the value is a length measurement

If the <min> and <max> value has no units, it is assumed that the value is aDB_DIMENSION and the units of the drawing are design units.

Either the <min> or <max> field can be omitted as long as the colon separators arespecified.



PULSE_PARAM

This is used by the Net – Timing – Setup/Hold tab of the Constraint Manager spreadsheetto store the description of a clock pulse. The value of this property is a string of the followingformat:

<frequency>:<duty_cycle>:<jitters>:<cycle_to_measure>

RATSNEST_ SCHEDULE

Attach to a net. The type of ratsnest calculation to be done by Allegro/APD for this net.Thepossible values are:

■ MIN_TREE indicates the net should be ratsnested with the minimum spanning treealgorithm. This can form Ts at pins.

■ MIN_DAISY_CHAIN indicates a minimum length daisy-chain schedule is to be formed.

■ SOURCE_LOAD_DAISY_CHAIN indicates that a source-to-load ECL daisy-chainschedule is to be used.

■ FAR_END_CLUSTERwill automatically place a single Tpoint in a schedule at a calculatedlocation.

The Tpoint is automatically placed when the last component on net is placed. No ratsnestwill be visible until then. All pins with a PINUSE = INPUT will be scheduled from theTpoint. If there are multiple drivers present they will be classified as main line and otherdrivers. The main line driver is the longest driver/receiver pair on the net. All other driversare daisy chained together. If there is a terminator pin on the net it will be connected tothe Tpoint.

If it is not referenced in a DELAY_RULE the Tpoint will be placed along the main lineapproximately 90% from the main line driver to the furthest receiver pin.

If there is a terminator pin on the net, but the net has no driver pin present, the net isterminated. In this case the terminator pin is scheduled first, as the main line driver.

Driver1

Driver2

Driver3 Load1

Load2

Load3

Ratsnest line: Main Line Driver:

Tpoint



STAR specifies a ratsnest similar to FAR_END_CLUSTER without the Tpoint added.

All of the driver pins are daisy-chained together and all of the receiver pins are connectedto one end of the daisy- chain.

The following will be the designation of pins with the pinuse for the STAR andFAR_END_CLUSTER algorithms:

■ Power, ground, loadout, tri, OCA, OCL will all be treated as DRIVERs

■ Loadin pins are always LOADs

■ Pins with BI will always be DRIVERS, unless there are no LOADs and no unspecifiedpins.

■ Unspecified pins are always LOADS, unless there are no DRIVERS and no BIs.

■ If there are no DRIVERS and no LOADS, all pins will be daisy-chained together.

Be aware of the following special conditions related to the RATSNEST_SCHEDULEproperty:

■ If there is no RATSNEST_SCHEDULE property specified for a net, then a MIN_TREEschedule is assumed.

■ If a MIN_TREE schedule is selected explicitly or by default and the TS_ALLOWEDconstraint has been set to TS_NOT_ALLOWED, then a MIN_DAISY_CHAIN schedule isgenerated instead.

■ If a MIN_TREE schedule is selected explicitly or by default and the net contains an ECLproperty, then the SOURCE_LOAD_DAISY_CHAIN schedule is generated instead.

■ The NORAT net property still operates normally and independently of theRATSNEST_SCHEDULE constraint.

■ If a net’s schedule is user defined, then Allegro/APD ignores the value of theRATSNEST_SCHEDULE constraint.

RELATIVE_PROPAGATION_DELAY

This property replaces MATCHED_DELAY in version 14.0. Electrical constraint attached topin pairs on a net. Specifies a group of pin pairs that are required to have interconnectpropagation delays that match a specified delta (offset) and tolerance. ARELATIVE_PROPAGATION_DELAY group has one or more reference pin pairs againstwhich all other pin pairs in the group are compared.

The format of a relative propagation delay as a property is



<gp>:<scope>:<p1>:<p2>:<delta>:<tol>[:<gp>:<scope>:<<p1>:<p2>:<delta>:<tol>]...

Where:

gp Defines the name of the matched group

scope Defines whether the constraint is unique to a net or extended net,or global to the entire design. Legal values are

L for local to the net/extended net

G for global to the design. This value has meaning only forconstraint values that come from a constraint set. When"flattened" to a specific net/extended net, the group name ismodified to make it unique for the net if the scope value is L. Ifthe value is G, the group name is assigned as is. If the scopevalue is omitted, L is assumed.

<p1>/<p2> Defines the two pins and/or rat_Ts in the pin pair. These can bespecific pins AD:AR, D:R, or L:S

The pin1 and pin2 syntax supports the following variations for defining pin pairs:

pin1:pin2 Add the specified pin pair to the matched group. Specify therefdes and pin number for both pins of the pin pair. Either pin'srefdes and pin number can reference a T point, which is specifiedas T.<number>. Both pins or T points must be a part of the net towhich the property is attached.

D:R Add the longest driver/receiver pin pair combination in the net tothe matched group. If no driver/receiver pin pairs are found, treatthe property value as if the group ::: tolerance format wasspecified.

AD:AR Add every driver/receiver pin pair combination in the net to thematched group. If no driver/receiver pin pairs are found, treat theproperty as if the group ::: tolerance format was specified.

L:S Add the longest pin pair in the net to the matched group. Allterminator pins in the net are ignored in the search for the longestpin pair.

delta is the delta expressed as either a delay or a length. If notspecified, a default of 0 is assumed.



tol is the tolerance of the match expressed as either a delay, alength, or a percentage. If not specified, a default of 5% isassumed.

One pin pair is always selected as the target pin pair. following these rules:

■ If only one pin pair has no delta value, it is selected.

■ If all of the pin pairs have delta values, the pin pair with the smallest delta is selected.

■ If there is more than one pin pair with the smallest delta value, the one with the longestpin pair length is selected.

■ If there is more than one pin pair without a delta value, the one with the longest pin pairlength is selected.

The CHECK_MIN_DELAYS environment variable associated with the obsolete MAX_DELAYconstraint does not apply to relative delays. Instead, you can usethe environment variableCHECK_UNROUTED_RELATIVE_PROP_DELAYS when youwant the DRC checker to check unrouted pin pairs based on themanhattan distance of their ratsnest connections.

STUB_LENGTH

Attach to ECL nets. The maximum length allowed for a stub, in database units. TheSTUB_LENGTH property overrides the ECL property, which indicates the net does not allowstubs. A value of zero for the STUB_LENGTH property means no stubs.

TIMING_DELAY_OVERRIDE

A user defined delay that can be specified to override any First Switch or Final Settle delaysthat are computed for a net. This value is used by the Constraint Manager when checkingsetup and hold violations for a net.

TOTAL_ETCH_LENGTH

Use this property as an override to the constraint by the same name. The value of thisproperty is a string with a format of <min>:<max>, where both <min> and <max> are etchlength values with optional units. If no units are specified, then the units of the drawing will be



assumed. Either value is optional. If only a max value is specified, the leading colon isrequired. If only a min value is defined, the trailing colon is optional.

By default, this constraint will be empty, that is, it will contain neither a min nor a max value.The constraint will be visible and active in Allegro expert and designer, APD andSPECCTRAQuest. Edits to the property at the net level will bubble up to the Xnet level.

XTALK_ACTIVE_TIME

Attach to a net. The time when this net is active (changing voltage). Used by SigNoise todetermine when this net will have an effect on other nets. Also used by constraints forcrosstalk analysis.

XTALK_IGNORE_ NETS

Attach to a net. A list of names (wildcards allowed) to be ignored by SigNoise when doingcrosstalk analysis of the net with this property. The ignore names can mean one of thefollowing:

■ A net name

■ The name value of an ELECTRICAL_CONSTRAINT_SET property.

SigNoise ignores a neighbor net as a source of crosstalk if the primary (victim) net hasan IGNORE = NEIGHBOR NET PROPERTY on it. Also used by constraints.

XTALK_SENSITIVE_TIME

Attach to a net. A list of times when this net is noise sensitive to voltage changes of anothernet. Used by constraints and SigNoise to determine when this net will be affected by othernets.


pcb systems properties referencestatistics.roma2.infn.it/~sabene/cadence...

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