pcb design compass...pcb design compass . location gars 5 2 base materials we use these materials...

PCB DESIGN COMPASS KSG Gars · 2019

PCB Design Compass . location Gars 3

TABLE OF CONTENTS1 Data ..................................................................................4

1.1 Scope of data …………………………………… 41.2 Data formats …………………………………… 4

2 Base materials ...............................................................52.1 Rigid base materials ……………………………… 52.2 Flexible base materials …………………………… 6

3 Panel layout / formats ...................................................73.1 Sub-panel ……………………………………… 73.2 Production format ……………………………… 93.3 Usable production area / formats ………………… 9

4 Multilayer Boards/HDI ...............................................104.1 Multilayer boards with up to 28 layers …………… 104.2 Microvia boards ………………………………… 114.3 Plugged PCBs …………………………………… 154.4 Impedance-controlled PCBs ……………………… 164.5 Design rules ……………………………………… 18

5 Rigid-flex PCBs ...........................................................255.1 Stack up ………………………………………… 255.2 Design rules ……………………………………… 275.3 ZIF (zero insertion force connectors for rigid-flex) … 285.4 Processing recommendations …………………… 295.5 Application guidelines …………………………… 29

6 Semiflexible PCBs ......................................................306.1 Stack ups ………………………………………… 306.2 Design rules ……………………………………… 316.3 Application guidelines …………………………… 31

7 High current technology ...........................................327.1 Areas of application for HSMtec ………………… 327.2 Stack up ………………………………………… 337.3 Design rules ……………………………………… 337.4 Current-carrying capacity ………………………… 357.5 Multidimensional HSMtec PCBs ………………… 367.6 Reliability ……………………………………… 36

8 Solder mask .................................................................378.1 Solder mask design ……………………………… 38

9 Surface finish ..............................................................399.1 Electroless nickel immersion gold (ENIG) ………… 399.2 Chemical tin ……………………………………… 399.3 Electroplated nickel / gold ………………………… 409.4 Reductive gold …………………………………… 419.5 Hot air levelling (leaded/lead-free) ………………… 41

10 Additional printing ......................................................4210.1 Inkjet identification printing ……………………… 4210.2 Identification and surface screen printing ………… 4210.3 Surface printing with white solder mask ………… 4310.4 Through-hole printing / closing of vias …………… 4310.5 Peelable solder mask / masking tape ……………… 44

11 Drilling ...........................................................................4511.1 Through-hole …………………………………… 4511.2 Microvia ………………………………………… 4611.3 Blind vias (mechanically drilled) …………………… 46

12 Contour processing ....................................................4712.1 Milling …………………………………………… 4712.2 Scoring ………………………………………… 4812.3 Gold ridge bevelling ……………………………… 49

13 Quality ...........................................................................5013.1 Quality standard ………………………………… 5013.2 Process control and regulation …………………… 5113.3 Product control …………………………………… 52

14 Technical services .....................................................53

The KSG Technology Guide contains the standardised information concerning the scope of supplies and services of our PCB production. We would be pleased to discuss any additional requirements with you personally.

4 PCB Design Compass . location Gars

1 DATA

According to the principle “as much as necessary, but as little as possible”, please provide us with the following information:

• Details of the topography of the PCB, e.g. the course of the tracks or the position of the solder pads and SMD pads

• Drilling data (Excellon or Sieb&Meyer format)• Specification of product-related features (e.g. material thickness,

copper lamination)• Details of deviations from the customer standard• Drawing with details of all mechanical processing (scoring,

countersinks, cut-outs....)

By providing the most precise information possible, you can avoid time-consuming queries and create the optimum conditions for a quick start of production.

Some data formats require additional information:

If this information is missing, further processing of your order will only be possible after consultation with you.

An exact data output (the highest possible number of decimal plac-es) prevents errors and inaccuracies in the layout.

Data format

Gerber RS-274-X

Gerber X2

ODB++

DPF

Data format Additional information required

Gerber RS-274-D Aperture information

HPGL/DXF Indication of pen widths

EagleIndication of Eagle versionLayer listIndication of the layers to be output

The customer data forms the basis for the fabrication of the PCB.

In principle, you can send us any standard data format. A majority of our customers, however, have come to appreciate the fast and smooth processing offered by the following formats:

1.1 Scope of data

1.2 Data formats


2 BASE MATERIALS

We use these materials for the fabrication of multilayer boards, single and double-sided PCBs, rigid-flex PCBs, and semi-flex PCBs.

2.1 Rigid base materials

EPOXY WOVEN GLASS FABRIC

FR4 Tg 135 °C FR4 Tg 150 °C halogen free

Dielectric constant εr at 1 MHz 4.6 - 4.9 4.95

Loss tangent tanδ at 1 MHz 0.019 0.011

Tracking resistance CTI Level 200 Level 500

Minimum electrical resistance 39 kV/mm 49 kV/mm

Dielectric strength (at material thickness ≥ 0,5 mm) 45 kV > 50 kV

Flammability classification UL 94V-0 UL 94V-0

Thermal expansion z-direction (50-260 °C) 4.1 % 2.4 %

Thermal conductivity λ 0.25 W/mK 0.63 W/mK

Multilayer boards

Copper films: 5 µm – 105 µm

Cores: 50 µm – 1.2 mm (excl. copper lamination 18, 35, 70, 105 µm)

Prepregs: 50 µm – 180 µm

Plated-through PCBs Laminates: 0.8 mm – 3.2 mm incl. copper lamination (18, 35, 70, 105 µm)

2.1.1 Material thicknesses


We use these materials in combination with rigid base materials for the fabrication of rigid-flex PCBs.

2.2 Flexible base materials

COPPER-LAMINATED MATERIAL COVER LAYER FLEX MASK

Nikaflex F-30V Pyralux AP Pyralux LF Pyralux FR SunFlex SD

Material Polyimide (PI) Polyimide (PI) Polyimide (PI) Polyimide (PI) Polyimide (PI)

Dielectric constant εr at 1 MHz 3.4 - 3.8 3.4 3.6 - 4.0 3.5 3.44

Dielectric strength min. 2 kV/mil 6 – 7 kV/mil min. 2 kV/mil min. 3.5 kV/mil 130 V/µm (50 Hz)

Flammability classificationUL94V-0UL94VTM-0

UL94V-0 --- UL94VTM-0 UL94V-0

Material thickness [µm] excl. base copper

50 50 25 25On track edge ≥ 5 µm

Electrolytic copper [µm] 18; 35 18; 35 --- --- ---

Adhesive thickness [µm] --- --- 50; 75 50; 75 ---


3 PANEL LAYOUT / FORMATSPanel-based processing makes the automated production of your electronic device more cost effective, especially in the case of small piece dimensions or formats with unusual contours.

KSG manufactures the subsequent breakaways (= predetermined break points) for separation into individual pieces. After separation, the PCBs will have scored or milled edges.

With a sub-panel, multiple PCBs are combined to form a unit and are only separated into individual pieces following the subsequent assembly process. Always clarify the panel layout with your assembler. Place tool holes in the edge of the panel to allow your assembler to accommodate the sub-panel.

The boards are placed together without any distance and then scored.Creating a scored panel makes the best possible use of the available space, but only straight lines can be scored.

Recommendation for transport during assembly:We recommend a minimum width of 5 mm for transport edges.For the panel corners, we recommend bevelling by means of mil-ling. The radii are negligible.

3.1 Sub-panel

Single unit Sub-panel = step and repeat panel

3.1.1 Scored panel

Scored edge Milled edge

Sub-panel 1Sub-panel 2


Breakaway tabSeparating slot

Separating holes

Separating slotBreakaway tab

The PCBs are placed together with identical distance and, apart from a few tabs, are milled out of the panel. The stability of the panel is ensured by having a sufficient number of tabs with a uniform distribution.The breakaway tabs are implemented in accordance with the customer data. Here are two examples:

This variant can be used cost-effectively if some contours have irregular shapes (e.g. recesses, radii – separation by milling), while other contours on the PCB are straight (separation by scoring). Straight sides should, however, be milled if a smooth contour edge and close tolerances are required (e.g. for PCB mounting purposes).

Milled breakaway tab

Milled breakaway tab with separation holes

3.1.2 Milled panel with breakway tabs

3.1.3 Combination of scored and milled panel


To increase cost-effectiveness, we combine individual PCBs or sub-panels to form a production panel. In so doing, we seek to achieve the best possible utilisation of the available production format. We then separate the production panel into the ordered units (sub-panels) prior to the electrical test by means of scoring or milling, in accordance with your specifications.

3.2 Production format

3.3 Usable production area / formats

Useable production area

Distance between the PCBs:separation by milling: 10 mmseparation by scoring: 0 mm

Sub-panel Sup-panels in the production format

Plated-through PCBs HSMtecMicroviaMultilayer

578 x 498 mm578 x 428 mm

Semiflexible PCBRigid-flex PCB

578 x 428 mm


KSG manufactures multilayer boards with up to 30 layers. Stack up is performed using the core materials, prepregs and base copper films specified in section 2.1 “Rigid base materials”. There should be at least two prepreg layers between the copper layers. The thickness of the prepreg layer should be at least equal to the thickness of the copper height of the inner layers + 50 µm.

The total thickness of a multilayer board is dependent on a variety of parameters, and can only be determined very imprecisely by adding the materials together. In the case of critical applications, please consult our engineers.

4 MULTILAYER BOARDS/HDI

4.1 Multilayer boards with up to 30 layers

DEFAULT VALUES FOR MULTILAYER AND MICROVIA BOARDS

Materials see 2.1.1

Final copper and tolerance

According to IPC 6012 current edition Class 2

Total thickness (incl. final copper and solder mask)

0.8 mm – 3.2 mm

Tolerances0.8 mm – 2.0 mm ± 10% > 2.0 mm – 3.2 mm ± 0.2 mm

max. number of layers 30

Base Copper

Prepeg

Core

Prepeg

Core

Prepreg

Base copper

Ever smaller components with increasing clock frequencies require impedance-controlled tracks, as well as EMC and signal integrity. Multilayer boards and HDI technology make it possible to separate the analogue and digital parts of a PCB.


4.2 Microvia boards

Advantages of microvia technology• Faster routing of the PCB layout (reduced costs)• Reduction of the number of layers• Reduction in track lengths and improved EMC behaviour of the

assembly• Reduction of assembly effort thanks to denser single-sided

device• More free space for EMC measures and shielding surfaces as a

result of less space being required for tracks

This is the cheapest way of integrating microvias in a layout. The entire multilayer board can be manufactured in one pressing process. Fabrication sequence:1. Lamination of L1 to Ln2. Drilling from L1 to Ln and drilling of microvias3. Plating through of holes (L1 to Ln) and microvias

4.2.1 Stack ups up to 1-x-1

Microvias in combination with through-holes

Ln

Ln-1

Ln-2

L3

L2

L1

Prepreg

Core

x layers

Core

Prepreg

Variable stack up withprepregs and cores

M 50 : 1

According to IPC-2226, the term “microvia” refers to the following layout geometries:• Via diameter ≤ 0.15 mm • Pad diameter ≤ 0.35 mmMicrovias require only around a quarter of the area of conventional holes. The pad size of microvias depends on the distance of the layers to be bonded.

For example: Pad diameter ≥ 300 µm at prepreg height of 63 µmPad diameter ≥ 320 µm at prepreg height of 100 µm

≥ 300 µm L2

max. 100 µm

L1

Aspect Ratio max. 1:1

With a prepreg height of 63 µm, the inner layer must be flooded with copper (e.g. Vcc, GND etc.)

Combinations with other technologies such as rigid-flex are possib-le. This can be agreed with us during the layout and design phase.


Microvias in combination with buried via cores and through-holes

Microvias in combination with buried vias and through-holes

Fabrication sequence:1. Drilling of plated-through cores2. Plating through of cores3. Lamination of L1 to Ln

4. Drilling from L1 to Ln and drilling of microvias L1/Ln5. Plating through of holes (L1 to Ln) and microvias L1/Ln

Fabrication sequence:1. Lamination of L2 to Ln-12. Drilling from L2 to Ln-13. Plating through of holes (L2 to Ln-1)

4. Lamination of L1 to Ln5. Drilling from L1 to Ln and drilling of microvias L1/Ln6. Plating through of holes (L1 to Ln) and microvias L1/Ln

Ln

Ln-1

Ln-2

L3

L2

L1

Prepreg

Core

x layers

Core

Prepreg

Buried ViaCore


Buried ViaCore

M 50 : 1

Ln

Ln-1

Ln-2

L3

L2

L1

Prepreg

Prepreg

x layers

Prepreg

Prepreg

Buried viasfrom

L2 to Ln-1


M 50 : 1


Staggered microvias in combination with buried vias and through-holes

Stacked microvias in combination with buried vias and through-holes

Fabrication sequence:1. Lamination of L3 to Ln-22. Drilling from L3 to Ln-23. Plating through of holes (L3 to Ln-2)4. Lamination of L2 to Ln-1

5. Drilling of microvias L2/Ln-16. Plating of microvias L2/Ln-17. Lamination of L1 to Ln8. Drilling from L1 to Ln and drilling of microvias L1/Ln9. Plating through of holes (L1 to Ln) and microvias L1/Ln

Fabrication sequence:1. Lamination of L3 to Ln-22. Drilling from L3 to Ln-23. Plating through of holes (L3 to Ln-2)4. Lamination of L2 to Ln-1

5. Drilling of microvias L2/Ln-16. Plating and filling of microvias L2/Ln-17. Lamination of L1 to Ln8. Drilling from L1 to Ln and drilling of microvias L1/Ln9. Plating through of holes (L1 to Ln) and microvias L1/Ln

Ln

Ln-1

Ln-2

Ln-3

L4

L3

L2

L1

Prepreg

Prepreg

Prepreg

x layers

Prepreg

Prepreg

Prepreg

Buried viasfrom

L3 to Ln-2


M 50 : 1

Ln

Ln-1

Ln-2

Ln-3

L4

L3

L2

L1

Prepreg

Prepreg

Prepreg

x layers

Prepreg

Prepreg

Prepreg

Buried viasfrom

L3 to Ln-2


M 50 : 1

A space-saving design can be achieved by staggering microvias over several layers.

For a space-saving layout, it is possible to stack vias. For this purpose, vias are filled with copper, if possible completely, in a special process called “via filling”.

4.2.2 Stack ups 2-x-2


4.2.3 Stack ups 3-x-3

Staggered and/or stacked microvias in combination with buried vias and through-holes

Fabrication sequence:1. Lamination of L4 to Ln-32. Drilling from L4 to Ln-33. Plating through of holes (L4 to Ln-3)4. Lamination of L3 to Ln-25. Drilling of microvias L3/Ln-26. Plating of microvias L3/Ln-2

7. Lamination of L2 to Ln-18. Drilling of microvias L2/Ln-19. Plating of microvias L2/Ln-110. Lamination of L1 to Ln11. Drilling from L1 to Ln and drilling of microvias L1/Ln12. Plating through of holes (L1 to Ln) and microvias L1/Ln

We recommend to align these layer stack ups with us during layout- and design-process.

M 50 : 1

i)

n)

o)

h)

g)

k)

l)

p)

d)

e)

c)

b)

c)

a)

f)

m)

f)

j)

q)

j)

Prepreg

Prepreg

Prepreg

Prepreg

x layers

Prepreg

Prepreg

Prepreg

PrepregBuried vias

from L4 to Ln-3


a) up to 30 layers; stack ups up to 3-x-3; thickness 0.8 – 2.4 mmb) min. diameter buried-vias ≥ 200 µmc) min. padsize on inner layer ≥ 500 µmd) min. drilling diameter ≥ 200 µme) min. pad diameter on outer layer ≥ 470 µmf) Aspect Ratio PTH: ≤ 1:10g) min. laser via diameter ≥ 100 µmh) min. pad for laser vias ≥ 300 µmi) dielectric between two layers ≥ 50 µmj) final copper on outer layer ≥ 35 µm

k) min. track width on outer layer ≥ 90 µml) min. distance (track to track) on outer layer ≥ 90 µmm) copper on inner layer ≥ 18 µmn) min. track width on inner layer with 35 µm copper ≥ 90 µm min. track width on inner layer with 18 µm copper ≥ 75 µmo) min. distance on inner layer with 35 µm copper ≥ 90 µm min. distance on inner layer with 18 µm copper ≥ 75 µmp) Clearance, distance between the hole and the inner layer copper ≥ 275 µmq) surface finish: ENIG, chem. tin, reductive gold


4.3 Plugged PCBs

Fabrication sequence:1. Drilling of buried vias L2 – Ln-12. Plating through of holes to be covered3. Filling of buried vias L2 – Ln-1 with epoxy paste4. Curing5. Sanding and cleaning the surface of plugging paste6. Copper-plating of surface L2 and Ln-17. Etching of pattern8. Lamination L1 - Ln

9. Drilling of holes to be covered10. Plating through of holes to be covered11. Filling of holes with plugging paste12. Curing13. Sanding and cleaning the surface of plugging paste14. Copper-plating of surface15. Drilling of through-holes16. Copper-plating of surface and through holes

The complete, planar and permanent covering of holes with copper on inner and outer layers opens up new possibilities in PCB design. Plugging a buried via on the inner layers allows component pads to be conducted to this buried via, thus making a higher integration density possible for HDI applications. With via-in-pad technology (plugging of blind vias or plated through holes on outer layers), components can be placed directly over the vias.

Ln

Ln-1

Ln-2

L3

L2

L1Prepreg

Prepreg

Prepreg

Prepreg

x layersVariable stack up with prepregs and cores

Filled Via

Filled Buried Via

M 50 : 1

This PCB is in accordance with IPC 4761, Filled and Capped Via, Type VII.


4.4 Impedance-controlled PCBs

In terms of the layer stack up and conductor structure, impedance-controlled circuits (high-speed applications) can be produced using various techniques.The thickness of the dielectric and the track width/length have a significant influence on the impedance value.

The dielectric constant and the copper height have a smaller effect. In differential structures (two parallel tracks), the distance between tracks should also be taken into account. Furthermore, the thickness and the dielectric constant of the solder mask can also have an influence (in the case of “microstrip lines”).

Based on our many years of expertise, and using state-of-the-art equipment from Polar Instruments (CITS900S4), we calculate and simulate the signal integrity of high-speed signals and adjust the layer stack up and track geometries to the required impedance behaviour.

43%

4%

5%

5%

4%

61% 48%

30%

Substrate thickness

Microstripline Impedance calculated tracks on outer layers

StriplineImpedance calculated tracks on inner layers

Track width Dielectric constant Track height

4.4.1 Variables influencing the impedance value

4.4.2 Implementation at KSG

Additional identification of impedance tracks in the layout is beneficial.


a................. Track width (base)b................. Track width (top)c, c1, c2 ..... Width of the dielectric εr ............... Dielectric constant of the dielectricd................. Copper heighte1............... Coating thickness of solder mask

on base material

e2............... Coating thickness of solder mask on tracke3............... Coating thickness of solder mask on base material

between the trackseεr .............. Dielectric constant of solder maskf ................. Distance between tracks at the base

d c1

c2

a a

fb

b

εr

εr

εr

εr

c

a

e2fb

d e3

e1

εr

eεr

εre2

e1

d

a

b

eεr

Offset Stripline Edge-Coupled Offset StriplineCoated Microstrip Edge-Coupled Coated Microstrip

The figure below shows four of the various options for an impedance-controlled stack up. With an asymmetrical stack up (a single track, “single-ended”), resistance values of around 50 – 70 Ω are normal. With differential structures (two parallel tracks), an impedance value of around 90 – 110 Ω is calculated. On account of manufacturing tolerances, a tolerance of ± 10% of the calculated resistance value is standard practice. The following drawings show the values required for the theoretical calculation.

If you wish to check the calculated impedance behaviour of your PCB, we can manufacture an individual board on the production panel as a test coupon. Thanks to its compact size, the test coupon specially designed by KSG makes it possible to achieve a more efficient PCB format layout.

You will receive the specific measurement and tolerance values in the form of a test report.

4.4.3 Stack up


4.5 Design rulesba

se c

oppe

r

final

cop

per 1

Track-Track min.

2Pad-Track min.

3Pad- Pad min.

4Track width min.

µm µm µm mil µm mil µm mil µm mil

Inner layers

18 18 75 3.0 75 3.0 75 3.0 75 3.0

35 35 90 3.5 90 3.5 90 3.5 90 3.5

70 70 125 4.9 125 4.9 125 4.9 150 5.9

105 105 200 7.9 200 7.9 200 7.9 200 7.9

Outer layers

5 35 90 3.5 90 3.5 90 3.5 90 3.5

12 40 100 3.9 100 3.9 100 3.9 100 3.9

35 70 150 5.9 150 5.9 150 5.9 175 6.9

70 105 225 8.9 225 8.9 225 8.9 250 9.8

105 140 275 10.8 275 10.8 275 10.8 300 11.8

43

2 1

1

“Clearance” is the distance between the hole wall and the inner layer copper.

8

7

6

9

5

41

23

1

M 25 : 1

Plated-hole

Non-plated-

hole

Extract from IPC A600: “The distance between the inner layer copper and the copper sleeve is greater than or equal to 0.1 mm (when a value is not specified by the procurement documentation).”

1 min. distance “track to track” 2 min. distance “pad to track” 3 min. distance “pad to pad” 4 min. track width

4.5.1 Printed circuit board layout

4.5.2 Clearance

The values shown are data values. The fabricated structures will deviate by the tolerance values in the manufacturing process. Please consult our engineers.

Description NPT drill hole

Layers Inner layers (8) Outer layers (9)

Min. Clearance 225 µm 250 µmPT drill hole: Final drill diameter ≥ 100 µm

In all cases, higher values are desireable!

Description PT drill hole Min. inner layer clearance

Min. inner layer value from centre

of drill holeClearance =

Min. distance

(as per IPC)+

Inner layer fabrication tolerance

Min. inner layer pad Ø

Final Ø (5) Drilling Ø (4) (3) (2) (1) (6) (7)

Example 1 100 µm 250 µm 650 µm 325 µm 275 µm = 100 µm + 175 µm 550 µm




The values shown are data values. The fabricated structures will deviate by the tolerance values in the manufacturing process.Please consult our engineers.

8

7

5

6

4

3

2

1

Base copper1

Final copper

2Min. annular

ring

µm µm µm mil

5 35 200 7.9

12 40 200 7.9

35 70 235 9.3

70 105 275 10.8

105 140 310 12.2

1Final copper on outer and inner

layers

5Pad diameter outer layers

min.

6Pad diameter inner layers

min.

7Final diameter (hole tolerance –0,05/+0,1 mm)

8Drilling diameter

PCB thickness

up to

µm mm mil mm mil mm mil mm mil mm

35 0.50 19.7 0.55 21.7 0.10 3.9 0.25 9.8 1.6

70 0.57 22.4 0.62 24.4 0.10 3.9 0.25 9.8 1.6

Example: Relationship between solder pad diameter and final drill diameter

Outer layers Inner layers

Annular ring and pad size are dependent on the copper plating thickness. For IPC Class 3, the increased copper deposition should be taken into account (see Copper plating thicknesses, sections 4.5.8 and 4.5.9).

4.5.3 Annular ring and pad size

Base copper3

Final copper

4Min. annular

ring

µm µm µm mil

18 18 215 8.5

35 35 225 8.9

70 70 260 10.2

105 105 310 12.2


4.5.4 BGA-FAN-OUT

1

2

5

4

3

3

8

9

67

10

11

2nd Inner layer1st Inner layerViasOuter layerM 10 : 1

1BGA pitch

2BGA pad

(solder pad)

3Position of via

pad

4Drilling diameter

5Min. via pad outer layer

6Min. via pad inner layer

mm mil mm mil mm mil mm mil mm mil mm mil

1.00 39.4 0.50 19.7 0.500 19.7 0.25 9.8 0.50 19.7 0.55 21.7

0.80 31.5 0.40 15.7 0.400 15.7 0.25 9.8 0.50 19.7 0.55 21.7

0.80 31.5 0.35 13.8 0.400 15.7 0.25 9.8 0.50 19.7 0.55 21.7

0.75 29.5 0.33 13.0 0.375 14.8 0.25 9.8 0.50 19.7 0.55 21.7

0.65 25.6 0.27 10.6 0.325 12.8 0.25 9.8 0.48 18.9 0.50 19.7

1 BGA pitch

7 Min. distance BGA pad - via

pad

8 Min. track width

outer layer

9Min. track width

inner layer

10Min. inner layer: Distance via pad

to track

11Inner layer:

Distance hole-track


1.00 39.4 0.100 3.9 0.115 4.5 0.110 4.3 0.100 3.9 - -

0.80 31.5 0.100 3.9 0.115 4.5 0.110 4.3 - - 0.220 8.7

0.80 31.5 0.100 3.9 0.115 4.5 0.110 4.3 - - 0.220 8.7

0.75 29.5 0.100 3.9 0.115 4.5 0.110 4.3 - - 0.193 7.6

0.65 25.6 0.085 3.3 0.115 4.5 0.090 3.5 - - *) *)

Vias in a dog bone design must always be positioned in the square centre of the BGA solder pad. This guarantees optimum solder mask design and solder dam, and thus an optimum soldering process.

*) No tracks can be routed between two vias placed in a grid of 0.65 mm pitch, due to required clearance distance (point 4.5.2). If one via position will be left out in a grid of 0.65 mm, tracks will be doable again.


1BGA pitch

2Min. via pad outer layer

3Drilling diameter

4Min. track width

Outer layer

5BGA pad

(solder pad)

6Target pad

for microvia


0.65 25.6 0.50 19.7 0.25 9.8 0.115 4.5 0.4 15.7 0.35 13.8

1BGA pitch

7Distance on inner layer

8Track width inner layer

9Min. track width

inner layer

mm mil mm mil mm mil mm mil

0.65 25.6 0.095 3.7 0.110 4.3 0.110 4.3

with 0.4 mm component pads including microvias – 145 balls

1

2

5

9

4

3

8 67

Microvias

L2 1st Inner layer (18 µm copper) Through holes

L1 Outer layer

M 10 : 1

M 20 : 1

4.5.5 BGA 0.65 mm pitch


4.5.6 BGA 0,50 mm pitchThe following two pages contain two design variants for BGAs with a matrix of 0.5 mm.

Up to 80 BGA pads connected individually

1BGA-pitch

2Viapad

outer layer min.

3Drilling diameter

4Track width outer layer

min.

5BGA pad

(solder pad)

6Target pad

for MV


0.50 19.7 0.50 19.7 0.25 9.8 0.100 3.9 0.35 13.8 0.27 10.6

1BGA-pitch

7Distance on inner layer

8Track width inner layer

9Track width

inner layer min.

mm mil mm mil mm mil mm mil

0.50 19.7 0.075 3.0 0.080 3.1 0.080 3.1

1

2

5

43

8

9

6

7

Ln

Ln-1

Ln-2

L3

L2

L1

Prepreg

Core

x layers

Core

Prepreg


M 50 : 1

Microvias

L2 1st Inner layer (18µm Copper) Through holes

L1 Outer layer

Layer stackup:Microvias in combination with through-holes

This is the cheapest way of integrating microvias in a layout.The entire multilayer board can be manufacturedin one pressing process.

M 10 : 1

M 20 : 1


4.5.7 BGA 0,50 mm pitch

Up to 144 BGA pads connected individually

12

5

4

3

8

9

6

7

13

1310

12

11

Microvias (MV1) from L1 to L2

Microvias (MV2) from L2 to L3L2 1st Inner layer

Through holes

L1 Outer layer

M 10 : 1

M 20 : 1

1BGA-pitch

2Viapad

outer layer

3Drilling

diameter

4Track width outer layer

5BGA pad

(solder pad)

6 Target pad

for MV1

7Start padfor MV2

8DistanceMV pads

mm mil mm mil mm mil mm mil mm mil mm mil mm mil mm mil

0.50 19.7 ≥ 0.50 ≥ 19.7 0.25 9.8 ≥ 0.10 ≥ 3.9 0.35 13.8 0.3 11.8 0.3 11.8 0.08 3.1

9Distance 1 MV to MV

10Distance 2 MV to MV

11Distance

inner layer 1

12Track widthinner layer 1

13Distance

MV1 to MV2

14Target pad

for MV2

15Distance

inner layer 2

16Track width inner layer 2

mm mil mm mil mm mil mm mil mm mil mm mil mm mil mm mil

0.4 15.7 0.6 23.6 ≥ 0.10 ≥ 3.9 ≥ 0.10 ≥ 3.9 0.15 5.9 0.27 10.6 0.075 3.0 ≥ 0.08 ≥ 3.1

16

6

1615

12

14

MV2

MV1

Ln

Ln-1

Ln-2

L3

L2

L1

Prepreg

Prepreg

x layers

Prepreg

Prepreg

Buried viasfrom

L2 to Ln-1


M 50 : 1

Layer stackup:Microvias in combination with buried vias and through-holes

Microvias (MV2) from L2 to L3

L3 2nd Inner layer (18 µm Copper)

L2 1st Inner layerM 10 : 1

M 20 : 1


Hole typeREQUIREMENTS FOR COPPER THICKNESS ACCORDING TO IPC-6012

Class 2 Class 3

Microvia12 µm average10 µm minimum

12 µm average10 µm minimum

Buried via core15 µm average13 µm minimum


Buried via20 µm average18 µm minimum


Through-hole/blind via20 µm average18 µm minimum


OUTER LAYERS

Base copperRequirements

Class 2 Class 3

5 µm ≥ 23.1 µm ≥ 28.1 µm

12 µm ≥ 29.3 µm ≥ 34.3 µm

18 µm ≥ 33.4 µm ≥ 38.4 µm

35 µm ≥ 47.9 µm ≥ 52.9 µm

70 µm ≥ 78.7 µm ≥ 83.7 µm

105 µm ≥ 108.6 µm ≥ 113.6 µm

INNER LAYERS

Base copper Requirements

18 µm ≥ 11.4 µm

35 µm ≥ 24.9 µm

70 µm ≥ 55.7 µm

105 µm ≥ 86.6 µm

Finished copper plating thickness after processing, extract from IPC 6012:

4.5.8 Finished copper plating thicknesses

4.5.9 Copper plating thicknesses in holes


5 RIGID-FLEX PCBS

Rigid-flex PCBs consist of rigid and flexible areas. The rigid parts are often multilayered and are connected to each other by means of a composite structure of flexible polyimide materials. The tracks are embedded in this composite structure. Polyimide materials offer the highest level of quality in the bending area and can be stressed accordingly. Using the smallest possible bending radius allows very small geometric figures to be produced.

Default values for rigid-flex PCBs with polyimide materials:• Max. no. of Cu layers: 10 layers• Max. flexible layers: 2 flexible layers• Conductor structures: ≥ 150 µm • Copper height: 35 or 70 µm • Min. bending radius: ≥ 1 mm • Total thickness: 0.8 - 2 mm ± 10%

Asymmetrical stack up: One flexible layer

The stack up of the rigid part can be varied by using different core materials and prepregs, but is dependent on parameters such as the total thickness and the maximum number of layers.The total thickness is calculated from the composite stack up including galvanic copper stack up and solder mask coating.

5.1 Stack up

Cover foil / Flex laquer

Core FR4 / PrepregNo flow PrepregPolyimideCopperSolder mask

35 - 70 µm

max. 70 µm

max. 70 µm

Final copper35 - 70 µm

Outer layer

Inner layer

Inner layer

Outerflex layer

M 50 : 1

Combinations with other technologies such as microvias are possi-ble. This can be agreed with us during the layout and design phase.


Asymmetrical stack up: Two flexible layers

Symmetrical stack up: Two flexible layersThis version requires an identical stack up of the rigid parts.

Cover foil / Flex laquer


35 - 70 µm

max. 70 µm


Outer layer

Innerflex layer

Inner layer

Outer layer

Inner layermax. 70 µm

18 or 35 µm18 or 35 µm

Cover foil

Cover foil

max. 70 µm

max. 70 µm

M 50 : 1

Cover foil


35 - 70 µm

max. 70 µm


Outer layer

Innerflex layer

Inner layer

Outerflex layer

Cover foil18 od. 35 µm

max. 70 µm

M 50 : 1


Flexible layer, outer

Flexible layer, inner

5.2 Design rules

6

5

4

1

2 3

Solder Mask Copper Polyimide/ Cover foil Surface finishing

2

3

45

5

6

1

PolyimideCopper

During pressing of the PCB polyimid material shows a lower dimensional stability than FR4 material.Therefore the minimum annular ring on the flex layer needs to be 0.35 mm/ 14 mil bigger than thefinal diameter.

Rigid area Flex area Rigid area

1. Distance copper to edge:min. 0.3 mm/12 mil for millingmin. 0.6 mm/23.6 mil for scoring (with material thickness ≤ 1.6 mm) min. 0.7 mm/27.6 mil for scoring (with material thickness > 1.6 mm)

2. Min. conductor structure in rigid area: 0.125 mm/5 mil

3. Overlap min. 1 mm (40 mil) on rigid part. There shall be no solder pads, holes or vias in this area.

4. Distance copper to edge min. 0.5 mm/20 mil5. Min. track width 0.15 mm/6 mil6. Min. track pitch 0.15 mm/6 mil

1. Min. track width in flex area 0.15 mm/6 mil2. Min. track distance in flex area 0.15 mm/6 mil3. min. distance to contour in flex area 1.0 mm/40 mil

4. Min. track width in rigid area 0.15 mm/6 mil5. Min. distance in rigid area 0.15 mm/6 mil6. Min. distance to contour in rigid area 1.0 mm/40 mil


5.3 ZIF (zero insertion force connectors for rigid-flex)

C ±0.05B ±0.07

0.35 ±0.030.5 ±0.03

0.5 ±0.1

2.85

(reinforcement board)

Applicable FPC Dimensions

T=0.3 ±0.05 (Conductive plating)

0.30 mm± 0.05 mm

Cover foil / Fley laquer


Controlled depth milling

M 50 : 1

The technical challenges for the PCB manufacturer consist firstly of the tolerance for the lateral distance between the contact pads and the connector contour, and secondly of the total thickness of 0.3 mm with a tolerance of ± 0.05 mm.

Example data sheet extract:

Tolerance-controlled depth milling for ZIF connectors


5.4 Processing recommendations

Baking (drying) of the rigid-flex circuits is essential before soldering.

Polyimide films are very hygroscopic (they absorb a lot of moisture). Even under standard room conditions, films that have already been dried will absorb moisture from the air and will reach their saturation level again within a few hours (up to max. 3%).

During the soldering process, the absorbed moisture can lead to delamination, blistering or breaks as a result of the thermal stress.

Baking• baking at 110 – 120 °C in the convection oven for around 2 hours• subsequent storage until soldering process:

humidity ≤ 50%

SolderingBaked rigid-flex PCBs can be soldered either manually or mechanically no later than 6 to 8 hours after drying. The techniques that are commonly used with rigid PCBs, such as infrared, convection and vapour-phase soldering, can also be applied to rigid-flex circuits.

Bending radius in flex area:Bending radius with one copper layer in flex area:Min. radius = thickness of flex area x 5(Corresponds to ≥ 1 mm)

Bending radius with two copper layers in flex area:Min. radius = thickness of flex area x 10(Corresponds to: ≥ 3 mm)

With a cover layer in the flex area, the copper is in the “neutral zone”. This results in very good bending behaviour.

Copper in neutral zone

Bending radius

Cover foil / flex laquer

No flow PrepregCore FR4PolyimideCopperSolder mask

5.5 Application guidelines

Bending stress with ED copper (electrolytic copper) in flex area:For static bending stress with simple installation and maintenance operations. Not suitable for dynamic bending stresses, i.e. if the flex part is constantly in motion!


3

2

1

35 - 70 µm

max. 105 µm

max. 105 µm

35 - 70 µm

Core FR4 / PrepregCover foilCopperSolder mask

Final copper

Outer layer

Inner layer

Inner layer

Outerflex layer

3 Chamfer 0.45 mm x 45°2 Thickness bending area1 Bending area

M 50 : 1

Cover foil

6 SEMIFLEXIBLE PCBSIn comparison with traditional rigid-flex PCBs, semi-flex PCBs offer significant cost advantages with restricted bending properties. A standard rigid FR4 PCB is produced. A flexible cover film is placed over the desired bending area instead of the standard solder mask. The area beneath this flexible cover film is deep-milled and thus made bendable at the end of the production process. The remaining FR4 thickness is around 150 µm. The semi-flex design deals well with static bending stresses during assembly and installation.

For technical production reasons, only an asymmetrical structure is possible.Default values for semiflexible PCBs:Max. no. of Cu layers: 30 layersMax. flexible layers: 2 flexible layersConductor structures: ≥ 100 µmCopper height: 35 or 70 µmMinimum bending radius: ≥ 5 mmTotal thickness: 0.8 – 2.0 mm ± 10% > 2.0 - 3.2 mm ± 0.2 mm

6.1 Stack upsThere are hardly any restrictions in the design of the layer structure of a semi-flex PCB. However, when it comes to the choice of prep-regs, thin glass mats should preferably be used in the bending area.

Typically, prepregs of the type 106, 1080, or 2116 are used for the residual web. If the use of the prepreg 7628 is necessary, consult with KSG.

Asymmetrical stack up: One flexible layer


3

2

1

35 - 70 µm

max. 105 µm

35 - 70 µm35 - 70 µm

35 - 70 µm

max. 105 µm

Core FR4 / PrepregCover foilCopperSolder mask

Final copper

Outer layer

Innerflex layer

Inner layer

Outerflex layer

3 Chamfer 0.45 mm x 45°2 Thickness bending area1 Bending area

M 50 : 1

Cover foil

Inner layer

Inner layer

Asymmetrical stack up: Two flexible layers

6.2 Design rules

4

1

2 3 Solder Mask Copper Cover foil

1. Distance copper to edge:min. 0.3 mm/12 mil for millingmin. 0.6 mm/23.6 mil for scoring (with material thickness ≤ 1.6 mm) min. 0.7 mm/27.6 mil for scoring (with material thickness > 1.6 mm)

2. Min. conductor structure: 0.1 mm/4 mil3. Overlap min. 1 mm (40 mil) on rigid part. There shall be no solder

pads, holes or vias in this area.4. Distance copper to edge min. 0.3 mm/12 mil

6.3 Application guidelinesThe following values apply for the most common bending angles (min. bending radius = 5 mm):Bending angle (α) Bending area (a)45 ° ≥ 4.8 mm90 ° ≥ 8.8 mm180 ° ≥ 16.6 mm

Larger bending areas and thus larger bending radii should be targeted.

Bending radius

Cover foil

Core FR4 / Prepreg

Cover foil

Copper

Solder mask

In the case of a two-layer design, the bending area must be multiplied by a factor of 1.5.


7 HIGH CURRENT TECHNOLOGY AND THERMAL MANAGEMENT

The HSMtec PCB technology makes it possible to swiftly reduce heat development in electronic devices to permissible partial and system temperatures. The FR4 and copper-based PCBs consist of multiple layers. Copper profiles are added in these layers to reinforce the tracks. This is done selectively and only at those points where high currents are to be transported or heat is to be dissipated. After lamination, these copper cross-sections are located in the interior of the PCB, so that valuable space is freed up on the surface of the board. In addition, HSMtec offers

the possibility of bending PCBs and thus designing complex 3D- designs.

Default values for HSMtec PCBs:• Total thickness: 0.8 - 3.2 mm• Max. number of layers: 12• Max. number of layers for copper cross-sections: 3• Bending radius: up to 90° on each bending point• Currents: up to 400 A

High current management• Currents of up to 400 A integrated in the PCB• Power and control electronics on a single PCB• Reduction in connectors, cables and assembly effort

Thermal management• Targeted heat control and dissipation in the PCB

(for HB-LEDs, MOSFETs, IGBTs, etc.)• Continuous copper path from the heat source to the heat sink

Multidimensional applications• Self-supporting multidimensional PCB structures• Integrated heat control and electrical connections

across the bending edge• Complex geometries of any type

7.1 Areas of application for HSMtec


Available copper cross-sections

7.3.1 Positioning of copper cross-sections

2 mm

4 mm

8 mm

12 mm

Copper profiles: Thickness 500 µm

4

3

2

1

M 100 : 1M 100 : 1

500 µm

500 µm

70 µm or 105 µmFinal copper:

70 µm or 105 µm

70 µm or 105 µm

150 µm - 510 µm0,8 mm to 3,2 mm

Min. 650 µm M 100 : 1

1. ≥ 0.5 mm – min. final drill diameter for holes in profiles2. ≥ 0.5 mm – distance between holes in a profile 3. ≥ 0.7 mm – distance between hole in profile and profile edge4. ≥ 0.4 mm – distance between hole and profile edge

The copper cross-sections must not be positioned on adjacent lay-ers. Profiles can be positioned on a maximum of 3 layers.

A copper pad area independent of potential should be provided on the opposite side of the copper element. In the case of profiles on inner layer cores, the copper of the pattern must be larger all around than the copper cross-section.

7.2 Stack up

7.3 Design rules

4-layer stack up (schematic representation)

7.3.2 Holes through copper profiles

FR4 Core FR4 CoreFR4 Core FR4 Core

The stack up can be varied by using different core materials, copper cross-sections and prepregs, but is dependent on parameters such as the total thickness (0.8 - 3.2 mm) and maximum number of layers (12).


7.3.3 Design rules for copper profiles

b

e

s

s

q

f

s

n

s

p

q

i

g

o ol

mk

h

j

r

pqr

r

r

f

ca

d

Outer layer Inner layer

Inner layer:g) ≥ 4.0 mm - min. track width for h) 2.0 mm profile width

i) ≥ 6.0 mm - min. track width for j) 4.0 mm profile width

k) ≥ 10.0 mm - min. track width for l) 8.0 mm profile width

m) ≥ 14.0 mm - min. track width for n) 12.0 mm profile width

o) ≥ 13 mm – min. track length for 2 mm and 4 mm profile width

p) ≥ 23 mm – min. track length for 8 mm and ≥ 21.0 mm for 12mm profile width

Outer and inner layer:q) ≥ 0.5 mm - min. final drill diameter for holes

in profiles r) ≥ 2.2 mm - min. distance profile to profile for two

adjacent profiless) ≥ 3.5 mm - min. distance profile to profile for three

or more adjacent profiles

Outer layer:a) ≥ 3.0 mm - min. track width for b) 2.0 mm profile width

c) ≥ 5.0 mm - min. track width for d) 4.0 mm profile width

e) ≥ 0.125 mm – min. distance between tracks

f) ≥ 12.0 mm – min. track length for 2.0 mm and 4.0 mm profile width


7.4 Current-carrying capacity

Calculator for high current tracksThe high current calculator at www.ksg-pcb.com offers you a simple and fast way of calculating the necessary track width for high current conductor tracks on an FR4 PCB.

Stack up

Low indirect heat spreading High indirect heat spreading

Cu Profile 2 x 0.5mm





Cu Profile4 x 0.5mm


Cu Profile12 x 0.5mm

Delta T [ °C] Amps Amps Amps Amps Amps Amps Amps Amps

10 11.1 18.4 30.4 40.8 20.1 33.2 54.9 73.7

20 15.7 26.0 43.0 57.6 28.4 47.0 77.7 104.3

30 19.3 31.8 52.6 70.6 34.8 57.6 95.2 127.7

40 22.2 36.8 60.7 81.5 40.2 66.5 109.9 147.4

50 24.9 41.1 67.9 91.1 45.0 74.3 122.9 164.9

60 27.2 45.0 74.4 99.8 49.3 81.4 134.6 180.6

70 29.4 48.6 80.4 107.8 53.2 88.0 145.4 195.1

80 31.4 52.0 85.9 115.3 56.9 94.0 155.4 208.5

90 33.4 55.1 91.1 122.3 60.3 99.7 164.8 221.2

100 35.2 58.1 96.0 128.9 63.6 105.1 173.8 233.1

FR4 160 mm x 100 mm x 1,6 mm FR4 160 mm x 100 mm x 1,6 mm

http://www.haeusermann.at


0

20

40

60

80

100

MC

- PCB

HSM

tec

/ FR4

Sour

ce: O

sram

OS

number of thermal cycles (-40° bis +125°C)

Shea

r for

ce in

% o

f ini

tial v

alue

1000 15000 = initial situationafter soldering

7.5 Multidimensional HSMtec PCBs

7.6 Reliability

1

3

90°

90°

2

500 µm

500 µm

V-cut opening

V-cut closing

The integrated profiles make it possible to construct self-supporting multidimensional PCBs and to conduct heat and high currents over the bending edge in a targeted fashion. The assembly of the PCB takes place in the flat state. For mounting, the assembled PCB is bent once – slight adjustment movements are permitted. For each bend, an angle of up to 90° can be achieved. After bending, the bending edge should be protected from environmental impact.

The reliability and performance potential of HSMtec have been repeatedly confirmed:

• Thermal conductivity of copper (300 W/mK) double that of aluminium (150 W/mK)

• OSRAM OS confirms the superiority of HSMtec over IMS metal core PCBs (see diagrams)

• Approved by independent test institutes• Approved in accordance with DIN EN 60068-2-14 and JEDEC A

101-A, and audited for aviation and automotive applications

1. 120° v-cut scoring with slot closing by bending2. 90° v-cut scoring with opening v-cut by bending3. ≥ 3.0 mm profile length to bending edge

High reliability thanks to minimal thermo-mechanical stress:

High reliability thanks to high thermal resilience:

0 1000 2000 3000

850

> 3000

> 3000

MC - PCB

HSMtec / FR4

Ceramics

Sour

ce: O

sram

OS

Number of thermal cycles up to 1% error rate (-40° to +85°C)


8 SOLDER MASK

The solder mask protects the surface from mechanical or chemical influences (corrosion) and prevents short circuits during soldering. It isolates the PCB surface from other elements (e.g. components or housing) and optimises electrical properties (increase in sparkover voltage).

Minimum clearance of solder maskSMD pad distance ≥ 170 µm Minimum solder mask web ≥ 60 µmSolder pad + 55 µm all around

Provision of dataThe clearances of the individual solder pads should be as large as the solder pad (“zero clearance”). Based on the tolerances in our manufacturing processes, we increase the clearance of the solder pads by 55 µm (all around).

Mask type Imagecure® XV501T

Surface quality according to IPC SM840E

Solder mask thick-ness

on track edge ≥ 4 µm

Electrical properties

Dielectric strength 160 V/µm IPC SM840E

Surface resistance 5 * 1010 Ω IPC SM840E

Creep tracking resistance:Standard value on laminate with CTI 500

> 325 V 575 V

IEC 112

Dielectric constant εr at 1 MHz 3.9 - 4.0 IEC 60250

Dielectric loss factor tan δ at 10² Hz - 106 Hz

0.02 IEC 60250

≥ 170 µm ≥ 60 µm

≥ 55 µm

Imagecure® XV501T product information (extract)


8.1 Solder mask design for vias with chemical surface finish

For vias in the BGA area, we recommend that the via pads should be masked and the via hole cleared.Vias are cleared from solder mask to achieve a clean metallised copper hole wall (microsection 1). This prevents carryover of process chemicals or long-term damage as a result of any bare copper.Covering with solder mask before the surface process would cause

an undefined state in the hole (microsection 2). Single-sided closing after the surface process with through-hole printing guarantees a technically flawless hole wall.

Fig. A: chemical tin Fig. B: ENIG Fig. C: ENIG vias covered on one side

Microsection 1: clean metallised hole wall of a cleared via

444

44

3

1a 1a1a

2 2 2

1 1

solder mask to thenext solder pad

Optional: trough-hole printing on the wave soldering sideto prevent solder discharge

1. Final diameter 1a. Drill hole 2. Viapad 3. Solder clearance = Final diameter4. Clearance = Final diameter (1) +0.30 mm = Drill hole (1a) + 0.15 mm

Optional: cover with one-sidedby ENIG possible

chem

ical

tin

ENIG

ENIG

*) Figure A *) Figure B Figure C

M 50 : 1

Microsection 2: undefined hole wall of a via covered with solder mask

bare copper solder mask residue in hole chemical tin

Example: Vias in the BGA area

Clearance of vias according to ZVEI/recommendation *)


9 SURFACE FINISH

9.1 Electroless nickel immersion gold (ENIG)

9.2 Chemical tin

The surface finish serves to protect the copper from oxidation, ensures the solderability of your PCB and increases the mechanical strength of plug-in or sliding contacts.The specified solderability assumes that the following storage

conditions are met:• Storage temperature: max. 30 °C (according to ZVEI) • Relative humidity: max. 70 % (according to ZVEI)

Application

• Al wire bonding • PCB in fine and ultra-fine line technology• SMT-PCB

Plating thicknesses

Nickel: ≥ 3 µmGold: 0.05 - 0.12 µm

PropertiesFlat solder surfaceRoHS compliant

Solderability 12 months

Application

• PCB with press-in holes• PCB in fine and ultra-fine line technology• SMT-PCB

Plating thicknesses 0.8 – 1.3 µm

PropertiesFlat solder surfaceRoHS compliant



9.3 Electroplated nickel / gold

• Layout parts that are to be gold-plated are connected to each other and across the edge of the PCB with interconnecting tracks.

• On multilayer boards, interconnecting tracks can also be passed through the inner layers.

• Before any other surface finish, the gold-plated layout parts must be masked (peelable solder mask or masking tape).

• The interconnecting tracks can either be etched, or milled or drilled without any great effort during final contour processing.

Application• Plug-in contacts• Sliding contacts

IPC Class 2 IPC Class 3

Ni plating thickness > 3 µm > 3 µm

Au plating thickness > 0.8 µm > 1.25 µm

Propertiesnot solderableVickers hardness 150RoHS compliant

Partial gold plating with interconnecting tracks

3

2

2

2

1

1

1

1

3

3

1 Interconnecting tracks cutted by milling2 Interconnecting tracks cutted by drilling3 Masking tape process requires min. 1.5 mm spacing between gold surface and adjacing tin surface!

Electroplated nickel gold

Surface finish (e.g. chemical tin)


9.4 Reductive gold

Application Au wire bonding

Plating thicknesses

Nickel: ≥ 3 µmGold: 0.4 - 0.6 µm

Properties RoHS compliant


9.5 Hot air levelling (leaded/lead-free)

Application• PCB with press-in holes• Multiple soldering possible

Plating thicknesses

Max. 40 µm

Properties

• High thermal load of PCB (240 - 280°C)

• Uneven distribution of plating thickness on the surface and in the holes, depending on layout

Leaded Lead-free

Alloy 37/63 % SnPbNOT RoHS compliant!

RoHS compliant


Note

• Unsuitable for lettering and pads in copper surfaces.

• No implementation for MV drill holes, blind holes, BGAs.

• Unsuitable in technology area ≥ 8 layers.

• Unsuitable for board thickness > 2mm.


10.1 Inkjet identification printing

Applications

• Component printing• Direct printing of codes

(barcode, data matrix code, numerical code)

• Consecutive numbering of parts for traceability solutions

TypeWhite: Dipamat Legend Ink Wh4Company Agfa

PropertiesMinimum character height: 0.5 mmMinimum line width: 75 µmPrint resolution: 1,440 dpi

10 ADDITIONAL PRINTING

Barcode

Consecutive numbering of parts, data matrix code

10.2 Identification and surface screen printing

Applications• Component printing• Complete surface printing

Type

White: SD 2692 TYellow: SD 2617Red: SD 2632 TBlue: SD 2652 TBlack: SD 2642 T

Peterswww.peters.de

Properties

Minimum character height: 1.25 mmMinimum line width: 125 µmMinimum ratio of letter height to line width: 10:1


0,31 mm

0,04 mm

Applications Closing of vias

TypeSD 2361 PBF-TPeterswww.peters.de

Properties

Max. height of the finished printed pad: 50 µmMax. hole diameter: 0.55 mm (21.6 mil)Max. drilling diameter: 0.75 mm (29.5 mil)Printed pad: drilling diameter + 0.25 mm (10 mil)

10.3 Surface printing with white solder mask

3

2

1

3

1 Size of the printed pad: Drilled hole + 0.2 mm (8 mil)

2 Drilled hole

3 Distance printed pad to solder pads ≥ 0.25 mm (10 mil)

Final height of the finished printed pad max. 50 µm

10.4 Through-hole printing / closing of vias

Applications LED applications

TypeWhite: SD 2491 TSWPeterswww.peters.de

Properties

Good light reflectionTemperature stable whiteHalogen-freeClearance from soldering area ≥ 0.3 mm

This printed PCB is in accordance with IPC 4761, Plugged Via, Type III-a.


10.5 Peelable solder mask / cover tape

3

3

2

1

1

2

1 Areas to be covered

2 Overlap of areas to be covered ≥ 1.0 mm

3 Distance peelable solder mask/ cover tape to solder pads ≥ 1.0 mm

PEELABLE SOLDER MASK

Applications Masking of layout parts

Type

SD 2955Blue-Green-Transparent Peterswww.peters.de

Properties

Minimum printed pad(single pad):2 mm x 10 mm or3 mm x 5 mm

COVER TAPE

Applications Masking of layout parts

Type

Polyimide film PPI 701Brown-TransparentPPIwww.ppi-germany.de

Properties

Temperature resistance short-term up to 300°CTotal thickness: 0.055 mmTensile strength: 50 N/cm

Peelable solder mask

Cover tape


11 DRILLING

11.1 Through-hole

Min. final diameter 0.1 mm (depending on surface finish)

Max. final diameter 7.0 mm (for larger plated through-holes, see 11.1.2)

Min. drilling diameter 0.25 mm

Aspect Ratio max. 1 : 10 (drilling diameter : board thickness)

Hole tolerance, plated-through hole -0.05/+0.1 mm

Hole tolerance, non-plated-through hole -0/+0.1 mm

Backdrill for high-frequency applications

With a high drilling density in a confined space, a material distance of 300 µm between the holes must be observed.

As an alternative to large plated-through holes, several plated-through holes can be arranged in the annular ring of a non-plated-through hole.

≥ 300 µm

1

2

3

M 25 : 13. Copper construction incl. surface finish

1. Final hole2. Drill hole

Several PTHs arranged in the annular ring

11.1.1 Thermal vias

11.1.2 Plated-through holes in the annular ring


11.2 Microvia

Drilling diameter 90 µm to 140 µm

Aspect Ratio max. 1 : 1 (drilling diameter : drilling depth)

Pad diameter see 4.2

KSG offers both mechanically and laser drilled microvias. A laser is used in the event of a large number of holes or if desired by the customer. If technically possible, prototypes with a small number of holes are drilled mechanically.

A special blind via drill is used to implement holes over several layers in multilayer boards. The conical shape of this drill determines the pad geometries shown in the following illustrations, depending on the depth of the holes. On account of the larger volume, blind vias cannot be placed in solder pads. Aspect Ratio max. 1 : 0.8

11.3 Blind vias (mechanically drilled)

LnLn-1

Ln-2

L3L2L1

1 2 4

31

4

5

PrepregCorePrepreg

x layers

PrepregCorePrepreg


M 50 : 1

Choosing the right pad diameter (schematic diagram):

1*MV pad

(*see point 4.2)

2Blind via pad outside

3Blind via pad inside

4Blind via pad

outside / inside

5Min. dielectric

distance

mm mil mm mil mm mil mm mil mm mil

≥ 0.30 ≥ 11.8 ≥ 0.55 ≥ 21.7 ≥ 0.35 ≥ 13.8 ≥ 0.55 ≥ 21.7 ≥ 0.10 ≥ 3.9

Laser-drilled Mechanically drilled

Etched microsection


Milling widths (diameter in mm) 0.8; 1.0; 1.2; 1.4; 1.6; 2.0; 2.4; 3.0

Distance between PCBs on KSG production panel

10 mm in both directions

Tolerance, length/width≤ 200 mm ± 0.1 mm > 200 mm ≤ 300 mm ± 0.15 mm > 300 mm ± 0.2 mm

Tolerance, drilling pattern to milled contour ± 0.2 mm

Tolerance, pattern to milled contour ± 0.2 mm

Tolerance, pattern to milled contour (camera milling) ± 0.05 mm

Copper to board edge ≥ 0.3 mm

Depth milling tolerance (see sketch) ± 0.1 mm bzw. ± 0.15 mm

± 0.10 mm

± 0.15 mm

Rest web based tolerance

Low relative tolerance

Depth milling

12 CONTOUR PROCESSING12.1 Milling


12.2 Scoring

Tolerances

Tolerance ± 0.10 mmTolerance ± 0.10 mmTolerance ± 0.10 mm

Center offsetScoring line offset top to bottom

Rest web 0.3 mm

15°

Scored edge

Material thicknesses Applicable for all material thicknesses

Distance between PCBs on KSG production panel

0 mm in both directions

Positioning accuracy ± 0.1 mm

Tolerance, length/width -0 / +0.25 mm with residual scored tab of 0.3 mm

Distance between copper and board edge for material thickness up to 1.6 mm

≥ 0.6 mm

Distance between copper and board edge for material thickness greater than 1.6 mm

≥ 0.7 mm

Minimum line length for jump scoring

20 mm

Score outlet 10 mm


12.3 Gold ridge bevelling

3

2

1

Board thickness1

Facet angle2

Facet depth3

Gold contacts set back from edge

≤ 1.00 mm 45° 0.30 mm ± 0.15 mm 0.60 mm ± 0.10 mm

1.20 mm 45° 0.40 mm ± 0.15 mm 0.70 mm ± 0.10 mm

≥ 1.60 mm 45° 0.50 mm ± 0.15 mm 0.80 mm ± 0.10 mm

≤ 1.00 mm 30° 0.50 mm ± 0.15 mm 0.80 mm ± 0.10 mm

1.20 mm 30° 0.70 mm ± 0.15 mm 1.00 mm ± 0.10 mm

≥ 1.60 mm 30° 0.80 mm ± 0.15 mm 1.10 mm ± 0.10 mm

≤ 1.00 mm 15° 0.70 mm ± 0.15 mm 1.00 mm ± 0.10 mm

1.20 mm 15° 0.80 mm ± 0.15 mm 1.10 mm ± 0.10 mm

≥ 1.60 mm 15° 0.90 mm ± 0.15 mm 1.20 mm ± 0.10 mm

For PCB production, the gold ridges are set back by the value “3” depending on the board thickness and the facet angle. This ensures that the gold-plated pad is not touched by the tool. Short circuits between the gold contacts can thus be avoided.


13 QUALITYKSG 's outstanding level of quality is based on standards of precision, strict quality control and continuous process monitoring.

13.1 Quality standard at location Gars am Kamp

Our PCBs meet the high European quality standard. Our adherence to this high standard is evidenced by, among other things, the following:

Certifications• Certification to ISO 9001:2015 since January 2016• First ISO 9001 certification in November 1991• Automotive standards: authorisation through two-party

auditing (VDA6.x or ISO/TS16949)• Aviation standards:

authorisation through two-party auditing (AS/EN9100)• UL listing for USA E72795 • UL listing for Canada E72795 • UL listing for rigid-flex (USA and Canada)

EnvironmentKSG manufactures PCBs that are RoHS compliant and, on request, halogen-free and meets the requirements of the REACH regulation.

Compliance with the relevant statutory provisions is demonstrated in our declarations of conformity.

Quality and safety certificates and declarations of conformity are available for downloading from our home page www.ksg-pcb.com.

Product-specific standards• IPC A 600 current edition Class 2• IPC A 600 current edition Class 3


Only controlled processes and parameters can guarantee a consistently high level of product quality. At KSG, each stage of production is therefore subject to extensive in-process controls. Accompanying analyses of process data ensure the continued optimisation of production processes.

13.2 Process control and regulation

Chemical process control• State of the art instrumentation provides ongoing monitoring of

all relevant parameters in the process bath. • We use an internal control sample system to ensure the accuracy

of these analyses.

3D coordinate measuring machineThe 3D coordinate measuring machine is used for the continuous monitoring of the drilling, milling, punching and exposure processes.At KSG, the automatic precision control of holes, contours and diameters is performed with a positional accuracy of ± 3 µm.

Physical process control• We use cutting-edge equipment to create and document

microsections.• We routinely measure surface finish plating thicknesses in our

laboratory using X-ray fluorescence spectroscopy.• For solderability testing, we use a wave soldering machine.


We ensure the quality of our PCBs by means of routine and rigorous product testing throughout the manufacturing process. The product is subjected to a series of tests, from the production planning department all the way through to electrical testing.

13.3 Product control

Design Rule CheckOur engineers use the design rule check, in accordance with IPC standard design parameters, to verify whether your layout data is valid and producible. This allows us to identify potential errors before manufacturing begins and to ensure the right conditions for the perfect production of your PCB. Of course, if anything is unclear or in the event of even minor abnormalities, we will contact you immediately.

At KSG, every PCB undergoes the “design rule check”.

Automated Optical InspectionWe use Automated Optical Inspection to compare the etched line track pattern with the CAM data. Even the most complex conductor structures can be checked with our equipment.

Reliability testsOur products are qualified in accordance with the following test methods:

Thermal shock test according to IPC-6012 3.10.8, IPC-TM-650 No. 2.6.7.2 Number of cycles: 100 for Tg 130 materialTemperature range: -55 °C to +105 °C

Number of cycles: 1.000 for Tg 150 materialTemperature range: -55 °C to +125 °C

Duration: 15 min each Thermal stress test according to IPC-6012 3.6.1.1; IPC–TM-650 No. 2.6.8Solder bath: Sn60Pb40Solder bath temperature: 288 ± 5 °CDwell time in the solder: 10 sec floating on the solder bath

Electrical testThe electrical test allows us to check the operational functionality of the PCB.Using two-point measurements, we check all connections on inner and outer layers for opens and shorts. We compare the measurements with the customer data (original netlist). Inspection points include SMD pads and plated through holes of any diameter. Every KSG PCB is electrically tested.

X-ray testing (layer offset check)After the lamination of the multilayer, we check the accuracy of fit of the various layers and align the drilling pattern precisely to the measurement results for the subsequent drilling process.

Every multilayer undergoes AOI testing at KSG.


CalculationsWe can calculate the following for you• Impedances• Multilayer stack ups• Current-carrying capacity of tracks• Thermal behaviour of PCBs and tracks

Measurements/analysesOn request, we can measure the following for you in our in-house laboratory• Layer structure, mask thicknesses, sleeve quality and copper

thicknesses by means of microsections • Thicknesses of surface finishes by means of X-ray fluorescence

(non-destructive measurement)• Currents and temperatures on PCBs with high current generators

and an infrared camera (multiswitch for online four-point resistance and temperature measurement)

SamplesWe manufacture your samples in series quality. This gives you the reassurance that your test results from the prototype phase (reproducibility, impedance control, etc.) will also be valid for series production.

Solder samples On special request, we will manufacture a specific solder sample for your production batch and enclose it with your PCB delivery.

Documentation - CertificatesWe will be pleased to send you the corresponding test report for your PCB. Upon request, we can produce • a KSG certificate• an initial sample test report in accordance with VDA or• a customer-specific certificate.

Design & LayoutWe can design layout parts for you, such as • BGAs • Partial gold hard-plating with interconnecting tracks • Gold and etching masks• Microvias• Impedance tracks • Layouts for high current• Layouts for heat management• Layouts for three-dimensional PCBs• Layouts for LED PCBs

14 TECHNICAL SERVICES

At KSG we place the highest priority on service and a customer-focused approach. In particular, we can offer you the following services:

Adhesive filmsApplication of adhesive films or printed films to the PCB. The films are selected in accordance with the customer's specifications, structured if required, and applied to the PCB.


Team up with experts to make great things hap-pen. You bring the ideas, and we contribute our curiosity and thirst for knowledge that can make your product even better.

We tick in the same way as you. Thanks to European quality standards, our PCBs have the precision of a Swiss watch. Gettin in contact with us is very easy.

You can only change the world by being ahead of your time. With fast processes, 100% binding dead-lines, and samples ready for series produc-tion, we provide the drive that will take you right to the top.

Speed to Market

European Quality

Engineering Support

KSG GmbH

Auerbacher Str. 3 – 5

09390 Gornsdorf | Germany

Phone +49 3721 266 - 0

Fax +49 3721 266 -175

KSG Austria GmbH

Zitternberg 100

3571 Gars am Kamp | Austria

Phone +43 2985 2141- 0

Fax +43 2985 2141- 444

[email protected]

www.ksg-pcb.com

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pcb design compass...pcb design compass . location gars 5 2 base materials we use these materials...

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