pcb checklist

8/12/2019 PCB Checklist

1/5

No Main Sub Description Comment

1 Generate the PCB footprints from PCB library.

Check the footprint is match with actual sample.

Check the footprint match part mechanical specification.

Check holes with enough tolerance for connector pins.

Check PTH hole is reserved and with enough tolerance for component guide pins.

Check NPTH hole is un-plated

Check that the pin number of the footprint is numbered according to the component specification.

There must have the polarity indication (+ sign) for the polarize component such as LED, diode or

electrolytic capacitor.Make sure pin 1 of IC is clearly indicated and not confuse with other nearby labeling.

For IC, use triangle instead of dot as pin "1". For capacitor, use plus " + " as indicator.

The size overlay track width and length, pls follow as in the comment.

20120919 meeti

Check the pin orientation of transistor and MOSFET sometimes easily confused.

Consider the footprint pad length/size for rework. Example: the Ze

footprint. But it

Fiducial pad Make sure the fiducial pad is place at the both corner of the BGA or IC and Make sure the pad is un-

paste (diagonal corner of pin 1)

2 Design Rules Check the minimum track width, hole, annular ring thickness, and thermal break whether is set. It should

not less than PCB manufacturer specification.

Min. track width = 0.2mm

Min. VIA hole diameter = 0.2mmMin. annular ring thickness = 0.15mm

min. distance between track/pad/via to the board edge is met.

Min = 0.254mm

Check the minimum track width, hole, annular ring thickness, and thermal break whether is set. It should

not less than PCB manufacturer specification.

Min. track width = 0.15mm

Min. VIA hole diameter = 0.25mm

Min. annular ring thickness = 0.15mm

Min. distance between track/pad/via to the board edge is met: 0.254mm

NPTH to conductive area spacing at least 0.254mm

1. Routing

a. Clearance Rule

b. Routing Via-Style Rule

c. Max-Min Width Rule2. Manufacturing

a. Minimum Annular Ring

b. Hole Size Constraint

c. Polygon Connect Style

3. Other

a. Short Circuit Constraint

b. Un-Routed Net Constraint

Check that thermal break is set between polygon and pad with the same net name.

Layer Stack

Manager

Check that the number of layer on the PCB is done as according to the layer stack.

Check that the drill hole pairs are assign according to the specification of the PCB manufacturer. (Blind via)

Stack holes Make sure there are at least 2-4 stack holes at the corner of PCB. The stack hole shall meet the

manufacturer requirement.

Stack hole diameter = 2.5mm

One of the stack holes is set as the origin and all the stack hole shall be label with coordinate.

For TestPoint Jig

Set the Origin at one of the Stack hole. For TestPoint Jig

Fiducial Min 2 fiducial that place diagonally the edge of PCB. (Optional: place the fiducial at the 4 corner of PCB

panel).

FileName Dont save file name too long, it will cause some error when generating DRC report and etc.

PCB Thickness Always use minimum 1.6mm except there is a requirement on the PCB to be 1mm. If the PCB is 1m

to match the thi

3 Connector Check the footprint for each connector on the board. Ensure that the correct footpr int and pitch size is

used.

Make sure the connectors pin assignment/polarityare match with the connected device/connector,

especially the FFC connector (sometime the pin 1 signal not necessary connected to the pin 1 of

Footprint

Component

Placement

Pre-route


2/5

Only one side of the PCB have the through hole components.

TH hole components (cap/header) polarity should be in the same direction. TH components

minimize the hu

Avoid the chip overlap EXACTLY to each others on top and bottom side.

Make sure all the capacitors and resistors are at the right source/destination components.

component to

component

distance

Make sure the component to component spacing have enough space.

**pls refer to **refer: ISITO Board Design Guidelines_component spacing.pdf for more information.

**refer: **refer

Guidelines_com

For reflow process:

0603 to 0603 pad edge to pad edge = 0.635mm (25mil)

**refer: ISITO Bo

spacing.pdf

Wave process:0603 to 0603 pad edge to pad edge = 1.27mm (50mil)

Wave soldering process need more space is there is smt component, pls refer to ISITO Board Design

Guidelines_component spacing.pdf to check the spacing.

**refer: ISITO Bospacing.pdf

component side Overlay center line to center line of conveyed edge: 0.75mm refer HRT300-SC

Layer Tab with layer numbering.

BKM BKM: imidiate route short track n punch via for used nets. To avoid no place to punch via when doing the

routing.

Start to route HighSpeed signals first before start route others normal signals.

High speed signals need to be routed:

a. as short as possible.b. no Stub.

c. don't cross other highspeed signal at adjacent plane .

d. don't cross noisy area. Ex: Crystal or switching Vreg.

e. minimize transition via as much as possible. (connector pin counted as 1 transition via.)

Top priority reference plane is GND.

Check the shielded signal. Eg. Clock, audio and high speed signal .

Make sure the high speed signals don't cross the split plane. If it must cross the split plane, use the

stiching capacitor beside the split plane.

Diff. Pair Differential pair must be routed in pair or side-by-side with the width/spacing that set by PCB vendor.

Put a ground Via around the differential pair when they change to others layer.

The diff pair reference plane should not break or cross the split plane.

Leave space at least 0.508mm air gap distance for differential pair to others signals.

Tuning Matching the track length in proper way as in comment figure. For more informa. High Speed US

b. Board design

Busses 1. Use the same layer to branch out the same buses or same differential pair. Ex: Tx at same layer and all

RX at another same layer.

No less that 90 degree angle track (for power and GND signal)

Avoid T or X connection on track connection unless VIA/pad is used

Don't route unnecessary bending of track

Connect the track to the center of pad (especially square pad)

Via hole must be set to tending

- precaution: If use * instead of PlaceVia, the via will NOT be tenting

Component pad close to each other and of the same net should not be connected using thick track

especially the GND and Power pin to avoid the thermal distribution during soldering.

Put vertical track as one layer (ex. Top layer) and horizontal track as another layer (ex. Bottom layer) for a

two layer board

Add via at the thermal padof footprint.

POWER/GND Min track width is 0.6mm or equal to pad size.

BKM BKM: Route top layer in horizontal and bottom layer in vertical or vice versa.

Polygon Double click on each polygon (if any). Check that the grip size is 0.2mm and the track size is 0.254mm.

Grip size = 0.2mm

Track size = 0.254mm

Check visually that there are thermal break between the connected pads and polygon. The thermal break

clearance shall be generated according to manufacturer specification.

Expected thermal break clearance = 0.254mm

Actual thermal break clearance = 0.3mm

Check whether the via is breaking or create the botttom neck at the GND or Power plane.

Consult with Design Engineer the current load for each Power net and calculate the suitable track/plane

Power Plane

Normal

Routing

High Speed

Signals


3/5

Make sure some open pin from BGA IC is tied out as test point.

Make sure the test point is labeled with designator. Generate the test point list for testing reference.

Make sure the TestPoint footprint is set as TestPoint Bottom.

No testpoint under the components.

Check that the PCB name, revision number, and the fabrication date on the PCB silk screen are label

accordingly.

Check that no Overlay on pad.

Check that all silk screens on the top layer are not mirroredand all silk screens on the bottom layer are

mirrored.

Make sure all components are designated, and the designator shall be placed clearly next to the particularcomponent.

Make sure the designator not covered by componentafter soldering.

Make sure the pin1 indicator is on via or covered by components.

For small component (0603,0805)Refdes size, Height: 0.6mm, Width:0.1mm

For Big component (connector, Jumper) Height: 1mm, Width:0.15mm

Place Refdes in 0degree(read from Right to Left) or 90degree(read from North to South) only.

Make sure thosegold contactpad is un-paste. Eg. battery contact and antenna contact

Make the solder mask for fine-pitch pad set to manufacturer minimum spec

Solder mask override = 0.075mm

Check the polarityof footprint is matching the schematic?? Example for LED in schematic, pin1 is cathode

but in footprint pin1 is anode.

check the diff pair track width and spacing.Refresh all the polygons.

Run the DRC. Make sure no errors to be encountered unless there are acceptable known constraints. The

result of the DRC shall be printed and filed.

All Via are tenting.

Recheck the importantConnector Coordinatebefore tape out.

Check the Product_Nameand Dateon PCB is correct.

TopOverlay pin1 indicator is not on via.

Check dangling via.

Check dangling track.

Double check the overlap polygon, sometime the polygon is void by another polygon as shown in the

commnet photo.

Panelize/ Panelize board Originat the fiducial, place Origin(0,0) OverlayTop.For multipack, the Refdesignator is samefor all duplicated PCB.

Check the PCB and gerber file that all PCB are copied exactly same.

Put the panel DIMENSION.

The outrigger NPTH need to be 5mmf rom NPTH edge to outr igger edge. (need to revise) 20120925: reque

The center of fiducial to outrigger board edge need at least 3mm. 20120930: emai

BKM BKM: Use copy , then EDIT-PasteSpecial -> copy refignator, paste special. Remember to change

Document>Option>SnapX&SnapY to 0.001mm in order to paste acurrately the new duplicated brd.

Before tape out Make sure the put the legend on Drill drawing layer **To add a Drill

the String ".LEGE

Check the size anddimensionof the PCB. It should be as specified.

Dimension = 98.2mm (X) x 80.8mm (Y)

Check product nameandRevisionon the the Drawing table.

For Prototype PCB, the soldermask color is RED. And for Mass production PCB, the soldermask color is

GREEN.

BKM If unsure on soldermask/solderPaste is open/closed, pls generate gerber and review the gerber files.

Generate CAM

files

.pcb file_name too long will cause error on generating gerber file, I did test and error on PicknPlace file.

(Max= 22characters)

Others

Gerber

Labeling/Over

lay

Finalize Singleboard Brd


4/5

Check all layers Gerber has been generated.

Example for 4layers board:

file_name.REP

file_name.GTL (Top Layer)

file_name.G1 (Middle Layer 1)

file_name.G2 (Middle Layer 2)

file_name.GBL (Bottom Layer)

file_name.GM1 (Mechanical 1)

file_name.GM3 (Mechanical 3)

file_name.GTO (Top Overlay)

file_name.GBO (Bottom Overlay)file_name.GTS (Top Soldermask)

file_name.GBS (Bottom Soldermask)

file_name.GTP (Top Paste)

file_name.GBP (Bottom Paste)

file_name.GPT (Top Pad Master)

file_name.GPB (Bottom Pad Master)

file_name.GG1 (Drill Guide)

file_name.GD1 (Drill Drawing) -- got the ABCD location of drill and Drill Legend.

'NC Drill Output '

file_name.DDR

file_name.DRL

file_name.txt

'Pick Place Output 1'

Pick Place for file_name.txt

Status Report.txt

PCB Spec.txt

Open the Gerber file with CAM manager and make sure the layout is correct (beware of me

which will appear at every layer)

Check the Readme.txt/PCB_Spec.txt has been included and describes the boards fabricatio

details.

Check the StackMark.txt is included in the files to be sent.


5/5

KingCredie PCB capability

min. Outer Track width

min. Inner Track width (0.5Oz)

min. PTH size

min OUter PTH_annular_ring

min Inner_PTH_annular_ring

min. space for Inner_track_edge to Conductive :

min. space for Outer_track_edge to Conductive :

min. space for track_edge to PTH_annular_ring_edge.

min. space for Outer_track_edge to Pad_edge:

min. space for track_edge to Polygon_edge.

min. space between PTH_annular_ring_edge to PTH_annular_ring_edge.

min. space between PTH_annular_ring_edge to Pad_edge.

min. space between PTH_annular_ring_edge to Polygon_edge.min. space between NPTH_edge to conductive:

min. space between Pad_edge to Polygon_edge.

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