Number of address field vs. performance-(Instruction format)+ Three-address instructions+ two-address instructions+ one-address instructions and ACC+Addressing mode-+ Immediate+ Direct/ Indirect+ Relative+ IndexedInstruction Set (IS) design-+ Complex Instructions Set (CISC)+ Reduced Instructions Set (RISC)Instruction field-+ Type field+ Opcode filed+ Dest+ Src+ ...

Chapter 4 - Part 1:

Instructions Set flowchart-Processor ASM chart -RISC processor Design-+ Data dependency+ Data forwarding+ Branch prediction

Chapter 4 - Part 2:

Simple datapath (datapath is ready)-- Standard datapath (datapath is ready)

+ Algorithm (pseudo-code) for a particular task+ Control word table for Datapath+ FSM for Control Unit+ Next state table & equations of Control Unit+ Output table & equations of Control Unit

Chapter 2 - Part 2:

Chapter 3 - Part 1:

+ ASM chart: State-based (Moore) chart, Input-based (Mealy) chart+ State-action table: State-based table, Input-based table+ Next state and Output equations of Control Unit+ Schematic

Design a Custom-design (ASIC) by FSMD model

- Register sharing+ Left-edge algorithm: sort list of variables table, register assignment, datapath schematic.+ Graph-partitioning algorithm: compatibility graph, variables merging, register assignment, datapath schematic.

- Functional-unit sharingGraph-partitioning algorithm: compatibility graph, operators merging, register assignment & functional unit allocation, datapath schematic.

- Bus sharing (slide part 3)Graph-partitioning algorithm: compatibility graph, wires merging, bus assignment, datapath schematic.

Chapter 3 - Part 2:

Overview of Final term - Digital Logic Design (CE118)12/26/2014 12:31 PM

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