organic ﬁeld-e•ect transistors and all-polymer integrated ... · and modeling the temperature...

Organic ®eld-e�ect transistors and all-polymer integratedcircuits

M. Matters *, D.M. de Leeuw, M.J.C.M. Vissenberg, C.M. Hart, P.T. Herwig,T. Geuns, C.M.J. Mutsaers, C.J. Drury

Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands

Abstract

Electrical properties of ®eld-e�ect transistors made of di�erent solution processable organic semiconductors are

described. The temperature and gate-voltage dependence of the mobility is shown and theoretically described using a

model based on the variable-range hopping of charge carriers in an exponential density of states. Furthermore, a

technology has been developed to make all-polymer integrated circuits. It involves reproducible fabrication of ®eld-

e�ect transistors on ¯exible substrates, where the semiconducting, conducting and insulating parts are all made of

polymers. Integrated circuits consisting of more than 300 ®eld-e�ect transistors are demonstrated. Ó 1999 Elsevier

Science B.V. All rights reserved.

PACS: 85.40.Le; 85.40.-e; 85.30.Tv; 72.80.Le

Keywords: Organic semiconductors; IC-technology

1. Introduction

In recent years the use of organic semiconduc-tors in ®eld-e�ect transistors has gained consider-able interest due to their potential application inlow-cost integrated circuits or as thin-®lm tran-sistors in active matrix LCD displays. Most e�orthas been put into increasing the hole mobility ofthe semiconductor and increasing the on±o� ratioof the ®eld-e�ect transistor by optimising existingmaterials and by applying new materials. Mobili-ties as high as 2 cm2/V s and on±o� ratios of 108have recently been reported in thin-®lm transistorsof evaporated pentacene [1,2]. Furthermore, at-tention has been focused on the improvement of

the processability of these materials by using di-rectly soluble [3] or precursor organic semicon-ductors [4]. Easy processing is a prerequisite forthe development of low-cost plastic electronicsthat can compete with silicon on the low-endmarket. This may also mean that the (organic)semiconductor is only a part of a complete inte-grated-circuit technology that is potentially cheapin total. Furthermore, the interesting property ofmechanical ¯exibility can only be exploited if theorganic semiconductor is used in a ¯exible envi-ronment. The combination of materials researchand integration technology is the subject of thispaper.

The paper is organized as follows. First theelectrical transport properties of two solution-processable organic semiconductors, a polymer(polythienylenevinylene, PTV) and a small mole-cule (pentacene), are investigated, by describing

Optical Materials 12 (1999) 189±197

* Corresponding author. Tel.: +31-40-2742114; fax: +31-40-

2743365; e-mail: [email protected].

0925-3467/99/$ ± see front matter Ó 1999 Elsevier Science B.V. All rights reserved.

PII: S 0 9 2 5 - 3 4 6 7 ( 9 9 ) 0 0 0 6 4 - 6

and modeling the temperature dependence of the®eld-e�ect mobility. Secondly, it is shown that theroom temperature mobility of these semiconduc-tors can be improved by optimising the processconditions. Finally, a technology is described tomake all-polymer integrated circuits. Functionalintegrated circuits of more than 300 transistors aredemonstrated.

2. Electrical transport in amorphous organic semi-

conductors

Besides the technical applicability of organicsemiconductors, their electronic and structuralproperties have been the subject of investigation aswell. Interesting questions like the connection be-tween molecular order and hole mobility in con-jugated oligomers and polymers have beenaddressed [1,8±11].

Experiments have indicated that the ®eld-e�ectmobility of holes in organic transistors depends onthe temperature as well as on the applied gate bias[4,12]. This has been described by Horowitz et al.[12] using a multiple trapping and release model.In this model the assumption is made that most ofthe charge carriers are trapped in localized states.Then the amount of (temporarily) released chargecarriers to an extended-state transport level (thevalence band for classical p-type semiconductors)depends on the energy level of the localized states,the temperature, and the gate voltage. However,while extended-state transport may occur in highlyordered vacuum-evaporated molecular ®lms [12] itis not expected to play a role in amorphous or-ganic ®lms [4] where the charge carriers arestrongly localized.

Here a theory for the ®eld-e�ect mobility inamorphous organic transistors is described, wherethe charge transport is governed by hopping, i.e.the thermally activated tunneling of carriers be-tween localized states, rather than by the activa-tion of carriers to an extended-state transportlevel. The concept of variable range hopping(VRH) is used, i.e. a carrier may either hop over asmall distance with a high activation energy or hopover a long distance with a low activation energy.In a ®eld-e�ect transistor, an applied gate voltage

gives rise to the accumulation of charge in the re-gion of the semiconducting layer that is close tothe insulator. As these accumulated charge carriers®ll the lower-lying states of the organic semicon-ductor, any additional charges in the accumulationlayer will occupy states at relatively high energies.Consequently, these additional charges will (onaverage) require less activation energy to hop awayto a neighboring site. This results in a higher mo-bility with increasing gate voltage. The in¯uence oftemperature and the in¯uence of the ®lling ofstates on the conductivity is studied in a VRHsystem with an exponential distribution of local-ized-state energies. Using percolation theory, ananalytic expression is derived for the conductivity.This expression is then used to derive the ®eld-ef-fect mobility of the carriers when the material isapplied in a transistor. Finally, the result is used tointerpret the experimentally observed temperatureand gate-voltage dependence of the ®eld-e�ectmobility in both a pentacene and a polythienylenevinylene (PTV) organic thin-®lm transistor [4].Here, only the main results of the calculation aregiven, for a full derivation see Ref. [13]. First anexpression is derived for the conductivity as afunction of temperature T and charge carrierdensity. At low carrier densities and low T, thetransport properties are determined by the tail ofthe density of (localized) states (DOS), which ismodeled by

g�e� � Nt

kBT0

expe

kBT0

� ��ÿ1 < e6 0�; �1�

where Nt is the number of states per unit volume,kB is Boltzmann's constant, and T0 is a parameterthat indicates the width of the exponential dis-tribution. The density of states g�e� � 0 for posi-tive values of e. Let the system be ®lled withcharge carriers, such that a fraction d 2[0,1] of thelocalized states is occupied by a carrier, i.e. suchthat the density of charge carriers is dNt. Inequilibrium, the energy distribution of the carriersis given by the Fermi±Dirac distribution f �e; eF�,where eF is the Fermi energy (or chemical po-tential). For a given carrier occupation d the po-sition of the Fermi energy eF is ®xed by thecondition

190 M. Matters et al. / Optical Materials 12 (1999) 189±197

d � 1

Nt

Zde g�e�f �e; eF�

� expeF

kBT0

� �C�1ÿ T=T0�C�1� T=T0�; �2�

where C � R10

exp�ÿy�yzÿ1. In Eq. (2) the as-sumption is made that most carriers occupy thesites with energies e� 0 i.e., ÿeF � kBT0. Thiscondition is ful®lled when d and T are low. Notethat at T� 0 the gamma functions are unity andthe carrier density is given by the density of stateswith energies lower than eF. The approximate ex-pression (2) breaks down at temperaturesT P T0, since most carriers are then located closeto e� 0.

The transport of carriers is governed by thehopping of carriers between localized states, whichis strongly dependent on the hopping distances aswell as the energy distribution of the states. At lowbias, the system can be described as a resistornetwork [14,15]. Based on percolation theory [15±17] an expression has been derived for the con-ductivity r as a function of the occupation d andthe temperature T [13]:

r�d; T �

� r0

pNtd�T0=T �3�2a�3BcC�1ÿ T=T0�C�1� T=T0�

!T0=T

;

�3�

where r0 is a (unknown) prefactor, a is an e�ectiveoverlap parameter, which governs the tunnelingprocess between two localized states, and Bc � 2:8is the critical number of bonds per site in thepercolating network [16,17].

Note that the conductivity has an Arrhenius-like temperature dependence r � exp�ÿEa=�kBT ��,with an activation energy Ea that is weakly (loga-rithmically) temperature dependent. This is instrong contrast with the well-known Mott formulafor VRH in a constant DOS, where r �� exp��ÿT1=T �1=4� [18]. The temperature depen-dence of the Mott formula is a consequence ofhopping over far distances and hopping to highenergies being equally important. In an exponen-tial DOS, however, the characteristic hop is an

activated jump, since there are much more avail-able states at higher energies.

Now the obtained conductivity (3) is applied todescribe the ®eld-e�ect mobility lFE in a transistor.In bulk material, the mobility l of the chargecarriers is given by l � r�d; T �=�edNt�. In a tran-sistor, however, the charge density is not uniform,but it decreases with the distance x from thesemiconductor-insulator interface. According toEq. (2), the occupation d�x� depends on the dis-tance x through the gate-induced potential V �x�,

d�x� � d0 expeV �x�kBT0

� �; �4�

where d0 is the carrier occupation far from thesemiconductor-insulator interface, where V �x� � 0.The variations of V �x� and d(x) with the distance xare determined by the Poisson equation. Substi-tuting the distance-dependent charge occupationd(x) into Eq. (3) for the conductivity, the source-drain current of the transistor in the linear re-gime�ÿVD < ÿVG� reads

I � WVD

L

Z t

odx r d�x�; T� �: �5�

Here, VD is the drain voltage (the source is theground electrode) and L, W and t are the length,width, and thickness of the channel, respectively.The ®eld-e�ect mobility then follows from thetransconductance (see, e.g., Ref. [4])

lFE �L

CiWVD

oIoVG

: �6�

From Eqs. (3)±(6) the following expression is ob-tained for the ®eld-e�ect mobility [13],

lFE �r0

ep�T0=T �3

�2a�3BCC�1ÿ T=T0�C�1� T =T0�

!T0=T

� �CiVG�22kBT0es

" #T0=Tÿ1

; �7�

where the assumption is made that the thickness tof the semiconductor layer is su�ciently large suchthat V(t)� 0. Then the ®eld-e�ect mobility is in-dependent of the thickness t as well as the bulkcarrier occupation q0.

M. Matters et al. / Optical Materials 12 (1999) 189±197 191

The result (7) is applied to the experimental dataof Ref. [4], where the drain current I versus gatevoltage VG characteristics have been measured ofboth a pentacene and a polythienylene vinylene(PTV) organic thin-®lm transistor at a range oftemperatures. The precursors of both organicsemiconductors are spin-coated from solution on asubstrate consisting of a heavily n-doped silicon(common) gate electrode, a 200 nm thick SiO2 in-sulating layer (Ci� 17 nF cmÿ2) and a patternedgold layer as the source and drain electrodes. Theprecursors are converted into the organic semi-conductors using a process described in Ref. [4].Typical channel widths and lengths were W� 10±20 mm and L� 2±20 lm, respectively. The ®lmthickness t varied from 30 to 50 nm. For bothsemiconductors, a relative dielectric constant er� 3is used, which is appropriate for most organicsolids. In Fig. 1 the ®eld-e�ect mobility in a pent-acene and in a PTV thin-®lm transistor is plottedagainst the inverse temperature for di�erent gatevoltages. Experimentally, the ®eld-e�ect mobilitiesare determined from Eq. (6) at VD�ÿ2 V. Thetheoretical curves (solid lines) follow from Eq. (7),where r0, a, and T0 are used as ®tting parameters.The agreement with experiment is quite good (theparameter values are given in Table 1). The

temperature dependence of lFE, as shown inFig. 1, follows a simple Arrhenius behaviorlFE � exp[ÿEa/(kBT)], where the activation energyEa depends on VG as plotted in Fig. 2. The de-crease of Ea with increasing (negative) gate voltageis the direct result of accumulated charges ®llingthe lower-lying states.

The ®eld-e�ect mobility in PTV is more thantwo orders of magnitude lower than the ®eld-e�ectmobility in pentacene. Furthermore, the activationenergy for PTV is about twice the activation en-ergy for pentacene. Surprisingly, these di�erencescannot be attributed to di�erences in the prefactorr0 nor to the width of the energy distribution T0,as these parameters have similar values for PTV aswell as pentacene (see Table 1). The main di�er-ence between pentacene and PTV appears to be inthe overlap parameter a, which determines thetunneling process between di�erent sites. Note thatthis key parameter is absent in a multiple-trapping

Fig. 1. Field-e�ect mobility lFE in a pentacene and a poly-

thienylene vinylene (PTV) thin-®lm transistor as a function of

temperature T for di�erent gate voltages VG�ÿ20 V (trian-

gles), ÿ10 V (circles) and ÿ5 V (squares). The experimental

data (symbols) are taken from Ref. [4]. The solid lines are ac-

cording to Eq. (7), using the parameters given in Table 1.

Table 1

The pre-exponential factor to the conductivity r0, the overlap

parameter aÿ1 and the width of the exponential distribution

o¯ocalized states T0 for both pentacene and polythienylene

vinylene (PTV) as obtained from the ®t of Eq. (7) to the ex-

perimental data of [4], see Fig. 1

r0 (1010 S/m) aÿ1 (A) T0 (K)

Pentacene 1.6 2.2 385

PTV 0.7 0.8 380

Fig. 2. Activation energy Ea for the ®eld-e�ect mobility in a

pentacene and a polythienylene vinylene (PTV) thin-®lm tran-

sistor as a function of the gate voltage VG. The experimental

data (squares) are taken from Ref. [4]. The solid lines are cal-

culated from Eq. (7), using the parameters given in Table 1.


model, where the transport is governed by thermalactivation from traps to a conduction band andsubsequent retrapping, without involving a tun-neling step. As the length scale aÿ1 is smaller thanthe size of a molecule, one must be cautious not tointerpret aÿ1 simply as the decay length of theelectronic wave function. The size and shape of themolecules and the morphology of the organic ®lmare expected to have an important in¯uence on thetunneling probability as well. The observed dif-ference in aÿ1 may be due to the fact that there ismore steric hindrance in the polymer PTV than ina system of small pentacene molecules. The betterstacking properties of pentacene give rise to alarger area of overlap of the electronic wavefunctions, which results in a larger e�ective overlapaÿ1 in the model. Hence in the solution-processedorganic transistors discussed here, the ®eld-e�ectmobility appears to be limited by the structuralorder of the organic semiconducting layer.

3. Improved processing of precursor organic semi-

conductors

As explained in the previous section the mo-bility of organic semiconductors depends on theordering of the material. As a consequence it isworthwhile trying to optimize the ordering in thethin ®lms by varying the process parameters, forexample the conversion conditions of the precur-sor materials. Furthermore, the main part of theelectrical transport in the thin-®lm transistorstakes place in the ®rst few nanometers of the ®lmat the semiconductor insulator interface. Improv-ing the interface can also lead to a better perfor-mance of the transistor. While the (microscopic)mechanisms are still subject of investigation, themobility of the precursor-route pentacene transis-tors was improved by more than one order ofmagnitude to 0.1 cm2/V s [19]. This was achievedby converting the precursor on a hot plate at200°C for 5 s, di�erent from the conditions usedearlier [4]. Also the SiO2 surface was treated withthe hydrophobic primer hexamethyldisilazane(HMDS). The conversion of precursor PTV on aprimed SiO2 surface also led to a higher mobility(0.001 cm2/V s) compared to previous results [4].

The transfer characteristics of both a pentaceneand a PTV thin-®lm transistor are shown in Fig. 3.The temperature and gate-voltage dependence ofthe mobility of these improved transistors is underinvestigation. However, it is interesting to notethat the high mobility of the pentacene transistorsis only one order of magnitude lower than themobility of the pentacene transistors prepared bythermal evaporation under controlled conditions[1,2].

4. All-polymer integrated circuits

As discussed in the previous section, organicsemiconductors have been applied as the activecomponent in thin ®lm transistors. Charge carriermobilities comparable to that of amorphous sili-con (0.1 cm2/V s) were obtained [1±3]. Organictransistors have also been combined [4] into logicgates. However, with a few exceptions [20], onlythe semiconductor consisted of an organic mate-rial. The other parts of the ®eld-e�ect transistors,namely source, drain and gate electrode, and gatedielectric, were made with standard lithographicand etching techniques of conventional inorganicmaterials. Recently, we have developed a tech-nology that makes it possible to fabricateall-polymer transistors that can be combined intoall-polymer integrated circuits. A summary of our

Fig. 3. Drain current versus gate voltage taken at drain voltages

of ÿ2 V (bottom curve) and ÿ20 V (top curve) for both a

pentacene (circles) a PTV (squares) thin ®lm transistor. The

capacitance of the insulator is 17 nF/cm2, the channel width

over length ratio is 1000.


results is given below. A more detailed descriptionis given in Refs. [5±7].

In order to fabricate the conducting parts of theall-polymer integrated circuits use is made ofphoto-chemically patterning [21] of doped poly-aniline (PANI) conducting ®lms as shown inFig. 4. A micrograph of a structured PANI ®lm isalso displayed.

Polyaniline p-doped with camphorsulfonic acidis dissolved [22] in m-cresol. A photoinitiator is

added to this solution which is then spin-coatedonto a substrate such as a polyimide foil. Under anitrogen atmosphere the ®lm is exposed through amask to deep UV radiation. Upon exposure theconducting polyaniline is reduced to the noncon-ducting form. The sheet resistance then increasesfrom 103 X/square to more than 1014 X/square. Asa result, conducting tracks are embedded in anotherwise insulating ®lm. The height di�erencesbetween the exposed and unexposed parts of the®lm, with thickness typically 0.2 lm, is less than 50nm and thus no further planarisation is necessary.Unexposed photoinitiator is removed throughsublimation by heating at 110°C.

The conducting PANI tracks are used as inter-connects and as terminals of all-polymer ®eld-ef-fect transistors.

A cross section of the discrete PMOS transistorsis shown schematically in Fig. 5. Only three masksare needed in the process. A polyimide foil gluedonto a carrier, e.g. currently a regular siliconwafer, is used as a substrate. The source and drainelectrodes are de®ned in the bottom PANI layerby UV light exposure through the ®rst mask.Then a 50 nm thin semiconducting [4] poly-thienylenevinylene (PTV) ®lm is applied by con-version of a spincoated precursor ®lm. The PTV®lm largely determines the electrical parameters ofthe transistor. It is noted that PTV is not a state-of-the-art organic semiconductor, it is being usedonly to optimize the technology. Onto the PTV®lm a 250 nm thin polyvinylphenol (PVP) layer isspin coated. The PVP layer is used as gate dielec-tric and also as insulator for the second layer ofinterconnect. This second level and the gate elec-trodes are de®ned in the top PANI layer using thesecond mask.

Stack-integrity is a requirement throughout thewhole process; dissolution or physical change of

Fig. 4. (a) Patterning of a conducting polyaniline ®lm using

deep UV light through a mask. (b) Micrograph of a structured

polyaniline ®lm. Shown here are the (interdigitated) source and

drain contacts of a single all-polymer transistor. Fig. 5. Cross section of an all-polymer thin ®lm transistor.


previously deposited layers must be prevented.Hence, for the PTV precursor a solvent is chosenwhich does not dissolve the structured bottomPANI layer. PTV itself is insoluble in commonorganic solvents and the PVP dielectric is madeinsoluble by cross-linking [5,6]. Finally, the inver-ted geometry of the transistors having a topcommon gate electrode prevents degradation ofthe PTV semiconductor by deep UV irradiation,see Fig. 5.

Transistors with channel lengths down to 2 lmare routinely obtained and even functional 1 lmtransistors have been fabricated. Electrical char-acteristics of a transistor with a channel length of 2lm and a channel width of 1 mm are presented inFig. 6.

The PMOS transistors operate in accumulationmode. The channel is already enhanced at 0 V bias;i.e. they are ``normally ON'' devices. Hysteresis isclockwise and may be due to charge trapping inthe PVP gate dielectric. The resulting thresholdvoltage shift is one of the reliability issues that arepresently being investigated. Other issues includeshelf- and operational lifetime. Limited prelimi-nary data show that shelf lifetime may depend onthe ambient: the presence of water sometimes isdetrimental. The operational lifetime varies fromseconds to hours. Current saturation is clearlyobserved at higher drain voltage. The charge car-rier mobility is 3 ´ 10ÿ4 cm2/V s at a gate voltageof ÿ10 V. This mobility is dependent on the gatevoltage. Combining several transistors into

integrated circuits requires the use of vertical in-terconnects (vias) between (bottom) source anddrain electrodes of one transistor and the (top)gate electrode of another transistor. A simplemechanical technique for the fabrication of thevertical interconnects is used. Sharp pins arepunched through overlapping contact pads de®nedin top and bottom electrode layers. Removal of thepins results in holes in the ®lm and in a local in-timate mixing of the top and bottom PANI elec-trodes. Complete foils with large quantities ofvertical interconnects are made using an auto-mated process with the third mask containing in-formation on the position of the vias. The contactresistance typically is 3 kX for each via.

Transistors were combined into simple test cir-cuits such as inverters and 2-input NAND gates.In the design the property that the ®eld-e�ecttransistors are already enhanced at 0 V gate-sourcebias is used. Therefore, the load transistor (seeFig. 7) can act as a constant current source.

Transfer characteristics for these test circuitswith channel lengths down to 2 lm show voltageampli®cation. Hence, they are successfully coupledinto 7-stage ring oscillators. The oscillators oper-ate at supply voltages as low as 3 V. Their oper-ating frequency typically is 40±200 Hz, and isdominated [4] by the RC time constant of the loadtransistors of the logic gates.

In more complex circuits the basic cells arelimited to single input inverters and 2-inputNAND gates. Similarly, the channel length was

Fig. 6. I±V characteristics of all-polymer thin ®lm transistor. Fig. 7. Schematic of a 2-input NAND gate.


chosen as 5 lm to order to get maximum robust-ness against spread in individual transistor pa-rameters.

As an example D-type ¯ip-¯ops were con-structed of 2-input NAND gates and successfullyoperated in a divide-by-2 arrangement.

To demonstrate the ability to fabricate func-tional integrated a 15-bit mechanically program-mable code generator was made. A micrograph ofpart of it is shown in Fig. 8. The channel widthsare 0.2 mm and 1 mm for the driver and loadtransistors respectively. The black spots in Fig. 8are the mechanically made vias. The width of theinterconnect is 10 lm. The integrated circuit,combining 326 transistors and over 300 vias,consists of an on-board clock generator, a 5 bitcounter, decoder logic and 15 programming pads.A large output transistor modulates the supplycurrent according to the programmed pattern. Thecircuit produces a user (mechanically) program-mable serial data stream of 15 bits. A DC voltageis applied and the current through the outputtransistor is measured.. The bit rate obtained is 30bits/s. The circuits remain functioning when thefoils are sharply bent. The code generator can forexample be used as a programmable load of atuned LC circuit, forming an electronic bar codelabel. The (programmed) serial data stream canthen be read at a distance when the label is put inan electromagnetic ®eld at the LC-resonance fre-

quency [6,7]. Note that the ®eld also provides thelabel with the necessary supply voltage. A photo-graph of a ®nished foil, presented in Fig. 9, showsa ¯exible substrate containing about 50 identicaldies. Each die contains a variety of componentsand electronic test circuits for characterization andmodeling as well as one 15-bit programmable codegenerator. These integrated circuits are visible asthe high-density rectangles.

5. Summary

In summary, the electrical properties of twosolution-processed organic semiconductors (pent-acene and PTV) were investigated and a model waspresented to describe the gate-voltage and tem-perature dependence of the mobility of (amor-phous) organic transistors. Furthermore, animprovement of the room temperature mobility byone order of magnitude of both pentacene andPTV was shown to be possible by optimizing theprocess conditions. Finally, functional all-polymerintegrated circuits have been realized using a sim-ple and potentially inexpensive technology. At-tention is now focused on further decrease of costand on increasing the operating frequency by usingpolymeric semiconductors with higher chargecarrier mobility and by scaling down the lateraldimensions.Fig. 8. Micrograph of part of the 15-bit code generator.

Fig. 9. Photograph of a 300 polyimide foil containing the all-

polymer integrated structures.


Acknowledgements

Financial support from the EC under ESPRITproject 24793 FREQUENT and from the DutchScience Foundation NWO/FOM is gratefully ac-knowledged.

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