Robust

Low

Power

VLSI

Optimizing SRAM Bitcell Reliability and Energy for

IoT Applications

Harsh N. Patel, Farah B. Yahya, Benton CalhounUniversity of Virginia

VA - USA

- Motivation- Metrics for evaluation- Metric trade-offs- Test Chip results- Conclusion

2

Outline

- SRAM dissipates more than 60% of total SoCspower[1]

- Demands lower operating VDD (CVDD2)

- Energy optimal point falls in sub-threshold region

3

Motivation

[1] ISSCC 2015

- Sub-threshold design challenges:

4

Motivation

0 200 400 600 800 1000 1200100

102

104

106

108

VDS (mV)

Nor

mal

ized

I ON

/ I O

FF R

atio

NMOS

0 200 400 600 800 1000 1200100

102

104

106

108

VDS (mV)

Nor

mal

ized

I ON

/ I O

FF R

atio

PMOS

TT FF FS SF SS

Higher Variation

20X

Ion/Ioff reduction

1000X

Dedicated Read Port

5

Motivation

Bitcell Device UsagePU PD PG RA

HVT high-VT high-VT high-VT high-VT

SVT Standard-VT Standard-VT Standard-VT Standard-VT

MVT1 high-VT high-VT Standard-VT Standard-VT

MVT2 Standard-VT Standard-VT high-VT high-VT

MVT3 high-VT high-VT high-VT Standard-VT

MVT4 high-VT Standard-VT Standard-VT Standard-VT

- Metrics of interest: Reliability and Energy.

6

Metric Consideration

Category Evaluation Metrics

Reliability Date Retention Voltage(DRV)

Hold & Read Static Noise Margins

(HSNM / RSNM)

Write Margin (WM)

Dynamic Leakage Power Read/Write Energy (Power-Delay product)

DRV: Minimum VDD below which the storage nodes (Q/QB) flip when the bitcell is un-accessed.

HSNM: Ability of an un-accessed bitcell (WWL/RWL=0, BL=BLB) to reject DC noise.

RSNM: Ability of the half-selected cell to maintain its state during pseudo-read operation (WWL=1, BL=BLB).WM: Ability of the bitcell to write into the cell (flip the content of storage nodes)

Setup: Variation Consideration: Intra-die: 1000-point Monte Carlo (MC) Inter-die: Across corners (FF, FS, TT, SF, SS) Temperature: [-50, 125]°C

7

Metric Consideration: Reliability

a) DRV

8

Reliability - Intra-die variation

100 150 200 250 300 350 400 450 5000

50

100

150

200

250

300

350

400

DRV (mV)

Occ

uran

ce

SVT HVT/MVT3 MVT1 MVT2 MVT4

(Max., + 3 )mVBest : HVT (245.3, 239.8)Worst: MVT4(487.8, 473)

-0.3 -0.2 -0.1 0 0.1 0.2 0.30

50

100

150

200

250

300

350

400

VT

DR

V (m

V)

PU1 PD1 PG1 PU2 PD2 PG2

PU1 & PD2: Increasing ON current

Bitcell holds ‘1’ (Q=‘1’ and QB=0)

PG2:Reducing OFF current

b) HSNM/RSNM

9

Reliability - Intra-die variation

50 100 150 200 250 3000

50

100

150

200

250

300

350

HSNM (mV)

Occ

uran

ce

Best : HVT / MVT3 (189, 232)Worst : MVT4 ( 73, 86)

(Min., - 3) mV

-100 -50 0 50 100 150 200 250 3000

50

100

150

200

250

300

350

400

RSNM (mV)

Occ

uran

ce

SVT HVT / MVT3 MVT1 MVT2 MVT4

(Min., - 3) mVBest : MVT2 (133, 130)Worst : MVT1 ( -56, -48)

c) WM

10

Reliability - Intra-die variation

-200 -100 0 100 200 300 400 5000

50

100

150

200

250

300

350

400

Write Margin (mV)

Occ

uran

ce

SVT HVT/MVT3 MVT1 MVT2 MVT4

Best : MVT1 (266, 269)Worst : MVT2 (-154, -141)

(Min., -3)mV

Variation Index (VI):“The maximum deviation in a metric that a chip, fabricated at any corner, can experience due to temperature variation”.

11

Reliability – Inter-die variation

-50 -25 0 25 50 75 100 125150

200

250

300

350

400

450

500

550

Temperature (oC)

DR

V (m

V)

TTFFFSSFSS

=

59mV

130mV

=

= 50mV

51mV =

50mV =

Variation Index = max(130, 59,50,50) SVT Bitcell

Variation Index (VI)

12

Reliability – Inter-die variation

Comparison of Variation Index (VI) for different metrics across bitcells

a) Leakage Power

13

Metric Consideration: Dynamic

-50 -25 0 25 50 75 100 12510

1

102

103

104

105

Temperature (oC)

Leak

age

Pow

er (n

W)

SVT HVT MVT1 MVT2 MVT3 MVT4

HVT Bitcell offers ~[142 – 755]% leakage power reduction compared to SVT bitcell

1KB Array

b) Write/Read Energy

14

Dynamic

0.4 0.5 0.6 0.7 0.8 0.9 110

-8

10-7

10-6

10-5

10-4

10-3

10-2

VDD (V)

Ener

gy (p

J)

Write Energy (Corner: FS)

SVTHVT / MVT3MVT1MVT2MVT4

0.4 0.5 0.6 0.7 0.8 0.9 110

-5

10-4

10-3

10-2

10-1

VDD (V)

Ener

gy (p

J)

Read Energy (Corner:SS)

SVT / MVT1 / MVT3 / MVT4HVT / MVT2

Standard-VT devices offer lower Eactive

Delay dominates the energy at lower VDDs

Leakage dominates the energy at higher VDDs

Worst corner array Write/Read energy comparison of different bitcells

15

Comparison

Dynamic

Leakage HVT/MVT3 MVT1 MVT2 MVT4 SVT

Write Energy MVT1 SVT MVT2 HVT/MVT3 MVT4

Read Energy SVT / MVT4 / MVT1 / MVT3 MVT2 / HVT

Static Best-to-Worst bitcell choice (left to right)

DRV HVT/MVT3 MVT1 SVT MVT2 MVT4

HSNM HVT/MVT3 MVT1 MVT2 SVT MVT4

RSNM MVT2 HVT/MVT3 SVT MVT4 MVT1

WM MVT1 SVT MVT4 HVT/MVT3 MVT2

16

Test chip results

0 5 10 15 20 25101

102

103

Chip number

Leak

age

Cur

rent

(nA

)

Leakage current across chips (VDD=0.5V)

HVT MVT3

MVT3 bitcell has ~2X higher leakage power compared to HVT bitcell due to standard-VT read port

17

Test chip results

Exponential increase in delay cause energy reduction

18

Conclusion

Design Metric

Best Bitcell choice

Trade-off(s) metrics Possible IoT application

DRV MVT2 WM + Leakage Applications w/ longer stand by time(e.g. remote sensing)

HSNM HVT/MVT3 WM + Write speed

Robust design to operate in noisyenvironments (difficult terrainsensing)

RSNM MVT2 WM + Leakage Low VDD write operation (low-powerapplication)

WM MVT1 RSNM + DRV

Leakage HVT Write/Read Delay + WM

‘Mostly Stand-by’ application (e.g.body sensing)

Active Energy MVT1 / MVT3

‘Mostly Active’ application (e.g.DSP, speech processing )

Optimal bitcell selection summary w/ trade-offs and targeted IoT application

19

Thank you!