optical fiber communications technology, systems and circuits overview

Optical Fiber CommunicationsTechnology, Systems and Circuits OverviewLecturer: Ali Fotowat AhmadyFeb 7, 2012Tabriz University Photonics Conference**Sharif University of Technology

Sharif University of Technology

AgendaWhy Optical Communications?Broadband Access TechnologiesFTTx PON TechnologyGPON: System Overview and Protocol StackOptical TransceiversCMOS Optoelectronic ReceiverCMOS CDR and DEMUX IC*Sharif University of Technology*


Traffic Growth and Power Consumption*Sharif University of Technology*


Limitations of Electrical LinksMarket Transition from Electrical to Optical*Sharif University of Technology*


Progress in Optical Communication Technology (2 of 2)*Sharif University of Technology*


Trend of Broadband Access Studies**Data speed (bps)1G100M10M100G10G20052000201020152020Year1995100BaseTGbE10GbE40/100GbEB-PONGE-PONG-PON10G-EPONNG-PON1Next targetSTM-PONIEEE802.3 STD2009.92010.5ADSLNG-PON2(WDM TDM Hybrid PON)P-PP-MPFTTH20 mill. users10 mill.(+ SCM-PON for video distribution)P-P: Point to PointP-MP: Point to MultipointSCM: Subcarrier ModulationNGA: Next Generation Accessmax.min.Sharif University of Technology


Access: Fiber To The X (FTTx)**Service NodeONUFTTHFTTBFTTCFTTCabOptical FiberPON SystemxDSLOLTONUNTNTFTTC: Fiber To The CurbFTTCab : Fiber To The CabinetFTTH : Fiber To The HomeFTTB : Fiber To The BuildingOperation SystemInternetLeased LineVOIPPSTN VideoTwisted PairONTONTPassive Optical SplitterSharif University of Technology


FTTX PON: The Critical Components**Optical AmplifierOptical Fiber CableONTWDM CouplerVideo TXOLTSplitter1490nm1310nm1550nmTxRxTxRxRx Up to 60 km* physical reach(* with G.984.6 Reach Extender)ONUAccess Node NBBBCCE1/DS1GbE STMn/OCn(and/or)Sharif University of Technology


xPON Comparison**Sharif University of Technology


PON Applications**STM1ONTSTM1ONTSTM1ONTATM10/100BTRemote DSLAM/DLC1. FTTP4. DSLAM Aggregation2. Cellular Backhaul3. CATV Multiple System OperatorSharif University of Technology


GPON Equipments**GPON OLTGPON ONUGPON ONUGPON ONTFiber CableTwisted PairElectrical or OpticalSplitterFTTCFTTHSharif University of Technology


GPON Equipments**Sharif University of Technology


Optical Food Chain*Sharif University of Technology*


Optical Communication Protocol Stack*Sharif University of Technology*


ITU-T Recommendations GPON Protocol Stack and Common Functions*Sharif University of Technology*Protocol stack for the GTCGPON common functions


GPON GTC Frame Format*Sharif University of Technology*GTC Layer Framing for Downstream and UpstreamDownstream GPON Frame Format


Generic Optical Fiber System*Sharif University of Technology*


D QFF

N

N

D QFF

*Sharif University of Technology*An 8.5-Gb/s Fully Integrated CMOS Optoelectronic Receiver Using Slope-Detection Adaptive Equalizer, JSCC 2010


Differential n-well Photodiode*Sharif University of Technology*LEE et al.: AN 8.5-Gb/s FULLY INTEGRATED CMOS OPTOELECTRONIC RECEIVER USING SLOPE-DETECTION ADAPTIVE EQUALIZER, JSCC 2010Rectangular n-well diodes are covered by light-blocking metals


Photodiode Responsivity Variation*Sharif University of Technology*LEE et al.: AN 8.5-Gb/s FULLY INTEGRATED CMOS OPTOELECTRONIC RECEIVER USING SLOPE-DETECTION ADAPTIVE EQUALIZER, JSCC 2010 Doping dependency of the photodiode responsivity at 3-dB frequency (5.9 GHz)temperature dependency of the photodiode responsivity


Variation of CPD*Sharif University of Technology*LEE et al.: AN 8.5-Gb/s FULLY INTEGRATED CMOS OPTOELECTRONIC RECEIVER USING SLOPE-DETECTION ADAPTIVE EQUALIZER, JSCC 2010Doping dependencies of CPDTemperature dependencies of CPD


Block diagram of the proposed adaptive equalizer*Sharif University of Technology*LEE et al.: AN 8.5-Gb/s FULLY INTEGRATED CMOS OPTOELECTRONIC RECEIVER USING SLOPE-DETECTION ADAPTIVE EQUALIZER, JSCC 2010


Proposed OEIC Receiver*Sharif University of Technology*LEE et al.: AN 8.5-Gb/s FULLY INTEGRATED CMOS OPTOELECTRONIC RECEIVER USING SLOPE-DETECTION ADAPTIVE EQUALIZER, JSCC 2010


Proposed Adaptation Circuit*Sharif University of Technology*LEE et al.: AN 8.5-Gb/s FULLY INTEGRATED CMOS OPTOELECTRONIC RECEIVER USING SLOPE-DETECTION ADAPTIVE EQUALIZER, JSCC 2010


Proposed Feedback TIA & DC-Balanced Buffer*Sharif University of Technology*LEE et al.: AN 8.5-Gb/s FULLY INTEGRATED CMOS OPTOELECTRONIC RECEIVER USING SLOPE-DETECTION ADAPTIVE EQUALIZER, JSCC 2010


Proposed Equalization Filter Cell*Sharif University of Technology*LEE et al.: AN 8.5-Gb/s FULLY INTEGRATED CMOS OPTOELECTRONIC RECEIVER USING SLOPE-DETECTION ADAPTIVE EQUALIZER, JSCC 2010Frequency ResponseSimulated frequency response of the proposed equalization lter cell for various capacitor control voltages


LA First Stage Gain Cell*Sharif University of Technology*LEE et al.: AN 8.5-Gb/s FULLY INTEGRATED CMOS OPTOELECTRONIC RECEIVER USING SLOPE-DETECTION ADAPTIVE EQUALIZER, JSCC 2010


LA Second Stage & Replica Bias Circuit*Sharif University of Technology*LEE et al.: AN 8.5-Gb/s FULLY INTEGRATED CMOS OPTOELECTRONIC RECEIVER USING SLOPE-DETECTION ADAPTIVE EQUALIZER, JSCC 2010


Temperature Variation*Sharif University of Technology*Simulated bandwidth of the silicon photodiode and the proposed receiver front-end at various temperatures.LEE et al.: AN 8.5-Gb/s FULLY INTEGRATED CMOS OPTOELECTRONIC RECEIVER USING SLOPE-DETECTION ADAPTIVE EQUALIZER, JSCC 2010


Chip microphotograph*Sharif University of Technology*LEE et al.: AN 8.5-Gb/s FULLY INTEGRATED CMOS OPTOELECTRONIC RECEIVER USING SLOPE-DETECTION ADAPTIVE EQUALIZER, JSCC 2010


Measurement*Sharif University of Technology*LEE et al.: AN 8.5-Gb/s FULLY INTEGRATED CMOS OPTOELECTRONIC RECEIVER USING SLOPE-DETECTION ADAPTIVE EQUALIZER, JSCC 2010


Measured Eye-Diagrams*Sharif University of Technology*LEE et al.: AN 8.5-Gb/s FULLY INTEGRATED CMOS OPTOELECTRONIC RECEIVER USING SLOPE-DETECTION ADAPTIVE EQUALIZER, JSCC 2010Minimal EqualizationOptimal Equalization


Measured BER of OEIC Receiver*Sharif University of Technology*LEE et al.: AN 8.5-Gb/s FULLY INTEGRATED CMOS OPTOELECTRONIC RECEIVER USING SLOPE-DETECTION ADAPTIVE EQUALIZER, JSCC 2010


*Sharif University of Technology*A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector, JSCC 2006


Dual loop architecture for wide frequency acquisition rangeFull integration of CDR, DEMUX, LVDS, LD, and LOS

BYUN et al.: A 10-Gb/s CMOS CDR AND DEMUX IC WITH A QUARTER-RATE LINEAR PHASE DETECTOR,JSCC 2006System Architecture**Sharif University of Technology


Proposed Quarter-rate Linear PDA 2.5GHz LC-QVCO generates four phase recovered clocksThere are 8 phase error pulsesfour UP[3:0] pulses four DN[3:0] pulsesBYUN et al.: A 10-Gb/s CMOS CDR AND DEMUX IC WITH A QUARTER-RATE LINEAR PHASE DETECTOR,JSCC 2006**Sharif University of Technology


Proposed Quarter-rate Linear PDUP pulse width = 150psDN pulse width = 100ps

Design issuesPhase errorDuty ratio distortionDelay matchingBYUN et al.: A 10-Gb/s CMOS CDR AND DEMUX IC WITH A QUARTER-RATE LINEAR PHASE DETECTOR,JSCC 2006**Sharif University of Technology


150ps

100ps

0

5

4

3

2

1

6

3

4

4

5

1

2

0

1

5

6

4

5

3

4

2

3

1

2

0

1

5

6

UP[0]

UP[1]

UP[3]

UP[2]

Trans-conductor CircuitBYUN et al.: A 10-Gb/s CMOS CDR AND DEMUX IC WITH A QUARTER-RATE LINEAR PHASE DETECTOR,JSCC 2006**Sharif University of Technology


IBIAS

3

3

2

3 : 2

1 : 1

1

INP

INN

IBIAS

2

INP

INN

IBIAS

UP 0

+

-

differentialUP[3:0]

1

INP

INN

IBIAS

+

bias

IBIAS a

-

DOWN 0

INP

bias

IBIAS

INN

INP

bias

IBIAS

INN

INP

bias

IBIAS

INN

differentialDN[3:0]

4

MP5

MP6

Loop filter

MN5

MN6

4

4

4

MUX

from CP

SEL

gm_CTRL[2:0]

3

Data Recovery CircuitBYUN et al.: A 10-Gb/s CMOS CDR AND DEMUX IC WITH A QUARTER-RATE LINEAR PHASE DETECTOR,JSCC 2006**Sharif University of Technology


Lock DetectorBYUN et al.: A 10-Gb/s CMOS CDR AND DEMUX IC WITH A QUARTER-RATE LINEAR PHASE DETECTOR,JSCC 2006**Sharif University of Technology


Die Photo & Performance Summary0.13m 1P8M CMOS + UTM, MIM optionsDie area = 10.2mm2 including ESD, PAD, and I/O terminationsBYUN et al.: A 10-Gb/s CMOS CDR AND DEMUX IC WITH A QUARTER-RATE LINEAR PHASE DETECTOR,JSCC 2006**Sharif University of Technology


VCO

PD

DR

4:16DEMUX

Preamplifier

LVDS driver

LVDS driver

Lock ctrl.

PLL blocks

Technology

Chip area

Package

Power consumption

0.13mm CMOS 1P8M + MIM, UTM

3mm X 3.4mm

8mm X 8mm 128 ball CABGA

100mA at 1.2V core, 205mA at 2.5V I/O

Bit rate

210mVpp at 10-12 BER

Sensitivity level

9.4Gb/s ~ 11.3Gb/s

Maximum usable level

Jitter tolerance

1.5Vpp at 10-12 BER

0.5UIpp

Recovered clock jitter

2.1psrms at 155.52MHz

POCLK/DOUT skew

140ps

BER

< 10-15

LDD (SB350)*Sharif University of Technology*


TIA (SB360) *Sharif University of Technology*


PA (SB370)*Sharif University of Technology*


TIA/PA (SB380)*Sharif University of Technology*


Question and Answer

Thanks for your attention*Sharif University of Technology*


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optical fiber communications technology, systems and circuits overview

Documents

system overview

broadband access studies

physical reach

gtc layer framing

ali fotowat ahmadyfeb

demux ic

circuits overviewlecturer

power consumption