operational simulation of lc ladder filter using vdta

Research ArticleOperational Simulation of LC Ladder Filter Using VDTA

Praveen Kumar1 Neeta Pandey2 and Sajal Kumar Paul1

1Department of Electronics Engineering Indian School of Mines Dhanbad India2Department of Electronics and Communications Delhi Technological University Delhi India

Correspondence should be addressed to Neeta Pandey n66pandeyrediffmailcom

Received 29 June 2016 Revised 18 November 2016 Accepted 4 December 2016 Published 23 January 2017

Academic Editor Jiun-Wei Horng

Copyright copy 2017 Praveen Kumar et alThis is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

In this paper a systematic approach for implementing operational simulation of LC ladder filter using voltage differencingtransconductance amplifier is presented The proposed filter structure uses only grounded capacitor and possesses electronictunability PSPICE simulation using 180 nm CMOS technology parameter is carried out to verify the functionality of thepresented approach Experimental verification is also performed through commercially available IC LM13700NS Simulationsand experimental results are found to be in close agreement with theoretical predictions

1 Introduction

Currentmode approach has received a considerable attentionin the last few years for analog signal processing applica-tions due to their low power consumption large dynamicrange higher frequency ranges of operation better accuracyhigher slew rate and less complexity As a result a largenumber of current mode active elements such as operationaltransconductance amplifier (OTA) current conveyor (CC)current controlled conveyor (CCC) current feedback ampli-fier (CFOA) operational transresistance amplifier (OTRA)differential voltage current conveyor (DVCC) current dif-ferencing buffered amplifier (CDBA) current differencingtransconductance amplifier (CDTA) and voltage differenc-ing transconductance amplifier (VDTA) are published Aliterature review of such analog active block is presented in[1 2]TheVDTA is a recently proposed analog building blockcomposed of two transconductance amplifiers and may beused to implement different analog processing applicationsuch as floating and grounded inductor simulation [3 4]analog filter [5ndash10] and oscillators [11ndash13]

For the active simulation of higher-order LC ladderfilter mainly three methods exist which are wave activemethod topological simulation and operational simulationIn wave active approach a wave equivalent is developed forinductor in series branch and then it is configured for other

passive components by making suitable connection [14ndash21]Large numbers of active blocks are used in this approachIn the second method topological simulation or elementreplacement method the inductor of LC ladder structure isreplaced by appropriate configured active elements [22 23]The drawback of this configuration is that a floating capacitoris generally required and this degrades the performance of thederived filter topology in high frequency application In thethird approach operational simulation or leap-frog method[23ndash30] simulation is carried out for the operation of ladderrather than its component

Literature survey reveals the operational simulation ofladder filter using operational amplifier (OA) and currentcontrolled conveyor (CCCII) [24] OTA [25 26] CC [27]multiple output second generation current controlled con-veyor (MO-CCCII) [28] current feedback amplifier (CFA)[29] and CFOA [30] This paper presents a systematicapproach for operational simulation of LC ladder filter usingvoltage differencing transconductance amplifier (VDTA)The proposed operational simulation of LC ladder usingVDTA has the following advantage over existing circuits

(i) Lesser numbers of active blocks are used as comparedto [24 26 28ndash30]

(ii) There is no use of resistors in realization while [2529 30] use both floating and grounded resistors and[27] uses only grounded resistors

HindawiActive and Passive Electronic ComponentsVolume 2017 Article ID 1836727 8 pageshttpsdoiorg10115520171836727

2 Active and Passive Electronic Components

(iii) Only grounded capacitors are used in proposedimplementation while [25 29] use floating capacitorstoo

(iv) Proposed operational simulation of LC ladder alsopossesses electronic tunability of cut-off frequencywhile [27 29 30] do not

As an example a fourth-order Butterworth low pass filteris simulated by outlined approach and the workability of thefilter is confirmed through PSPICE simulation using 180 nmCMOS technology parameterThe functionality of the ladderfilter is also tested experimentally through IC LM13700NS

2 VDTA

The voltage differencing transconductance amplifier is con-sisting of two transconductance amplifiers [5] Figures 1and 2 represent the symbolic representation and CMOSimplementation of VDTA

The port relationship of VDTA in matrix form is charac-terized by the following equation

[[[

119868119885119868119883+119868119883minus]]]= [[[

119892119898119894 minus119892119898119894 00 0 1198921198981199000 0 minus119892119898119900

]]][[[

119881119875119881119873119881119885]]] (1)

where 119892119898119894 and 119892119898119900 are the input and output transconduc-tance gain of VDTA The input transconductance amplifier

converts the input voltage difference (119881119875 minus 119881119873) into currentat 119885 terminal and the voltage developed at 119885 terminal isconverted into current at 119883+ and 119883minus terminal by outputtransconductance amplifier In this paper VDTA is used asan active analog building block because of

(i) the simple CMOS implementation of VDTA(ii) presence of two transconductance amplifiers giving

resistorless realization(iii) the transconductance gain of VDTA which can vary

via bias current therefore providing the electronictunability to designed filter

3 Operational Simulation Using VDTA

Theoperational simulationmethod takes a different approachfrom topological simulation or wave active method as itsimulates the operation of ladder rather than its component[23] The circuit equations and voltage-current relationshipof each element are written using KVL and KCL Then theseequations are represented by block diagrams or signal flowgraph Each block represents some analog operation such assummation integration and subtraction The final circuit isobtained by properly combining these blocks

To explain the above statement a fourth-order low passButterworth filter of Figure 3 has been taken as a prototypeThe transfer function of this prototype filter can be expressedas

119881119900119881in= 11987711987111990441198621119862211987111198712119877119871 + 1199043 (119862111987111198712 + 119862111986221198712119877119904119877119871) + 1199042 (11987111198621119877119871 + 11987111198622119877119871 + 11987121198622119877119871 + 11987121198621119877119904) + 119904 (1198771199041198771198711198621 + 1198771199041198771198711198622 + 1198711 + 1198712) + (119877119904 + 119877119871)

(2)

To develop operational simulation in a systematic mannerconsider the general ladder of Figure 4 where the seriesbranch elements are labelled by admittance 119884119894 and the shuntbranch elements are labelled by impedance 119885119894 The ladder ofFigure 4 can be described by the voltage and current equationas in (3a) (3b) (3c) and (3d) as follows

1198681 = 1198841 (119881in minus 1198812) (3a)

1198812 = 1198851 (1198681 minus 1198683) (3b)

1198683 = 1198842 (1198812 minus 119881119900) (3c)

119881119900 = 1198852 (1198683 minus 1198685) assume 1198685 = 0then 119881119900 = 11988521198683

(3d)

where

1198841 = 1119877119904 + 1199041198711

1198842 = 11199041198712

1198851 = 11199041198621

1198852 = 11199041198622 + 1119877119871

(4)Both voltage and current terms are present in (3a) (3b) (3c)and (3d)This problem can be easily resolved by scaling theseequations by a resistor 119877119881

1198771198811198681 = 1198771198811198841 (119881in minus 1198812) 997904rArr1198811198681 = 119877119881119877119904 + 1199041198711 (119881in minus 1198812)

(5a)

1198812 = 1198851119877119881 (1198771198811198681 minus 1198771198811198683) 997904rArr

1198812 = 11199041198621119877119881 (1198811198681 minus 1198811198683) (5b)

Active and Passive Electronic Components 3

VDTA

P

N

X+

XminusZ

IP

IN

IZ

IB1 IB2 IB3 IB4

VN

VP

VZ

VXminus

VX+

IXminus

IX+

Figure 1 Symbolic representation of VDTA

PN

Z

VSS

VDD

M1 M2 M3 M4

M5 M6 M7 M8

IB1

IB2

IB3

IB4

X+Xminus

Figure 2 CMOS representation of VDTA

Vin V2

V1 V3

C2C1

+

+

++

+

I3

I2

I5

I4

I1RS

RL

L1 L2

minusminus

minus minus

minus

VO

Figure 3 Fourth-order Butterworth low pass LC ladder

Zzzz

minusminus

minus minus

Vin VO

++

minus

+

+ +

I3

I2 I4

I1 I5Y2Y1

Z2Z1V2

V3V1

Figure 4 The ladder of Figure 3 with admittance in series arm andimpedance in shunt arm

VDTA

P

ZN Xminus

X+

Vo1V2

V1

CV

Figure 5 Lossy integrator using VDTA

1198771198811198683 = 1198771198811198842 (1198812 minus 119881119900) 997904rArr

1198811198683 = 1198771198811199041198712 (1198812 minus 119881119900) (5c)

119881119900 = 11988521198771198811198771198811198683 997904rArr

119881119900 = 11199041198622119877119881 + 1198771198811198771198711198811198683

(5d)

where 1198811198681 = 1198771198811198681 1198811198683 = 1198771198811198683The subscript 119868 with voltages represents the fact that this

voltage is derived from a current in the circuitRealization of (5a) to (5d) gives the operational simula-

tion of prototype ladder filter of Figure 3 Implementation of(5a) and (5d) requires lossy integrator while implementationof (5b) and (5c) requires lossless integrator The lossy andlossless integrator can be easily realized using VDTA asdiscussed in the following section

31 Lossy Integration The implementation of lossy integra-tion using VDTA is shown in Figure 5 The expression foroutput voltage of lossy integrator can be written as

1198811198741 = 11 + 119904120591 (1198811 minus 1198812) (6a)

where

120591 = 119862119881119892119898 (with 119892119898119894 = 119892119898119900 = 119892119898) (6b)

32 Lossless Integrator Lossless integrator can be imple-mented using VDTA as shown in Figure 6 and its outputvoltage expression is

1198811199002 = 1119904120591 (1198811 minus 1198812) (7a)

Again

120591 = 119862119881119892119898 (with 119892119898119894 = 119892119898119900 = 119892119898) (7b)


VDTA

P

ZN Xminus

X+

Vo2

V2

V1

CV

Figure 6 Lossless integrator using VDTA

VDTAP

ZN

VDTAP

Z

X+

Xminus

X+

Xminus

X+

Xminus

X+

Xminus

N

VDTAP

ZN

VDTAP

ZN

11

2

34

Vin

VO

CV4

CV3

CV1

CV2

VI1

V2

VI3

Figure 7 VDTA implementation of Figure 3 using operationalsimulation approach

33 Complete Realization Using VDTA With the help oflossy and lossless integrator of Figures 5 and 6 the completerealization of prototype 4th-order filter using operationalsimulation approach is shown in Figure 7

The value of capacitor used in VDTA 1 and VDTA 4 canbe calculated by comparing (6a) and (6b) with (5a) and (5d)as follows

From (6a) and (6b) and (5a)

119877119904119877119881 = 1 997904rArr

119877119904 = 119877119881(8)

And 120591 = 1198621198811119892119898 = 1198711119877119881 rArr 1198621198811 = 1198711119892119898119877119881Take the value of scaling resistor

119877119881 = 1119892119898 (9)

Then

1198621198811 = 11987111198921198982 (10)

minus100

minus80

minus60

minus40

minus20

0

Gai

n (d

B)

10MHz 10MHz100KHz 50MHzFrequency

Figure 8 Simulated frequency response of 4th-order Butterworthlow pass filter

And from (6a) and (6b) and (5d)

119877119881119877119871 = 1 997904rArr

119877119871 = 119877119881(11)

120591 = 1198621198814119892119898 = 1198622119877119881 997904rArr

1198621198814 = 1198622(12)

Similarly the value of capacitor used in VDTA 2 and VDTA3 can be calculated by comparing (7a) and (7b) with (5b) and(5c) as follows

From (7a) and (7b) and (5b)

120591 = 1198621198812119892119898 = 1198621119877119881 997904rArr

1198621198812 = 1198621(13)

And from (7a) and (7b) and (5c)

120591 = 1198621198813119892119898 =1198712119877119881 997904rArr

1198621198813 = 11987121198921198982(14)

4 Simulation

The normalized component values of the prototype filter ofFigure 3 are 119877119904 = 1 1198711 = 7654 1198621 = 18485 1198712 = 184851198622 = 7654 and 119877119871 = 1 The aspect ratio of various transistorused in CMOS implementation of VDTA is given in Table 1The values of supply voltage and bias current for VDTA are119881DD = 119881SS = minus09V and IB1 = IB2 = IB3 = IB4 = 150120583A (119892119898119894 =119892119898119900 = 119892119898 = 627 120583S) respectively

For cut-off frequency of 5MHz the values of capacitorused in Figure 7 can be calculated by (10) (12) (13) and (14)as 1198621198811 = 1528 pF 1198621198812 = 369 pF 1198621198813 = 369 pF and 1198621198814 =1528 pF Figure 8 shows the frequency response of the lowpass fourth-order Butterworth filter The simulated cut-off


200u175u100u 125u 150u 225u 250u50u 75u25uBias current (A)

0

5M

10M

Cut-o

ff fre

quen

cy (H

z)

(a)

minus120

minus80

minus40

0

Gai

n (d

B)

100KHz 10MHz10MHz 50MHzFrequency

(b)

Figure 9 Electronic tuning demonstration (a)Cut-off frequency variationwith bias current (b) Frequency response for various bias currents

Table 1 Aspect ratio of various transistors used in CMOS imple-mentation of VDTA

Transistors Aspect ratios (119882 (120583m)119871 (120583m))M1ndashM4 3636M5ndashM8 166436

minus100mV

0V

100mV

Inpu

t

minus40mV

0V

40mV

Out

put

20us 40us 60us0 sTime

Figure 10 Transient response of input and output signals

frequency is 499MHz which is very close to the theoreticalcut-off frequency of 5MHz The electronic tunability of thefilter through simulation is demonstrated in Figure 9 byvarying bias current from 25 120583A to 250 120583A Time domainanalysis is studied by applying two signals of frequency500KHz and 20MHz and of magnitude 50mV at input Thetransient response and its spectrum are shown in Figures 10and 11 respectivelyThe proposed filter structure is also testedfor total harmonic distortion at output and it is found that itis within acceptable limit of 3 up to 600mV p-p signal offrequency 1MHz as shown in Figure 12

Noise analysis is also carried out for the proposedcircuit by determining noise at output of the filter throughsimulation The output noise variation within pass bandfrequencies is depicted in Figure 13 which shows that noiseis in acceptable limit of nanovolt range To examine effect of

0V

50mV

100mV

Inpu

t

0V

20mV

40mVO

utpu

t

20MHz 40MHz 50MHz0HzFrequency

Figure 11 Frequency spectrum of input and output signals

0

1

2

3

4

5

100 200 300 400 500 600

T

HD

Input signal amplitude p-p (mV)

Figure 12 THD variation with p-p input signal amplitude

temperature variation on proposed filter circuit the circuitis simulated at five different temperatures 10∘C 25∘C 27∘C50∘C and 100∘C and the results are depicted in Figure 14Thevalues of cut-off frequency for these temperatures are listed inTable 2 It is observed that cut-off frequency shifts towardslower frequencies as temperature decreases This is due tothe fact that the transconductance decreases with increasesin temperature due to decrease in mobility This shifting incut-off frequency can be compensated through bias current


0

2

4

6

8

Out

put n

oise

(nV

Hz1

2 )

1MHz 10MHz 100MHz01MHzFrequency

Figure 13 Output noise variation of proposed filter with frequency

minus120

minus80

minus40

0

Gai

n (d

B)

100KHz 10MHz 50MHz10MHzFrequency

T = 10∘C

T = 25∘C

T = 27∘C

T = 50∘C

T = 100∘C

Figure 14 Demonstration of effect of temperature on proposedfilter

Table 2 Cut-off frequency at various temperatures

Temperature Cut-off frequency10∘C 52MHz25∘C 5MHz27∘C 498MHz50∘C 47MHz100∘C 417MHz

variation from 104 120583A (for f 0 = 417MHz at 100∘C) to 164 120583A(for f 0 = 52MHz at 10∘C)

All the key parameters of the proposed filter structure aresummarized in Table 3The total power dissipated and outputnoise in simulation of the prototype filter are 216mWand 57times 10minus9 VHz12 while simulated values of these parametersfor the VDTA implementation of the same-order filter usingwave active method are 648mW and 165 times 10minus8 VHz12[20]

Experimental verification is carried out for proposedcircuit through commercially available IC LM13700NS The

+

+

minus

minus

P

N Z

O

O

TA1

TA2 X+

IBiasIBias

+

minus

OTA3 Xminus

IBias

Figure 15 VDTA implantation using OTA

Figure 16 Bread-boarded circuit of Figure 7

Table 3 Key parameters of simulated 4th-order low pass ladderfilter

Bias current 150120583AVDTA transconductance 119892119898 627 120583S at bias current of 150 120583ATheoretical cut-off frequency 5MHzSimulated cut-off frequency 499MHzRoll-off rate 80 dBdecadeTotal power consumption 216mWTotal output noise voltage 57 nVHz12

THD lt3 for input signal up to 600mVp-p

VDTA implementation using IC LM13700NS is shown inFigure 15 The circuit of Figure 7 is bread-boarded as shownin Figure 16 for experimental testing Supply voltage of plusmn15 Vis used The bias current of 135mA is set to obtain thetransconductance of 2489mAV The capacitor values areselected as 119862V1 = Cv4 = 10 nF and 119862V2 = Cv3 = 25 nF for cut-off frequency of 303 kHz The measured magnitude responsealong with simulated response is depicted in Figure 17 Theexperimental cut-off frequency is observed to be 292 kHz

5 Conclusion

The paper presents a systematic methodology for activeimplementation of operational simulation of LC ladder filterTo explain the outlined approach a 4th-order Butterworth


SimulatedExperimented

minus150

minus100

minus50

0

Gai

n (d

B)

10MHZ100KHz 1MHz10KHZ1KHZFrequency

Figure 17 Simulated and experimentedmagnitude response of 4th-order low pass filter

filter is taken as prototype and for active implementationVDTA is used as an analog building block The proposedimplementation is resistorless and uses only grounded capac-itors which is suitable for IC implementation The proposedstructure also possesses electronic tunability of cut-off fre-quency Workability of the proposed implementation is ver-ified through PSPICE simulation using 180 nm TSMC tech-nology parameters The functionality of proposed LC ladderis also verified experimentally through IC LM13700NS

Competing Interests

The authors declare that they have no competing interests

References

[1] K K Abdalla D R Bhaskar and R Senani ldquoA review of theevolution of current-mode circuits and techniques and variousmodern analog circuit building blocksrdquoNature and Science vol10 no 10 2012

[2] D Biolek R Senani V Biolkova and Z Kolka ldquoActive elementsfor analog signal processing classification review and newproposalsrdquo Radioengineering vol 17 no 4 pp 15ndash32 2008

[3] D Prasad and D R Bhaskar ldquoGrounded and floating induc-tance simulation circuits using VDTAsrdquo Circuits and Systemsvol 3 no 4 pp 342ndash347 2012

[4] W Tangsrirat and S Unhavanich ldquoVoltage differencingtransconductance amplifier-based floating simulators with asingle grounded capacitorrdquo Indian Journal of Pure and AppliedPhysics vol 52 no 6 pp 423ndash428 2014

[5] A Yesil F Kacar and H Kuntman ldquoNew simple CMOSrealization of voltage differencing transconductance amplifierand its RF filter applicationrdquo Radioengineering vol 20 no 3pp 632ndash637 2011

[6] A Yesil and F Kacar ldquoElectronically tunable resistorless mixedmode biquad filtersrdquo Radioengineering vol 22 no 4 pp 1016ndash1025 2013

[7] J Satansup andW Tangsrirat ldquoCompact VDTA-based current-mode electronically tunable universal filters using groundedcapacitorsrdquoMicroelectronics Journal vol 45 no 6 pp 613ndash6182014

[8] D Prasadl D R Bhaskar andM Srivastava ldquoUniversal voltage-mode biquad filter using voltage differencing transconductanceamplifierrdquo Indian Journal of Pure andApplied Physics vol 51 no12 pp 864ndash868 2013

[9] J Satansup T Pukkalanun and W Tangsrirat ldquoElectroni-cally tunable current-mode universal filter using VDTAs andgrounded capacitorsrdquo in Proceedings of the International Mul-tiConference of Engineers and Computer Scientists (IMECS rsquo13)pp 647ndash650 Hong Kong China March 2013

[10] A Uygur and H Kuntman ldquoDTMOS-based 04V ultra low-voltage low-powerVDTAdesign and its application to EEGdataprocessingrdquo Radioengineering vol 22 no 2 pp 458ndash466 2013

[11] D Prasad M Srivastava and D R Bhaskar ldquoElectronicallycontrollable fully-uncoupled explicit current-mode quadratureoscillator using VDTAs and grounded capacitorsrdquo Circuits andSystems vol 4 no 2 pp 169ndash172 2013

[12] D Prasad and D R Bhaskar ldquoElectronically ControllableExplicit CurrentOutput SinusoidalOscillator Employing SingleVDTArdquo ISRN Electronics vol 2012 Article ID 382560 5 pages2012

[13] R Sotner J Jerabek N Herencsar J Petrzela K Vrba and ZKincl ldquoLinearly tunable quadrature oscillator derived from LCColpitts structure using voltage differencing transconductanceamplifier and adjustable current amplifierrdquo Analog IntegratedCircuits and Signal Processing vol 81 no 1 pp 121ndash136 2014

[14] I Haritantis A Constantinides andTDeliyannis ldquoWave activefilterrdquo Proceedings of the Institution of Electrical Engineers vol123 no 7 pp 676ndash682 1976

[15] K Georgia and P Costas ldquoModular filter structures usingCFOArdquo Radio Engineering vol 19 no 4 pp 662ndash666 2010

[16] N Pandey and P Kumar ldquoRealization of resistorless wave activefilter using differential voltage current controlled conveyortransconductance amplifierrdquo Radioengineering vol 20 no 4pp 911ndash916 2011

[17] N Pandey P Kumar and J Choudhary ldquoCurrent controlled dif-ferential difference current conveyor transconductance ampli-fier and its application as wave active filterrdquo ISRN Electronicsvol 2013 Article ID 968749 11 pages 2013

[18] M Bothra R Pandey N Pandey and S K Paul ldquoOperationaltrans-resistance amplifier based tunable wave active filterrdquoRadioengineering vol 22 no 1 pp 159ndash166 2013

[19] H Singh K Arora and D Prasad ldquoVDTA-based wave activefilterrdquo Circuits and Systems vol 5 no 5 pp 124ndash131 2014

[20] N Pandey P Kumar and S K Paul ldquoVoltage differencingtransconductance amplifier based resistorless and electronicallytunable wave active filterrdquo Analog Integrated Circuits and SignalProcessing vol 84 no 1 pp 107ndash117 2015

[21] H Wupper and K Meerkotter ldquoNew active filter synthesisbased on scattering parametersrdquo IEEE Transaction on Circuitand System vol 22 no 7 pp 594ndash602 1975

[22] A A M Shkir ldquo10kHz lpw power 8th order eliptic bandmdashpass filter employing CMOS VDTArdquo International Journal ofEnhanced Research in Science Technology amp Engineering vol 4no 1 pp 162ndash168 2015

[23] M E Van Valkenburg and R Shaumann Design of AnalogFilters Oxford University Press Oxford UK 2001

[24] Y Xi and H Peng ldquoRealization of lowpass and bandpassleapfrog filters using OAs and CCCIIsrdquo in Proceedings of theInternational Conference on Management and Service Science(MASS rsquo09) Wuhan China September 2009


[25] M V Katageri M M Mutsaddi and R S Mathad ldquoCompar-ative study of LC ladder active filter using OTA and currentconveyorrdquo International Journal of Advanced Computer andMathematical Sciences vol 3 no 3 pp 321ndash325 2012

[26] R Schaumann ldquoSimulating lossless ladders with transconduct-ance-C circuitsrdquo IEEE Transactions on Circuits and Systems IIAnalog and Digital Signal Processing vol 45 no 3 pp 407ndash4101998

[27] V Novotny and K Vrba ldquoLC ladder filter emulation by struc-tures with current conveyorrdquo in Proceedings of the 4th WSEASInternational Conference on Signal Processing ComputationalGeometry amp Artificial Vision (ISCGAV rsquo04) Tenerife SpainDecember 2004

[28] A Campeanu and J Gal ldquoLC-ladder filters emulated by circuitswith current controlled conveyors and grounded capacitorsrdquo inProceedings of the International Symposium On Signals Circuitsand Systems (ISSCS rsquo07) vol 2 Iasi Romania July 2007

[29] T S Rathore and U P Khot ldquoCFA-based grounded-capacitoroperational simulation of ladder filtersrdquo International Journalof Circuit Theory and Applications vol 36 no 5-6 pp 697ndash7162008

[30] P K Sinha A Saini P Kumar and S Mishra ldquoCFOA based lowpass and high pass ladder filtermdasha new configurationrdquo Circuitsand Systems vol 5 no 12 pp 293ndash300 2014

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DistributedSensor Networks



(iii) Only grounded capacitors are used in proposedimplementation while [25 29] use floating capacitorstoo

(iv) Proposed operational simulation of LC ladder alsopossesses electronic tunability of cut-off frequencywhile [27 29 30] do not

As an example a fourth-order Butterworth low pass filteris simulated by outlined approach and the workability of thefilter is confirmed through PSPICE simulation using 180 nmCMOS technology parameterThe functionality of the ladderfilter is also tested experimentally through IC LM13700NS

2 VDTA

The voltage differencing transconductance amplifier is con-sisting of two transconductance amplifiers [5] Figures 1and 2 represent the symbolic representation and CMOSimplementation of VDTA

The port relationship of VDTA in matrix form is charac-terized by the following equation

[[[

119868119885119868119883+119868119883minus]]]= [[[

119892119898119894 minus119892119898119894 00 0 1198921198981199000 0 minus119892119898119900

]]][[[

119881119875119881119873119881119885]]] (1)

where 119892119898119894 and 119892119898119900 are the input and output transconduc-tance gain of VDTA The input transconductance amplifier

converts the input voltage difference (119881119875 minus 119881119873) into currentat 119885 terminal and the voltage developed at 119885 terminal isconverted into current at 119883+ and 119883minus terminal by outputtransconductance amplifier In this paper VDTA is used asan active analog building block because of

(i) the simple CMOS implementation of VDTA(ii) presence of two transconductance amplifiers giving

resistorless realization(iii) the transconductance gain of VDTA which can vary

via bias current therefore providing the electronictunability to designed filter

3 Operational Simulation Using VDTA

Theoperational simulationmethod takes a different approachfrom topological simulation or wave active method as itsimulates the operation of ladder rather than its component[23] The circuit equations and voltage-current relationshipof each element are written using KVL and KCL Then theseequations are represented by block diagrams or signal flowgraph Each block represents some analog operation such assummation integration and subtraction The final circuit isobtained by properly combining these blocks

To explain the above statement a fourth-order low passButterworth filter of Figure 3 has been taken as a prototypeThe transfer function of this prototype filter can be expressedas

119881119900119881in= 11987711987111990441198621119862211987111198712119877119871 + 1199043 (119862111987111198712 + 119862111986221198712119877119904119877119871) + 1199042 (11987111198621119877119871 + 11987111198622119877119871 + 11987121198622119877119871 + 11987121198621119877119904) + 119904 (1198771199041198771198711198621 + 1198771199041198771198711198622 + 1198711 + 1198712) + (119877119904 + 119877119871)

(2)

To develop operational simulation in a systematic mannerconsider the general ladder of Figure 4 where the seriesbranch elements are labelled by admittance 119884119894 and the shuntbranch elements are labelled by impedance 119885119894 The ladder ofFigure 4 can be described by the voltage and current equationas in (3a) (3b) (3c) and (3d) as follows

1198681 = 1198841 (119881in minus 1198812) (3a)

1198812 = 1198851 (1198681 minus 1198683) (3b)

1198683 = 1198842 (1198812 minus 119881119900) (3c)

119881119900 = 1198852 (1198683 minus 1198685) assume 1198685 = 0then 119881119900 = 11988521198683

(3d)

where

1198841 = 1119877119904 + 1199041198711

1198842 = 11199041198712

1198851 = 11199041198621

1198852 = 11199041198622 + 1119877119871

(4)Both voltage and current terms are present in (3a) (3b) (3c)and (3d)This problem can be easily resolved by scaling theseequations by a resistor 119877119881

1198771198811198681 = 1198771198811198841 (119881in minus 1198812) 997904rArr1198811198681 = 119877119881119877119904 + 1199041198711 (119881in minus 1198812)

(5a)

1198812 = 1198851119877119881 (1198771198811198681 minus 1198771198811198683) 997904rArr

1198812 = 11199041198621119877119881 (1198811198681 minus 1198811198683) (5b)


VDTA

P

N

X+

XminusZ

IP

IN

IZ

IB1 IB2 IB3 IB4

VN

VP

VZ

VXminus

VX+

IXminus

IX+


PN

Z

VSS

VDD

M1 M2 M3 M4

M5 M6 M7 M8

IB1

IB2

IB3

IB4

X+Xminus


Vin V2

V1 V3

C2C1

+

+

++

+

I3

I2

I5

I4

I1RS

RL

L1 L2

minusminus

minus minus

minus

VO


Zzzz

minusminus

minus minus

Vin VO

++

minus

+

+ +

I3

I2 I4

I1 I5Y2Y1

Z2Z1V2

V3V1


VDTA

P

ZN Xminus

X+

Vo1V2

V1

CV


1198771198811198683 = 1198771198811198842 (1198812 minus 119881119900) 997904rArr

1198811198683 = 1198771198811199041198712 (1198812 minus 119881119900) (5c)

119881119900 = 11988521198771198811198771198811198683 997904rArr

119881119900 = 11199041198622119877119881 + 1198771198811198771198711198811198683

(5d)





1198811198741 = 11 + 119904120591 (1198811 minus 1198812) (6a)

where

120591 = 119862119881119892119898 (with 119892119898119894 = 119892119898119900 = 119892119898) (6b)


1198811199002 = 1119904120591 (1198811 minus 1198812) (7a)

Again

120591 = 119862119881119892119898 (with 119892119898119894 = 119892119898119900 = 119892119898) (7b)


VDTA

P

ZN Xminus

X+

Vo2

V2

V1

CV


VDTAP

ZN

VDTAP

Z

X+

Xminus

X+

Xminus

X+

Xminus

X+

Xminus

N

VDTAP

ZN

VDTAP

ZN

11

2

34

Vin

VO

CV4

CV3

CV1

CV2

VI1

V2

VI3





119877119904119877119881 = 1 997904rArr

119877119904 = 119877119881(8)


119877119881 = 1119892119898 (9)

Then

1198621198811 = 11987111198921198982 (10)

minus100

minus80

minus60

minus40

minus20

0

Gai

n (d

B)




119877119881119877119871 = 1 997904rArr

119877119871 = 119877119881(11)

120591 = 1198621198814119892119898 = 1198622119877119881 997904rArr

1198621198814 = 1198622(12)



120591 = 1198621198812119892119898 = 1198621119877119881 997904rArr

1198621198812 = 1198621(13)


120591 = 1198621198813119892119898 =1198712119877119881 997904rArr

1198621198813 = 11987121198921198982(14)

4 Simulation





0

5M

10M

Cut-o

ff fre

quen

cy (H

z)

(a)

minus120

minus80

minus40

0

Gai

n (d

B)


(b)




minus100mV

0V

100mV

Inpu

t

minus40mV

0V

40mV

Out

put





0V

50mV

100mV

Inpu

t

0V

20mV

40mVO

utpu

t



0

1

2

3

4

5

100 200 300 400 500 600

T

HD





0

2

4

6

8

Out

put n

oise

(nV

Hz1

2 )



minus120

minus80

minus40

0

Gai

n (d

B)


T = 10∘C

T = 25∘C

T = 27∘C

T = 50∘C

T = 100∘C







+

+

minus

minus

P

N Z

O

O

TA1

TA2 X+

IBiasIBias

+

minus

OTA3 Xminus

IBias







5 Conclusion




minus150

minus100

minus50

0

Gai

n (d

B)




Competing Interests


References


































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










VDTA

P

N

X+

XminusZ

IP

IN

IZ

IB1 IB2 IB3 IB4

VN

VP

VZ

VXminus

VX+

IXminus

IX+


PN

Z

VSS

VDD

M1 M2 M3 M4

M5 M6 M7 M8

IB1

IB2

IB3

IB4

X+Xminus


Vin V2

V1 V3

C2C1

+

+

++

+

I3

I2

I5

I4

I1RS

RL

L1 L2

minusminus

minus minus

minus

VO


Zzzz

minusminus

minus minus

Vin VO

++

minus

+

+ +

I3

I2 I4

I1 I5Y2Y1

Z2Z1V2

V3V1


VDTA

P

ZN Xminus

X+

Vo1V2

V1

CV


1198771198811198683 = 1198771198811198842 (1198812 minus 119881119900) 997904rArr

1198811198683 = 1198771198811199041198712 (1198812 minus 119881119900) (5c)

119881119900 = 11988521198771198811198771198811198683 997904rArr

119881119900 = 11199041198622119877119881 + 1198771198811198771198711198811198683

(5d)





1198811198741 = 11 + 119904120591 (1198811 minus 1198812) (6a)

where

120591 = 119862119881119892119898 (with 119892119898119894 = 119892119898119900 = 119892119898) (6b)


1198811199002 = 1119904120591 (1198811 minus 1198812) (7a)

Again

120591 = 119862119881119892119898 (with 119892119898119894 = 119892119898119900 = 119892119898) (7b)


VDTA

P

ZN Xminus

X+

Vo2

V2

V1

CV


VDTAP

ZN

VDTAP

Z

X+

Xminus

X+

Xminus

X+

Xminus

X+

Xminus

N

VDTAP

ZN

VDTAP

ZN

11

2

34

Vin

VO

CV4

CV3

CV1

CV2

VI1

V2

VI3





119877119904119877119881 = 1 997904rArr

119877119904 = 119877119881(8)


119877119881 = 1119892119898 (9)

Then

1198621198811 = 11987111198921198982 (10)

minus100

minus80

minus60

minus40

minus20

0

Gai

n (d

B)




119877119881119877119871 = 1 997904rArr

119877119871 = 119877119881(11)

120591 = 1198621198814119892119898 = 1198622119877119881 997904rArr

1198621198814 = 1198622(12)



120591 = 1198621198812119892119898 = 1198621119877119881 997904rArr

1198621198812 = 1198621(13)


120591 = 1198621198813119892119898 =1198712119877119881 997904rArr

1198621198813 = 11987121198921198982(14)

4 Simulation





0

5M

10M

Cut-o

ff fre

quen

cy (H

z)

(a)

minus120

minus80

minus40

0

Gai

n (d

B)


(b)




minus100mV

0V

100mV

Inpu

t

minus40mV

0V

40mV

Out

put





0V

50mV

100mV

Inpu

t

0V

20mV

40mVO

utpu

t



0

1

2

3

4

5

100 200 300 400 500 600

T

HD





0

2

4

6

8

Out

put n

oise

(nV

Hz1

2 )



minus120

minus80

minus40

0

Gai

n (d

B)


T = 10∘C

T = 25∘C

T = 27∘C

T = 50∘C

T = 100∘C







+

+

minus

minus

P

N Z

O

O

TA1

TA2 X+

IBiasIBias

+

minus

OTA3 Xminus

IBias







5 Conclusion




minus150

minus100

minus50

0

Gai

n (d

B)




Competing Interests


References


































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










VDTA

P

ZN Xminus

X+

Vo2

V2

V1

CV


VDTAP

ZN

VDTAP

Z

X+

Xminus

X+

Xminus

X+

Xminus

X+

Xminus

N

VDTAP

ZN

VDTAP

ZN

11

2

34

Vin

VO

CV4

CV3

CV1

CV2

VI1

V2

VI3





119877119904119877119881 = 1 997904rArr

119877119904 = 119877119881(8)


119877119881 = 1119892119898 (9)

Then

1198621198811 = 11987111198921198982 (10)

minus100

minus80

minus60

minus40

minus20

0

Gai

n (d

B)




119877119881119877119871 = 1 997904rArr

119877119871 = 119877119881(11)

120591 = 1198621198814119892119898 = 1198622119877119881 997904rArr

1198621198814 = 1198622(12)



120591 = 1198621198812119892119898 = 1198621119877119881 997904rArr

1198621198812 = 1198621(13)


120591 = 1198621198813119892119898 =1198712119877119881 997904rArr

1198621198813 = 11987121198921198982(14)

4 Simulation





0

5M

10M

Cut-o

ff fre

quen

cy (H

z)

(a)

minus120

minus80

minus40

0

Gai

n (d

B)


(b)




minus100mV

0V

100mV

Inpu

t

minus40mV

0V

40mV

Out

put





0V

50mV

100mV

Inpu

t

0V

20mV

40mVO

utpu

t



0

1

2

3

4

5

100 200 300 400 500 600

T

HD





0

2

4

6

8

Out

put n

oise

(nV

Hz1

2 )



minus120

minus80

minus40

0

Gai

n (d

B)


T = 10∘C

T = 25∘C

T = 27∘C

T = 50∘C

T = 100∘C







+

+

minus

minus

P

N Z

O

O

TA1

TA2 X+

IBiasIBias

+

minus

OTA3 Xminus

IBias







5 Conclusion




minus150

minus100

minus50

0

Gai

n (d

B)




Competing Interests


References


































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











0

5M

10M

Cut-o

ff fre

quen

cy (H

z)

(a)

minus120

minus80

minus40

0

Gai

n (d

B)


(b)




minus100mV

0V

100mV

Inpu

t

minus40mV

0V

40mV

Out

put





0V

50mV

100mV

Inpu

t

0V

20mV

40mVO

utpu

t



0

1

2

3

4

5

100 200 300 400 500 600

T

HD





0

2

4

6

8

Out

put n

oise

(nV

Hz1

2 )



minus120

minus80

minus40

0

Gai

n (d

B)


T = 10∘C

T = 25∘C

T = 27∘C

T = 50∘C

T = 100∘C







+

+

minus

minus

P

N Z

O

O

TA1

TA2 X+

IBiasIBias

+

minus

OTA3 Xminus

IBias







5 Conclusion




minus150

minus100

minus50

0

Gai

n (d

B)




Competing Interests


References


































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










0

2

4

6

8

Out

put n

oise

(nV

Hz1

2 )



minus120

minus80

minus40

0

Gai

n (d

B)


T = 10∘C

T = 25∘C

T = 27∘C

T = 50∘C

T = 100∘C







+

+

minus

minus

P

N Z

O

O

TA1

TA2 X+

IBiasIBias

+

minus

OTA3 Xminus

IBias







5 Conclusion




minus150

minus100

minus50

0

Gai

n (d

B)




Competing Interests


References


































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











minus150

minus100

minus50

0

Gai

n (d

B)




Competing Interests


References


































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation


















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









operational simulation of lc ladder filter using vdta

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