openram - f-siopenram_fsic2019.pdfdoesn’t perform drc/lvs estimates power/delay analytically...

https://vlsida.github.io/OpenRAM/

OpenRAMAn Open-Source Memory Compiler

Matthew [email protected]


Banana Slugs


Why an Open Source Memory Compiler?● Memories have become a commodity part...

○ but there are none available for “free”.

● Many IP cores are available for “free”... ○ but these don’t include necessary memories.

● Memories are a bottleneck for performance and power...○ but their performance and power vary drastically.

● Memories have a regular structure which leads to automation...○ but developing for multiple technologies and tool methodologies is hard.

● Academic designers have access to cell libraries...○ but memories have limited availability.


Why NOT an Open Source Memory Compiler?● Bit cells are proprietary from the foundry

○ Lithography issues and DRC waivers

○ Need to characterize real silicon

● Design rules are not accessible○ PDKs are hard to access and not “open”

● It’s a lot of work

● You can just buy memory IP


Contemporary Compilers and/or IPIndustry compilers:

● Cadence Legato Memory Solution

● Synopsys DesignWare (acquired Virage Logic)

● ARM Memory IP (acquired Artisan)

● Mobile Semiconductor Trailblaze

● Faraday Technologies

● Dolphin Technology

● Many others...

Only free option, but depends on Cadence Skill:

● FabMem (NCSU)

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Optimists vs Pessimists vs Engineers● An optimist sees the glass as half full.

● A pessimist sees the glass as half empty.

● An engineer asks why the glass is twice as big as it needs to be.


OpenRAM Guiding Principles1. Be “extensible” by hardware engineers

2. Be “independent” of technology

3. Be “independent” of specific tools or methodologies

4. Support multiple memory types/configurations


OpenRAM Features● Implemented in Python 3.5+

● Licensed with 3-clause BSD

● Provides reference circuit and physical implementations

○ FreePDK45 (generic, non-fabricable 45nm)

○ MOSIS Scalable CMOS (scn4m_subm 0.35um)

● Provides a timing/power characterization methodology and functional verification

● Generates GDSII layout data, SPICE netlist, Verilog model, DRC/LVS verification

reports and P&R macro view.

● Wrappers for both open-source and commercial tools

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OpenRAM SRAM Architecture

● Bit-cell Array

● Each port:

○ Hierarchical Address

Decoder(s)

○ Wordline Driver(s)

○ Column Multiplexer(s)

○ Bitline Precharge(s)

○ Sense Amplifier(s)

○ Write Driver(s)

○ Control Logic with

Replica Bitline

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Multiport Bitcells● Based on 6T SRAM cell

○ Standard read-write

○ Isolated read-only

ports

○ Write-only port (not

sized for reads)

● Can accommodate

foundry bitcells


Relative Bitcell Sizes(0.35um SCMOS)

DFF21.9um x 21.2um(from OSU standard cell library)

Isolated Read 10T (1rw, 1r)10.9um x 13.9um

Standard 6T (1rw)6.8um x 9.2um


Wish list: Thin Cells● Most sub-65nm SRAMs use “thin cell” bit cells

○ Reduces bitline capacitance

○ Must reorient cell layout so poly is opposite to bitlines

■ But in sub-28nm, all poly must be same orientation!

Freescale 65nm cell, 0.69μm2


OpenRAM Implementation● Front-end mode

○ Generates spice, layout views, timing models

■ Netlist only mode can skip the physical design too

○ Doesn’t perform DRC/LVS

○ Estimates power/delay analytically

● Back-end mode○ Generates spice, layout views, timing models

○ Performs DRC/LVS

■ Can perform at each level of hierarchy or at the end

○ Simulates power/delay

■ Can be back-annotated or not


Configuration Files● Usage:

● Uses Python instead of

additional language

● Can specify tools when

multiple available

● Can override modules

with custom

implementations

# Size and technologytech_name = "scn4m_subm"word_size = 16num_words = 256

# Corners are process x supply x temperatureprocess_corners = ["TT"]supply_voltages = [ 3.3 ]temperatures = [ 25 ]

# Output storageoutput_path = "/my/results/directory"output_name = "btb_sram"

# Toolsspice = "ngspice"drc_name = "magic"lvs_name = "netgen"pex_name = "magic"

# Custom logic moduledecoder = "mydecoder"

myconfig.py

$ openram.py myconfig

$ openram.py myconfig.py


In Progress: OpenRAM Library (IP)● Downloadable IP

● Pre-characterized

● Various sizes and

configs

● Technologies○ SCMOS (scn4m_subm

0.35um)

○ FreePDK45 (45nm)

○ TODO: Morehttps://vlsida.github.io/OpenRAMLibrary/

https://vlsida.github.io/OpenRAMLibrary/


OpenRAM HTML Data Sheets


Some Gory Details


Design Classes● Spice and GDS2 Interfaces

○ Custom cells (read gds and spice)

○ Generated cells (creates gds and spice “on the fly”)

● Netlist functions○ Add (directional) pins

○ Add and connect instances

● Layout functions ○ Place instances

○ Add wires, routes, vias

○ Channel and Power router

● Verification functions (wrap around DRC and LVS tools)


Required Custom Design● A few library cells with layout and spice:

○ Bitcell (and replica bitcell)

■ Could be from the foundry

○ Sense amplifier

○ DFF (from a standard cell library)

○ (Removing soon: write driver, tristate)

● P&R border layer defined for placement

● Sense amplifier pitch matched width to bitcell

Standard 6T (1rw)6.8um x 9.2um


Parameterized Gates and Transistors● Parameterized transistors

○ NMOS, PMOS

○ Variable fingers

○ (Optional) source/drain routing

● Parameterized logic gates

○ Inverter, nand2, nor2, nand3

○ Variable rail spacing and sizes

● Multi-stage drivers

● Precharge

● Column mux

● (Soon: write driver, tristate, FinFET)


Hierarchical Modules● Memory building blocks

○ SRAM, Bank, Control Logic, Decoders, Column Mux, Various arrays (DFF, drivers)

○ Can override every module with a custom one in the configuration file

● Each module must:○ Create netlist

■ Define inputs/outputs

■ Instantiate and connect sub-modules and cells

○ Create layout

■ Place and route itself

■ Route vdd/gnd to M3

■ (Optional) Run DRC/LVS

○ Analytically model timing and power


Power Supply Router● Power pins are brought up to M3 throughout design

● Horizontal/vertical power grid (M3 and M4)○ Blockage-aware

○ Uses conservative routing pitch

○ Wide metal DRC spacing supported

● Multi-pass algorithm○ 1st: Route vertical and horizontal grids (blockage aware, allow connection to correct supply)

○ 2nd: Check direct overlaps of power pins

○ 3rd: Single direction probes to connect

○ 4th: A* maze router


Channel Router● SRAMs typically try to use minimal layers of metal

○ We restrict to 4 layers

● Primarily used to connect decoders, input/output circuitry, or

control logic

● Wish list: Minimize number of tracks

○ Must consider impact on floorplan

Sense amp to data flop connectionColumn decoder to column mux

Credit: Chen & Chang, EDA Handbook, Chapter 12, Global and detailed routing


Tool Portability● OpenRAM provides a wrapper interface for DRC and LVS tools

○ Currently supports: Magic+Netgen, Calibre, Assura

■ Wish list: klayout, icv

■ Wish list: open source DRC and extraction?

○ DRC and LVS can be performed at all levels of the design hierarchy to enhance bug tracking.

○ DRC and LVS can be disabled for improved run-time or if tool licenses are not available.

● OpenRAM uses standard spice syntax○ Currently supports: ngspice, hspice, xa

■ Wish list: xyce

○ Multi-threaded support is highly recommended (e.g. ngspice with OpenMP)


Technology● Uses a technology path ($OPENRAM_TECH) to allow separation of code and

technology

● Setup file must configure PDK settings for DRC/LVS wrappers

● Simple design rule tech file with subset of DRC rules

● GDS layer map

● Spice corner models and constants

● Custom designed library cells (6T, sense amp)


Power/Delay Characterization● Prunes unused portions of circuit for run-time

● Setup time, hold time, and delay are found using a bidirectional search.

○ Find a feasible period

○ Iterate until convergence

● Dynamic and leakage measured

● Output saved in Liberty (.lib) file.

○ Uses NLDM

○ Wish list: CCS


Functional Simulation● Assumes uninitialized memory

● Random operations○ Uses multiple ports when available

○ Read, write, or noop

○ Random address

○ Random data

● Memory checks○ Uses standard CMOS noise margins

○ Compares read with last write (or feed-through value if being written)

● Wish list: formal properties of analog and timing?


Unit Tests● Uses Python unit test framework

● Unit tests guide users when porting to new technologies.

● Unit tests allow users to add features without worrying about breaking

functionality.

● Every module has its own regression test.

● There are regression tests for memory functionality, library cell verification,

timing verification, and technology verification.


Results and Comparisons


GDSII Result Samples

512 x 16b x 1rw FreePDK45 2048 x 32b x 1rw FreePDK45


SRAM Area

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Timing and Density Results for Generated SRAMs


Comparison with Fabricated SRAMs

Ref. Feature Size Tech. Density [Mb/mm2]

IEEE-VLSI’08 65 nm CMOS 0.7700

JSSC’11 45 nm CMOS 0.3300

JSSC’13 40 nm CMOS 0.9400

OpenRAM 45 nm FreePDK45 0.8260

JSSC’92 0.5 um CMOS 0.0036

JSSC’94 0.5 um BICMOS 0.0020

JSSC’99 0.5 um CMOS 0.0050

OpenRAM 0.5 um SCMOS 0.0050


Some Features in Progress● FreePDK15 (15nm FinFET process)

○ Creating a pfinfet.py parameterized FinFET class

● XFab XH018 (180nm)○ Working on collaboration to tape out memories

● Asynchronous control interface

● Built in Self Test (BIST)

● Error Correcting Codes (ECC)

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Conclusions● OpenRAM generates the circuit, functional model, and layout of variable-sized

SRAMs.

● OpenRAM provides a memory characterizer for synthesis timing and power

models.

● OpenRAM is open-sourced, flexible, and portable.

● OpenRAM aims to be independent of specific tools and methodologies.

● We are actively developing new features and improvements.

● We are actively seeking feedback and collaborations (and, of course,

funding!)


Contributors● Numerous UCSC Graduate Students

○ Bin Wu, Hunter Nichols, Jennifer Sowash, Jesse Cirimelli-Low

○ Former Students: Michael Grimes (Achronix), Jeff Butera (Mentor)

● Oklahoma State University○ Prof. James Stine

○ Dr. Samira Ataei (post-doc at Yale now)

● Other Collaboration○ Tim Edwards (eFabless, Open Circuit Design)

○ Edmund Humenberger & Others (Symbiotic EDA)


Thanks!

[email protected]

openram - f-siopenram_fsic2019.pdfdoesn’t perform drc/lvs estimates power/delay analytically...

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