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Open Process Specification
OPS 1.0 Status and Plans
October 9th, 2012
17th SI2 Conference
Gilles Namur
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OPS 1.0 has been completed
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OPS 1.0 has been approved by the Technical Steering Group of the SI2 OPDK
Coalition.
The TSG members have voted “yes” to start the 60 day exclusion period for OPS 1.0 with
the following statement on the purpose of OPS 1.0 and the plan for OPS 1.1.
OPS v1.0 is Targeted at Process producing companies (Foundries), to enable study and creation
of electronic versions of DRM, to gather early feed-back on completeness.
OPS v1.1 is the first release targeted for consideration by EDA Vendors.
It should be complete enough to enable DRC & technology file creation to support PDKs creation.
Today, the missing items for that 1.1 release are :
connectivity below M1 (including local interconnect).
manufacturing grid per layer
and the Items to be improved are :
tool mapping (toolInterfaces)
enums <> OA enums
TSG Members (Cadence , IBM , Intel , ST , Global Foundries , Mentor Graphics ,
NXP , Silvaco , Synopsys & Springsoft)
have Voted with a unanimous yes to proceed with the 60 day exclusion period
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Agenda
OPS Definition & Contents
OPS Working Model
OPS DRC : Link with openDFM Templates
OPS Next Steps Roadmap
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SI2 OPDK Coalition is about to release the first version of
Open Process Specification (OPS) that is a standardized format
for exchanging all data needed to generate a PDK.
OPS is the given name to the Standard Document (XSD format),
used as “syntax template” for an XML file.
Standardized PDK Input format that enables
a single and automated PDK generation flow.
OPS Definition
OPS.xsd
OPS.xml <Process>
<Libraries>
<Devices>
<Layers>
<Rules>
<…>
<…>
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PDK
DRM DB
OPS Inputs & Outputs
Device Spec Layer Info Process Data
DRC Code LVS Code Device Library
&
Techfile
PEX Code
…. DRC code info
Tiller Code EMG,
Spices,
…
…
OPS
Inputs
Outputs
Exchange
Format
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LVS
d i t a
FM
… …
PEX
Customer Supplier Exchange (standardized)
r t f
Library
Tiler
SPICE
EM
DRC
OPS : an exchange format
OPS.xsd
OPS.xml <Process>
<Libraries>
<Devices>
<Layers>
<Rules>
<…>
<…>
XSL
parser
parser
parser
parser
parser
parser
parser
parser
XSL
XSL
DRM DB PDK
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OPS is an XSD Format
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<xsd:element name="CADLayer">
<xsd:complexType>
<xsd:complexContent>
<xsd:extension base="Layer" >
<xsd:sequence>
<xsd:element ref="Display" minOccurs="0" />
<xsd:element ref="ToolMappingNumber" maxOccurs="unbounded" minOccurs="0" />
<xsd:element ref="StreamIO“ maxOccurs="unbounded" minOccurs="0" />
</xsd:sequence>
<xsd:attribute name="rootLayer" type="xsd:string" />
<xsd:attribute name="purpose" type="xsd:string" />
<xsd:attribute name="alias" type="xsd:string" />
<xsd:attribute name="role" type="Function" />
</xsd:extension>
</xsd:complexContent>
</xsd:complexType>
</xsd:element>
OPS.xml <Process> <Libraries>
<Devices> <Layers>
<Rules> <…>
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What does OPS look like ?
Human Readable Layer List
<ops:RootLayer name="OD“ abbreviation="OD“ destination="core">
<ops:ToolMappingNumber number="17" tool="OA"/>
</ops:RootLayer>
<ops:Purpose opsName="drawing“ name="drawing“ abbreviation="drg“ destination="core">
<ops:ToolMappingNumber number="-1" tool="OA"/>
</ops:Purpose>
<ops:CADLayer name = "OD;drawing" alias="OD" opsRole="DIFFUSION" role="DIFFUSION" description = "Defines
ACTIVE Area" destination = "core" expoNumber = "1">
<ops:RefRootLayerName value="OD"/>
<ops:RefPurposeName value="drawing"/>
<ops:StreamIO format="GDSII" number="1" dataType="0"/>
<ops:StreamIO format="OASIS" number="501" dataType="500"/>
<ops:ToolMappingNumber number="1001" tool="Calibre"/>
<ops:Display transparencyOrder="1" visible="True" selectable="True" con2ChgLy="True" drgEnbl="True" valid="True"
stipple="stipple3" lineStyle="lineStyle0" fill="lime" outline="lime" fillStyle=""/>
</ops:CADLayer>
Machine Readable Layer Declaration in OPS.xml
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What does OPS look like ?
Human Readable DRM Machine Readable OPS.xml
<ops:DerivedLayer name="Gate" description="PO over OD">
<ops:Template name="AND">
<ops:RefCADLayerAlias value="OD"/>
<ops:RefCADLayerAlias value="PO"/>
</ops:Template>
</ops:DerivedLayer>
• PP_OD: (OD .and. PP) .not. PO
heavily doped P type
OD that does not
include transistor
channels
<ops:DerivedLayer name="PP_OD description="Heavily
doped P type OD that does not include transistor channels">
<ops:Template name="NOT">
<ops:DerivedLayer name="">
<ops:Template name="AND">
<ops:RefCADLayerAlias value="OD"/>
<ops:RefCADLayerAlias value="PP"/>
</ops:Template>
</ops:DerivedLayer>
<ops:RefCADLayerAlias value="PO"/>
</ops:Template>
</ops:DerivedLayer>
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<ops:Rule name="PO.S.4">
<opc:Documentation sectionTitle="PO Design Rules (POLY)">
<opc:Description>PO space if at least one PO width is > 0.120 µm (W) and if the parallel run
length is > 0.140 µm (L)</opc:Description>
</opc:Documentation>
<ops:Template name="">
<opc:Parameter name="V1" value="0.120" type="FLOAT"/>
<opc:Parameter name="V2" value="0.140" type="FLOAT"/>
<opc:Parameter name="MAIN" value="0.160" type="FLOAT">
<opc:SIUnit prefix="µ" siName="m"/>
</opc:Parameter>
<ops:RefCADLayerAlias value="PO"/>
<ops:RefCADLayerAlias value="PO"/>
</ops:Template>
</ops:Rule>
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What does OPS look like ?
Human Readable DRM
Machine Readable OPS.xml
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What does OPS look like ?
<edsDevice name="nfet" libName="demo45" description="Regular-Vt FET" symbolName="nmos3"
symbolPinOrderMappingList="D=d;G=g;S=s;B=b" layoutName="nfet" layoutType="PCELL" >
<edsDeviceParameter name="w" description="Total Gate Width" defaultValue="240n"
type="string" units="lengthMetric" >
<edsDDFDeviceParameter callback="Check_Width_Fet('w)" parseAsNumber="1"
parseAsCEL="1" editable='cdfgData->dimensionMode->value==\"TotalWidth\"' display="1" storeDefault="1" />
</edsDeviceParameter>
<edsDeviceParameter name="l" description="Gate Length" defaultValue=“80n" type="string"
units="lengthMetric" >
<edsDDFDeviceParameter editable="1" callback="Check_Length_Fet()"
parseAsNumber="1" parseAsCEL="1" display="1" storeDefault="1" />
</edsDeviceParameter>
<edsDeviceNetlistingInfos>
<edsDeviceNetlistingInfo toolName="auCdl" modelName="nfet"
netlistProcedure="_ansCdlCompParamPrim" instParameters="(w l)" componentName="mos" termOrder="(d
g s b)" namePrefix="M" />
</edsDeviceNetlistingInfos>
</edsDevice>
Library device description Parameter Pin Order Netlister
demo45 nfet Regular-Vt FET w & l D;G;S;B CDL
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Agenda
OPS Definition & Contents
OPS Working Model
OPS DRC : Link with openDFM Templates
OPS Next Steps Roadmap
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OPS Working Model is not part of the standard
1.Several Working Models around OPS exist.
2.OPS WG purpose is to produce a standard format,
not a working model to use it.
3.The following slides present several possible
examples of OPS use cases.
4.Any of these working models shares the same
OPS.xsd format.
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Merge Operation
Check the consistency in
between the data from both
initial OPS
If consistent Merge
If not need source
correction = iteration
OPS
DRM DB
OPS
Layer Info
OPS
Device Spec
Process Data
OPS OPS
Ground
Ruler
LVS Coder
Device Lib Coder
Enriched OPS
DRC Code
LVS Code
Device Library & Techfile
PEX Code
OPS with
Template Info
OPS with
LVS Info OPS with
Device Info
DRC Coder
Device
Owner
Layer
Owner
Working Model #1
Process
Eng.
OPS
…
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DRM DB
Layer Info
Device Spec
Process Data
Ground
Ruler
Device
Owner
Layer
Owner
Process
Eng.
OPS
DRC Code LVS Code Device Library & Techfile PEX Code
DRC Coder LVS Coder Device Lib
Coder
Working Model #2
…
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Ground
Ruler
Device
Owner
Layer
Owner
Process
Eng.
OPS
DRC Code LVS Code Device Library & Techfile PEX Code
DRC Coder LVS Coder Device Lib
Coder
Working Model #3
…
OPS
OPS
OPS
OPS
OPS
OPS
Merge
OPS
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Agenda
OPS Definition & Contents
OPS Working Model
OPS DRC : Link with openDFM Templates
OPS Next Steps Roadmap
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New
Template
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In-House
Template DB
Generator
DRM DB
DRC Coder
openDFM
Template DB
Enriched OPS
DRC
Code
GroundRuler
Reference to
OPS
The DRC Coder will enrich the OPS with the
Rule Template Info:
openDFM Template if there is one
template corresponding to the rule exists.
OPS to DRC : a Working Model / Use Case
In-House Template if there is no
openDFM one, and if there is an in-house
template corresponding to the rule.
If there is no existing template for the rule,
then the DRC Coder will create a New
Template and will refer to this template in
the OPS.
New Template
The DRC code can then be automaticaly
generated.
SI2 Already provides the « OPS to
openDFM » script.
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Translation from OPS XML to OpenDFM and back
OpenDFM
Runset
ICV/Calibre/
PVS/Quartz
DRC Runset
Plug-in Plug-in
ops2odfm
Translation
Original OPS XML
OpenDFM Parser
Enriched
OPS
XML
OPS2ODFM Translation Parse the OPS XML and extract parameters for
OpenDFM.
Templates allow easily customization of
translation.
OPS XML is easy to parse and pick out
parameters
Only 200 lines of Tcl with good performance
(greater then 1,000 lines/second).
openDFM Parser Parse OpenDFM functions and translate into
ICV, Calibre, PVS, Quartz and now XML via
plug-ins supplied by EDA Vendors
OpenDFM Parser uses a plug-in architecture.
A new XML plug-in was easily added
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OPS & openDFM concrete example
1. Provided by DRM owner: generic template placeholder, and related layers and values.
<OPS:Rule name="OD.S.1">
<OPS:Documentation sectionTitle="OD Design Rules">
<OPS:Description>OD space</OPS:Description>
</OPS:Documentation>
<OPS:Template name=""/>
<OPS:Parameter name="MAIN" value=“0.080" type="FLOAT">
<OPS:SIUnit SIName="m" prefix="µ" />
<OPS:Parameter />
<OPS:RefCADLayerAlias value="OD" />
</OPS:Template>
</OPS:Rule>
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OPS & openDFM concrete example
2. Enriched by DRC coder: template name set and linked to provided layers and values.
<OPS:Rule name="OD.S.1">
<OPS:Documentation sectionTitle="OD Design Rules">
<OPS:Description>OD space</OPS:Description>
</OPS:Documentation>
<odfmc:Check_space cmnt="" edge_direction="ALL" edge_membership="ALL"
edge_pair="ALL" extension_type="RADIAL" length_interval="0.0" marker_layer=""
out_layer="" rule_name="" space_less_than="MAIN"/>
<OPS:InLayer>
<OPS:RefCADLayerAlias value="OD" />
<OPS:InLayer/>
<OPS:Parameter name="MAIN" value="0.080" type="FLOAT">
<OPS:SIUnit SIName="m" prefix="µ" />
<OPS:Parameter />
</OPS:Check_space>
</OPS:Rule>
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OPS & openDFM concrete example
3. Enriched by DRC coder: If we deal with a generic Template (In-House).
<OPS:Rule name="OD.S.1">
<OPS:Documentation sectionTitle="OD Design Rules">
<OPS:Description>OD space</OPS:Description>
</OPS:Documentation>
<OPS:Template name="myTemplate "/>
<OPS:Parameter name="MAIN" value="0.080" type="FLOAT">
<OPS:SIUnit SIName="m" prefix="µ" />
<OPS:Parameter />
<OPS:RefCADLayerAlias value="OD" />
<OPS:Parameter type="template_option" name="inside_layer" value="OD">
<OPS:Parameter type="template_option" name="value" value="MAIN">
</OPS:Template>
</OPS:Rule>
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Agenda
OPS Definition & Contents
OPS Working Model
OPS DRC : Link with openDFM Templates
OPS Next Steps Roadmap
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OPS Next Steps Roadmap
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2013
2012
OPS 1.0 :
Targeted at Process producing companies (Foundries) to enable study and creation of
electronic versions of DRM.
Implementation example: Demo DRM 45nm v1.5 aligned on OPS 1.0
OPS 2.0
Contents :
Objects for LVS + Link with ODFM Coalition OPEX WG
Tiler + description of Tilling Layers through table
Electrical Parameters & Electromigration
Device & Library Description Improvement (SCP WG Results integration in OPS)
New WG : OA Techfile Constraint Templates based on openDFM results
+ Sub Dedicated WG on Analog Constraints
New WG : Pcells specification in OPS
Implementation example: Demo DRM 45nm v3.0 aligned on OPS 2.0 & Library Example
generated from OPS (CDF, callback, techfile, symbols)
Q1
Q3
Q4
OPS.xml <Process>
<Libraries>
<Devices>
<Layers>
<Rules>
<…>
<…>
OPS 1.1
first release targeted for consideration by EDA Vendors complete enough to enable
DRC & technology file creation
Contents
Connectivity below M1 (including local interconnect).
Manufacturing grid per layer
Tool mapping / Interfaces
Improved enumerations
Implementation example: Demo DRM 45nm v2.0 aligned on OPS 1.1
Q2
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