on the single-chip implementation of ieee802.11a
DESCRIPTION
On the Single-Chip Implementation of IEEE802.11a. 長庚電機通訊組 碩一 張晉銓 指導教授 : 黃文傑博士. Outline. Software simulation of the C-code The system concept and main parameters Analog Front-End introduction A scheme of synchronization blocks SAW filter. IEEE 802.11a structure. - PowerPoint PPT PresentationTRANSCRIPT
On the Single-Chip Implementation of
IEEE802.11a
長庚電機通訊組 碩一 張晉銓
指導教授 : 黃文傑博士
Outline
Software simulation of the C-code The system concept and main parameters Analog Front-End introduction A scheme of synchronization blocks SAW filter
IEEE 802.11a structure
Data rate ranging from 6-54 Mb/s Bandwidth 20MHz Modulation: BPSK, QPSK ,QAM. Symbol duration : 4us including 0.8us guard
interval Why we use single-chip?
Computational Requirements of the Baseband Processor
● Software of the model (C-code) on a SUN Sparcstatsion 10 transmitted 1024 bytes 500 times at different bit rates from 6-54 Mb/s
Computational Requirements of the Baseband Processor
●In the receiver, the Viterbi decoder consumes most of the calculation power
●Processing power of the 802.11a system is distributed in an asymmetric fashion between transmit and receive operations.
The OFDM synchronization unit was not modeled
99.9%
The system concept and mainparameters
The complete modem have three main blocks Analog front- end Digital baseband
processor DLC layer
The system concept and mainparameters (conventional)
Super-heterodyne transceiver
Require a narrowband filter (SAW surface acoustic wave).
The I/Q separation be done in the analog domain, which mean that two A/D converters with an analog BW of 10 MHz.
The IF chosen is 810 MHz. Need to be routed off-chip which lead to an increase in p
ower dissipation. Two A/D converter resolution is 10 Bits. Oversampling of 80 MHz. (A/D & D/A)
Super-heterodyne transceiver
Digital IF Receiver Advantage: Gain is distributed ove
r several amplifiers Good selectivity (due t
o the presence of preselect and channel filter
Conversion from a real to complex signal is done at one fixed freq.
● Disadvantage:
●A/D has to be least 20 MHz
●Numerically NCO
●The linearity of receiver hardware need be maintained
Homodyne (Zero IF) receiver LO will translate the desired channel to 0 Hz IF SAW filter are placed with low-pass filter Research Issue:
DC offset Maintenance of I/Q balance Maintenance of low second order distortion
A scheme of synchronization blocks
SPW Model of baseband with synchronization
The estimator is mainly based on autocorrelation and crosscorrelation, and the preamble structure has to be optimized in order to minimize the estimator varience.
Symbol/frame timing offset Carrier frequency offset Sampling clock frequency offset
Approach for synchronization
Sampling clock freq. offset use a fixed clock and an interpolator filter and the filter factor that depend on some error signal.
Use pilot for channel estimation A Gaussian or Lagrange interpolator filter Due to the nearly independent behavior of
correlation functions in time and freq. ,the problem is simplified by using two-dimension Wiener Filters
This SAW filter for the receiving RF circuit of GSM mobile communication equipment operating at 935 MHz ~ 960 MHz.
End
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