On Codes Correcting BidirectionalLimited-Magnitude Errors for Flash Memories

Myeongwoon Jeon and Jungwoo LeeSchool of Electrical Engineering and Computer Sciences

Seoul National University, Seoul 151-744, KoreaEmail: ifindme@wspl.snu.ac.kr and junglee@snu.ac.kr

Abstract—NAND multi-level cell (MLC) flash memories arewidely used due to low cost and high capacity. However, theincreased number of levels in MLC results in larger interferenceand errors. The errors in MLC flash memories tend to bedirectional and limited-magnitude. Many related works focus onasymmetric errors, but bidirectional errors also occur becauseof the bidirectional interference and the adjustment of the hard-decision reference voltages. To take advantage of the charac-teristics, we propose 𝑡 bidirectional (𝑙𝑢, 𝑙𝑑) limited-magnitudeerror correction codes, which can reduce errors more effectively.The proposed code is systematic, and can correct 𝑡 bidirectionalerrors with upward and downward magnitude of 𝑙𝑢 and 𝑙𝑑,respectively. The proposed method is advantageous in that theparity size is reduced, and the error rate performance is betterthan conventional error correction codes when the code rate isequal.

I. INTRODUCTION

NAND flash memory has been used widely because of itsnon-volatility and portability. Recently, multi level cell (MLC)flash memories have been studied for improving memorycapacity. Multi level cell flash memories use more than 2levels, and store two or more bits in a single cell. However,error increases rapidly with the number of levels in a cellbecause of the interference caused by cell-to-cell coupling,temperature, disturbance, and so on. MLC flash memory errorstend to be directional and have limited-magnitude. Variousfactors of interference lead to the threshold voltage (𝑉𝑡ℎ) shiftof the cells, and especially dominant factors such as cell tocell interference and over-programming increase 𝑉𝑡ℎ [1].

Most noise and interference have limited amplitude, andmost errors occur between adjacent levels. The conventionalerror correction codes can be inefficient for MLC flashmemory because these codes are constructed for all possibleerror types where error magnitude and direction are random.Therefore, we can use the error characteristics of MLC flashmemories to construct efficient error correction codes. Forflash memories, the error correction codes for asymmetricchannels with limited-magnitude error were introduced in [2].Although the inter-cell interference leads to upward 𝑉𝑡ℎ shiftmostly, there are also bidirectional or downward interferenceeffects [3]. The hard-decision reference voltages (𝑉𝑟𝑒𝑎𝑑) forreading cell data is determined based on the 𝑉𝑡ℎ distributionconsidering the interference effect, so it is already near op-timal, which results in a symmetric (bidirectional channel).Therefore, bidirectional errors need to be considered in de-

signing channel codes. [4] introduced the symmetric limitederror correction codes which can correct only one single error,so it is not practical for flash memories.

In this paper, we introduce bidirectional limited-magnitudeerror correction codes (BLM-ECC) which has low redundancyfor flash memory applications. The proposed code extendsthe technique of the asymmetric error correction codes [2] tothe bidirectional error correction codes. The code treats bothupward and downward errors when the error magnitude ofeach direction can be different. The maximum magnitudesof the upward error and downward error are 𝑙𝑢 and 𝑙𝑑,respectively. Bidirectional errors can be corrected using non-binary conventional error correction codes. With an 8-level cellmodel, the proposed code is simulated to check the error rateperformance. The simulation result shows that the bit errorrate performance of the proposed algorithm is better than theconventional block codes and the asymmetric error correctioncodes when the code rates are equal. In the following section,the shift of the threshold voltage and the bidirectional limited-magnitude errors are discussed. We then propose new efficienterror correcting codes for MLC flash memories in SectionIII. Simulation results of the new algorithm are presented inSection IV. Finally, we conclude the paper in Section V.

II. MLC FLASH MEMORY INTERFERENCE AND

BIDIRECTIONAL LIMITED-MAGNITUDE ERRORS

A cell of the NAND flash memory is a floating gatetransistor, and its threshold voltage can be programmed byinjecting certain amount of charges into the floating gate [5].The threshold voltage (𝑉𝑡ℎ) is used to distinguish data levelsin MLC memory. Several factors may change the distributionof the floating-gate threshold-voltage. These factors includecell to cell interference, cell leakage, temperature, programvoltage (𝑉𝑝𝑔𝑚) disturbance, the pass voltage (𝑉𝑝𝑎𝑠𝑠) applied tounselected word-lines, etc [1]. One of the dominant factors isthe cell to cell interference, which is caused by the 𝑉𝑡ℎ changeof the neighbor cells in the programming (writing) operation.If the data of neighbor cells change, the cell to cell couplinginterference occurs. In this case, the 𝑉𝑡ℎ shift is known tobe upward (unidirectional). The cell to cell interference isapproximately proportional to the voltage change of neighborcells in the programming operation, but it is also affected bythe structure of flash memories, the program order, and thenumber of levels (MLC) in a cell. The quantitative interference

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Copyright 2012 IEICE 96

Fig. 1. 𝑉𝑡ℎ shift and bidirectional errors with adjusted 𝑉𝑟𝑒𝑎𝑑.

can be estimated by measurements and simulations [6]. Forthese asymmetric interference factors, the error correctioncodes for the asymmetric channel can be useful [2]. Althoughthe cell-to-cell interference which leads to upward errors arethe dominant factor in MLC flash memories, there are alsobidirectional (random-telegraph noise) or downward (retentionnoise) interference [3]. The hard-decision reference voltagesfor reading flash memory cells is determined based on the𝑉𝑡ℎ distribution after the cell-to-cell interference, not beforethe cell-to-cell interference, which means the hard-decisionreference voltages for reading is already near optimal. Fig. 1illustrates the threshold voltage shift, and the adjusted 𝑉𝑟𝑒𝑎𝑑.After adjusting 𝑉𝑟𝑒𝑎𝑑 to be near optimal, the number oferrors decreases, but the number of downward errors increases.Therefore, bidirectional errors should be considered in orderto improve the BER performance. Even if the errors arebidirectional, the magnitude of the errors is still limited.The magnitudes of downward error and upward error can bedifferent. The upward error magnitude can be larger than thedownward magnitude in general since the dominant interfer-ence effect is still upward even if the optimal 𝑉𝑟𝑒𝑎𝑑 is usedas in Fig. 1. We will discuss the bidirectional and the limited-magnitude error correction codes in the next section.

III. BIDIRECTIONAL LIMITED MAGNITUDE ERROR

CORRECTION CODES

A. Bidirectional Limited Magnitude Error Correction Codes

As described in the previous section, bidirectional errorsshould be considered in the flash memories. We propose the’bidirectional limited magnitude error correction code (BLM-ECC)’ which deals with both upward and downward errors. In(𝑙𝑢, 𝑙𝑑) BLM-ECC, 𝑙𝑢 and 𝑙𝑑 represent the maximum magni-tudes of the upward error and the downward error, respectively.Fig. 2 (a), (b), (c) illustrate the difference of various errortypes. [2] discuss the asymmetric limited magnitude error in(a), and [4] consider the symmetric limited magnitude errors

Fig. 2. Various limited magnitude error types and (𝑙𝑢, 𝑙𝑑) bidirectional errorchannel.

in (b). However, little is known of the bidirectional limitedmagnitude error in (c). Fig. 2 (d) show the 𝑙𝑢 = 2, 𝑙𝑑 = 1 bidi-rectional error channel in a 6-ary cell. The threshold voltage(𝑉𝑡ℎ) of the cell is not integer, but it is assumed that the celldata and the error values are integer. Since we do not know theexact threshold voltage or the interference voltage by memoryreading operation, only the integer decision after hard-decisionis possible. 𝑡 − (𝑙𝑢, 𝑙𝑑) BLM-ECC can correct the codewordwith 𝑡 errors of (𝑙𝑢, 𝑙𝑑) magnitude. The code construction isas follows. Let Ω be a 𝑞′-ary code and 𝑞′ = 𝑙𝑢 + 𝑙𝑑 + 1. The𝑞-ary code 𝒞 (𝑞 > 𝑞′) is defined as

𝒞 = {c = (𝑐1, ..., 𝑐𝑛) ∣ c mod (𝑙𝑢 + 𝑙𝑑 + 1) ∈ Ω} (1)

𝒞 correct 𝑡 bidirectional (𝑙𝑢, 𝑙𝑑) limited-magnitude errors ifΩ corrects 𝑡 symmetric errors. The process of encoding anddecoding of the proposed codes are described as follows.

B. Encoding

Let x = {𝑥1, . . . , 𝑥𝑘} be a 𝑞-ary message codeword, and𝑞-ary multi-level cell memory is assumed to be used. We getthe 𝑞′-ary remainder of the 𝑞-ary message x by modular 𝑞′

operation (𝑞′ = 𝑙𝑢 + 𝑙𝑑 + 1, 𝑞′ < 𝑞). The 𝑞′-ary remaindercodes are called base codes. In order to encode by the basecodes, conventional 𝑝-ary 𝑡 symmetric error correction codesare used, which is called base error correction codes. Withx mod 𝑞′ codeword, the 𝑝-ary parity codes can be obtainedusing base error correction codes. A 𝑝-ary parity codewordneeds to be converted to a 𝑞-ary codeword p = {𝑝1, . . . , 𝑝𝑟}in order to be stored in a 𝑞-ary memory cell. The systematicencoded codeword is then c = [x p] = {𝑐1, 𝑐2, . . . , 𝑐𝑛} and𝑛 = 𝑘 + 𝑟. ’Systematic’ means that the original message partand the parity part are separated in the encoded codeword.Since 𝑞 > 𝑞′, the base code size can be reduced thanthe original message, and the parity code size can be alsoreduced. Therefore, the code rate of the codes is larger thanconventional error correction, and this is the key advantage ofthe proposed code.

However, the above encoding method can cause the errorcount mismatch problem. The problem means one erratic cellusually causes two or more errors. There are two kinds of theproblem, one is a message correction problem when 𝑝 < 𝑞′,

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𝑙 ≥ 2, and the other is a parity code writing problem when𝑝 < 𝑞, 𝑙 ≥ 2. Let us discuss the message correction problemfirst. One error in a 𝑞-ary cell can cause two or more errors in a𝑝-ary message codeword if 𝑝 < 𝑞′. For example, in a (2𝑢, 1𝑑)memory channel, let us assume that 𝑞 = 8, 𝑞′ = 4, and 𝑝 = 2(binary) are the parameters for the base error correction codes.Note that 𝑎𝑏 means 𝑏-ary 𝑎 value for convenience. A messagecode 18 is 14 and 012. If 𝑙 = 2 error occurs in the 𝑞-ary cell,18 is changed to 38 which is 34 and 102 when the gray codesare used. Two bits are different between 012 and 102, and onecell error in the message cannot be corrected by 𝑡 = 1 binarybase error correction codes in this example.

Next, let us describe the parity code writing problem when𝑝 < 𝑞, 𝑙 ≥ 2. The proposed codes are systematic codes,and a 𝑞-ary message is written in a 𝑞-ary cell. However, 𝑝-ary base error correction codes are used, and a 𝑝-ary paritycodeword needs to be written in a 𝑞-ary cell. For example,𝑞 = 16 and 𝑝 = 4, a parity code 134 is written in the cellas 1 × 41 + 3 × 40 = 716. If 𝑙 = 2 error is added to thecell, the cell value becomes ’916’ which is ’214’. Therefore,one 𝑞-ary cell parity code error with 𝑙 = 2 causes two 𝑝-aryparity code errors. This problem can be avoided when 𝑝 ≥ 𝑞.Consequently, 𝑝 should be larger than 𝑞 and 𝑞′ (𝑝 ≥ 𝑞 ≥ 𝑞′)to avoid the error count mismatch problem. Thus, non-binary𝑝-ary error correction codes such as Reed-Solomon(RS) codescan be used. In order to achieve the maximum code rate, 𝑝, 𝑞,and 𝑞′ are two’s power of 𝑘 (𝑘 is integer), and log2𝑝 is amultiple of LCM(log2𝑞,log2𝑞′).

C. Decoding

Decoding of the proposed code is also based on the modular𝑞′ operation, and 𝑝-ary base error correcting codes. c′ =(𝑐′1, . . . , 𝑐

′𝑛) is the received codeword, and 𝝐 = (𝜖1, . . . , 𝜖𝑛)

is the error vector where each component is an integer. Itis assumed that its magnitude is limited to −𝑙𝑑 ≤ 𝜖 ≤ 𝑙𝑢where 𝑙𝑑 and 𝑙𝑢 are positive integers. The received codewordis c′ = c+ 𝝐 = [x p] + 𝝐 = [y p′]. y = (𝑦1, . . . , 𝑦𝑘) isthe received message part in the received codeword. At first,modular 𝑞′ is performed on the received message y, which issimilar to the encoding process. We then have 𝝋 = y mod 𝑞′.The received 𝑞-ary parity part p′ and 𝝋 need to be converteda 𝑝-ary codeword to be decoded by the base error correctioncodes. We can correct 𝑡 symmetric errors for the codewordwith 𝝋 and the parity code, and the corrected 𝑞′-ary messagecan be obtained if the 𝑡 errors are within the (𝑙𝑢, 𝑙𝑑) bound.We can then estimate the error codeword 𝝐′ by the differencebetween the corrected message code and the received messagecode. However, the estimated error may exceed the error bounddue to the modular operation, although the error codeword iswithin the (𝑙𝑢, 𝑙𝑑) bound, Fortunately, the estimated error canbe recovered by a simple shift. The procedure is described asfollows.

We define x,y, and 𝝐 by a transmitted codeword, a received

Fig. 3. Adjustment of estimated error to be in the bound (𝑙𝑢 = 𝑙𝑑 isassumed).

codeword, and a (𝑙𝑢, 𝑙𝑑) error codeword, respectively.

y mod 𝑞′ = (x+ 𝝐) mod 𝑞′

= (x mod 𝑞′ + 𝝐 mod 𝑞′) mod 𝑞′

= (𝜼 + 𝝃) mod 𝑞′

(𝜼 = x mod 𝑞′,𝝋 = y mod 𝑞′, 𝝃 = 𝝐 mod 𝑞′)

(2)

Since the modular operation with a negative integer may beconfusing, we deal with the downward error and the upwarderror separately.Case I. downward error. if 𝜖𝑖 = 𝜖↓ (−𝑙𝑑 ≤ 𝜖↓ ≤ −1)

𝜑𝑖 = (𝜂𝑖 + 𝜉𝑖) mod 𝑞′ = (𝜂𝑖 + 𝜖↓ + 𝑞′) mod 𝑞′

=

{𝜂𝑖 + 𝜖↓ + 𝑞′ (0 < 𝜂𝑖 + 𝜖↓ + 𝑞′ < 𝑞′)𝜂𝑖 + 𝜖↓ (𝑞′ ≤ 𝜂𝑖 + 𝜖↓ + 𝑞′ < 2𝑞′)

(3)

Case II. upward error. if 𝜖𝑖 = 𝜖↑ (0 ≤ 𝜖↑ ≤ 𝑙𝑢)

𝜑𝑖 = (𝜂𝑖 + 𝜉𝑖) mod 𝑞′ = (𝜂𝑖 + 𝜖↑) mod 𝑞′

=

{𝜂𝑖 + 𝜖↑ (0 < 𝜂𝑖 + 𝜖↑ < 𝑞′)𝜂𝑖 + 𝜖↑ − 𝑞′ (𝑞′ ≤ 𝜂𝑖 + 𝜖↑ < 2𝑞′)

(4)

It was assumed that 𝜼 ∈ Ω and Ω corrects 𝑡 symmetricerrors. Therefore, 𝑡 symmetric errors of 𝝋 can be corrected.𝝋′ is the corrected codeword of 𝝋, so 𝝋′ = 𝜼. The estimatederror 𝜖′𝑖 is 𝜑𝑖 − 𝜑′𝑖. As for case I with downward error, wehave 𝜖′𝑖 = 𝜖↓ + 𝑞′ or 𝜖↓. As for case II with upward error, wehave 𝜖′𝑖 = 𝜖↑ or 𝜖↑ − 𝑞. Therefore, four types of error showup in the estimated error codeword, and −𝑞′ ≤ 𝜖′𝑖 < 𝑞′ − 1.The original error is in the range of −𝑙𝑑 ≤ 𝜖 ≤ 𝑙𝑢, but theestimated error may exceed the bound (range). However, thefour types of error have their own distinct ranges as −𝑞′ ≤𝜖↑ − 𝑞′ ≤ −𝑙𝑑 − 1, −𝑙𝑑 ≤ 𝜖↓ ≤ −1, 0 ≤ 𝜖↑ ≤ 𝑞′ − 𝑙𝑑 − 1,and 𝑞′ − 𝑙𝑑 ≤ 𝜖↓ + 𝑞′ ≤ 𝑞′ − 1 where we used only 𝑞′ and𝑙𝑑 (𝑙𝑢 = 𝑞′ − 𝑙𝑑 − 1). Thus, we can distinguish them with therange, and recover the estimated error by adding or subtracting𝑞′. The adjustment of estimated error is illustrated in Fig. 3.

The encoding and the decoding algorithms of bidirectionallimited magnitude error correction codes (BLM-ECC) aredescribed as follows.

Bidirectional Limited Magnitude Error CorrectionCodes Algorithm𝑬𝒏𝒄𝒐𝒅𝒊𝒏𝒈

(Initialization) 𝑞-ary message codeword x𝑞′ = 𝑙𝑢 + 𝑙𝑑 + 1, where 𝑙𝑢 and 𝑙𝑑 are upward anddownward error magnitude bounds, respectively.

1) Get the remainder of message x by mod 𝑞′.𝜼 = x mod 𝑞′.

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Fig. 4. BLM-ECC encoding, decoding process example.

2) Generate the 𝑝-ary parity codes for 𝜼 using 𝑝-arybase error correction codes and convert the codes to𝑞-ary codes, p (𝑝 ≥ 𝑞 ≥ 𝑞′).

3) A systematic encoded codeword is c = [x p]. Writethe codeword to the 𝑞-ary memory cell.

𝑫𝒆𝒄𝒐𝒅𝒊𝒏𝒈

(Initialization) Received codeword c′ = [x p] + 𝝐= [y p′], where 𝝐 = (𝜖1, . . . , 𝜖𝑛) is the error vectorwith each integer component within (𝑙𝑢, 𝑙𝑑), y is thereceived message code, and p′ is the received paritycode.

1) Get the remainder of received message mod 𝑞′.𝝋 = y mod 𝑞′.

2) Convert 𝝋 and p′ to 𝑝-ary codes for base ECCdecoding. Corrected 𝑞′-ary message is 𝝋′.

3) Estimate the error by 𝝐′ = 𝝋 − 𝝋′, 𝝐′ =(𝜖′1, . . . , 𝜖

′𝑘) is estimated error of the message.

4) If the estimated error exceeds the bound (𝜖′𝑖 > 𝑙𝑢 or𝜖′𝑖 < −𝑙𝑑), let 𝜖′𝑖 = 𝜖′𝑖 + 𝑞′ or 𝜖′𝑖 = 𝜖′𝑖 − 𝑞′ to be inthe range of −𝑙𝑑 ≤ 𝜖′𝑖 ≤ 𝑙𝑢.

5) The corrected message x′ is obtained by x′ = y−𝝐′.The example of BLM-ECC encoding and decoding process

is illustrated in Fig. 4.

D. Discussion of the Codes

The number of codewords of 𝒞 in (1) is bounded by thefollowing inequalities.⌊ 𝑞

𝑙𝑢 + 𝑙𝑑 + 1

⌋𝑛⋅ ∣Ω∣ ≤ ∣𝒞∣ ≤

⌈ 𝑞

𝑙𝑢 + 𝑙𝑑 + 1

⌉𝑛⋅ ∣Ω∣ (5)

𝜼 = (𝜂1, . . . , 𝜂𝑛) is considered to be a codeword of Ω in(1). The codewords of 𝒞 can be obtained by replacing each𝜂 by the element of the set Λ = {𝜆∣𝜆 mod 𝑞′ = 𝜂𝑖, 𝜆 ∈{0, 1, . . . , 𝑞 − 1}}. The size of Λ is ⌈𝑞/𝑞′⌉𝑛 if 𝜂𝑖 < (𝑞 mod

𝑞′), and ⌊𝑞/𝑞′⌋𝑛 otherwise. In (5), the upper bound is ∣𝒞∣ ≤⌈𝑞

𝑙𝑢+𝑙𝑑+1

⌉𝑛⋅ ∣Ω∣. Ω is 𝑞′-ary, and can correct 𝑡 symmetric

errors, and we have ∣Ω∣⋅∑𝑡𝑘=0

(𝑛𝑘

)(𝑞′−1)𝑘 ≤ 𝑞′𝑛. Substituting

the latter into the former, the following is obtained. If 𝒞 is a(𝑙𝑑, 𝑙𝑢) limited-magnitude 𝑡-error correcting codes of length 𝑛over an alphabet of size 𝑞, we have

∣𝒞∣ ≤ 𝑞𝑛∑𝑡𝑘=0

(𝑛𝑘

)(𝑙𝑑 + 𝑙𝑢)𝑘

. (6)

The code rate of the BLM-ECC depends on the 𝑝-ary baseerror correction codes. If (2𝑚−1, 2𝑚−1−2𝑡) Reed-Solomon(RS) codes are used as the 𝑝-ary base ECC, a code rate is givenby

𝑅𝐵𝐿𝑀 ≤ (2𝑚 − 1− 2𝑡)log2𝑞

(2𝑚 − 1− 2𝑡)log2𝑞 + 2𝑡log2𝑞′ . (7)

The RS codes encodes the 𝑝-ary message with 𝑝 = 2𝑚.The equality can be achieved when log2𝑝, log2𝑞, log2𝑞′ arepositive integers with 𝑝 ≥ 𝑞 ≥ 𝑞′, and log2𝑝 is a multiple ofLCM(log2𝑞,log2𝑞′). The code rate of (2𝑚 − 1, 2𝑚 − 1 − 2𝑡)

Reed-Solomon (RS) codes is 𝑅𝑅𝑆 ≤ (2𝑚−1−2𝑡)(2𝑚−1) . If 𝑞 > 𝑞′,

the parity size of BLM-ECC is reduced than the RS codes,we have 𝑅𝐵𝐿𝑀 ≥ 𝑅𝑅𝑆 . If most errors are in the (𝑙𝑢, 𝑙𝑑)bound, the BLM-ECC (based on RS) can have better errorrate performance than the conventional RS codes with equalcode rate when 𝑞 > 𝑞′, which is verified in simulations.

IV. SIMULATION RESULTS

A. MLC Flash Memory Interference and Simulation Model

We simulated the bit error rate performance of the proposedbidirectional limited magnitude error correction codes (BLM-ECC). In simulations, the multi-level cell model of flash mem-ories with interference is used. The cell to cell interferencemodel depends on the program order, the page architecture,and the conventional LSB/MSB techniques, and these factorsare considered in simulations. To simulate flash memorieswith interference, we need not only an interference model,but also a threshold voltage distribution model. To write dataonto flash memories inherently involves errors due to the noisein the physical process. We can approximate the cell thresholdvoltage distribution as Gaussian. It should be noted thatthe empirical distribution obtained from measurements is notexactly a Gaussian distribution, but rather a kind of truncatedGaussian distribution. An 8-level flash memory model (3 bitsin a cell) is used with an equal noise distribution model.The equal noise distribution model assumes that each levelhas equal threshold voltage distribution which is Gaussian.The hard-decision reference voltages for reading is alreadynear-optimal in practical systems. We use both original hard-decision reference voltages and the adjusted near-optimalreference voltages in the Fig. 5 and 6 simulations in order toverify the performance of asymmetric error correction codes.(2𝑢, 1𝑑) BLM-ECC and 1𝐴1𝑀 asymmetric error correctioncode simulations are performed. 1𝐴1𝑀 means systematicasymmetric error correction codes with 𝑡 = 1 and 𝑙 = 1 as

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0.78 0.8 0.82 0.84 0.86 0.88 0.9 0.92 0.9410

−5

10−4

10−3

10−2

Code Rate

BE

R

No ECC (63,63−2t) RSAsymmetric ECC (1A1M)(2u,1d) BLM−ECC (Proposed)

Fig. 5. BER plots with original 𝑉𝑟𝑒𝑎𝑑 (asymmetric channel).

defined in [2]. The code has equal correction capability com-pared to the (1𝑢, 0𝑑) BLM-ECC if the base error correctioncodes are the same. We use the Reed-Solomon codes as the𝑝-ary base error correction codes in the 1𝐴1𝑀 asymmetriccodes and the (2𝑢, 1𝑑) BLM-ECC. In the (2𝑢, 1𝑑) BLM-ECC,we use 𝑞′ = 22, 𝑞 = 23 and 𝑝 = 26 − 1.

B. BER Performance

Fig. 5 shows the BER performance of the BLM-ECCand the asymmetric error correction codes with the originalhard-decision reference voltage(𝑉𝑟𝑒𝑎𝑑). The code rate of thehorizontal axis is determined as 𝑡 changes. The ’No ECC’ plotshows the bit error rate without any error correction codes,and the plot is flat. In other ECC plots, as the code ratedecreases, 𝑡 gets larger and the bit error rate gets lower. Atthe high code rate range, 1𝐴1𝑀 asymmetric error correctioncodes show the best performance. Because most errors (over99%) are upward when original 𝑉𝑟𝑒𝑎𝑑 is used as the hard-decision reference voltage. However at the low code rate range,1𝐴1𝑀 asymmetric ECC cannot correct the out of bounderrors, especially downward errors. Therefore, the plot is flatat lower code rate than 0.88, and the performance of BLM-ECC has better than asymmetric error correction codes atthe range. The (2𝑢, 1𝑑) BLM-ECC has better performancethan the original RS codes at all range because the BLM-ECC parity size is reduced. In the Fig. 6, the hard-decisionreference voltage (𝑉𝑟𝑒𝑎𝑑) is already adjusted based on thethe average interference quantity with writing random data.The adjusted hard-decision reference voltage compensates theupward 𝑉𝑡ℎ shift by the cell to cell interference, which makesthe errors more symmetric rather than asymmetric. Therefore,the performance of asymmetric error correction codes getsworse. The (2𝑢, 1𝑑) BLM-ECC algorithm shows the best BERperformance at all code rate, and it is shown that the proposedalgorithm is efficient for the MLC flash memory model.

0.88 0.9 0.92 0.94 0.96 0.98

10−6

10−5

10−4

10−3

Code Rate

BE

R

No ECC (63,63−2t) RSAsymmetric ECC (1A1M)(2u,1d) BLM−ECC(Proposed)

Fig. 6. BER plots with adjusted near optimal 𝑉𝑟𝑒𝑎𝑑 (bidirectional channel).

V. CONCLUSIONS

To reduce errors in MLC flash memories, we proposenew error correction codes by taking advantage of limitedmagnitude of errors. Key advantages of the proposed methodare that it can reduce the parity size, and that it has better errorcorrection performance than the conventional error correctioncodes when the code rate is equal. Practical issues of encodingand decoding for the proposed method are discussed, andefficient methods are proposed. We discussed the potentialproblems of existing limited-magnitude error correction codes,and show that proposed code is more suitable to practical flashmemory devices in simulations.

ACKNOWLEDGMENT

This research was supported in part by Basic ScienceResearch Program (2010-0013397) and Mid-career ResearcherProgram (2010-0027155) through the NRF funded by theMEST, the KETEP grant funded by the Ministry of KnowledgeEconomy (No. 2011T100100151), the INMAC, and BK21.

REFERENCES

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