oif spi system packet interface applied micro circuits corporation
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OIF SPI System Packet Interface
Applied Micro Circuits Corporation
SERDES FramerInterface (SFI)
FEC
Data
Clock
Data
Clock
OR
SERDES FramerInterface (SFI)
OpticalInterface
SERDES Device
andOptics
Data
Clock
Data
Clock
OIF Electrical Specifications
Status
Transmit Link Layer
Device
Receive Link Layer
Device
System PacketInterface (SPI)
Data
Status
Data
Data
Data
T F I
PHYDevice
TDM Fabric to Framer Interface (TFI)
Transmit Link Layer
Device
Receive Link Layer Device
PHYDevice
Data
TransmitInterface
Status
Data
Status
ReceiveInterface
System PacketInterface (SPI)
System Packet Interface (SPI-n)S y s t e m t o O p t i c s
O p t i c s t o S y s t e m
TFCLK
TXREFCKTXREFCK
RXREFCK
SerdesLink
LayerNP
ATM SAR
Framer
TMOD[1:0]
TDATA [31:0]TENB
TXDCK
TXDATA [15:0]
TXDSC
TXCKSRC
RXREFCK
DC
AB
TADR[1:0]
DTPA[3:0]STPA
RSX
RXDCK
RXDATA [15:0]
RXDSC
RXS
AB
S y s t e m t o O p t i c s
O p t i c s t o S y s t e m
SPI-3: OIF SPI3-01.0
Support up to 2.5Gb/s bi-directional data throughput
TPRTYTSOPTEOP
TERRTSX
RERRREOP
RSOP
RVAL
PTPA
RFCLKRENBRDAT[31:0]
RMOD[1:0]
RRPRTY
TX
RX
SONET/SDH OC-48
4xOC-1216xOC-3
8 bit or 32 bit interface options LVCMOS signals; point to point operationIn-band addressing
TFCLK
TXREFCK
TXREFCK
RXREFCK
SerdesLink
LayerNP
ATM SAR
Framer
TMOD[1:0]
TDATA [31:0]TENB
TXDCK
TXDATA [15:0]
TXDSC
TXCKSRC
RXREFCK
DC
AB
TADR[1:0]
DTPA[3:0]STPA
RSX
RXDCK
RXDATA [15:0]
RXDSC
RXS
AB
S y s t e m t o O p t i c s
O p t i c s t o S y s t e m
SPI-3: OIF SPI3-01.0
8 bit operation supports 1xOC-12 (622 MB/s)
TPRTYTSOPTEOP
TERRTSX
RERRREOP
RSOP
RVAL
PTPA
RFCLKRENBRDAT[31:0]
RMOD[1:0]
RPRTY
TX
RX
Supports:Packet over SONETATM over SONET
Frame Relay over SONET
Error indication signal
Data transfer independent of line bit rateTransfers ATM cells, packets including IP, FR, etc.Flow control on interface
TXCLK
TXREFCK
TXREFCK
RXREFCK
SerdesLink
LayerNP
ATM SAR
Framer
TXSIZE[2:0]
TXDATA [63:0]TXADDR[N-1:0]
TXDCK
TXDATA [15:0]
TXDSC
TXCKSRC
RXREFCK
DC
ABTXSTARTTXFULL[3:0]
RXSTART
RXDCK
RXDATA [15:0]
RXDSC
RXS
AB
S y s t e m t o O p t i c s
O p t i c s t o S y s t e m
SPI-4 Phase 1: OIF-SPI4-01.0
Support up to 10GB/s bi-directional data throughput
TXPRTY[3:0]TXSOCPTXEOP
TXERRTXVALID
RXVALIDRXERR
RXEOP
RXSOCP
RXCLKRXDATA[63:0]RXADDR[N-1:0]
RXSIZE[2:0]
RXPRTY[3:0]
TX
RX
RXFULL[3:0]
SONET/SDH OC-192
10GE WAN/LAN4xOC-48
16xOC-1264xOC-3
256xSTS-1
First generation; 200 MHz operation implementable in FPGA technology
64 bit interface @ 200 MHz (lower rate operation supported)HSTL Class 1 signals; source synchronous clocking; point to point operationOut-of-band addressing
TXCLK
TXREFCK
TXREFCK
RXREFCK
SerdesLink
LayerNP
ATM SAR
FramerTXSIZE[2:0]
TXDATA [63:0]TXADDR[N-1:0]
TXDCK
TXDATA [15:0]
TXDSC
TXCKSRC
RXREFCK
DC
ABTXSTARTTXFULL[3:0]
RXSTART
RXDCK
RXDATA [15:0]
RXDSC
RXS
AB
S y s t e m t o O p t i c s
O p t i c s t o S y s t e m
SPI-4 Phase 1: OIF-SPI4-01.0
4x16bit mode of operation for 4xOC-48 multi-phy applications
TXPRTY[3:0]TXSOCPTXEOP
TXERRTXVALID
RXVALIDRXERR
RXEOP
RXSOCP
RXCLKRXDATA[63:0]RXADDR[N-1:0]
RXSIZE[2:0]
RXPRTY[3:0]
TX
RX
RXFULL[3:0]
Supports:POS/HDLCEoS/X.86
ATM10GE LAN10GE WAN
Supports Packet over SONET (POS); Ethernet over SONET (EoS/X.86); ATM over SONET; 10GE WAN/LAN PHY (IEEE 802.3ae)
TDCLK
TXREFCK
TXREFCK
RXREFCK
SerdesLink
LayerNP
ATM SAR
FramerTDAT [15:0]TCTL
TXDCK
TXDATA [15:0]
TXDSC
TXCKSRC
RXREFCK
DC
AB
RXDCK
RXDATA [15:0]
RXDSC
RXS
AB
S y s t e m t o O p t i c s
O p t i c s t o S y s t e m
SPI-4 Phase 2
Support up to 10GB/s bi-directional data throughput
SONET/SDH OC-192
10GE WAN/LAN4xOC-48
16xOC-1264xOC-3
256xSTS-1
TSCLKTSTAT[1:0]
RSTAT[1:0]
RDCLKRDAT[15:0]RCTL
RSCLK
TX
RX
Next generation technology; faster and narrower interface 16 bit LVDS interface @ 800 MHz (622 MHz minimum operation)
TDCLK
TXREFCK TXREFCK
RXREFCK
SerdesLink
LayerNP
ATM SAR
FramerTDAT [15:0]TCTL
TXDCK
TXDATA [15:0]
TXDSC
TXCKSRC
RXREFCK
DC
AB
RXDCK
RXDATA [15:0]
RXDSC
RXS
AB
S y s t e m t o O p t i c s
O p t i c s t o S y s t e m
SPI-4 Phase 2: OIF-SPI4-02.0
TSCLKTSTAT[1:0]
RSTAT[1:0]
RDCLKRDAT[15:0]RCTL
RSCLK
TX
RX
Supports:POS/HDLCEoS/X.86
ATM10GE LAN10GE WAN
FIFO status out of band; 2 options for status signal rate (full and 1/4 speed)
Supports Packet over SONET (POS); Ethernet over SONET (EoS/X.86); ATM over SONET; 10GE WAN/LAN PHY (IEEE 802.3ae)
SPI-5: OIF-SPI5-01.0 System Packet Interface
OC-768 System Interface for Physical and Link Layer Devices
Transmit Link Layer
Device
Receive Link Layer Device
PHYDevice
Data
TransmitInterface
Status
Data
Status
ReceiveInterface
System PacketInterface (SPI)
SERDESDevice
SERDES FramerInterface (SFI-5)
SPI-5: OIF-SPI5-01.0 System Packet Interface
Point-to-point connection (i.e. single PHY / single Link Layer device)
Transmit Link Layer Device
Receive Link Layer Device
PHYDevice
Transmit Interface
Receive Interface
TCTL
TDCLK
TSTAT
TDAT [15:0]
RCTL
RDCLK
RSTAT
RDAT [15:0]
Support for 256 ports with address extension to 2144 ports
Point-to-point connection
Support for 256 ports
SPI-5: OIF-SPI5-01.0 System Packet Interface
Control words carry In-band Port Address, start/end of packet indication & error-control mode
Transmit Link Layer Device
Receive Link Layer Device
PHYDevice
Transmit Interface
Receive Interface
TCTL
TDCLK
TSTAT
TDAT [15:0]
RCTL
RDCLK
RSTAT
RDAT [15:0]
Data transfer segmented in bursts that are multiples of 16 words (32 bytes)2.488 Gb/s minimum data rate per line on data path
2.488 Gb/s
SPI-5: OIF-SPI5-01.0 System Packet Interface
Independent transmit/receive pool status channel
Transmit Link Layer Device
Receive Link Layer Device
PHYDevice
Transmit Interface
Receive Interface
TCTL
TDCLK
TSTAT
TDAT [15:0]
RCTL
RDCLK
RSTAT
RDAT [15:0]
Operates at the same clock rate as the data path
Control Word
PayloadData
Words
SPI-5: OIF-SPI5-01.0 System Packet Interface
Anatomy of a Transfer
Payload Control Word
Address Data Word(s)
Address Control Word
Max 16 bytes
Optional
32n Bytes (except End-of-Packet Transfers)